2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Backdoor for changing "FIFO Threshold for processing next packet"
28 * ethtool -C eth1 adaptive-rx on adaptive-tx on \
29 * rx-usecs 250 rx-frames-low N
30 * N := 16 | 32 | 64 | 128
34 * Timeline before release:
35 * Stage 5: Advanced offloading support.
37 * - Implement VLAN offloading.
39 * - Implement scatter-gather offloading.
40 * Use pci_map_page on scattered sk_buff for HIGHMEM support
41 * - Implement TCP Segement offloading.
42 * Due to TX FIFO size, we should turn off tso when mtu > 1500.
44 * Stage 6: CPU Load balancing.
47 * Along with multiple RX queue, for CPU load balancing.
50 * - Cleanup/re-orginize code, performence tuneing(alignment etc...).
51 * - Test and Release 1.0
54 * - Use NAPI instead of rx_tasklet?
55 * PCC Support Both Packet Counter and Timeout Interrupt for
56 * receive and transmit complete, does NAPI really needed?
57 * - Decode register dump for ethtool.
60 #include <linux/version.h>
61 #include <linux/module.h>
62 #include <linux/kernel.h>
63 #include <linux/pci.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/ethtool.h>
67 #include <linux/mii.h>
68 #include <linux/crc32.h>
69 #include <linux/delay.h>
70 #include <linux/spinlock.h>
73 #include <linux/ipv6.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
78 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
79 static struct net_device_stats *
80 jme_get_stats(struct net_device *netdev)
82 struct jme_adapter *jme = netdev_priv(netdev);
88 jme_mdio_read(struct net_device *netdev, int phy, int reg)
90 struct jme_adapter *jme = netdev_priv(netdev);
93 jwrite32(jme, JME_SMI, SMI_OP_REQ |
98 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
100 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
105 jeprintk(netdev->name, "phy read timeout : %d\n", reg);
109 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
113 jme_mdio_write(struct net_device *netdev,
114 int phy, int reg, int val)
116 struct jme_adapter *jme = netdev_priv(netdev);
119 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
120 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
121 smi_phy_addr(phy) | smi_reg_addr(reg));
124 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
126 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
131 jeprintk(netdev->name, "phy write timeout : %d\n", reg);
136 __always_inline static void
137 jme_reset_phy_processor(struct jme_adapter *jme)
141 jme_mdio_write(jme->dev,
143 MII_ADVERTISE, ADVERTISE_ALL |
144 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
146 jme_mdio_write(jme->dev,
149 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
151 val = jme_mdio_read(jme->dev,
155 jme_mdio_write(jme->dev,
157 MII_BMCR, val | BMCR_RESET);
163 __always_inline static void
164 jme_reset_mac_processor(struct jme_adapter *jme)
166 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
168 jwrite32(jme, JME_GHC, jme->reg_ghc);
169 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
170 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
171 jwrite32(jme, JME_WFODP, 0);
172 jwrite32(jme, JME_WFOI, 0);
173 jwrite32(jme, JME_GPREG0, GPREG0_DEFAULT);
174 jwrite32(jme, JME_GPREG1, 0);
177 __always_inline static void
178 jme_clear_pm(struct jme_adapter *jme)
180 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
181 pci_set_power_state(jme->pdev, PCI_D0);
182 pci_enable_wake(jme->pdev, PCI_D0, 0);
186 jme_reload_eeprom(struct jme_adapter *jme)
191 val = jread32(jme, JME_SMBCSR);
193 if(val & SMBCSR_EEPROMD)
196 jwrite32(jme, JME_SMBCSR, val);
197 val |= SMBCSR_RELOAD;
198 jwrite32(jme, JME_SMBCSR, val);
201 for (i = JME_SMB_TIMEOUT; i > 0; --i)
204 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
209 jeprintk(jme->dev->name, "eeprom reload timeout\n");
220 jme_load_macaddr(struct net_device *netdev)
222 struct jme_adapter *jme = netdev_priv(netdev);
223 unsigned char macaddr[6];
226 spin_lock(&jme->macaddr_lock);
227 val = jread32(jme, JME_RXUMA_LO);
228 macaddr[0] = (val >> 0) & 0xFF;
229 macaddr[1] = (val >> 8) & 0xFF;
230 macaddr[2] = (val >> 16) & 0xFF;
231 macaddr[3] = (val >> 24) & 0xFF;
232 val = jread32(jme, JME_RXUMA_HI);
233 macaddr[4] = (val >> 0) & 0xFF;
234 macaddr[5] = (val >> 8) & 0xFF;
235 memcpy(netdev->dev_addr, macaddr, 6);
236 spin_unlock(&jme->macaddr_lock);
239 __always_inline static void
240 jme_set_rx_pcc(struct jme_adapter *jme, int p)
244 jwrite32(jme, JME_PCCRX0,
245 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
246 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
249 jwrite32(jme, JME_PCCRX0,
250 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
251 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
254 jwrite32(jme, JME_PCCRX0,
255 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
256 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
262 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
266 jme_start_irq(struct jme_adapter *jme)
268 register struct dynpcc_info *dpi = &(jme->dpi);
270 jme_set_rx_pcc(jme, PCC_P1);
272 dpi->attempt = PCC_P1;
275 jwrite32(jme, JME_PCCTX,
276 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
277 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
284 jwrite32(jme, JME_IENS, INTR_ENABLE);
287 __always_inline static void
288 jme_stop_irq(struct jme_adapter *jme)
293 jwrite32(jme, JME_IENC, INTR_ENABLE);
297 __always_inline static void
298 jme_enable_shadow(struct jme_adapter *jme)
302 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
305 __always_inline static void
306 jme_disable_shadow(struct jme_adapter *jme)
308 jwrite32(jme, JME_SHBA_LO, 0x0);
312 jme_check_link(struct net_device *netdev, int testonly)
314 struct jme_adapter *jme = netdev_priv(netdev);
315 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
319 phylink = jread32(jme, JME_PHY_LINK);
321 if (phylink & PHY_LINK_UP) {
322 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
324 * If we did not enable AN
325 * Speed/Duplex Info should be obtained from SMI
327 phylink = PHY_LINK_UP;
329 bmcr = jme_mdio_read(jme->dev,
334 phylink |= ((bmcr & BMCR_SPEED1000) &&
335 (bmcr & BMCR_SPEED100) == 0) ?
336 PHY_LINK_SPEED_1000M :
337 (bmcr & BMCR_SPEED100) ?
338 PHY_LINK_SPEED_100M :
341 phylink |= (bmcr & BMCR_FULLDPLX) ?
344 strcpy(linkmsg, "Forced: ");
348 * Keep polling for speed/duplex resolve complete
350 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
354 phylink = jread32(jme, JME_PHY_LINK);
359 jeprintk(netdev->name,
360 "Waiting speed resolve timeout.\n");
362 strcpy(linkmsg, "ANed: ");
365 if(jme->phylink == phylink) {
372 jme->phylink = phylink;
374 switch(phylink & PHY_LINK_SPEED_MASK) {
375 case PHY_LINK_SPEED_10M:
377 strcpy(linkmsg, "10 Mbps, ");
379 case PHY_LINK_SPEED_100M:
380 ghc = GHC_SPEED_100M;
381 strcpy(linkmsg, "100 Mbps, ");
383 case PHY_LINK_SPEED_1000M:
384 ghc = GHC_SPEED_1000M;
385 strcpy(linkmsg, "1000 Mbps, ");
391 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
393 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
397 if(phylink & PHY_LINK_MDI_STAT)
398 strcat(linkmsg, "MDI-X");
400 strcat(linkmsg, "MDI");
402 if(phylink & PHY_LINK_DUPLEX)
403 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
405 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
409 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
410 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
412 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
416 jwrite32(jme, JME_GHC, ghc);
418 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
419 netif_carrier_on(netdev);
425 jprintk(netdev->name, "Link is down.\n");
427 netif_carrier_off(netdev);
436 jme_alloc_txdesc(struct jme_adapter *jme,
439 struct jme_ring *txring = jme->txring;
442 idx = txring->next_to_use;
444 if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
447 atomic_sub(nr_alloc, &txring->nr_free);
449 if((txring->next_to_use += nr_alloc) >= RING_DESC_NR)
450 txring->next_to_use -= RING_DESC_NR;
456 jme_tx_csum(struct sk_buff *skb, unsigned mtu, __u8 *flags)
458 if(skb->ip_summed == CHECKSUM_PARTIAL) {
461 switch (skb->protocol) {
462 case __constant_htons(ETH_P_IP):
463 ip_proto = ip_hdr(skb)->protocol;
465 case __constant_htons(ETH_P_IPV6):
466 ip_proto = ipv6_hdr(skb)->nexthdr;
476 *flags |= TXFLAG_TCPCS;
479 *flags |= TXFLAG_UDPCS;
482 jeprintk("jme", "Error upper layer protocol.\n");
489 jme_set_new_txdesc(struct jme_adapter *jme,
492 struct jme_ring *txring = jme->txring;
493 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
494 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
500 idx = jme_alloc_txdesc(jme, nr_desc);
503 return NETDEV_TX_BUSY;
505 for(i = 1 ; i < nr_desc ; ++i) {
506 ctxdesc = txdesc + ((idx + i) & (RING_DESC_NR-1));
507 ctxbi = txbi + ((idx + i) & (RING_DESC_NR-1));
509 dmaaddr = pci_map_single(jme->pdev,
514 pci_dma_sync_single_for_device(jme->pdev,
521 ctxdesc->desc2.flags = TXFLAG_OWN;
522 if(jme->dev->features & NETIF_F_HIGHDMA)
523 ctxdesc->desc2.flags |= TXFLAG_64BIT;
524 ctxdesc->desc2.datalen = cpu_to_le16(skb->len);
525 ctxdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
526 ctxdesc->desc2.bufaddrl = cpu_to_le32(
527 (__u64)dmaaddr & 0xFFFFFFFFUL);
529 ctxbi->mapping = dmaaddr;
530 ctxbi->len = skb->len;
533 ctxdesc = txdesc + idx;
540 ctxdesc->desc1.pktsize = cpu_to_le16(skb->len);
542 * Set OWN bit at final.
543 * When kernel transmit faster than NIC.
544 * And NIC trying to send this descriptor before we tell
545 * it to start sending this TX queue.
546 * Other fields are already filled correctly.
549 flags = TXFLAG_OWN | TXFLAG_INT;
550 jme_tx_csum(skb, jme->dev->mtu, &flags);
551 ctxdesc->desc1.flags = flags;
553 * Set tx buffer info after telling NIC to send
554 * For better tx_clean timing
557 ctxbi->nr_desc = nr_desc;
560 tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, nr_desc);
567 jme_setup_tx_resources(struct jme_adapter *jme)
569 struct jme_ring *txring = &(jme->txring[0]);
571 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
578 txring->dmaalloc = 0;
586 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
588 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
589 txring->next_to_use = 0;
590 txring->next_to_clean = 0;
591 atomic_set(&txring->nr_free, RING_DESC_NR);
594 * Initiallize Transmit Descriptors
596 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE);
597 memset(txring->bufinf, 0,
598 sizeof(struct jme_buffer_info) * RING_DESC_NR);
604 jme_free_tx_resources(struct jme_adapter *jme)
607 struct jme_ring *txring = &(jme->txring[0]);
608 struct jme_buffer_info *txbi = txring->bufinf;
611 for(i = 0 ; i < RING_DESC_NR ; ++i) {
612 txbi = txring->bufinf + i;
614 dev_kfree_skb(txbi->skb);
622 dma_free_coherent(&(jme->pdev->dev),
627 txring->alloc = NULL;
629 txring->dmaalloc = 0;
632 txring->next_to_use = 0;
633 txring->next_to_clean = 0;
634 atomic_set(&txring->nr_free, 0);
638 __always_inline static void
639 jme_enable_tx_engine(struct jme_adapter *jme)
644 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
647 * Setup TX Queue 0 DMA Bass Address
649 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
650 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
651 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
654 * Setup TX Descptor Count
656 jwrite32(jme, JME_TXQDC, RING_DESC_NR);
662 jwrite32(jme, JME_TXCS, jme->reg_txcs |
668 __always_inline static void
669 jme_restart_tx_engine(struct jme_adapter *jme)
674 jwrite32(jme, JME_TXCS, jme->reg_txcs |
679 __always_inline static void
680 jme_disable_tx_engine(struct jme_adapter *jme)
688 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
690 val = jread32(jme, JME_TXCS);
691 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
694 val = jread32(jme, JME_TXCS);
698 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
699 jme_reset_mac_processor(jme);
706 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
708 struct jme_ring *rxring = jme->rxring;
709 register volatile struct rxdesc* rxdesc = rxring->desc;
710 struct jme_buffer_info *rxbi = rxring->bufinf;
716 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
717 rxdesc->desc1.bufaddrl = cpu_to_le32(
718 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
719 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
720 if(jme->dev->features & NETIF_F_HIGHDMA)
721 rxdesc->desc1.flags = RXFLAG_64BIT;
723 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
727 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
729 struct jme_ring *rxring = &(jme->rxring[0]);
730 struct jme_buffer_info *rxbi = rxring->bufinf;
731 unsigned long offset;
734 skb = netdev_alloc_skb(jme->dev,
735 jme->dev->mtu + RX_EXTRA_LEN);
739 if(unlikely(skb_is_nonlinear(skb))) {
740 dprintk(jme->dev->name,
741 "Allocated skb fragged(%d).\n",
742 skb_shinfo(skb)->nr_frags);
748 (unsigned long)(skb->data)
749 & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
750 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
754 rxbi->len = skb_tailroom(skb);
755 rxbi->mapping = pci_map_single(jme->pdev,
764 jme_free_rx_buf(struct jme_adapter *jme, int i)
766 struct jme_ring *rxring = &(jme->rxring[0]);
767 struct jme_buffer_info *rxbi = rxring->bufinf;
771 pci_unmap_single(jme->pdev,
775 dev_kfree_skb(rxbi->skb);
783 jme_free_rx_resources(struct jme_adapter *jme)
786 struct jme_ring *rxring = &(jme->rxring[0]);
789 for(i = 0 ; i < RING_DESC_NR ; ++i)
790 jme_free_rx_buf(jme, i);
792 dma_free_coherent(&(jme->pdev->dev),
796 rxring->alloc = NULL;
798 rxring->dmaalloc = 0;
801 rxring->next_to_use = 0;
802 rxring->next_to_clean = 0;
806 jme_setup_rx_resources(struct jme_adapter *jme)
809 struct jme_ring *rxring = &(jme->rxring[0]);
811 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
817 rxring->dmaalloc = 0;
825 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
827 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
828 rxring->next_to_use = 0;
829 rxring->next_to_clean = 0;
832 * Initiallize Receive Descriptors
834 for(i = 0 ; i < RING_DESC_NR ; ++i) {
835 if(unlikely(jme_make_new_rx_buf(jme, i))) {
836 jme_free_rx_resources(jme);
840 jme_set_clean_rxdesc(jme, i);
846 __always_inline static void
847 jme_enable_rx_engine(struct jme_adapter *jme)
850 * Setup RX DMA Bass Address
852 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
853 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
854 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
857 * Setup RX Descptor Count
859 jwrite32(jme, JME_RXQDC, RING_DESC_NR);
862 * Setup Unicast Filter
864 jme_set_multi(jme->dev);
870 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
876 __always_inline static void
877 jme_restart_rx_engine(struct jme_adapter *jme)
882 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
889 __always_inline static void
890 jme_disable_rx_engine(struct jme_adapter *jme)
898 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
900 val = jread32(jme, JME_RXCS);
901 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
904 val = jread32(jme, JME_RXCS);
908 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
913 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx, int summed)
915 struct jme_ring *rxring = &(jme->rxring[0]);
916 volatile struct rxdesc *rxdesc = rxring->desc;
917 struct jme_buffer_info *rxbi = rxring->bufinf;
925 pci_dma_sync_single_for_cpu(jme->pdev,
930 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
931 pci_dma_sync_single_for_device(jme->pdev,
936 ++(NET_STAT(jme).rx_dropped);
939 framesize = le16_to_cpu(rxdesc->descwb.framesize)
942 skb_reserve(skb, RX_PREPAD_SIZE);
943 skb_put(skb, framesize);
944 skb->protocol = eth_type_trans(skb, jme->dev);
947 skb->ip_summed = CHECKSUM_UNNECESSARY;
949 skb->ip_summed = CHECKSUM_NONE;
953 if(le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST_MUL)
954 ++(NET_STAT(jme).multicast);
956 jme->dev->last_rx = jiffies;
957 NET_STAT(jme).rx_bytes += framesize;
958 ++(NET_STAT(jme).rx_packets);
961 jme_set_clean_rxdesc(jme, idx);
966 jme_rxsum_bad(struct jme_adapter *jme, __u16 flags)
968 if(unlikely((flags & RXWBFLAG_TCPON) &&
969 !(flags & RXWBFLAG_TCPCS))) {
970 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
973 else if(unlikely((flags & RXWBFLAG_UDPON) &&
974 !(flags & RXWBFLAG_UDPCS))) {
975 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
978 else if(unlikely((flags & RXWBFLAG_IPV4) &&
979 !(flags & RXWBFLAG_IPCS))) {
980 csum_dbg(jme->dev->name, "IPV4 Checksum error.\n");
989 jme_process_receive(struct jme_adapter *jme, int limit)
991 struct jme_ring *rxring = &(jme->rxring[0]);
992 volatile struct rxdesc *rxdesc = rxring->desc;
993 int i, j, ccnt, desccnt;
995 i = rxring->next_to_clean;
998 rxdesc = rxring->desc;
1001 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
1002 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1005 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1007 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
1009 if(unlikely(desccnt > 1 ||
1010 rxdesc->descwb.errstat & RXWBERR_ALLERR ||
1011 jme_rxsum_bad(jme, rxdesc->descwb.flags))) {
1013 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
1014 ++(NET_STAT(jme).rx_crc_errors);
1015 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
1016 ++(NET_STAT(jme).rx_fifo_errors);
1018 ++(NET_STAT(jme).rx_errors);
1021 rx_dbg(jme->dev->name,
1022 "RX: More than one(%d) descriptor, "
1024 desccnt, le16_to_cpu(rxdesc->descwb.framesize));
1025 limit -= desccnt - 1;
1028 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
1029 jme_set_clean_rxdesc(jme, j);
1031 if(unlikely(++j == RING_DESC_NR))
1037 jme_alloc_and_feed_skb(jme, i,
1038 (rxdesc->descwb.flags &
1044 if((i += desccnt) >= RING_DESC_NR)
1049 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
1050 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
1051 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
1054 rxring->next_to_clean = i;
1056 return limit > 0 ? limit : 0;
1061 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1063 if(likely(atmp == dpi->cur))
1066 if(dpi->attempt == atmp) {
1070 dpi->attempt = atmp;
1077 jme_dynamic_pcc(struct jme_adapter *jme)
1079 register struct dynpcc_info *dpi = &(jme->dpi);
1081 if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1082 jme_attempt_pcc(dpi, PCC_P3);
1083 else if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P2_THRESHOLD
1084 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1085 jme_attempt_pcc(dpi, PCC_P2);
1087 jme_attempt_pcc(dpi, PCC_P1);
1089 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 20)) {
1090 jme_set_rx_pcc(jme, dpi->attempt);
1091 dpi->cur = dpi->attempt;
1097 jme_start_pcc_timer(struct jme_adapter *jme)
1099 struct dynpcc_info *dpi = &(jme->dpi);
1100 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1101 dpi->last_pkts = NET_STAT(jme).rx_packets;
1103 jwrite32(jme, JME_TMCSR,
1104 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1108 jme_stop_pcc_timer(struct jme_adapter *jme)
1110 jwrite32(jme, JME_TMCSR, 0);
1114 jme_pcc_tasklet(unsigned long arg)
1116 struct jme_adapter *jme = (struct jme_adapter*)arg;
1117 struct net_device *netdev = jme->dev;
1120 if(unlikely(netif_queue_stopped(netdev) ||
1121 (atomic_read(&jme->link_changing) != 1)
1123 jme_stop_pcc_timer(jme);
1127 jme_dynamic_pcc(jme);
1128 jme_start_pcc_timer(jme);
1132 jme_link_change_tasklet(unsigned long arg)
1134 struct jme_adapter *jme = (struct jme_adapter*)arg;
1135 struct net_device *netdev = jme->dev;
1136 int timeout = WAIT_TASKLET_TIMEOUT;
1139 if(!atomic_dec_and_test(&jme->link_changing))
1142 if(jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1145 jme->old_mtu = netdev->mtu;
1146 netif_stop_queue(netdev);
1148 while(--timeout > 0 &&
1150 atomic_read(&jme->rx_cleaning) != 1 ||
1151 atomic_read(&jme->tx_cleaning) != 1
1157 if(netif_carrier_ok(netdev)) {
1158 jme_stop_pcc_timer(jme);
1159 jme_reset_mac_processor(jme);
1160 jme_free_rx_resources(jme);
1161 jme_free_tx_resources(jme);
1164 jme_check_link(netdev, 0);
1165 if(netif_carrier_ok(netdev)) {
1166 rc = jme_setup_rx_resources(jme);
1168 jeprintk(netdev->name,
1169 "Allocating resources for RX error"
1170 ", Device STOPPED!\n");
1175 rc = jme_setup_tx_resources(jme);
1177 jeprintk(netdev->name,
1178 "Allocating resources for TX error"
1179 ", Device STOPPED!\n");
1180 goto err_out_free_rx_resources;
1183 jme_enable_rx_engine(jme);
1184 jme_enable_tx_engine(jme);
1186 netif_start_queue(netdev);
1187 jme_start_pcc_timer(jme);
1192 err_out_free_rx_resources:
1193 jme_free_rx_resources(jme);
1195 atomic_inc(&jme->link_changing);
1199 jme_rx_clean_tasklet(unsigned long arg)
1201 struct jme_adapter *jme = (struct jme_adapter*)arg;
1202 struct dynpcc_info *dpi = &(jme->dpi);
1204 if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1207 if(unlikely(atomic_read(&jme->link_changing) != 1))
1210 if(unlikely(netif_queue_stopped(jme->dev)))
1213 jme_process_receive(jme, RING_DESC_NR);
1217 atomic_inc(&jme->rx_cleaning);
1221 jme_rx_empty_tasklet(unsigned long arg)
1223 struct jme_adapter *jme = (struct jme_adapter*)arg;
1225 if(unlikely(atomic_read(&jme->link_changing) != 1))
1228 if(unlikely(netif_queue_stopped(jme->dev)))
1231 queue_dbg(jme->dev->name, "RX Queue empty!\n");
1233 jme_rx_clean_tasklet(arg);
1234 jme_restart_rx_engine(jme);
1238 jme_tx_clean_tasklet(unsigned long arg)
1240 struct jme_adapter *jme = (struct jme_adapter*)arg;
1241 struct jme_ring *txring = &(jme->txring[0]);
1242 volatile struct txdesc *txdesc = txring->desc;
1243 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1244 int i, j, cnt = 0, max, err;
1246 if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1249 if(unlikely(atomic_read(&jme->link_changing) != 1))
1252 if(unlikely(netif_queue_stopped(jme->dev)))
1255 max = RING_DESC_NR - atomic_read(&txring->nr_free);
1257 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1259 for(i = txring->next_to_clean ; cnt < max ; ) {
1263 if(ctxbi->skb && !(txdesc[i].descwb.flags & TXWBFLAG_OWN)) {
1265 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1267 tx_dbg(jme->dev->name,
1268 "Tx Tasklet: Clean %d+%d\n",
1271 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
1272 ttxbi = txbi + ((i + j) & (RING_DESC_NR - 1));
1273 txdesc[(i+j)&(RING_DESC_NR-1)].dw[0] = 0;
1275 pci_unmap_single(jme->pdev,
1281 NET_STAT(jme).tx_bytes += ttxbi->len;
1287 dev_kfree_skb(ctxbi->skb);
1290 cnt += ctxbi->nr_desc;
1293 ++(NET_STAT(jme).tx_carrier_errors);
1295 ++(NET_STAT(jme).tx_packets);
1299 tx_dbg(jme->dev->name,
1301 " Stoped due to no skb.\n");
1303 tx_dbg(jme->dev->name,
1305 "Stoped due to not done.\n");
1309 if(unlikely((i += ctxbi->nr_desc) >= RING_DESC_NR))
1315 tx_dbg(jme->dev->name,
1316 "Tx Tasklet: Stop %d Jiffies %lu\n",
1318 txring->next_to_clean = i;
1320 atomic_add(cnt, &txring->nr_free);
1323 atomic_inc(&jme->tx_cleaning);
1327 jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
1332 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1335 * Write 1 clear interrupt status
1337 jwrite32f(jme, JME_IEVE, intrstat);
1339 if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1340 tasklet_schedule(&jme->linkch_task);
1344 if(intrstat & INTR_TMINTR)
1345 tasklet_schedule(&jme->pcc_task);
1347 if(intrstat & INTR_RX0EMP)
1348 tasklet_schedule(&jme->rxempty_task);
1350 if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1351 tasklet_schedule(&jme->rxclean_task);
1353 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
1354 tasklet_schedule(&jme->txclean_task);
1356 if((intrstat & ~INTR_ENABLE) != 0) {
1358 * Some interrupt not handled
1359 * but not enabled also (for debug)
1365 * Re-enable interrupt
1367 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1373 jme_intr(int irq, void *dev_id)
1375 struct net_device *netdev = dev_id;
1376 struct jme_adapter *jme = netdev_priv(netdev);
1379 intrstat = jread32(jme, JME_IEVE);
1382 * Check if it's really an interrupt for us
1384 if(unlikely(intrstat == 0))
1388 * Check if the device still exist
1390 if(unlikely(intrstat == ~((typeof(intrstat))0)))
1393 jme_intr_msi(jme, intrstat);
1399 jme_msi(int irq, void *dev_id)
1401 struct net_device *netdev = dev_id;
1402 struct jme_adapter *jme = netdev_priv(netdev);
1405 pci_dma_sync_single_for_cpu(jme->pdev,
1407 sizeof(__u32) * SHADOW_REG_NR,
1408 PCI_DMA_FROMDEVICE);
1409 intrstat = jme->shadow_regs[SHADOW_IEVE];
1410 jme->shadow_regs[SHADOW_IEVE] = 0;
1412 jme_intr_msi(jme, intrstat);
1419 jme_reset_link(struct jme_adapter *jme)
1422 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1426 jme_restart_an(struct jme_adapter *jme)
1429 unsigned long flags;
1431 spin_lock_irqsave(&jme->phy_lock, flags);
1432 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1433 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1434 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1435 spin_unlock_irqrestore(&jme->phy_lock, flags);
1439 jme_request_irq(struct jme_adapter *jme)
1442 struct net_device *netdev = jme->dev;
1443 irq_handler_t handler = jme_intr;
1444 int irq_flags = IRQF_SHARED;
1446 if (!pci_enable_msi(jme->pdev)) {
1447 jme->flags |= JME_FLAG_MSI;
1452 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1455 jeprintk(netdev->name,
1456 "Unable to allocate %s interrupt (return: %d)\n",
1457 jme->flags & JME_FLAG_MSI ? "MSI":"INTx", rc);
1459 if(jme->flags & JME_FLAG_MSI) {
1460 pci_disable_msi(jme->pdev);
1461 jme->flags &= ~JME_FLAG_MSI;
1465 netdev->irq = jme->pdev->irq;
1472 jme_free_irq(struct jme_adapter *jme)
1474 free_irq(jme->pdev->irq, jme->dev);
1475 if (jme->flags & JME_FLAG_MSI) {
1476 pci_disable_msi(jme->pdev);
1477 jme->flags &= ~JME_FLAG_MSI;
1478 jme->dev->irq = jme->pdev->irq;
1483 jme_open(struct net_device *netdev)
1485 struct jme_adapter *jme = netdev_priv(netdev);
1486 int rc, timeout = 100;
1491 atomic_read(&jme->link_changing) != 1 ||
1492 atomic_read(&jme->rx_cleaning) != 1 ||
1493 atomic_read(&jme->tx_cleaning) != 1
1503 jme_reset_mac_processor(jme);
1505 rc = jme_request_irq(jme);
1509 jme_enable_shadow(jme);
1511 jme_reset_link(jme);
1516 netif_stop_queue(netdev);
1517 netif_carrier_off(netdev);
1522 jme_close(struct net_device *netdev)
1524 struct jme_adapter *jme = netdev_priv(netdev);
1526 netif_stop_queue(netdev);
1527 netif_carrier_off(netdev);
1530 jme_disable_shadow(jme);
1533 tasklet_kill(&jme->linkch_task);
1534 tasklet_kill(&jme->txclean_task);
1535 tasklet_kill(&jme->rxclean_task);
1536 tasklet_kill(&jme->rxempty_task);
1538 jme_reset_mac_processor(jme);
1539 jme_free_rx_resources(jme);
1540 jme_free_tx_resources(jme);
1546 * This function is already protected by netif_tx_lock()
1549 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1551 struct jme_adapter *jme = netdev_priv(netdev);
1554 if(unlikely(netif_queue_stopped(jme->dev)))
1555 return NETDEV_TX_BUSY;
1559 ("jme", "Frags: %d Headlen: %d Len: %d Sum:%d\n",
1560 skb_shinfo(skb)->nr_frags,
1567 rc = jme_set_new_txdesc(jme, skb);
1569 if(unlikely(rc != NETDEV_TX_OK))
1572 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1573 TXCS_SELECT_QUEUE0 |
1576 netdev->trans_start = jiffies;
1578 return NETDEV_TX_OK;
1582 jme_set_macaddr(struct net_device *netdev, void *p)
1584 struct jme_adapter *jme = netdev_priv(netdev);
1585 struct sockaddr *addr = p;
1588 if(netif_running(netdev))
1591 spin_lock(&jme->macaddr_lock);
1592 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1594 val = addr->sa_data[3] << 24 |
1595 addr->sa_data[2] << 16 |
1596 addr->sa_data[1] << 8 |
1598 jwrite32(jme, JME_RXUMA_LO, val);
1599 val = addr->sa_data[5] << 8 |
1601 jwrite32(jme, JME_RXUMA_HI, val);
1602 spin_unlock(&jme->macaddr_lock);
1608 jme_set_multi(struct net_device *netdev)
1610 struct jme_adapter *jme = netdev_priv(netdev);
1611 u32 mc_hash[2] = {};
1613 unsigned long flags;
1615 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1617 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1619 if (netdev->flags & IFF_PROMISC) {
1620 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1622 else if (netdev->flags & IFF_ALLMULTI) {
1623 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1625 else if(netdev->flags & IFF_MULTICAST) {
1626 struct dev_mc_list *mclist;
1629 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1630 for (i = 0, mclist = netdev->mc_list;
1631 mclist && i < netdev->mc_count;
1632 ++i, mclist = mclist->next) {
1634 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1635 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
1638 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1639 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
1643 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1645 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1649 jme_change_mtu(struct net_device *netdev, int new_mtu)
1651 struct jme_adapter *jme = netdev_priv(netdev);
1653 if(new_mtu == jme->old_mtu)
1656 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
1657 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
1660 if(new_mtu > 4000) {
1661 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1662 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1663 jme_restart_rx_engine(jme);
1666 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1667 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1668 jme_restart_rx_engine(jme);
1671 if(new_mtu > 1900) {
1672 netdev->features &= ~NETIF_F_HW_CSUM;
1675 netdev->features |= NETIF_F_HW_CSUM;
1678 netdev->mtu = new_mtu;
1679 jme_reset_link(jme);
1685 jme_tx_timeout(struct net_device *netdev)
1687 struct jme_adapter *jme = netdev_priv(netdev);
1691 * And the link change will reinitiallize all RX/TX resources
1693 jme_reset_link(jme);
1697 jme_get_drvinfo(struct net_device *netdev,
1698 struct ethtool_drvinfo *info)
1700 struct jme_adapter *jme = netdev_priv(netdev);
1702 strcpy(info->driver, DRV_NAME);
1703 strcpy(info->version, DRV_VERSION);
1704 strcpy(info->bus_info, pci_name(jme->pdev));
1708 jme_get_regs_len(struct net_device *netdev)
1714 mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
1718 for(i = 0 ; i < len ; i += 4)
1719 p[i >> 2] = jread32(jme, reg + i);
1724 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
1726 struct jme_adapter *jme = netdev_priv(netdev);
1727 __u32 *p32 = (__u32*)p;
1729 memset(p, 0, 0x400);
1732 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
1735 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
1738 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
1741 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
1746 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1748 struct jme_adapter *jme = netdev_priv(netdev);
1750 ecmd->use_adaptive_rx_coalesce = true;
1751 ecmd->tx_coalesce_usecs = PCC_TX_TO;
1752 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
1754 switch(jme->dpi.cur) {
1756 ecmd->rx_coalesce_usecs = PCC_P1_TO;
1757 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
1760 ecmd->rx_coalesce_usecs = PCC_P2_TO;
1761 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
1764 ecmd->rx_coalesce_usecs = PCC_P3_TO;
1765 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
1775 * It's not actually for coalesce.
1776 * It changes internell FIFO related setting for testing.
1779 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1781 struct jme_adapter *jme = netdev_priv(netdev);
1783 if(ecmd->use_adaptive_rx_coalesce &&
1784 ecmd->use_adaptive_tx_coalesce &&
1785 ecmd->rx_coalesce_usecs == 250 &&
1786 (ecmd->rx_max_coalesced_frames_low == 16 ||
1787 ecmd->rx_max_coalesced_frames_low == 32 ||
1788 ecmd->rx_max_coalesced_frames_low == 64 ||
1789 ecmd->rx_max_coalesced_frames_low == 128)) {
1790 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1791 switch(ecmd->rx_max_coalesced_frames_low) {
1793 jme->reg_rxcs |= RXCS_FIFOTHNP_16QW;
1796 jme->reg_rxcs |= RXCS_FIFOTHNP_32QW;
1799 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1803 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1805 jme_restart_rx_engine(jme);
1815 jme_get_pauseparam(struct net_device *netdev,
1816 struct ethtool_pauseparam *ecmd)
1818 struct jme_adapter *jme = netdev_priv(netdev);
1819 unsigned long flags;
1822 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
1823 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
1825 spin_lock_irqsave(&jme->phy_lock, flags);
1826 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1827 spin_unlock_irqrestore(&jme->phy_lock, flags);
1828 ecmd->autoneg = (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
1832 jme_set_pauseparam(struct net_device *netdev,
1833 struct ethtool_pauseparam *ecmd)
1835 struct jme_adapter *jme = netdev_priv(netdev);
1836 unsigned long flags;
1839 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
1840 (ecmd->tx_pause != 0)) {
1843 jme->reg_txpfc |= TXPFC_PF_EN;
1845 jme->reg_txpfc &= ~TXPFC_PF_EN;
1847 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
1850 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1851 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
1852 (ecmd->rx_pause != 0)) {
1855 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
1857 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
1859 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1861 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1863 spin_lock_irqsave(&jme->phy_lock, flags);
1864 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1865 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
1866 (ecmd->autoneg != 0)) {
1869 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1871 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1873 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE, val);
1875 spin_unlock_irqrestore(&jme->phy_lock, flags);
1881 jme_get_wol(struct net_device *netdev,
1882 struct ethtool_wolinfo *wol)
1884 struct jme_adapter *jme = netdev_priv(netdev);
1886 wol->supported = WAKE_MAGIC | WAKE_PHY;
1890 if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1891 wol->wolopts |= WAKE_PHY;
1893 if(jme->reg_pmcs & PMCS_MFEN)
1894 wol->wolopts |= WAKE_MAGIC;
1899 jme_set_wol(struct net_device *netdev,
1900 struct ethtool_wolinfo *wol)
1902 struct jme_adapter *jme = netdev_priv(netdev);
1904 if(wol->wolopts & (WAKE_MAGICSECURE |
1913 if(wol->wolopts & WAKE_PHY)
1914 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
1916 if(wol->wolopts & WAKE_MAGIC)
1917 jme->reg_pmcs |= PMCS_MFEN;
1923 jme_get_settings(struct net_device *netdev,
1924 struct ethtool_cmd *ecmd)
1926 struct jme_adapter *jme = netdev_priv(netdev);
1928 unsigned long flags;
1930 spin_lock_irqsave(&jme->phy_lock, flags);
1931 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
1932 spin_unlock_irqrestore(&jme->phy_lock, flags);
1937 jme_set_settings(struct net_device *netdev,
1938 struct ethtool_cmd *ecmd)
1940 struct jme_adapter *jme = netdev_priv(netdev);
1942 unsigned long flags;
1944 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
1947 if(jme->mii_if.force_media &&
1948 ecmd->autoneg != AUTONEG_ENABLE &&
1949 (jme->mii_if.full_duplex != ecmd->duplex))
1952 spin_lock_irqsave(&jme->phy_lock, flags);
1953 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
1954 spin_unlock_irqrestore(&jme->phy_lock, flags);
1957 jme_reset_link(jme);
1960 jme->flags |= JME_FLAG_SSET;
1961 jme->old_ecmd = *ecmd;
1968 jme_get_link(struct net_device *netdev)
1970 struct jme_adapter *jme = netdev_priv(netdev);
1971 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
1975 jme_get_rx_csum(struct net_device *netdev)
1977 struct jme_adapter *jme = netdev_priv(netdev);
1979 return jme->reg_rxmcs & RXMCS_CHECKSUM;
1983 jme_set_rx_csum(struct net_device *netdev, u32 on)
1985 struct jme_adapter *jme = netdev_priv(netdev);
1986 unsigned long flags;
1988 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1990 jme->reg_rxmcs |= RXMCS_CHECKSUM;
1992 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
1993 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1994 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2000 jme_set_tx_csum(struct net_device *netdev, u32 on)
2003 netdev->features |= NETIF_F_HW_CSUM;
2005 netdev->features &= ~NETIF_F_HW_CSUM;
2011 jme_nway_reset(struct net_device *netdev)
2013 struct jme_adapter *jme = netdev_priv(netdev);
2014 jme_restart_an(jme);
2018 static const struct ethtool_ops jme_ethtool_ops = {
2019 .get_drvinfo = jme_get_drvinfo,
2020 .get_regs_len = jme_get_regs_len,
2021 .get_regs = jme_get_regs,
2022 .get_coalesce = jme_get_coalesce,
2023 .set_coalesce = jme_set_coalesce,
2024 .get_pauseparam = jme_get_pauseparam,
2025 .set_pauseparam = jme_set_pauseparam,
2026 .get_wol = jme_get_wol,
2027 .set_wol = jme_set_wol,
2028 .get_settings = jme_get_settings,
2029 .set_settings = jme_set_settings,
2030 .get_link = jme_get_link,
2031 .get_rx_csum = jme_get_rx_csum,
2032 .set_rx_csum = jme_set_rx_csum,
2033 .set_tx_csum = jme_set_tx_csum,
2034 .nway_reset = jme_nway_reset,
2038 jme_pci_dma64(struct pci_dev *pdev)
2040 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2041 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2044 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2045 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2048 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2049 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2055 static int __devinit
2056 jme_init_one(struct pci_dev *pdev,
2057 const struct pci_device_id *ent)
2059 int rc = 0, using_dac;
2060 struct net_device *netdev;
2061 struct jme_adapter *jme;
2064 * set up PCI device basics
2066 rc = pci_enable_device(pdev);
2068 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2072 using_dac = jme_pci_dma64(pdev);
2074 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2076 goto err_out_disable_pdev;
2079 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2080 printk(KERN_ERR PFX "No PCI resource region found.\n");
2082 goto err_out_disable_pdev;
2085 rc = pci_request_regions(pdev, DRV_NAME);
2087 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2088 goto err_out_disable_pdev;
2091 pci_set_master(pdev);
2094 * alloc and init net device
2096 netdev = alloc_etherdev(sizeof(*jme));
2099 goto err_out_release_regions;
2101 netdev->open = jme_open;
2102 netdev->stop = jme_close;
2103 netdev->hard_start_xmit = jme_start_xmit;
2104 netdev->set_mac_address = jme_set_macaddr;
2105 netdev->set_multicast_list = jme_set_multi;
2106 netdev->change_mtu = jme_change_mtu;
2107 netdev->ethtool_ops = &jme_ethtool_ops;
2108 netdev->tx_timeout = jme_tx_timeout;
2109 netdev->watchdog_timeo = TX_TIMEOUT;
2110 NETDEV_GET_STATS(netdev, &jme_get_stats);
2111 netdev->features = NETIF_F_HW_CSUM;
2113 netdev->features |= NETIF_F_HIGHDMA;
2115 SET_NETDEV_DEV(netdev, &pdev->dev);
2116 pci_set_drvdata(pdev, netdev);
2121 jme = netdev_priv(netdev);
2124 jme->old_mtu = netdev->mtu = 1500;
2126 jme->regs = ioremap(pci_resource_start(pdev, 0),
2127 pci_resource_len(pdev, 0));
2130 goto err_out_free_netdev;
2132 jme->shadow_regs = pci_alloc_consistent(pdev,
2133 sizeof(__u32) * SHADOW_REG_NR,
2134 &(jme->shadow_dma));
2135 if (!(jme->shadow_regs)) {
2140 spin_lock_init(&jme->phy_lock);
2141 spin_lock_init(&jme->macaddr_lock);
2142 spin_lock_init(&jme->rxmcs_lock);
2144 atomic_set(&jme->link_changing, 1);
2145 atomic_set(&jme->rx_cleaning, 1);
2146 atomic_set(&jme->tx_cleaning, 1);
2148 tasklet_init(&jme->pcc_task,
2150 (unsigned long) jme);
2151 tasklet_init(&jme->linkch_task,
2152 &jme_link_change_tasklet,
2153 (unsigned long) jme);
2154 tasklet_init(&jme->txclean_task,
2155 &jme_tx_clean_tasklet,
2156 (unsigned long) jme);
2157 tasklet_init(&jme->rxclean_task,
2158 &jme_rx_clean_tasklet,
2159 (unsigned long) jme);
2160 tasklet_init(&jme->rxempty_task,
2161 &jme_rx_empty_tasklet,
2162 (unsigned long) jme);
2163 jme->mii_if.dev = netdev;
2164 jme->mii_if.phy_id = 1;
2165 jme->mii_if.supports_gmii = 1;
2166 jme->mii_if.mdio_read = jme_mdio_read;
2167 jme->mii_if.mdio_write = jme_mdio_write;
2169 jme->dpi.cur = PCC_P1;
2171 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
2172 jme->reg_rxcs = RXCS_DEFAULT;
2173 jme->reg_rxmcs = RXMCS_DEFAULT;
2177 * Get Max Read Req Size from PCI Config Space
2179 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2182 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2185 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2188 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2194 * Reset MAC processor and reload EEPROM for MAC Address
2197 jme_reset_phy_processor(jme);
2198 jme_reset_mac_processor(jme);
2199 rc = jme_reload_eeprom(jme);
2202 "Rload eeprom for reading MAC Address error.\n");
2203 goto err_out_free_shadow;
2205 jme_load_macaddr(netdev);
2209 * Tell stack that we are not ready to work until open()
2211 netif_carrier_off(netdev);
2212 netif_stop_queue(netdev);
2217 rc = register_netdev(netdev);
2219 printk(KERN_ERR PFX "Cannot register net device.\n");
2220 goto err_out_free_shadow;
2223 jprintk(netdev->name,
2224 "JMC250 gigabit eth %02x:%02x:%02x:%02x:%02x:%02x\n",
2225 netdev->dev_addr[0],
2226 netdev->dev_addr[1],
2227 netdev->dev_addr[2],
2228 netdev->dev_addr[3],
2229 netdev->dev_addr[4],
2230 netdev->dev_addr[5]);
2234 err_out_free_shadow:
2235 pci_free_consistent(pdev,
2236 sizeof(__u32) * SHADOW_REG_NR,
2241 err_out_free_netdev:
2242 pci_set_drvdata(pdev, NULL);
2243 free_netdev(netdev);
2244 err_out_release_regions:
2245 pci_release_regions(pdev);
2246 err_out_disable_pdev:
2247 pci_disable_device(pdev);
2252 static void __devexit
2253 jme_remove_one(struct pci_dev *pdev)
2255 struct net_device *netdev = pci_get_drvdata(pdev);
2256 struct jme_adapter *jme = netdev_priv(netdev);
2258 unregister_netdev(netdev);
2259 pci_free_consistent(pdev,
2260 sizeof(__u32) * SHADOW_REG_NR,
2264 pci_set_drvdata(pdev, NULL);
2265 free_netdev(netdev);
2266 pci_release_regions(pdev);
2267 pci_disable_device(pdev);
2272 jme_set_10m_half(struct jme_adapter *jme)
2276 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
2277 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
2278 BMCR_SPEED1000 | BMCR_FULLDPLX);
2281 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
2283 jwrite32(jme, JME_GHC, GHC_SPEED_10M);
2287 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2289 struct net_device *netdev = pci_get_drvdata(pdev);
2290 struct jme_adapter *jme = netdev_priv(netdev);
2293 atomic_dec(&jme->link_changing);
2295 netif_device_detach(netdev);
2296 netif_stop_queue(netdev);
2300 while(--timeout > 0 &&
2302 atomic_read(&jme->rx_cleaning) != 1 ||
2303 atomic_read(&jme->tx_cleaning) != 1
2308 jeprintk(netdev->name, "Waiting tasklets timeout.\n");
2311 jme_disable_shadow(jme);
2313 if(netif_carrier_ok(netdev)) {
2314 jme_stop_pcc_timer(jme);
2315 jme_reset_mac_processor(jme);
2316 jme_free_rx_resources(jme);
2317 jme_free_tx_resources(jme);
2318 netif_carrier_off(netdev);
2322 jme_set_10m_half(jme);
2324 pci_save_state(pdev);
2326 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2327 pci_enable_wake(pdev, PCI_D3cold, 1);
2330 pci_enable_wake(pdev, PCI_D3cold, 0);
2332 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2338 jme_resume(struct pci_dev *pdev)
2340 struct net_device *netdev = pci_get_drvdata(pdev);
2341 struct jme_adapter *jme = netdev_priv(netdev);
2344 pci_restore_state(pdev);
2346 if(jme->flags & JME_FLAG_SSET)
2347 jme_set_settings(netdev, &jme->old_ecmd);
2349 jme_reset_phy_processor(jme);
2351 jme_reset_mac_processor(jme);
2352 jme_enable_shadow(jme);
2353 jme_request_irq(jme);
2355 netif_device_attach(netdev);
2357 atomic_inc(&jme->link_changing);
2359 jme_reset_link(jme);
2364 static struct pci_device_id jme_pci_tbl[] = {
2365 { PCI_VDEVICE(JMICRON, 0x250) },
2369 static struct pci_driver jme_driver = {
2371 .id_table = jme_pci_tbl,
2372 .probe = jme_init_one,
2373 .remove = __devexit_p(jme_remove_one),
2375 .suspend = jme_suspend,
2376 .resume = jme_resume,
2377 #endif /* CONFIG_PM */
2381 jme_init_module(void)
2383 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2384 "driver version %s\n", DRV_VERSION);
2385 return pci_register_driver(&jme_driver);
2389 jme_cleanup_module(void)
2391 pci_unregister_driver(&jme_driver);
2394 module_init(jme_init_module);
2395 module_exit(jme_cleanup_module);
2397 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
2398 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2399 MODULE_LICENSE("GPL");
2400 MODULE_VERSION(DRV_VERSION);
2401 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);