drivers/net/*.c: Use static const
[jme.git] / jme.c
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7  *
8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  *
23  */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/mii.h>
34 #include <linux/crc32.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <linux/ipv6.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/if_vlan.h>
43 #include <linux/slab.h>
44 #include <net/ip6_checksum.h>
45 #include "jme.h"
46
47 static int force_pseudohp = -1;
48 static int no_pseudohp = -1;
49 static int no_extplug = -1;
50 module_param(force_pseudohp, int, 0);
51 MODULE_PARM_DESC(force_pseudohp,
52         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53 module_param(no_pseudohp, int, 0);
54 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55 module_param(no_extplug, int, 0);
56 MODULE_PARM_DESC(no_extplug,
57         "Do not use external plug signal for pseudo hot-plug.");
58
59 static int
60 jme_mdio_read(struct net_device *netdev, int phy, int reg)
61 {
62         struct jme_adapter *jme = netdev_priv(netdev);
63         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
64
65 read_again:
66         jwrite32(jme, JME_SMI, SMI_OP_REQ |
67                                 smi_phy_addr(phy) |
68                                 smi_reg_addr(reg));
69
70         wmb();
71         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72                 udelay(20);
73                 val = jread32(jme, JME_SMI);
74                 if ((val & SMI_OP_REQ) == 0)
75                         break;
76         }
77
78         if (i == 0) {
79                 pr_err("phy(%d) read timeout : %d\n", phy, reg);
80                 return 0;
81         }
82
83         if (again--)
84                 goto read_again;
85
86         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
87 }
88
89 static void
90 jme_mdio_write(struct net_device *netdev,
91                                 int phy, int reg, int val)
92 {
93         struct jme_adapter *jme = netdev_priv(netdev);
94         int i;
95
96         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98                 smi_phy_addr(phy) | smi_reg_addr(reg));
99
100         wmb();
101         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102                 udelay(20);
103                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104                         break;
105         }
106
107         if (i == 0)
108                 pr_err("phy(%d) write timeout : %d\n", phy, reg);
109 }
110
111 static inline void
112 jme_reset_phy_processor(struct jme_adapter *jme)
113 {
114         u32 val;
115
116         jme_mdio_write(jme->dev,
117                         jme->mii_if.phy_id,
118                         MII_ADVERTISE, ADVERTISE_ALL |
119                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120
121         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122                 jme_mdio_write(jme->dev,
123                                 jme->mii_if.phy_id,
124                                 MII_CTRL1000,
125                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126
127         val = jme_mdio_read(jme->dev,
128                                 jme->mii_if.phy_id,
129                                 MII_BMCR);
130
131         jme_mdio_write(jme->dev,
132                         jme->mii_if.phy_id,
133                         MII_BMCR, val | BMCR_RESET);
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138                        const u32 *mask, u32 crc, int fnr)
139 {
140         int i;
141
142         /*
143          * Setup CRC pattern
144          */
145         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146         wmb();
147         jwrite32(jme, JME_WFODP, crc);
148         wmb();
149
150         /*
151          * Setup Mask
152          */
153         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154                 jwrite32(jme, JME_WFOI,
155                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156                                 (fnr & WFOI_FRAME_SEL));
157                 wmb();
158                 jwrite32(jme, JME_WFODP, mask[i]);
159                 wmb();
160         }
161 }
162
163 static inline void
164 jme_reset_mac_processor(struct jme_adapter *jme)
165 {
166         static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167         u32 crc = 0xCDCDCDCD;
168         u32 gpreg0;
169         int i;
170
171         jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172         udelay(2);
173         jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177         jwrite32(jme, JME_RXQDC, 0x00000000);
178         jwrite32(jme, JME_RXNDA, 0x00000000);
179         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181         jwrite32(jme, JME_TXQDC, 0x00000000);
182         jwrite32(jme, JME_TXNDA, 0x00000000);
183
184         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187                 jme_setup_wakeup_frame(jme, mask, crc, i);
188         if (jme->fpgaver)
189                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190         else
191                 gpreg0 = GPREG0_DEFAULT;
192         jwrite32(jme, JME_GPREG0, gpreg0);
193         jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194 }
195
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
198 {
199         jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200         jwrite32(jme, JME_GHC, jme->reg_ghc);
201 }
202
203 static inline void
204 jme_clear_pm(struct jme_adapter *jme)
205 {
206         jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207         pci_set_power_state(jme->pdev, PCI_D0);
208         pci_enable_wake(jme->pdev, PCI_D0, false);
209 }
210
211 static int
212 jme_reload_eeprom(struct jme_adapter *jme)
213 {
214         u32 val;
215         int i;
216
217         val = jread32(jme, JME_SMBCSR);
218
219         if (val & SMBCSR_EEPROMD) {
220                 val |= SMBCSR_CNACK;
221                 jwrite32(jme, JME_SMBCSR, val);
222                 val |= SMBCSR_RELOAD;
223                 jwrite32(jme, JME_SMBCSR, val);
224                 mdelay(12);
225
226                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227                         mdelay(1);
228                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229                                 break;
230                 }
231
232                 if (i == 0) {
233                         pr_err("eeprom reload timeout\n");
234                         return -EIO;
235                 }
236         }
237
238         return 0;
239 }
240
241 static void
242 jme_load_macaddr(struct net_device *netdev)
243 {
244         struct jme_adapter *jme = netdev_priv(netdev);
245         unsigned char macaddr[6];
246         u32 val;
247
248         spin_lock_bh(&jme->macaddr_lock);
249         val = jread32(jme, JME_RXUMA_LO);
250         macaddr[0] = (val >>  0) & 0xFF;
251         macaddr[1] = (val >>  8) & 0xFF;
252         macaddr[2] = (val >> 16) & 0xFF;
253         macaddr[3] = (val >> 24) & 0xFF;
254         val = jread32(jme, JME_RXUMA_HI);
255         macaddr[4] = (val >>  0) & 0xFF;
256         macaddr[5] = (val >>  8) & 0xFF;
257         memcpy(netdev->dev_addr, macaddr, 6);
258         spin_unlock_bh(&jme->macaddr_lock);
259 }
260
261 static inline void
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
263 {
264         switch (p) {
265         case PCC_OFF:
266                 jwrite32(jme, JME_PCCRX0,
267                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269                 break;
270         case PCC_P1:
271                 jwrite32(jme, JME_PCCRX0,
272                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274                 break;
275         case PCC_P2:
276                 jwrite32(jme, JME_PCCRX0,
277                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279                 break;
280         case PCC_P3:
281                 jwrite32(jme, JME_PCCRX0,
282                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284                 break;
285         default:
286                 break;
287         }
288         wmb();
289
290         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291                 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
292 }
293
294 static void
295 jme_start_irq(struct jme_adapter *jme)
296 {
297         register struct dynpcc_info *dpi = &(jme->dpi);
298
299         jme_set_rx_pcc(jme, PCC_P1);
300         dpi->cur                = PCC_P1;
301         dpi->attempt            = PCC_P1;
302         dpi->cnt                = 0;
303
304         jwrite32(jme, JME_PCCTX,
305                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307                         PCCTXQ0_EN
308                 );
309
310         /*
311          * Enable Interrupts
312          */
313         jwrite32(jme, JME_IENS, INTR_ENABLE);
314 }
315
316 static inline void
317 jme_stop_irq(struct jme_adapter *jme)
318 {
319         /*
320          * Disable Interrupts
321          */
322         jwrite32f(jme, JME_IENC, INTR_ENABLE);
323 }
324
325 static u32
326 jme_linkstat_from_phy(struct jme_adapter *jme)
327 {
328         u32 phylink, bmsr;
329
330         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332         if (bmsr & BMSR_ANCOMP)
333                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335         return phylink;
336 }
337
338 static inline void
339 jme_set_phyfifoa(struct jme_adapter *jme)
340 {
341         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342 }
343
344 static inline void
345 jme_set_phyfifob(struct jme_adapter *jme)
346 {
347         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348 }
349
350 static int
351 jme_check_link(struct net_device *netdev, int testonly)
352 {
353         struct jme_adapter *jme = netdev_priv(netdev);
354         u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
355         char linkmsg[64];
356         int rc = 0;
357
358         linkmsg[0] = '\0';
359
360         if (jme->fpgaver)
361                 phylink = jme_linkstat_from_phy(jme);
362         else
363                 phylink = jread32(jme, JME_PHY_LINK);
364
365         if (phylink & PHY_LINK_UP) {
366                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
367                         /*
368                          * If we did not enable AN
369                          * Speed/Duplex Info should be obtained from SMI
370                          */
371                         phylink = PHY_LINK_UP;
372
373                         bmcr = jme_mdio_read(jme->dev,
374                                                 jme->mii_if.phy_id,
375                                                 MII_BMCR);
376
377                         phylink |= ((bmcr & BMCR_SPEED1000) &&
378                                         (bmcr & BMCR_SPEED100) == 0) ?
379                                         PHY_LINK_SPEED_1000M :
380                                         (bmcr & BMCR_SPEED100) ?
381                                         PHY_LINK_SPEED_100M :
382                                         PHY_LINK_SPEED_10M;
383
384                         phylink |= (bmcr & BMCR_FULLDPLX) ?
385                                          PHY_LINK_DUPLEX : 0;
386
387                         strcat(linkmsg, "Forced: ");
388                 } else {
389                         /*
390                          * Keep polling for speed/duplex resolve complete
391                          */
392                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
393                                 --cnt) {
394
395                                 udelay(1);
396
397                                 if (jme->fpgaver)
398                                         phylink = jme_linkstat_from_phy(jme);
399                                 else
400                                         phylink = jread32(jme, JME_PHY_LINK);
401                         }
402                         if (!cnt)
403                                 pr_err("Waiting speed resolve timeout\n");
404
405                         strcat(linkmsg, "ANed: ");
406                 }
407
408                 if (jme->phylink == phylink) {
409                         rc = 1;
410                         goto out;
411                 }
412                 if (testonly)
413                         goto out;
414
415                 jme->phylink = phylink;
416
417                 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
418                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
419                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
420                 switch (phylink & PHY_LINK_SPEED_MASK) {
421                 case PHY_LINK_SPEED_10M:
422                         ghc |= GHC_SPEED_10M |
423                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
424                         strcat(linkmsg, "10 Mbps, ");
425                         break;
426                 case PHY_LINK_SPEED_100M:
427                         ghc |= GHC_SPEED_100M |
428                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
429                         strcat(linkmsg, "100 Mbps, ");
430                         break;
431                 case PHY_LINK_SPEED_1000M:
432                         ghc |= GHC_SPEED_1000M |
433                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
434                         strcat(linkmsg, "1000 Mbps, ");
435                         break;
436                 default:
437                         break;
438                 }
439
440                 if (phylink & PHY_LINK_DUPLEX) {
441                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
442                         ghc |= GHC_DPX;
443                 } else {
444                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
445                                                 TXMCS_BACKOFF |
446                                                 TXMCS_CARRIERSENSE |
447                                                 TXMCS_COLLISION);
448                         jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
449                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
450                                 TXTRHD_TXREN |
451                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
452                 }
453
454                 gpreg1 = GPREG1_DEFAULT;
455                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
456                         if (!(phylink & PHY_LINK_DUPLEX))
457                                 gpreg1 |= GPREG1_HALFMODEPATCH;
458                         switch (phylink & PHY_LINK_SPEED_MASK) {
459                         case PHY_LINK_SPEED_10M:
460                                 jme_set_phyfifoa(jme);
461                                 gpreg1 |= GPREG1_RSSPATCH;
462                                 break;
463                         case PHY_LINK_SPEED_100M:
464                                 jme_set_phyfifob(jme);
465                                 gpreg1 |= GPREG1_RSSPATCH;
466                                 break;
467                         case PHY_LINK_SPEED_1000M:
468                                 jme_set_phyfifoa(jme);
469                                 break;
470                         default:
471                                 break;
472                         }
473                 }
474
475                 jwrite32(jme, JME_GPREG1, gpreg1);
476                 jwrite32(jme, JME_GHC, ghc);
477                 jme->reg_ghc = ghc;
478
479                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
480                                         "Full-Duplex, " :
481                                         "Half-Duplex, ");
482                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
483                                         "MDI-X" :
484                                         "MDI");
485                 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
486                 netif_carrier_on(netdev);
487         } else {
488                 if (testonly)
489                         goto out;
490
491                 netif_info(jme, link, jme->dev, "Link is down\n");
492                 jme->phylink = 0;
493                 netif_carrier_off(netdev);
494         }
495
496 out:
497         return rc;
498 }
499
500 static int
501 jme_setup_tx_resources(struct jme_adapter *jme)
502 {
503         struct jme_ring *txring = &(jme->txring[0]);
504
505         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
506                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
507                                    &(txring->dmaalloc),
508                                    GFP_ATOMIC);
509
510         if (!txring->alloc)
511                 goto err_set_null;
512
513         /*
514          * 16 Bytes align
515          */
516         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
517                                                 RING_DESC_ALIGN);
518         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
519         txring->next_to_use     = 0;
520         atomic_set(&txring->next_to_clean, 0);
521         atomic_set(&txring->nr_free, jme->tx_ring_size);
522
523         txring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
524                                         jme->tx_ring_size, GFP_ATOMIC);
525         if (unlikely(!(txring->bufinf)))
526                 goto err_free_txring;
527
528         /*
529          * Initialize Transmit Descriptors
530          */
531         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
532         memset(txring->bufinf, 0,
533                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
534
535         return 0;
536
537 err_free_txring:
538         dma_free_coherent(&(jme->pdev->dev),
539                           TX_RING_ALLOC_SIZE(jme->tx_ring_size),
540                           txring->alloc,
541                           txring->dmaalloc);
542
543 err_set_null:
544         txring->desc = NULL;
545         txring->dmaalloc = 0;
546         txring->dma = 0;
547         txring->bufinf = NULL;
548
549         return -ENOMEM;
550 }
551
552 static void
553 jme_free_tx_resources(struct jme_adapter *jme)
554 {
555         int i;
556         struct jme_ring *txring = &(jme->txring[0]);
557         struct jme_buffer_info *txbi;
558
559         if (txring->alloc) {
560                 if (txring->bufinf) {
561                         for (i = 0 ; i < jme->tx_ring_size ; ++i) {
562                                 txbi = txring->bufinf + i;
563                                 if (txbi->skb) {
564                                         dev_kfree_skb(txbi->skb);
565                                         txbi->skb = NULL;
566                                 }
567                                 txbi->mapping           = 0;
568                                 txbi->len               = 0;
569                                 txbi->nr_desc           = 0;
570                                 txbi->start_xmit        = 0;
571                         }
572                         kfree(txring->bufinf);
573                 }
574
575                 dma_free_coherent(&(jme->pdev->dev),
576                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
577                                   txring->alloc,
578                                   txring->dmaalloc);
579
580                 txring->alloc           = NULL;
581                 txring->desc            = NULL;
582                 txring->dmaalloc        = 0;
583                 txring->dma             = 0;
584                 txring->bufinf          = NULL;
585         }
586         txring->next_to_use     = 0;
587         atomic_set(&txring->next_to_clean, 0);
588         atomic_set(&txring->nr_free, 0);
589 }
590
591 static inline void
592 jme_enable_tx_engine(struct jme_adapter *jme)
593 {
594         /*
595          * Select Queue 0
596          */
597         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
598         wmb();
599
600         /*
601          * Setup TX Queue 0 DMA Bass Address
602          */
603         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
604         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
605         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
606
607         /*
608          * Setup TX Descptor Count
609          */
610         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
611
612         /*
613          * Enable TX Engine
614          */
615         wmb();
616         jwrite32(jme, JME_TXCS, jme->reg_txcs |
617                                 TXCS_SELECT_QUEUE0 |
618                                 TXCS_ENABLE);
619
620 }
621
622 static inline void
623 jme_restart_tx_engine(struct jme_adapter *jme)
624 {
625         /*
626          * Restart TX Engine
627          */
628         jwrite32(jme, JME_TXCS, jme->reg_txcs |
629                                 TXCS_SELECT_QUEUE0 |
630                                 TXCS_ENABLE);
631 }
632
633 static inline void
634 jme_disable_tx_engine(struct jme_adapter *jme)
635 {
636         int i;
637         u32 val;
638
639         /*
640          * Disable TX Engine
641          */
642         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
643         wmb();
644
645         val = jread32(jme, JME_TXCS);
646         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
647                 mdelay(1);
648                 val = jread32(jme, JME_TXCS);
649                 rmb();
650         }
651
652         if (!i)
653                 pr_err("Disable TX engine timeout\n");
654 }
655
656 static void
657 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
658 {
659         struct jme_ring *rxring = &(jme->rxring[0]);
660         register struct rxdesc *rxdesc = rxring->desc;
661         struct jme_buffer_info *rxbi = rxring->bufinf;
662         rxdesc += i;
663         rxbi += i;
664
665         rxdesc->dw[0] = 0;
666         rxdesc->dw[1] = 0;
667         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
668         rxdesc->desc1.bufaddrl  = cpu_to_le32(
669                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
670         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
671         if (jme->dev->features & NETIF_F_HIGHDMA)
672                 rxdesc->desc1.flags = RXFLAG_64BIT;
673         wmb();
674         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
675 }
676
677 static int
678 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
679 {
680         struct jme_ring *rxring = &(jme->rxring[0]);
681         struct jme_buffer_info *rxbi = rxring->bufinf + i;
682         struct sk_buff *skb;
683
684         skb = netdev_alloc_skb(jme->dev,
685                 jme->dev->mtu + RX_EXTRA_LEN);
686         if (unlikely(!skb))
687                 return -ENOMEM;
688
689         rxbi->skb = skb;
690         rxbi->len = skb_tailroom(skb);
691         rxbi->mapping = pci_map_page(jme->pdev,
692                                         virt_to_page(skb->data),
693                                         offset_in_page(skb->data),
694                                         rxbi->len,
695                                         PCI_DMA_FROMDEVICE);
696
697         return 0;
698 }
699
700 static void
701 jme_free_rx_buf(struct jme_adapter *jme, int i)
702 {
703         struct jme_ring *rxring = &(jme->rxring[0]);
704         struct jme_buffer_info *rxbi = rxring->bufinf;
705         rxbi += i;
706
707         if (rxbi->skb) {
708                 pci_unmap_page(jme->pdev,
709                                  rxbi->mapping,
710                                  rxbi->len,
711                                  PCI_DMA_FROMDEVICE);
712                 dev_kfree_skb(rxbi->skb);
713                 rxbi->skb = NULL;
714                 rxbi->mapping = 0;
715                 rxbi->len = 0;
716         }
717 }
718
719 static void
720 jme_free_rx_resources(struct jme_adapter *jme)
721 {
722         int i;
723         struct jme_ring *rxring = &(jme->rxring[0]);
724
725         if (rxring->alloc) {
726                 if (rxring->bufinf) {
727                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
728                                 jme_free_rx_buf(jme, i);
729                         kfree(rxring->bufinf);
730                 }
731
732                 dma_free_coherent(&(jme->pdev->dev),
733                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
734                                   rxring->alloc,
735                                   rxring->dmaalloc);
736                 rxring->alloc    = NULL;
737                 rxring->desc     = NULL;
738                 rxring->dmaalloc = 0;
739                 rxring->dma      = 0;
740                 rxring->bufinf   = NULL;
741         }
742         rxring->next_to_use   = 0;
743         atomic_set(&rxring->next_to_clean, 0);
744 }
745
746 static int
747 jme_setup_rx_resources(struct jme_adapter *jme)
748 {
749         int i;
750         struct jme_ring *rxring = &(jme->rxring[0]);
751
752         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
753                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
754                                    &(rxring->dmaalloc),
755                                    GFP_ATOMIC);
756         if (!rxring->alloc)
757                 goto err_set_null;
758
759         /*
760          * 16 Bytes align
761          */
762         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
763                                                 RING_DESC_ALIGN);
764         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
765         rxring->next_to_use     = 0;
766         atomic_set(&rxring->next_to_clean, 0);
767
768         rxring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
769                                         jme->rx_ring_size, GFP_ATOMIC);
770         if (unlikely(!(rxring->bufinf)))
771                 goto err_free_rxring;
772
773         /*
774          * Initiallize Receive Descriptors
775          */
776         memset(rxring->bufinf, 0,
777                 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
778         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
779                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
780                         jme_free_rx_resources(jme);
781                         return -ENOMEM;
782                 }
783
784                 jme_set_clean_rxdesc(jme, i);
785         }
786
787         return 0;
788
789 err_free_rxring:
790         dma_free_coherent(&(jme->pdev->dev),
791                           RX_RING_ALLOC_SIZE(jme->rx_ring_size),
792                           rxring->alloc,
793                           rxring->dmaalloc);
794 err_set_null:
795         rxring->desc = NULL;
796         rxring->dmaalloc = 0;
797         rxring->dma = 0;
798         rxring->bufinf = NULL;
799
800         return -ENOMEM;
801 }
802
803 static inline void
804 jme_enable_rx_engine(struct jme_adapter *jme)
805 {
806         /*
807          * Select Queue 0
808          */
809         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
810                                 RXCS_QUEUESEL_Q0);
811         wmb();
812
813         /*
814          * Setup RX DMA Bass Address
815          */
816         jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
817         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
818         jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
819
820         /*
821          * Setup RX Descriptor Count
822          */
823         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
824
825         /*
826          * Setup Unicast Filter
827          */
828         jme_set_multi(jme->dev);
829
830         /*
831          * Enable RX Engine
832          */
833         wmb();
834         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
835                                 RXCS_QUEUESEL_Q0 |
836                                 RXCS_ENABLE |
837                                 RXCS_QST);
838 }
839
840 static inline void
841 jme_restart_rx_engine(struct jme_adapter *jme)
842 {
843         /*
844          * Start RX Engine
845          */
846         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
847                                 RXCS_QUEUESEL_Q0 |
848                                 RXCS_ENABLE |
849                                 RXCS_QST);
850 }
851
852 static inline void
853 jme_disable_rx_engine(struct jme_adapter *jme)
854 {
855         int i;
856         u32 val;
857
858         /*
859          * Disable RX Engine
860          */
861         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
862         wmb();
863
864         val = jread32(jme, JME_RXCS);
865         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
866                 mdelay(1);
867                 val = jread32(jme, JME_RXCS);
868                 rmb();
869         }
870
871         if (!i)
872                 pr_err("Disable RX engine timeout\n");
873
874 }
875
876 static int
877 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
878 {
879         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
880                 return false;
881
882         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
883                         == RXWBFLAG_TCPON)) {
884                 if (flags & RXWBFLAG_IPV4)
885                         netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
886                 return false;
887         }
888
889         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
890                         == RXWBFLAG_UDPON)) {
891                 if (flags & RXWBFLAG_IPV4)
892                         netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
893                 return false;
894         }
895
896         if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
897                         == RXWBFLAG_IPV4)) {
898                 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
899                 return false;
900         }
901
902         return true;
903 }
904
905 static void
906 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
907 {
908         struct jme_ring *rxring = &(jme->rxring[0]);
909         struct rxdesc *rxdesc = rxring->desc;
910         struct jme_buffer_info *rxbi = rxring->bufinf;
911         struct sk_buff *skb;
912         int framesize;
913
914         rxdesc += idx;
915         rxbi += idx;
916
917         skb = rxbi->skb;
918         pci_dma_sync_single_for_cpu(jme->pdev,
919                                         rxbi->mapping,
920                                         rxbi->len,
921                                         PCI_DMA_FROMDEVICE);
922
923         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
924                 pci_dma_sync_single_for_device(jme->pdev,
925                                                 rxbi->mapping,
926                                                 rxbi->len,
927                                                 PCI_DMA_FROMDEVICE);
928
929                 ++(NET_STAT(jme).rx_dropped);
930         } else {
931                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
932                                 - RX_PREPAD_SIZE;
933
934                 skb_reserve(skb, RX_PREPAD_SIZE);
935                 skb_put(skb, framesize);
936                 skb->protocol = eth_type_trans(skb, jme->dev);
937
938                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
939                         skb->ip_summed = CHECKSUM_UNNECESSARY;
940                 else
941                         skb_checksum_none_assert(skb);
942
943                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
944                         if (jme->vlgrp) {
945                                 jme->jme_vlan_rx(skb, jme->vlgrp,
946                                         le16_to_cpu(rxdesc->descwb.vlan));
947                                 NET_STAT(jme).rx_bytes += 4;
948                         } else {
949                                 dev_kfree_skb(skb);
950                         }
951                 } else {
952                         jme->jme_rx(skb);
953                 }
954
955                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
956                     cpu_to_le16(RXWBFLAG_DEST_MUL))
957                         ++(NET_STAT(jme).multicast);
958
959                 NET_STAT(jme).rx_bytes += framesize;
960                 ++(NET_STAT(jme).rx_packets);
961         }
962
963         jme_set_clean_rxdesc(jme, idx);
964
965 }
966
967 static int
968 jme_process_receive(struct jme_adapter *jme, int limit)
969 {
970         struct jme_ring *rxring = &(jme->rxring[0]);
971         struct rxdesc *rxdesc = rxring->desc;
972         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
973
974         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
975                 goto out_inc;
976
977         if (unlikely(atomic_read(&jme->link_changing) != 1))
978                 goto out_inc;
979
980         if (unlikely(!netif_carrier_ok(jme->dev)))
981                 goto out_inc;
982
983         i = atomic_read(&rxring->next_to_clean);
984         while (limit > 0) {
985                 rxdesc = rxring->desc;
986                 rxdesc += i;
987
988                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
989                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
990                         goto out;
991                 --limit;
992
993                 rmb();
994                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
995
996                 if (unlikely(desccnt > 1 ||
997                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
998
999                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1000                                 ++(NET_STAT(jme).rx_crc_errors);
1001                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1002                                 ++(NET_STAT(jme).rx_fifo_errors);
1003                         else
1004                                 ++(NET_STAT(jme).rx_errors);
1005
1006                         if (desccnt > 1)
1007                                 limit -= desccnt - 1;
1008
1009                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1010                                 jme_set_clean_rxdesc(jme, j);
1011                                 j = (j + 1) & (mask);
1012                         }
1013
1014                 } else {
1015                         jme_alloc_and_feed_skb(jme, i);
1016                 }
1017
1018                 i = (i + desccnt) & (mask);
1019         }
1020
1021 out:
1022         atomic_set(&rxring->next_to_clean, i);
1023
1024 out_inc:
1025         atomic_inc(&jme->rx_cleaning);
1026
1027         return limit > 0 ? limit : 0;
1028
1029 }
1030
1031 static void
1032 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1033 {
1034         if (likely(atmp == dpi->cur)) {
1035                 dpi->cnt = 0;
1036                 return;
1037         }
1038
1039         if (dpi->attempt == atmp) {
1040                 ++(dpi->cnt);
1041         } else {
1042                 dpi->attempt = atmp;
1043                 dpi->cnt = 0;
1044         }
1045
1046 }
1047
1048 static void
1049 jme_dynamic_pcc(struct jme_adapter *jme)
1050 {
1051         register struct dynpcc_info *dpi = &(jme->dpi);
1052
1053         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1054                 jme_attempt_pcc(dpi, PCC_P3);
1055         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1056                  dpi->intr_cnt > PCC_INTR_THRESHOLD)
1057                 jme_attempt_pcc(dpi, PCC_P2);
1058         else
1059                 jme_attempt_pcc(dpi, PCC_P1);
1060
1061         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1062                 if (dpi->attempt < dpi->cur)
1063                         tasklet_schedule(&jme->rxclean_task);
1064                 jme_set_rx_pcc(jme, dpi->attempt);
1065                 dpi->cur = dpi->attempt;
1066                 dpi->cnt = 0;
1067         }
1068 }
1069
1070 static void
1071 jme_start_pcc_timer(struct jme_adapter *jme)
1072 {
1073         struct dynpcc_info *dpi = &(jme->dpi);
1074         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1075         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1076         dpi->intr_cnt           = 0;
1077         jwrite32(jme, JME_TMCSR,
1078                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1079 }
1080
1081 static inline void
1082 jme_stop_pcc_timer(struct jme_adapter *jme)
1083 {
1084         jwrite32(jme, JME_TMCSR, 0);
1085 }
1086
1087 static void
1088 jme_shutdown_nic(struct jme_adapter *jme)
1089 {
1090         u32 phylink;
1091
1092         phylink = jme_linkstat_from_phy(jme);
1093
1094         if (!(phylink & PHY_LINK_UP)) {
1095                 /*
1096                  * Disable all interrupt before issue timer
1097                  */
1098                 jme_stop_irq(jme);
1099                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1100         }
1101 }
1102
1103 static void
1104 jme_pcc_tasklet(unsigned long arg)
1105 {
1106         struct jme_adapter *jme = (struct jme_adapter *)arg;
1107         struct net_device *netdev = jme->dev;
1108
1109         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1110                 jme_shutdown_nic(jme);
1111                 return;
1112         }
1113
1114         if (unlikely(!netif_carrier_ok(netdev) ||
1115                 (atomic_read(&jme->link_changing) != 1)
1116         )) {
1117                 jme_stop_pcc_timer(jme);
1118                 return;
1119         }
1120
1121         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1122                 jme_dynamic_pcc(jme);
1123
1124         jme_start_pcc_timer(jme);
1125 }
1126
1127 static inline void
1128 jme_polling_mode(struct jme_adapter *jme)
1129 {
1130         jme_set_rx_pcc(jme, PCC_OFF);
1131 }
1132
1133 static inline void
1134 jme_interrupt_mode(struct jme_adapter *jme)
1135 {
1136         jme_set_rx_pcc(jme, PCC_P1);
1137 }
1138
1139 static inline int
1140 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1141 {
1142         u32 apmc;
1143         apmc = jread32(jme, JME_APMC);
1144         return apmc & JME_APMC_PSEUDO_HP_EN;
1145 }
1146
1147 static void
1148 jme_start_shutdown_timer(struct jme_adapter *jme)
1149 {
1150         u32 apmc;
1151
1152         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1153         apmc &= ~JME_APMC_EPIEN_CTRL;
1154         if (!no_extplug) {
1155                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1156                 wmb();
1157         }
1158         jwrite32f(jme, JME_APMC, apmc);
1159
1160         jwrite32f(jme, JME_TIMER2, 0);
1161         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1162         jwrite32(jme, JME_TMCSR,
1163                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1164 }
1165
1166 static void
1167 jme_stop_shutdown_timer(struct jme_adapter *jme)
1168 {
1169         u32 apmc;
1170
1171         jwrite32f(jme, JME_TMCSR, 0);
1172         jwrite32f(jme, JME_TIMER2, 0);
1173         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1174
1175         apmc = jread32(jme, JME_APMC);
1176         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1177         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1178         wmb();
1179         jwrite32f(jme, JME_APMC, apmc);
1180 }
1181
1182 static void
1183 jme_link_change_tasklet(unsigned long arg)
1184 {
1185         struct jme_adapter *jme = (struct jme_adapter *)arg;
1186         struct net_device *netdev = jme->dev;
1187         int rc;
1188
1189         while (!atomic_dec_and_test(&jme->link_changing)) {
1190                 atomic_inc(&jme->link_changing);
1191                 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1192                 while (atomic_read(&jme->link_changing) != 1)
1193                         netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1194         }
1195
1196         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1197                 goto out;
1198
1199         jme->old_mtu = netdev->mtu;
1200         netif_stop_queue(netdev);
1201         if (jme_pseudo_hotplug_enabled(jme))
1202                 jme_stop_shutdown_timer(jme);
1203
1204         jme_stop_pcc_timer(jme);
1205         tasklet_disable(&jme->txclean_task);
1206         tasklet_disable(&jme->rxclean_task);
1207         tasklet_disable(&jme->rxempty_task);
1208
1209         if (netif_carrier_ok(netdev)) {
1210                 jme_reset_ghc_speed(jme);
1211                 jme_disable_rx_engine(jme);
1212                 jme_disable_tx_engine(jme);
1213                 jme_reset_mac_processor(jme);
1214                 jme_free_rx_resources(jme);
1215                 jme_free_tx_resources(jme);
1216
1217                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218                         jme_polling_mode(jme);
1219
1220                 netif_carrier_off(netdev);
1221         }
1222
1223         jme_check_link(netdev, 0);
1224         if (netif_carrier_ok(netdev)) {
1225                 rc = jme_setup_rx_resources(jme);
1226                 if (rc) {
1227                         pr_err("Allocating resources for RX error, Device STOPPED!\n");
1228                         goto out_enable_tasklet;
1229                 }
1230
1231                 rc = jme_setup_tx_resources(jme);
1232                 if (rc) {
1233                         pr_err("Allocating resources for TX error, Device STOPPED!\n");
1234                         goto err_out_free_rx_resources;
1235                 }
1236
1237                 jme_enable_rx_engine(jme);
1238                 jme_enable_tx_engine(jme);
1239
1240                 netif_start_queue(netdev);
1241
1242                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1243                         jme_interrupt_mode(jme);
1244
1245                 jme_start_pcc_timer(jme);
1246         } else if (jme_pseudo_hotplug_enabled(jme)) {
1247                 jme_start_shutdown_timer(jme);
1248         }
1249
1250         goto out_enable_tasklet;
1251
1252 err_out_free_rx_resources:
1253         jme_free_rx_resources(jme);
1254 out_enable_tasklet:
1255         tasklet_enable(&jme->txclean_task);
1256         tasklet_hi_enable(&jme->rxclean_task);
1257         tasklet_hi_enable(&jme->rxempty_task);
1258 out:
1259         atomic_inc(&jme->link_changing);
1260 }
1261
1262 static void
1263 jme_rx_clean_tasklet(unsigned long arg)
1264 {
1265         struct jme_adapter *jme = (struct jme_adapter *)arg;
1266         struct dynpcc_info *dpi = &(jme->dpi);
1267
1268         jme_process_receive(jme, jme->rx_ring_size);
1269         ++(dpi->intr_cnt);
1270
1271 }
1272
1273 static int
1274 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1275 {
1276         struct jme_adapter *jme = jme_napi_priv(holder);
1277         int rest;
1278
1279         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1280
1281         while (atomic_read(&jme->rx_empty) > 0) {
1282                 atomic_dec(&jme->rx_empty);
1283                 ++(NET_STAT(jme).rx_dropped);
1284                 jme_restart_rx_engine(jme);
1285         }
1286         atomic_inc(&jme->rx_empty);
1287
1288         if (rest) {
1289                 JME_RX_COMPLETE(netdev, holder);
1290                 jme_interrupt_mode(jme);
1291         }
1292
1293         JME_NAPI_WEIGHT_SET(budget, rest);
1294         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1295 }
1296
1297 static void
1298 jme_rx_empty_tasklet(unsigned long arg)
1299 {
1300         struct jme_adapter *jme = (struct jme_adapter *)arg;
1301
1302         if (unlikely(atomic_read(&jme->link_changing) != 1))
1303                 return;
1304
1305         if (unlikely(!netif_carrier_ok(jme->dev)))
1306                 return;
1307
1308         netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1309
1310         jme_rx_clean_tasklet(arg);
1311
1312         while (atomic_read(&jme->rx_empty) > 0) {
1313                 atomic_dec(&jme->rx_empty);
1314                 ++(NET_STAT(jme).rx_dropped);
1315                 jme_restart_rx_engine(jme);
1316         }
1317         atomic_inc(&jme->rx_empty);
1318 }
1319
1320 static void
1321 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1322 {
1323         struct jme_ring *txring = &(jme->txring[0]);
1324
1325         smp_wmb();
1326         if (unlikely(netif_queue_stopped(jme->dev) &&
1327         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1328                 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1329                 netif_wake_queue(jme->dev);
1330         }
1331
1332 }
1333
1334 static void
1335 jme_tx_clean_tasklet(unsigned long arg)
1336 {
1337         struct jme_adapter *jme = (struct jme_adapter *)arg;
1338         struct jme_ring *txring = &(jme->txring[0]);
1339         struct txdesc *txdesc = txring->desc;
1340         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1341         int i, j, cnt = 0, max, err, mask;
1342
1343         tx_dbg(jme, "Into txclean\n");
1344
1345         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1346                 goto out;
1347
1348         if (unlikely(atomic_read(&jme->link_changing) != 1))
1349                 goto out;
1350
1351         if (unlikely(!netif_carrier_ok(jme->dev)))
1352                 goto out;
1353
1354         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1355         mask = jme->tx_ring_mask;
1356
1357         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1358
1359                 ctxbi = txbi + i;
1360
1361                 if (likely(ctxbi->skb &&
1362                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1363
1364                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1365                                i, ctxbi->nr_desc, jiffies);
1366
1367                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1368
1369                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1370                                 ttxbi = txbi + ((i + j) & (mask));
1371                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1372
1373                                 pci_unmap_page(jme->pdev,
1374                                                  ttxbi->mapping,
1375                                                  ttxbi->len,
1376                                                  PCI_DMA_TODEVICE);
1377
1378                                 ttxbi->mapping = 0;
1379                                 ttxbi->len = 0;
1380                         }
1381
1382                         dev_kfree_skb(ctxbi->skb);
1383
1384                         cnt += ctxbi->nr_desc;
1385
1386                         if (unlikely(err)) {
1387                                 ++(NET_STAT(jme).tx_carrier_errors);
1388                         } else {
1389                                 ++(NET_STAT(jme).tx_packets);
1390                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1391                         }
1392
1393                         ctxbi->skb = NULL;
1394                         ctxbi->len = 0;
1395                         ctxbi->start_xmit = 0;
1396
1397                 } else {
1398                         break;
1399                 }
1400
1401                 i = (i + ctxbi->nr_desc) & mask;
1402
1403                 ctxbi->nr_desc = 0;
1404         }
1405
1406         tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1407         atomic_set(&txring->next_to_clean, i);
1408         atomic_add(cnt, &txring->nr_free);
1409
1410         jme_wake_queue_if_stopped(jme);
1411
1412 out:
1413         atomic_inc(&jme->tx_cleaning);
1414 }
1415
1416 static void
1417 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1418 {
1419         /*
1420          * Disable interrupt
1421          */
1422         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1423
1424         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1425                 /*
1426                  * Link change event is critical
1427                  * all other events are ignored
1428                  */
1429                 jwrite32(jme, JME_IEVE, intrstat);
1430                 tasklet_schedule(&jme->linkch_task);
1431                 goto out_reenable;
1432         }
1433
1434         if (intrstat & INTR_TMINTR) {
1435                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1436                 tasklet_schedule(&jme->pcc_task);
1437         }
1438
1439         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1440                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1441                 tasklet_schedule(&jme->txclean_task);
1442         }
1443
1444         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1445                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1446                                                      INTR_PCCRX0 |
1447                                                      INTR_RX0EMP)) |
1448                                         INTR_RX0);
1449         }
1450
1451         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1452                 if (intrstat & INTR_RX0EMP)
1453                         atomic_inc(&jme->rx_empty);
1454
1455                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1456                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1457                                 jme_polling_mode(jme);
1458                                 JME_RX_SCHEDULE(jme);
1459                         }
1460                 }
1461         } else {
1462                 if (intrstat & INTR_RX0EMP) {
1463                         atomic_inc(&jme->rx_empty);
1464                         tasklet_hi_schedule(&jme->rxempty_task);
1465                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1466                         tasklet_hi_schedule(&jme->rxclean_task);
1467                 }
1468         }
1469
1470 out_reenable:
1471         /*
1472          * Re-enable interrupt
1473          */
1474         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1475 }
1476
1477 static irqreturn_t
1478 jme_intr(int irq, void *dev_id)
1479 {
1480         struct net_device *netdev = dev_id;
1481         struct jme_adapter *jme = netdev_priv(netdev);
1482         u32 intrstat;
1483
1484         intrstat = jread32(jme, JME_IEVE);
1485
1486         /*
1487          * Check if it's really an interrupt for us
1488          */
1489         if (unlikely((intrstat & INTR_ENABLE) == 0))
1490                 return IRQ_NONE;
1491
1492         /*
1493          * Check if the device still exist
1494          */
1495         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1496                 return IRQ_NONE;
1497
1498         jme_intr_msi(jme, intrstat);
1499
1500         return IRQ_HANDLED;
1501 }
1502
1503 static irqreturn_t
1504 jme_msi(int irq, void *dev_id)
1505 {
1506         struct net_device *netdev = dev_id;
1507         struct jme_adapter *jme = netdev_priv(netdev);
1508         u32 intrstat;
1509
1510         intrstat = jread32(jme, JME_IEVE);
1511
1512         jme_intr_msi(jme, intrstat);
1513
1514         return IRQ_HANDLED;
1515 }
1516
1517 static void
1518 jme_reset_link(struct jme_adapter *jme)
1519 {
1520         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1521 }
1522
1523 static void
1524 jme_restart_an(struct jme_adapter *jme)
1525 {
1526         u32 bmcr;
1527
1528         spin_lock_bh(&jme->phy_lock);
1529         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1530         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1531         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1532         spin_unlock_bh(&jme->phy_lock);
1533 }
1534
1535 static int
1536 jme_request_irq(struct jme_adapter *jme)
1537 {
1538         int rc;
1539         struct net_device *netdev = jme->dev;
1540         irq_handler_t handler = jme_intr;
1541         int irq_flags = IRQF_SHARED;
1542
1543         if (!pci_enable_msi(jme->pdev)) {
1544                 set_bit(JME_FLAG_MSI, &jme->flags);
1545                 handler = jme_msi;
1546                 irq_flags = 0;
1547         }
1548
1549         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1550                           netdev);
1551         if (rc) {
1552                 netdev_err(netdev,
1553                            "Unable to request %s interrupt (return: %d)\n",
1554                            test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1555                            rc);
1556
1557                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1558                         pci_disable_msi(jme->pdev);
1559                         clear_bit(JME_FLAG_MSI, &jme->flags);
1560                 }
1561         } else {
1562                 netdev->irq = jme->pdev->irq;
1563         }
1564
1565         return rc;
1566 }
1567
1568 static void
1569 jme_free_irq(struct jme_adapter *jme)
1570 {
1571         free_irq(jme->pdev->irq, jme->dev);
1572         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1573                 pci_disable_msi(jme->pdev);
1574                 clear_bit(JME_FLAG_MSI, &jme->flags);
1575                 jme->dev->irq = jme->pdev->irq;
1576         }
1577 }
1578
1579 static inline void
1580 jme_phy_on(struct jme_adapter *jme)
1581 {
1582         u32 bmcr;
1583
1584         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1585         bmcr &= ~BMCR_PDOWN;
1586         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1587 }
1588
1589 static int
1590 jme_open(struct net_device *netdev)
1591 {
1592         struct jme_adapter *jme = netdev_priv(netdev);
1593         int rc;
1594
1595         jme_clear_pm(jme);
1596         JME_NAPI_ENABLE(jme);
1597
1598         tasklet_enable(&jme->linkch_task);
1599         tasklet_enable(&jme->txclean_task);
1600         tasklet_hi_enable(&jme->rxclean_task);
1601         tasklet_hi_enable(&jme->rxempty_task);
1602
1603         rc = jme_request_irq(jme);
1604         if (rc)
1605                 goto err_out;
1606
1607         jme_start_irq(jme);
1608
1609         if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1610                 jme_phy_on(jme);
1611                 jme_set_settings(netdev, &jme->old_ecmd);
1612         } else {
1613                 jme_reset_phy_processor(jme);
1614         }
1615
1616         jme_reset_link(jme);
1617
1618         return 0;
1619
1620 err_out:
1621         netif_stop_queue(netdev);
1622         netif_carrier_off(netdev);
1623         return rc;
1624 }
1625
1626 static void
1627 jme_set_100m_half(struct jme_adapter *jme)
1628 {
1629         u32 bmcr, tmp;
1630
1631         jme_phy_on(jme);
1632         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1633         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1634                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1635         tmp |= BMCR_SPEED100;
1636
1637         if (bmcr != tmp)
1638                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1639
1640         if (jme->fpgaver)
1641                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1642         else
1643                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1644 }
1645
1646 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1647 static void
1648 jme_wait_link(struct jme_adapter *jme)
1649 {
1650         u32 phylink, to = JME_WAIT_LINK_TIME;
1651
1652         mdelay(1000);
1653         phylink = jme_linkstat_from_phy(jme);
1654         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1655                 mdelay(10);
1656                 phylink = jme_linkstat_from_phy(jme);
1657         }
1658 }
1659
1660 static inline void
1661 jme_phy_off(struct jme_adapter *jme)
1662 {
1663         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1664 }
1665
1666 static void
1667 jme_powersave_phy(struct jme_adapter *jme)
1668 {
1669         if (jme->reg_pmcs) {
1670                 jme_set_100m_half(jme);
1671
1672                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1673                         jme_wait_link(jme);
1674
1675                 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1676         } else {
1677                 jme_phy_off(jme);
1678         }
1679 }
1680
1681 static int
1682 jme_close(struct net_device *netdev)
1683 {
1684         struct jme_adapter *jme = netdev_priv(netdev);
1685
1686         netif_stop_queue(netdev);
1687         netif_carrier_off(netdev);
1688
1689         jme_stop_irq(jme);
1690         jme_free_irq(jme);
1691
1692         JME_NAPI_DISABLE(jme);
1693
1694         tasklet_disable(&jme->linkch_task);
1695         tasklet_disable(&jme->txclean_task);
1696         tasklet_disable(&jme->rxclean_task);
1697         tasklet_disable(&jme->rxempty_task);
1698
1699         jme_reset_ghc_speed(jme);
1700         jme_disable_rx_engine(jme);
1701         jme_disable_tx_engine(jme);
1702         jme_reset_mac_processor(jme);
1703         jme_free_rx_resources(jme);
1704         jme_free_tx_resources(jme);
1705         jme->phylink = 0;
1706         jme_phy_off(jme);
1707
1708         return 0;
1709 }
1710
1711 static int
1712 jme_alloc_txdesc(struct jme_adapter *jme,
1713                         struct sk_buff *skb)
1714 {
1715         struct jme_ring *txring = &(jme->txring[0]);
1716         int idx, nr_alloc, mask = jme->tx_ring_mask;
1717
1718         idx = txring->next_to_use;
1719         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1720
1721         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1722                 return -1;
1723
1724         atomic_sub(nr_alloc, &txring->nr_free);
1725
1726         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1727
1728         return idx;
1729 }
1730
1731 static void
1732 jme_fill_tx_map(struct pci_dev *pdev,
1733                 struct txdesc *txdesc,
1734                 struct jme_buffer_info *txbi,
1735                 struct page *page,
1736                 u32 page_offset,
1737                 u32 len,
1738                 u8 hidma)
1739 {
1740         dma_addr_t dmaaddr;
1741
1742         dmaaddr = pci_map_page(pdev,
1743                                 page,
1744                                 page_offset,
1745                                 len,
1746                                 PCI_DMA_TODEVICE);
1747
1748         pci_dma_sync_single_for_device(pdev,
1749                                        dmaaddr,
1750                                        len,
1751                                        PCI_DMA_TODEVICE);
1752
1753         txdesc->dw[0] = 0;
1754         txdesc->dw[1] = 0;
1755         txdesc->desc2.flags     = TXFLAG_OWN;
1756         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1757         txdesc->desc2.datalen   = cpu_to_le16(len);
1758         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1759         txdesc->desc2.bufaddrl  = cpu_to_le32(
1760                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1761
1762         txbi->mapping = dmaaddr;
1763         txbi->len = len;
1764 }
1765
1766 static void
1767 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1768 {
1769         struct jme_ring *txring = &(jme->txring[0]);
1770         struct txdesc *txdesc = txring->desc, *ctxdesc;
1771         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1772         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1773         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1774         int mask = jme->tx_ring_mask;
1775         struct skb_frag_struct *frag;
1776         u32 len;
1777
1778         for (i = 0 ; i < nr_frags ; ++i) {
1779                 frag = &skb_shinfo(skb)->frags[i];
1780                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1781                 ctxbi = txbi + ((idx + i + 2) & (mask));
1782
1783                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1784                                  frag->page_offset, frag->size, hidma);
1785         }
1786
1787         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1788         ctxdesc = txdesc + ((idx + 1) & (mask));
1789         ctxbi = txbi + ((idx + 1) & (mask));
1790         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1791                         offset_in_page(skb->data), len, hidma);
1792
1793 }
1794
1795 static int
1796 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1797 {
1798         if (unlikely(skb_shinfo(skb)->gso_size &&
1799                         skb_header_cloned(skb) &&
1800                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1801                 dev_kfree_skb(skb);
1802                 return -1;
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int
1809 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1810 {
1811         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1812         if (*mss) {
1813                 *flags |= TXFLAG_LSEN;
1814
1815                 if (skb->protocol == htons(ETH_P_IP)) {
1816                         struct iphdr *iph = ip_hdr(skb);
1817
1818                         iph->check = 0;
1819                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1820                                                                 iph->daddr, 0,
1821                                                                 IPPROTO_TCP,
1822                                                                 0);
1823                 } else {
1824                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1825
1826                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1827                                                                 &ip6h->daddr, 0,
1828                                                                 IPPROTO_TCP,
1829                                                                 0);
1830                 }
1831
1832                 return 0;
1833         }
1834
1835         return 1;
1836 }
1837
1838 static void
1839 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1840 {
1841         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1842                 u8 ip_proto;
1843
1844                 switch (skb->protocol) {
1845                 case htons(ETH_P_IP):
1846                         ip_proto = ip_hdr(skb)->protocol;
1847                         break;
1848                 case htons(ETH_P_IPV6):
1849                         ip_proto = ipv6_hdr(skb)->nexthdr;
1850                         break;
1851                 default:
1852                         ip_proto = 0;
1853                         break;
1854                 }
1855
1856                 switch (ip_proto) {
1857                 case IPPROTO_TCP:
1858                         *flags |= TXFLAG_TCPCS;
1859                         break;
1860                 case IPPROTO_UDP:
1861                         *flags |= TXFLAG_UDPCS;
1862                         break;
1863                 default:
1864                         netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1865                         break;
1866                 }
1867         }
1868 }
1869
1870 static inline void
1871 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1872 {
1873         if (vlan_tx_tag_present(skb)) {
1874                 *flags |= TXFLAG_TAGON;
1875                 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1876         }
1877 }
1878
1879 static int
1880 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1881 {
1882         struct jme_ring *txring = &(jme->txring[0]);
1883         struct txdesc *txdesc;
1884         struct jme_buffer_info *txbi;
1885         u8 flags;
1886
1887         txdesc = (struct txdesc *)txring->desc + idx;
1888         txbi = txring->bufinf + idx;
1889
1890         txdesc->dw[0] = 0;
1891         txdesc->dw[1] = 0;
1892         txdesc->dw[2] = 0;
1893         txdesc->dw[3] = 0;
1894         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1895         /*
1896          * Set OWN bit at final.
1897          * When kernel transmit faster than NIC.
1898          * And NIC trying to send this descriptor before we tell
1899          * it to start sending this TX queue.
1900          * Other fields are already filled correctly.
1901          */
1902         wmb();
1903         flags = TXFLAG_OWN | TXFLAG_INT;
1904         /*
1905          * Set checksum flags while not tso
1906          */
1907         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1908                 jme_tx_csum(jme, skb, &flags);
1909         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1910         jme_map_tx_skb(jme, skb, idx);
1911         txdesc->desc1.flags = flags;
1912         /*
1913          * Set tx buffer info after telling NIC to send
1914          * For better tx_clean timing
1915          */
1916         wmb();
1917         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1918         txbi->skb = skb;
1919         txbi->len = skb->len;
1920         txbi->start_xmit = jiffies;
1921         if (!txbi->start_xmit)
1922                 txbi->start_xmit = (0UL-1);
1923
1924         return 0;
1925 }
1926
1927 static void
1928 jme_stop_queue_if_full(struct jme_adapter *jme)
1929 {
1930         struct jme_ring *txring = &(jme->txring[0]);
1931         struct jme_buffer_info *txbi = txring->bufinf;
1932         int idx = atomic_read(&txring->next_to_clean);
1933
1934         txbi += idx;
1935
1936         smp_wmb();
1937         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1938                 netif_stop_queue(jme->dev);
1939                 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1940                 smp_wmb();
1941                 if (atomic_read(&txring->nr_free)
1942                         >= (jme->tx_wake_threshold)) {
1943                         netif_wake_queue(jme->dev);
1944                         netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1945                 }
1946         }
1947
1948         if (unlikely(txbi->start_xmit &&
1949                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1950                         txbi->skb)) {
1951                 netif_stop_queue(jme->dev);
1952                 netif_info(jme, tx_queued, jme->dev,
1953                            "TX Queue Stopped %d@%lu\n", idx, jiffies);
1954         }
1955 }
1956
1957 /*
1958  * This function is already protected by netif_tx_lock()
1959  */
1960
1961 static netdev_tx_t
1962 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1963 {
1964         struct jme_adapter *jme = netdev_priv(netdev);
1965         int idx;
1966
1967         if (unlikely(jme_expand_header(jme, skb))) {
1968                 ++(NET_STAT(jme).tx_dropped);
1969                 return NETDEV_TX_OK;
1970         }
1971
1972         idx = jme_alloc_txdesc(jme, skb);
1973
1974         if (unlikely(idx < 0)) {
1975                 netif_stop_queue(netdev);
1976                 netif_err(jme, tx_err, jme->dev,
1977                           "BUG! Tx ring full when queue awake!\n");
1978
1979                 return NETDEV_TX_BUSY;
1980         }
1981
1982         jme_fill_tx_desc(jme, skb, idx);
1983
1984         jwrite32(jme, JME_TXCS, jme->reg_txcs |
1985                                 TXCS_SELECT_QUEUE0 |
1986                                 TXCS_QUEUE0S |
1987                                 TXCS_ENABLE);
1988
1989         tx_dbg(jme, "xmit: %d+%d@%lu\n",
1990                idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
1991         jme_stop_queue_if_full(jme);
1992
1993         return NETDEV_TX_OK;
1994 }
1995
1996 static int
1997 jme_set_macaddr(struct net_device *netdev, void *p)
1998 {
1999         struct jme_adapter *jme = netdev_priv(netdev);
2000         struct sockaddr *addr = p;
2001         u32 val;
2002
2003         if (netif_running(netdev))
2004                 return -EBUSY;
2005
2006         spin_lock_bh(&jme->macaddr_lock);
2007         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2008
2009         val = (addr->sa_data[3] & 0xff) << 24 |
2010               (addr->sa_data[2] & 0xff) << 16 |
2011               (addr->sa_data[1] & 0xff) <<  8 |
2012               (addr->sa_data[0] & 0xff);
2013         jwrite32(jme, JME_RXUMA_LO, val);
2014         val = (addr->sa_data[5] & 0xff) << 8 |
2015               (addr->sa_data[4] & 0xff);
2016         jwrite32(jme, JME_RXUMA_HI, val);
2017         spin_unlock_bh(&jme->macaddr_lock);
2018
2019         return 0;
2020 }
2021
2022 static void
2023 jme_set_multi(struct net_device *netdev)
2024 {
2025         struct jme_adapter *jme = netdev_priv(netdev);
2026         u32 mc_hash[2] = {};
2027
2028         spin_lock_bh(&jme->rxmcs_lock);
2029
2030         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2031
2032         if (netdev->flags & IFF_PROMISC) {
2033                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2034         } else if (netdev->flags & IFF_ALLMULTI) {
2035                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2036         } else if (netdev->flags & IFF_MULTICAST) {
2037                 struct netdev_hw_addr *ha;
2038                 int bit_nr;
2039
2040                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2041                 netdev_for_each_mc_addr(ha, netdev) {
2042                         bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2043                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2044                 }
2045
2046                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2047                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2048         }
2049
2050         wmb();
2051         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2052
2053         spin_unlock_bh(&jme->rxmcs_lock);
2054 }
2055
2056 static int
2057 jme_change_mtu(struct net_device *netdev, int new_mtu)
2058 {
2059         struct jme_adapter *jme = netdev_priv(netdev);
2060
2061         if (new_mtu == jme->old_mtu)
2062                 return 0;
2063
2064         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2065                 ((new_mtu) < IPV6_MIN_MTU))
2066                 return -EINVAL;
2067
2068         if (new_mtu > 4000) {
2069                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2070                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2071                 jme_restart_rx_engine(jme);
2072         } else {
2073                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2074                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2075                 jme_restart_rx_engine(jme);
2076         }
2077
2078         if (new_mtu > 1900) {
2079                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2080                                 NETIF_F_TSO | NETIF_F_TSO6);
2081         } else {
2082                 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2083                         netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2084                 if (test_bit(JME_FLAG_TSO, &jme->flags))
2085                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2086         }
2087
2088         netdev->mtu = new_mtu;
2089         jme_reset_link(jme);
2090
2091         return 0;
2092 }
2093
2094 static void
2095 jme_tx_timeout(struct net_device *netdev)
2096 {
2097         struct jme_adapter *jme = netdev_priv(netdev);
2098
2099         jme->phylink = 0;
2100         jme_reset_phy_processor(jme);
2101         if (test_bit(JME_FLAG_SSET, &jme->flags))
2102                 jme_set_settings(netdev, &jme->old_ecmd);
2103
2104         /*
2105          * Force to Reset the link again
2106          */
2107         jme_reset_link(jme);
2108 }
2109
2110 static inline void jme_pause_rx(struct jme_adapter *jme)
2111 {
2112         atomic_dec(&jme->link_changing);
2113
2114         jme_set_rx_pcc(jme, PCC_OFF);
2115         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2116                 JME_NAPI_DISABLE(jme);
2117         } else {
2118                 tasklet_disable(&jme->rxclean_task);
2119                 tasklet_disable(&jme->rxempty_task);
2120         }
2121 }
2122
2123 static inline void jme_resume_rx(struct jme_adapter *jme)
2124 {
2125         struct dynpcc_info *dpi = &(jme->dpi);
2126
2127         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2128                 JME_NAPI_ENABLE(jme);
2129         } else {
2130                 tasklet_hi_enable(&jme->rxclean_task);
2131                 tasklet_hi_enable(&jme->rxempty_task);
2132         }
2133         dpi->cur                = PCC_P1;
2134         dpi->attempt            = PCC_P1;
2135         dpi->cnt                = 0;
2136         jme_set_rx_pcc(jme, PCC_P1);
2137
2138         atomic_inc(&jme->link_changing);
2139 }
2140
2141 static void
2142 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2143 {
2144         struct jme_adapter *jme = netdev_priv(netdev);
2145
2146         jme_pause_rx(jme);
2147         jme->vlgrp = grp;
2148         jme_resume_rx(jme);
2149 }
2150
2151 static void
2152 jme_get_drvinfo(struct net_device *netdev,
2153                      struct ethtool_drvinfo *info)
2154 {
2155         struct jme_adapter *jme = netdev_priv(netdev);
2156
2157         strcpy(info->driver, DRV_NAME);
2158         strcpy(info->version, DRV_VERSION);
2159         strcpy(info->bus_info, pci_name(jme->pdev));
2160 }
2161
2162 static int
2163 jme_get_regs_len(struct net_device *netdev)
2164 {
2165         return JME_REG_LEN;
2166 }
2167
2168 static void
2169 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2170 {
2171         int i;
2172
2173         for (i = 0 ; i < len ; i += 4)
2174                 p[i >> 2] = jread32(jme, reg + i);
2175 }
2176
2177 static void
2178 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2179 {
2180         int i;
2181         u16 *p16 = (u16 *)p;
2182
2183         for (i = 0 ; i < reg_nr ; ++i)
2184                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2185 }
2186
2187 static void
2188 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2189 {
2190         struct jme_adapter *jme = netdev_priv(netdev);
2191         u32 *p32 = (u32 *)p;
2192
2193         memset(p, 0xFF, JME_REG_LEN);
2194
2195         regs->version = 1;
2196         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2197
2198         p32 += 0x100 >> 2;
2199         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2200
2201         p32 += 0x100 >> 2;
2202         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2203
2204         p32 += 0x100 >> 2;
2205         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2206
2207         p32 += 0x100 >> 2;
2208         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2209 }
2210
2211 static int
2212 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2213 {
2214         struct jme_adapter *jme = netdev_priv(netdev);
2215
2216         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2217         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2218
2219         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2220                 ecmd->use_adaptive_rx_coalesce = false;
2221                 ecmd->rx_coalesce_usecs = 0;
2222                 ecmd->rx_max_coalesced_frames = 0;
2223                 return 0;
2224         }
2225
2226         ecmd->use_adaptive_rx_coalesce = true;
2227
2228         switch (jme->dpi.cur) {
2229         case PCC_P1:
2230                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2231                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2232                 break;
2233         case PCC_P2:
2234                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2235                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2236                 break;
2237         case PCC_P3:
2238                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2239                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2240                 break;
2241         default:
2242                 break;
2243         }
2244
2245         return 0;
2246 }
2247
2248 static int
2249 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2250 {
2251         struct jme_adapter *jme = netdev_priv(netdev);
2252         struct dynpcc_info *dpi = &(jme->dpi);
2253
2254         if (netif_running(netdev))
2255                 return -EBUSY;
2256
2257         if (ecmd->use_adaptive_rx_coalesce &&
2258             test_bit(JME_FLAG_POLL, &jme->flags)) {
2259                 clear_bit(JME_FLAG_POLL, &jme->flags);
2260                 jme->jme_rx = netif_rx;
2261                 jme->jme_vlan_rx = vlan_hwaccel_rx;
2262                 dpi->cur                = PCC_P1;
2263                 dpi->attempt            = PCC_P1;
2264                 dpi->cnt                = 0;
2265                 jme_set_rx_pcc(jme, PCC_P1);
2266                 jme_interrupt_mode(jme);
2267         } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2268                    !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2269                 set_bit(JME_FLAG_POLL, &jme->flags);
2270                 jme->jme_rx = netif_receive_skb;
2271                 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2272                 jme_interrupt_mode(jme);
2273         }
2274
2275         return 0;
2276 }
2277
2278 static void
2279 jme_get_pauseparam(struct net_device *netdev,
2280                         struct ethtool_pauseparam *ecmd)
2281 {
2282         struct jme_adapter *jme = netdev_priv(netdev);
2283         u32 val;
2284
2285         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2286         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2287
2288         spin_lock_bh(&jme->phy_lock);
2289         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2290         spin_unlock_bh(&jme->phy_lock);
2291
2292         ecmd->autoneg =
2293                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2294 }
2295
2296 static int
2297 jme_set_pauseparam(struct net_device *netdev,
2298                         struct ethtool_pauseparam *ecmd)
2299 {
2300         struct jme_adapter *jme = netdev_priv(netdev);
2301         u32 val;
2302
2303         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2304                 (ecmd->tx_pause != 0)) {
2305
2306                 if (ecmd->tx_pause)
2307                         jme->reg_txpfc |= TXPFC_PF_EN;
2308                 else
2309                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2310
2311                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2312         }
2313
2314         spin_lock_bh(&jme->rxmcs_lock);
2315         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2316                 (ecmd->rx_pause != 0)) {
2317
2318                 if (ecmd->rx_pause)
2319                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2320                 else
2321                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2322
2323                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2324         }
2325         spin_unlock_bh(&jme->rxmcs_lock);
2326
2327         spin_lock_bh(&jme->phy_lock);
2328         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2329         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2330                 (ecmd->autoneg != 0)) {
2331
2332                 if (ecmd->autoneg)
2333                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2334                 else
2335                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2336
2337                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2338                                 MII_ADVERTISE, val);
2339         }
2340         spin_unlock_bh(&jme->phy_lock);
2341
2342         return 0;
2343 }
2344
2345 static void
2346 jme_get_wol(struct net_device *netdev,
2347                 struct ethtool_wolinfo *wol)
2348 {
2349         struct jme_adapter *jme = netdev_priv(netdev);
2350
2351         wol->supported = WAKE_MAGIC | WAKE_PHY;
2352
2353         wol->wolopts = 0;
2354
2355         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2356                 wol->wolopts |= WAKE_PHY;
2357
2358         if (jme->reg_pmcs & PMCS_MFEN)
2359                 wol->wolopts |= WAKE_MAGIC;
2360
2361 }
2362
2363 static int
2364 jme_set_wol(struct net_device *netdev,
2365                 struct ethtool_wolinfo *wol)
2366 {
2367         struct jme_adapter *jme = netdev_priv(netdev);
2368
2369         if (wol->wolopts & (WAKE_MAGICSECURE |
2370                                 WAKE_UCAST |
2371                                 WAKE_MCAST |
2372                                 WAKE_BCAST |
2373                                 WAKE_ARP))
2374                 return -EOPNOTSUPP;
2375
2376         jme->reg_pmcs = 0;
2377
2378         if (wol->wolopts & WAKE_PHY)
2379                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2380
2381         if (wol->wolopts & WAKE_MAGIC)
2382                 jme->reg_pmcs |= PMCS_MFEN;
2383
2384         jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2385
2386         return 0;
2387 }
2388
2389 static int
2390 jme_get_settings(struct net_device *netdev,
2391                      struct ethtool_cmd *ecmd)
2392 {
2393         struct jme_adapter *jme = netdev_priv(netdev);
2394         int rc;
2395
2396         spin_lock_bh(&jme->phy_lock);
2397         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2398         spin_unlock_bh(&jme->phy_lock);
2399         return rc;
2400 }
2401
2402 static int
2403 jme_set_settings(struct net_device *netdev,
2404                      struct ethtool_cmd *ecmd)
2405 {
2406         struct jme_adapter *jme = netdev_priv(netdev);
2407         int rc, fdc = 0;
2408
2409         if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2410                 return -EINVAL;
2411
2412         /*
2413          * Check If user changed duplex only while force_media.
2414          * Hardware would not generate link change interrupt.
2415          */
2416         if (jme->mii_if.force_media &&
2417         ecmd->autoneg != AUTONEG_ENABLE &&
2418         (jme->mii_if.full_duplex != ecmd->duplex))
2419                 fdc = 1;
2420
2421         spin_lock_bh(&jme->phy_lock);
2422         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2423         spin_unlock_bh(&jme->phy_lock);
2424
2425         if (!rc) {
2426                 if (fdc)
2427                         jme_reset_link(jme);
2428                 jme->old_ecmd = *ecmd;
2429                 set_bit(JME_FLAG_SSET, &jme->flags);
2430         }
2431
2432         return rc;
2433 }
2434
2435 static int
2436 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2437 {
2438         int rc;
2439         struct jme_adapter *jme = netdev_priv(netdev);
2440         struct mii_ioctl_data *mii_data = if_mii(rq);
2441         unsigned int duplex_chg;
2442
2443         if (cmd == SIOCSMIIREG) {
2444                 u16 val = mii_data->val_in;
2445                 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2446                     (val & BMCR_SPEED1000))
2447                         return -EINVAL;
2448         }
2449
2450         spin_lock_bh(&jme->phy_lock);
2451         rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2452         spin_unlock_bh(&jme->phy_lock);
2453
2454         if (!rc && (cmd == SIOCSMIIREG)) {
2455                 if (duplex_chg)
2456                         jme_reset_link(jme);
2457                 jme_get_settings(netdev, &jme->old_ecmd);
2458                 set_bit(JME_FLAG_SSET, &jme->flags);
2459         }
2460
2461         return rc;
2462 }
2463
2464 static u32
2465 jme_get_link(struct net_device *netdev)
2466 {
2467         struct jme_adapter *jme = netdev_priv(netdev);
2468         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2469 }
2470
2471 static u32
2472 jme_get_msglevel(struct net_device *netdev)
2473 {
2474         struct jme_adapter *jme = netdev_priv(netdev);
2475         return jme->msg_enable;
2476 }
2477
2478 static void
2479 jme_set_msglevel(struct net_device *netdev, u32 value)
2480 {
2481         struct jme_adapter *jme = netdev_priv(netdev);
2482         jme->msg_enable = value;
2483 }
2484
2485 static u32
2486 jme_get_rx_csum(struct net_device *netdev)
2487 {
2488         struct jme_adapter *jme = netdev_priv(netdev);
2489         return jme->reg_rxmcs & RXMCS_CHECKSUM;
2490 }
2491
2492 static int
2493 jme_set_rx_csum(struct net_device *netdev, u32 on)
2494 {
2495         struct jme_adapter *jme = netdev_priv(netdev);
2496
2497         spin_lock_bh(&jme->rxmcs_lock);
2498         if (on)
2499                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2500         else
2501                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2502         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2503         spin_unlock_bh(&jme->rxmcs_lock);
2504
2505         return 0;
2506 }
2507
2508 static int
2509 jme_set_tx_csum(struct net_device *netdev, u32 on)
2510 {
2511         struct jme_adapter *jme = netdev_priv(netdev);
2512
2513         if (on) {
2514                 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2515                 if (netdev->mtu <= 1900)
2516                         netdev->features |=
2517                                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2518         } else {
2519                 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2520                 netdev->features &=
2521                                 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2522         }
2523
2524         return 0;
2525 }
2526
2527 static int
2528 jme_set_tso(struct net_device *netdev, u32 on)
2529 {
2530         struct jme_adapter *jme = netdev_priv(netdev);
2531
2532         if (on) {
2533                 set_bit(JME_FLAG_TSO, &jme->flags);
2534                 if (netdev->mtu <= 1900)
2535                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2536         } else {
2537                 clear_bit(JME_FLAG_TSO, &jme->flags);
2538                 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2539         }
2540
2541         return 0;
2542 }
2543
2544 static int
2545 jme_nway_reset(struct net_device *netdev)
2546 {
2547         struct jme_adapter *jme = netdev_priv(netdev);
2548         jme_restart_an(jme);
2549         return 0;
2550 }
2551
2552 static u8
2553 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2554 {
2555         u32 val;
2556         int to;
2557
2558         val = jread32(jme, JME_SMBCSR);
2559         to = JME_SMB_BUSY_TIMEOUT;
2560         while ((val & SMBCSR_BUSY) && --to) {
2561                 msleep(1);
2562                 val = jread32(jme, JME_SMBCSR);
2563         }
2564         if (!to) {
2565                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2566                 return 0xFF;
2567         }
2568
2569         jwrite32(jme, JME_SMBINTF,
2570                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2571                 SMBINTF_HWRWN_READ |
2572                 SMBINTF_HWCMD);
2573
2574         val = jread32(jme, JME_SMBINTF);
2575         to = JME_SMB_BUSY_TIMEOUT;
2576         while ((val & SMBINTF_HWCMD) && --to) {
2577                 msleep(1);
2578                 val = jread32(jme, JME_SMBINTF);
2579         }
2580         if (!to) {
2581                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2582                 return 0xFF;
2583         }
2584
2585         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2586 }
2587
2588 static void
2589 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2590 {
2591         u32 val;
2592         int to;
2593
2594         val = jread32(jme, JME_SMBCSR);
2595         to = JME_SMB_BUSY_TIMEOUT;
2596         while ((val & SMBCSR_BUSY) && --to) {
2597                 msleep(1);
2598                 val = jread32(jme, JME_SMBCSR);
2599         }
2600         if (!to) {
2601                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2602                 return;
2603         }
2604
2605         jwrite32(jme, JME_SMBINTF,
2606                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2607                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2608                 SMBINTF_HWRWN_WRITE |
2609                 SMBINTF_HWCMD);
2610
2611         val = jread32(jme, JME_SMBINTF);
2612         to = JME_SMB_BUSY_TIMEOUT;
2613         while ((val & SMBINTF_HWCMD) && --to) {
2614                 msleep(1);
2615                 val = jread32(jme, JME_SMBINTF);
2616         }
2617         if (!to) {
2618                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2619                 return;
2620         }
2621
2622         mdelay(2);
2623 }
2624
2625 static int
2626 jme_get_eeprom_len(struct net_device *netdev)
2627 {
2628         struct jme_adapter *jme = netdev_priv(netdev);
2629         u32 val;
2630         val = jread32(jme, JME_SMBCSR);
2631         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2632 }
2633
2634 static int
2635 jme_get_eeprom(struct net_device *netdev,
2636                 struct ethtool_eeprom *eeprom, u8 *data)
2637 {
2638         struct jme_adapter *jme = netdev_priv(netdev);
2639         int i, offset = eeprom->offset, len = eeprom->len;
2640
2641         /*
2642          * ethtool will check the boundary for us
2643          */
2644         eeprom->magic = JME_EEPROM_MAGIC;
2645         for (i = 0 ; i < len ; ++i)
2646                 data[i] = jme_smb_read(jme, i + offset);
2647
2648         return 0;
2649 }
2650
2651 static int
2652 jme_set_eeprom(struct net_device *netdev,
2653                 struct ethtool_eeprom *eeprom, u8 *data)
2654 {
2655         struct jme_adapter *jme = netdev_priv(netdev);
2656         int i, offset = eeprom->offset, len = eeprom->len;
2657
2658         if (eeprom->magic != JME_EEPROM_MAGIC)
2659                 return -EINVAL;
2660
2661         /*
2662          * ethtool will check the boundary for us
2663          */
2664         for (i = 0 ; i < len ; ++i)
2665                 jme_smb_write(jme, i + offset, data[i]);
2666
2667         return 0;
2668 }
2669
2670 static const struct ethtool_ops jme_ethtool_ops = {
2671         .get_drvinfo            = jme_get_drvinfo,
2672         .get_regs_len           = jme_get_regs_len,
2673         .get_regs               = jme_get_regs,
2674         .get_coalesce           = jme_get_coalesce,
2675         .set_coalesce           = jme_set_coalesce,
2676         .get_pauseparam         = jme_get_pauseparam,
2677         .set_pauseparam         = jme_set_pauseparam,
2678         .get_wol                = jme_get_wol,
2679         .set_wol                = jme_set_wol,
2680         .get_settings           = jme_get_settings,
2681         .set_settings           = jme_set_settings,
2682         .get_link               = jme_get_link,
2683         .get_msglevel           = jme_get_msglevel,
2684         .set_msglevel           = jme_set_msglevel,
2685         .get_rx_csum            = jme_get_rx_csum,
2686         .set_rx_csum            = jme_set_rx_csum,
2687         .set_tx_csum            = jme_set_tx_csum,
2688         .set_tso                = jme_set_tso,
2689         .set_sg                 = ethtool_op_set_sg,
2690         .nway_reset             = jme_nway_reset,
2691         .get_eeprom_len         = jme_get_eeprom_len,
2692         .get_eeprom             = jme_get_eeprom,
2693         .set_eeprom             = jme_set_eeprom,
2694 };
2695
2696 static int
2697 jme_pci_dma64(struct pci_dev *pdev)
2698 {
2699         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2700             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2701                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2702                         return 1;
2703
2704         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2705             !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2706                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2707                         return 1;
2708
2709         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2710                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2711                         return 0;
2712
2713         return -1;
2714 }
2715
2716 static inline void
2717 jme_phy_init(struct jme_adapter *jme)
2718 {
2719         u16 reg26;
2720
2721         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2722         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2723 }
2724
2725 static inline void
2726 jme_check_hw_ver(struct jme_adapter *jme)
2727 {
2728         u32 chipmode;
2729
2730         chipmode = jread32(jme, JME_CHIPMODE);
2731
2732         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2733         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2734 }
2735
2736 static const struct net_device_ops jme_netdev_ops = {
2737         .ndo_open               = jme_open,
2738         .ndo_stop               = jme_close,
2739         .ndo_validate_addr      = eth_validate_addr,
2740         .ndo_do_ioctl           = jme_ioctl,
2741         .ndo_start_xmit         = jme_start_xmit,
2742         .ndo_set_mac_address    = jme_set_macaddr,
2743         .ndo_set_multicast_list = jme_set_multi,
2744         .ndo_change_mtu         = jme_change_mtu,
2745         .ndo_tx_timeout         = jme_tx_timeout,
2746         .ndo_vlan_rx_register   = jme_vlan_rx_register,
2747 };
2748
2749 static int __devinit
2750 jme_init_one(struct pci_dev *pdev,
2751              const struct pci_device_id *ent)
2752 {
2753         int rc = 0, using_dac, i;
2754         struct net_device *netdev;
2755         struct jme_adapter *jme;
2756         u16 bmcr, bmsr;
2757         u32 apmc;
2758
2759         /*
2760          * set up PCI device basics
2761          */
2762         rc = pci_enable_device(pdev);
2763         if (rc) {
2764                 pr_err("Cannot enable PCI device\n");
2765                 goto err_out;
2766         }
2767
2768         using_dac = jme_pci_dma64(pdev);
2769         if (using_dac < 0) {
2770                 pr_err("Cannot set PCI DMA Mask\n");
2771                 rc = -EIO;
2772                 goto err_out_disable_pdev;
2773         }
2774
2775         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2776                 pr_err("No PCI resource region found\n");
2777                 rc = -ENOMEM;
2778                 goto err_out_disable_pdev;
2779         }
2780
2781         rc = pci_request_regions(pdev, DRV_NAME);
2782         if (rc) {
2783                 pr_err("Cannot obtain PCI resource region\n");
2784                 goto err_out_disable_pdev;
2785         }
2786
2787         pci_set_master(pdev);
2788
2789         /*
2790          * alloc and init net device
2791          */
2792         netdev = alloc_etherdev(sizeof(*jme));
2793         if (!netdev) {
2794                 pr_err("Cannot allocate netdev structure\n");
2795                 rc = -ENOMEM;
2796                 goto err_out_release_regions;
2797         }
2798         netdev->netdev_ops = &jme_netdev_ops;
2799         netdev->ethtool_ops             = &jme_ethtool_ops;
2800         netdev->watchdog_timeo          = TX_TIMEOUT;
2801         netdev->features                =       NETIF_F_IP_CSUM |
2802                                                 NETIF_F_IPV6_CSUM |
2803                                                 NETIF_F_SG |
2804                                                 NETIF_F_TSO |
2805                                                 NETIF_F_TSO6 |
2806                                                 NETIF_F_HW_VLAN_TX |
2807                                                 NETIF_F_HW_VLAN_RX;
2808         if (using_dac)
2809                 netdev->features        |=      NETIF_F_HIGHDMA;
2810
2811         SET_NETDEV_DEV(netdev, &pdev->dev);
2812         pci_set_drvdata(pdev, netdev);
2813
2814         /*
2815          * init adapter info
2816          */
2817         jme = netdev_priv(netdev);
2818         jme->pdev = pdev;
2819         jme->dev = netdev;
2820         jme->jme_rx = netif_rx;
2821         jme->jme_vlan_rx = vlan_hwaccel_rx;
2822         jme->old_mtu = netdev->mtu = 1500;
2823         jme->phylink = 0;
2824         jme->tx_ring_size = 1 << 10;
2825         jme->tx_ring_mask = jme->tx_ring_size - 1;
2826         jme->tx_wake_threshold = 1 << 9;
2827         jme->rx_ring_size = 1 << 9;
2828         jme->rx_ring_mask = jme->rx_ring_size - 1;
2829         jme->msg_enable = JME_DEF_MSG_ENABLE;
2830         jme->regs = ioremap(pci_resource_start(pdev, 0),
2831                              pci_resource_len(pdev, 0));
2832         if (!(jme->regs)) {
2833                 pr_err("Mapping PCI resource region error\n");
2834                 rc = -ENOMEM;
2835                 goto err_out_free_netdev;
2836         }
2837
2838         if (no_pseudohp) {
2839                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2840                 jwrite32(jme, JME_APMC, apmc);
2841         } else if (force_pseudohp) {
2842                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2843                 jwrite32(jme, JME_APMC, apmc);
2844         }
2845
2846         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2847
2848         spin_lock_init(&jme->phy_lock);
2849         spin_lock_init(&jme->macaddr_lock);
2850         spin_lock_init(&jme->rxmcs_lock);
2851
2852         atomic_set(&jme->link_changing, 1);
2853         atomic_set(&jme->rx_cleaning, 1);
2854         atomic_set(&jme->tx_cleaning, 1);
2855         atomic_set(&jme->rx_empty, 1);
2856
2857         tasklet_init(&jme->pcc_task,
2858                      jme_pcc_tasklet,
2859                      (unsigned long) jme);
2860         tasklet_init(&jme->linkch_task,
2861                      jme_link_change_tasklet,
2862                      (unsigned long) jme);
2863         tasklet_init(&jme->txclean_task,
2864                      jme_tx_clean_tasklet,
2865                      (unsigned long) jme);
2866         tasklet_init(&jme->rxclean_task,
2867                      jme_rx_clean_tasklet,
2868                      (unsigned long) jme);
2869         tasklet_init(&jme->rxempty_task,
2870                      jme_rx_empty_tasklet,
2871                      (unsigned long) jme);
2872         tasklet_disable_nosync(&jme->linkch_task);
2873         tasklet_disable_nosync(&jme->txclean_task);
2874         tasklet_disable_nosync(&jme->rxclean_task);
2875         tasklet_disable_nosync(&jme->rxempty_task);
2876         jme->dpi.cur = PCC_P1;
2877
2878         jme->reg_ghc = 0;
2879         jme->reg_rxcs = RXCS_DEFAULT;
2880         jme->reg_rxmcs = RXMCS_DEFAULT;
2881         jme->reg_txpfc = 0;
2882         jme->reg_pmcs = PMCS_MFEN;
2883         set_bit(JME_FLAG_TXCSUM, &jme->flags);
2884         set_bit(JME_FLAG_TSO, &jme->flags);
2885
2886         /*
2887          * Get Max Read Req Size from PCI Config Space
2888          */
2889         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2890         jme->mrrs &= PCI_DCSR_MRRS_MASK;
2891         switch (jme->mrrs) {
2892         case MRRS_128B:
2893                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2894                 break;
2895         case MRRS_256B:
2896                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2897                 break;
2898         default:
2899                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2900                 break;
2901         }
2902
2903         /*
2904          * Must check before reset_mac_processor
2905          */
2906         jme_check_hw_ver(jme);
2907         jme->mii_if.dev = netdev;
2908         if (jme->fpgaver) {
2909                 jme->mii_if.phy_id = 0;
2910                 for (i = 1 ; i < 32 ; ++i) {
2911                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2912                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2913                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2914                                 jme->mii_if.phy_id = i;
2915                                 break;
2916                         }
2917                 }
2918
2919                 if (!jme->mii_if.phy_id) {
2920                         rc = -EIO;
2921                         pr_err("Can not find phy_id\n");
2922                         goto err_out_unmap;
2923                 }
2924
2925                 jme->reg_ghc |= GHC_LINK_POLL;
2926         } else {
2927                 jme->mii_if.phy_id = 1;
2928         }
2929         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2930                 jme->mii_if.supports_gmii = true;
2931         else
2932                 jme->mii_if.supports_gmii = false;
2933         jme->mii_if.phy_id_mask = 0x1F;
2934         jme->mii_if.reg_num_mask = 0x1F;
2935         jme->mii_if.mdio_read = jme_mdio_read;
2936         jme->mii_if.mdio_write = jme_mdio_write;
2937
2938         jme_clear_pm(jme);
2939         jme_set_phyfifoa(jme);
2940         pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2941         if (!jme->fpgaver)
2942                 jme_phy_init(jme);
2943         jme_phy_off(jme);
2944
2945         /*
2946          * Reset MAC processor and reload EEPROM for MAC Address
2947          */
2948         jme_reset_mac_processor(jme);
2949         rc = jme_reload_eeprom(jme);
2950         if (rc) {
2951                 pr_err("Reload eeprom for reading MAC Address error\n");
2952                 goto err_out_unmap;
2953         }
2954         jme_load_macaddr(netdev);
2955
2956         /*
2957          * Tell stack that we are not ready to work until open()
2958          */
2959         netif_carrier_off(netdev);
2960
2961         rc = register_netdev(netdev);
2962         if (rc) {
2963                 pr_err("Cannot register net device\n");
2964                 goto err_out_unmap;
2965         }
2966
2967         netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2968                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2969                    "JMC250 Gigabit Ethernet" :
2970                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2971                    "JMC260 Fast Ethernet" : "Unknown",
2972                    (jme->fpgaver != 0) ? " (FPGA)" : "",
2973                    (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2974                    jme->rev, netdev->dev_addr);
2975
2976         return 0;
2977
2978 err_out_unmap:
2979         iounmap(jme->regs);
2980 err_out_free_netdev:
2981         pci_set_drvdata(pdev, NULL);
2982         free_netdev(netdev);
2983 err_out_release_regions:
2984         pci_release_regions(pdev);
2985 err_out_disable_pdev:
2986         pci_disable_device(pdev);
2987 err_out:
2988         return rc;
2989 }
2990
2991 static void __devexit
2992 jme_remove_one(struct pci_dev *pdev)
2993 {
2994         struct net_device *netdev = pci_get_drvdata(pdev);
2995         struct jme_adapter *jme = netdev_priv(netdev);
2996
2997         unregister_netdev(netdev);
2998         iounmap(jme->regs);
2999         pci_set_drvdata(pdev, NULL);
3000         free_netdev(netdev);
3001         pci_release_regions(pdev);
3002         pci_disable_device(pdev);
3003
3004 }
3005
3006 static void
3007 jme_shutdown(struct pci_dev *pdev)
3008 {
3009         struct net_device *netdev = pci_get_drvdata(pdev);
3010         struct jme_adapter *jme = netdev_priv(netdev);
3011
3012         jme_powersave_phy(jme);
3013         pci_pme_active(pdev, true);
3014 }
3015
3016 #ifdef CONFIG_PM
3017 static int
3018 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3019 {
3020         struct net_device *netdev = pci_get_drvdata(pdev);
3021         struct jme_adapter *jme = netdev_priv(netdev);
3022
3023         atomic_dec(&jme->link_changing);
3024
3025         netif_device_detach(netdev);
3026         netif_stop_queue(netdev);
3027         jme_stop_irq(jme);
3028
3029         tasklet_disable(&jme->txclean_task);
3030         tasklet_disable(&jme->rxclean_task);
3031         tasklet_disable(&jme->rxempty_task);
3032
3033         if (netif_carrier_ok(netdev)) {
3034                 if (test_bit(JME_FLAG_POLL, &jme->flags))
3035                         jme_polling_mode(jme);
3036
3037                 jme_stop_pcc_timer(jme);
3038                 jme_reset_ghc_speed(jme);
3039                 jme_disable_rx_engine(jme);
3040                 jme_disable_tx_engine(jme);
3041                 jme_reset_mac_processor(jme);
3042                 jme_free_rx_resources(jme);
3043                 jme_free_tx_resources(jme);
3044                 netif_carrier_off(netdev);
3045                 jme->phylink = 0;
3046         }
3047
3048         tasklet_enable(&jme->txclean_task);
3049         tasklet_hi_enable(&jme->rxclean_task);
3050         tasklet_hi_enable(&jme->rxempty_task);
3051
3052         pci_save_state(pdev);
3053         jme_powersave_phy(jme);
3054         pci_enable_wake(jme->pdev, PCI_D3hot, true);
3055         pci_set_power_state(pdev, PCI_D3hot);
3056
3057         return 0;
3058 }
3059
3060 static int
3061 jme_resume(struct pci_dev *pdev)
3062 {
3063         struct net_device *netdev = pci_get_drvdata(pdev);
3064         struct jme_adapter *jme = netdev_priv(netdev);
3065
3066         jme_clear_pm(jme);
3067         pci_restore_state(pdev);
3068
3069         if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3070                 jme_phy_on(jme);
3071                 jme_set_settings(netdev, &jme->old_ecmd);
3072         } else {
3073                 jme_reset_phy_processor(jme);
3074         }
3075
3076         jme_start_irq(jme);
3077         netif_device_attach(netdev);
3078
3079         atomic_inc(&jme->link_changing);
3080
3081         jme_reset_link(jme);
3082
3083         return 0;
3084 }
3085 #endif
3086
3087 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3088         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3089         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3090         { }
3091 };
3092
3093 static struct pci_driver jme_driver = {
3094         .name           = DRV_NAME,
3095         .id_table       = jme_pci_tbl,
3096         .probe          = jme_init_one,
3097         .remove         = __devexit_p(jme_remove_one),
3098 #ifdef CONFIG_PM
3099         .suspend        = jme_suspend,
3100         .resume         = jme_resume,
3101 #endif /* CONFIG_PM */
3102         .shutdown       = jme_shutdown,
3103 };
3104
3105 static int __init
3106 jme_init_module(void)
3107 {
3108         pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3109         return pci_register_driver(&jme_driver);
3110 }
3111
3112 static void __exit
3113 jme_cleanup_module(void)
3114 {
3115         pci_unregister_driver(&jme_driver);
3116 }
3117
3118 module_init(jme_init_module);
3119 module_exit(jme_cleanup_module);
3120
3121 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3122 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3123 MODULE_LICENSE("GPL");
3124 MODULE_VERSION(DRV_VERSION);
3125 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3126