2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 * Along with multiple RX queue, for CPU load balancing.
28 * - Decode register dump for ethtool.
30 * PCC Support Both Packet Counter and Timeout Interrupt for
31 * receive and transmit complete, does NAPI really needed?
34 #include <linux/version.h>
35 #include <linux/module.h>
36 #include <linux/kernel.h>
37 #include <linux/pci.h>
38 #include <linux/netdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/crc32.h>
43 #include <linux/delay.h>
44 #include <linux/spinlock.h>
47 #include <linux/ipv6.h>
48 #include <linux/tcp.h>
49 #include <linux/udp.h>
50 #include <linux/if_vlan.h>
53 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
54 static struct net_device_stats *
55 jme_get_stats(struct net_device *netdev)
57 struct jme_adapter *jme = netdev_priv(netdev);
63 jme_mdio_read(struct net_device *netdev, int phy, int reg)
65 struct jme_adapter *jme = netdev_priv(netdev);
68 jwrite32(jme, JME_SMI, SMI_OP_REQ |
73 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
75 val = jread32(jme, JME_SMI);
76 if ((val & SMI_OP_REQ) == 0)
81 jeprintk(netdev->name, "phy read timeout : %d\n", reg);
85 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
89 jme_mdio_write(struct net_device *netdev,
90 int phy, int reg, int val)
92 struct jme_adapter *jme = netdev_priv(netdev);
95 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
96 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
97 smi_phy_addr(phy) | smi_reg_addr(reg));
100 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
102 val = jread32(jme, JME_SMI);
103 if ((val & SMI_OP_REQ) == 0)
108 jeprintk(netdev->name, "phy write timeout : %d\n", reg);
113 __always_inline static void
114 jme_reset_phy_processor(struct jme_adapter *jme)
118 jme_mdio_write(jme->dev,
120 MII_ADVERTISE, ADVERTISE_ALL |
121 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
123 jme_mdio_write(jme->dev,
126 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
128 val = jme_mdio_read(jme->dev,
132 jme_mdio_write(jme->dev,
134 MII_BMCR, val | BMCR_RESET);
140 jme_setup_wakeup_frame(struct jme_adapter *jme,
141 __u32 *mask, __u32 crc, int fnr)
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
150 jwrite32(jme, JME_WFODP, crc);
156 for(i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
161 jwrite32(jme, JME_WFODP, mask[i]);
166 __always_inline static void
167 jme_reset_mac_processor(struct jme_adapter *jme)
169 __u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0,0,0,0};
170 __u32 crc = 0xCDCDCDCD;
173 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
175 jwrite32(jme, JME_GHC, jme->reg_ghc);
176 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
177 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
178 for(i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
179 jme_setup_wakeup_frame(jme, mask, crc, i);
180 jwrite32(jme, JME_GPREG0, GPREG0_DEFAULT);
181 jwrite32(jme, JME_GPREG1, 0);
184 __always_inline static void
185 jme_clear_pm(struct jme_adapter *jme)
187 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
188 pci_set_power_state(jme->pdev, PCI_D0);
189 pci_enable_wake(jme->pdev, PCI_D0, false);
193 jme_reload_eeprom(struct jme_adapter *jme)
198 val = jread32(jme, JME_SMBCSR);
200 if(val & SMBCSR_EEPROMD)
203 jwrite32(jme, JME_SMBCSR, val);
204 val |= SMBCSR_RELOAD;
205 jwrite32(jme, JME_SMBCSR, val);
208 for (i = JME_SMB_TIMEOUT; i > 0; --i)
211 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
216 jeprintk(jme->dev->name, "eeprom reload timeout\n");
227 jme_load_macaddr(struct net_device *netdev)
229 struct jme_adapter *jme = netdev_priv(netdev);
230 unsigned char macaddr[6];
233 spin_lock(&jme->macaddr_lock);
234 val = jread32(jme, JME_RXUMA_LO);
235 macaddr[0] = (val >> 0) & 0xFF;
236 macaddr[1] = (val >> 8) & 0xFF;
237 macaddr[2] = (val >> 16) & 0xFF;
238 macaddr[3] = (val >> 24) & 0xFF;
239 val = jread32(jme, JME_RXUMA_HI);
240 macaddr[4] = (val >> 0) & 0xFF;
241 macaddr[5] = (val >> 8) & 0xFF;
242 memcpy(netdev->dev_addr, macaddr, 6);
243 spin_unlock(&jme->macaddr_lock);
246 __always_inline static void
247 jme_set_rx_pcc(struct jme_adapter *jme, int p)
251 jwrite32(jme, JME_PCCRX0,
252 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
253 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
256 jwrite32(jme, JME_PCCRX0,
257 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
258 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
261 jwrite32(jme, JME_PCCRX0,
262 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
263 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
273 jme_start_irq(struct jme_adapter *jme)
275 register struct dynpcc_info *dpi = &(jme->dpi);
277 jme_set_rx_pcc(jme, PCC_P1);
279 dpi->attempt = PCC_P1;
282 jwrite32(jme, JME_PCCTX,
283 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
284 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
291 jwrite32(jme, JME_IENS, INTR_ENABLE);
294 __always_inline static void
295 jme_stop_irq(struct jme_adapter *jme)
300 jwrite32(jme, JME_IENC, INTR_ENABLE);
304 __always_inline static void
305 jme_enable_shadow(struct jme_adapter *jme)
309 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
312 __always_inline static void
313 jme_disable_shadow(struct jme_adapter *jme)
315 jwrite32(jme, JME_SHBA_LO, 0x0);
319 jme_check_link(struct net_device *netdev, int testonly)
321 struct jme_adapter *jme = netdev_priv(netdev);
322 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
327 phylink = jread32(jme, JME_PHY_LINK);
329 if (phylink & PHY_LINK_UP) {
330 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
332 * If we did not enable AN
333 * Speed/Duplex Info should be obtained from SMI
335 phylink = PHY_LINK_UP;
337 bmcr = jme_mdio_read(jme->dev,
342 phylink |= ((bmcr & BMCR_SPEED1000) &&
343 (bmcr & BMCR_SPEED100) == 0) ?
344 PHY_LINK_SPEED_1000M :
345 (bmcr & BMCR_SPEED100) ?
346 PHY_LINK_SPEED_100M :
349 phylink |= (bmcr & BMCR_FULLDPLX) ?
352 strcat(linkmsg, "Forced: ");
356 * Keep polling for speed/duplex resolve complete
358 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
362 phylink = jread32(jme, JME_PHY_LINK);
367 jeprintk(netdev->name,
368 "Waiting speed resolve timeout.\n");
370 strcat(linkmsg, "ANed: ");
373 if(jme->phylink == phylink) {
380 jme->phylink = phylink;
382 switch(phylink & PHY_LINK_SPEED_MASK) {
383 case PHY_LINK_SPEED_10M:
385 strcat(linkmsg, "10 Mbps, ");
387 case PHY_LINK_SPEED_100M:
388 ghc = GHC_SPEED_100M;
389 strcat(linkmsg, "100 Mbps, ");
391 case PHY_LINK_SPEED_1000M:
392 ghc = GHC_SPEED_1000M;
393 strcat(linkmsg, "1000 Mbps, ");
399 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
401 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
405 if(phylink & PHY_LINK_MDI_STAT)
406 strcat(linkmsg, "MDI-X");
408 strcat(linkmsg, "MDI");
410 if(phylink & PHY_LINK_DUPLEX)
411 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
413 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
417 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
418 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
420 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
424 jwrite32(jme, JME_GHC, ghc);
426 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
427 netif_carrier_on(netdev);
433 jprintk(netdev->name, "Link is down.\n");
435 netif_carrier_off(netdev);
443 jme_setup_tx_resources(struct jme_adapter *jme)
445 struct jme_ring *txring = &(jme->txring[0]);
447 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
448 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
454 txring->dmaalloc = 0;
462 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
464 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
465 txring->next_to_use = 0;
466 txring->next_to_clean = 0;
467 atomic_set(&txring->nr_free, jme->tx_ring_size);
470 * Initialize Transmit Descriptors
472 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
473 memset(txring->bufinf, 0,
474 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
480 jme_free_tx_resources(struct jme_adapter *jme)
483 struct jme_ring *txring = &(jme->txring[0]);
484 struct jme_buffer_info *txbi = txring->bufinf;
487 for(i = 0 ; i < jme->tx_ring_size ; ++i) {
488 txbi = txring->bufinf + i;
490 dev_kfree_skb(txbi->skb);
498 dma_free_coherent(&(jme->pdev->dev),
499 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
503 txring->alloc = NULL;
505 txring->dmaalloc = 0;
508 txring->next_to_use = 0;
509 txring->next_to_clean = 0;
510 atomic_set(&txring->nr_free, 0);
514 __always_inline static void
515 jme_enable_tx_engine(struct jme_adapter *jme)
520 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
523 * Setup TX Queue 0 DMA Bass Address
525 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
526 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
527 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
530 * Setup TX Descptor Count
532 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
538 jwrite32(jme, JME_TXCS, jme->reg_txcs |
544 __always_inline static void
545 jme_restart_tx_engine(struct jme_adapter *jme)
550 jwrite32(jme, JME_TXCS, jme->reg_txcs |
555 __always_inline static void
556 jme_disable_tx_engine(struct jme_adapter *jme)
564 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
566 val = jread32(jme, JME_TXCS);
567 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
570 val = jread32(jme, JME_TXCS);
574 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
575 jme_reset_mac_processor(jme);
582 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
584 struct jme_ring *rxring = jme->rxring;
585 register volatile struct rxdesc* rxdesc = rxring->desc;
586 struct jme_buffer_info *rxbi = rxring->bufinf;
592 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
593 rxdesc->desc1.bufaddrl = cpu_to_le32(
594 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
595 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
596 if(jme->dev->features & NETIF_F_HIGHDMA)
597 rxdesc->desc1.flags = RXFLAG_64BIT;
599 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
603 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
605 struct jme_ring *rxring = &(jme->rxring[0]);
606 struct jme_buffer_info *rxbi = rxring->bufinf + i;
607 unsigned long offset;
610 skb = netdev_alloc_skb(jme->dev,
611 jme->dev->mtu + RX_EXTRA_LEN);
616 (unsigned long)(skb->data)
617 & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
618 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
621 rxbi->len = skb_tailroom(skb);
622 rxbi->mapping = pci_map_page(jme->pdev,
623 virt_to_page(skb->data),
624 offset_in_page(skb->data),
632 jme_free_rx_buf(struct jme_adapter *jme, int i)
634 struct jme_ring *rxring = &(jme->rxring[0]);
635 struct jme_buffer_info *rxbi = rxring->bufinf;
639 pci_unmap_page(jme->pdev,
643 dev_kfree_skb(rxbi->skb);
651 jme_free_rx_resources(struct jme_adapter *jme)
654 struct jme_ring *rxring = &(jme->rxring[0]);
657 for(i = 0 ; i < jme->rx_ring_size ; ++i)
658 jme_free_rx_buf(jme, i);
660 dma_free_coherent(&(jme->pdev->dev),
661 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
664 rxring->alloc = NULL;
666 rxring->dmaalloc = 0;
669 rxring->next_to_use = 0;
670 rxring->next_to_clean = 0;
674 jme_setup_rx_resources(struct jme_adapter *jme)
677 struct jme_ring *rxring = &(jme->rxring[0]);
679 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
680 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
685 rxring->dmaalloc = 0;
693 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
695 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
696 rxring->next_to_use = 0;
697 rxring->next_to_clean = 0;
700 * Initiallize Receive Descriptors
702 for(i = 0 ; i < jme->rx_ring_size ; ++i) {
703 if(unlikely(jme_make_new_rx_buf(jme, i))) {
704 jme_free_rx_resources(jme);
708 jme_set_clean_rxdesc(jme, i);
714 __always_inline static void
715 jme_enable_rx_engine(struct jme_adapter *jme)
718 * Setup RX DMA Bass Address
720 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
721 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
722 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
725 * Setup RX Descriptor Count
727 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
730 * Setup Unicast Filter
732 jme_set_multi(jme->dev);
738 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
744 __always_inline static void
745 jme_restart_rx_engine(struct jme_adapter *jme)
750 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
757 __always_inline static void
758 jme_disable_rx_engine(struct jme_adapter *jme)
766 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
768 val = jread32(jme, JME_RXCS);
769 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
772 val = jread32(jme, JME_RXCS);
776 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
781 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
783 struct jme_ring *rxring = &(jme->rxring[0]);
784 volatile struct rxdesc *rxdesc = rxring->desc;
785 struct jme_buffer_info *rxbi = rxring->bufinf;
793 pci_dma_sync_single_for_cpu(jme->pdev,
798 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
799 pci_dma_sync_single_for_device(jme->pdev,
804 ++(NET_STAT(jme).rx_dropped);
807 framesize = le16_to_cpu(rxdesc->descwb.framesize)
810 skb_reserve(skb, RX_PREPAD_SIZE);
811 skb_put(skb, framesize);
812 skb->protocol = eth_type_trans(skb, jme->dev);
814 if((rxdesc->descwb.flags &
818 skb->ip_summed = CHECKSUM_UNNECESSARY;
820 skb->ip_summed = CHECKSUM_NONE;
823 if(rxdesc->descwb.flags & RXWBFLAG_TAGON) {
824 vlan_dbg(jme->dev->name, "VLAN: %04x\n",
825 rxdesc->descwb.vlan);
827 vlan_dbg(jme->dev->name,
828 "VLAN Passed to kernel.\n");
829 vlan_hwaccel_rx(skb, jme->vlgrp,
830 le32_to_cpu(rxdesc->descwb.vlan));
831 NET_STAT(jme).rx_bytes += 4;
838 if((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
840 ++(NET_STAT(jme).multicast);
842 jme->dev->last_rx = jiffies;
843 NET_STAT(jme).rx_bytes += framesize;
844 ++(NET_STAT(jme).rx_packets);
847 jme_set_clean_rxdesc(jme, idx);
852 jme_rxsum_bad(struct jme_adapter *jme, __u16 flags)
854 if(unlikely((flags & RXWBFLAG_TCPON) &&
855 !(flags & RXWBFLAG_TCPCS))) {
856 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
859 else if(unlikely((flags & RXWBFLAG_UDPON) &&
860 !(flags & RXWBFLAG_UDPCS))) {
861 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
864 else if(unlikely((flags & RXWBFLAG_IPV4) &&
865 !(flags & RXWBFLAG_IPCS))) {
866 csum_dbg(jme->dev->name, "IPv4 Checksum error.\n");
875 jme_process_receive(struct jme_adapter *jme, int limit)
877 struct jme_ring *rxring = &(jme->rxring[0]);
878 volatile struct rxdesc *rxdesc = rxring->desc;
879 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
881 i = rxring->next_to_clean;
884 rxdesc = rxring->desc;
887 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
888 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
891 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
893 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
895 if(unlikely(desccnt > 1 ||
896 rxdesc->descwb.errstat & RXWBERR_ALLERR ||
897 jme_rxsum_bad(jme, rxdesc->descwb.flags))) {
899 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
900 ++(NET_STAT(jme).rx_crc_errors);
901 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
902 ++(NET_STAT(jme).rx_fifo_errors);
904 ++(NET_STAT(jme).rx_errors);
907 rx_dbg(jme->dev->name,
908 "RX: More than one(%d) descriptor, "
910 desccnt, le16_to_cpu(rxdesc->descwb.framesize));
911 limit -= desccnt - 1;
914 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
915 jme_set_clean_rxdesc(jme, j);
917 j = (j + 1) & (mask);
922 jme_alloc_and_feed_skb(jme, i);
925 i = (i + desccnt) & (mask);
929 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
930 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
931 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
934 rxring->next_to_clean = i;
936 return limit > 0 ? limit : 0;
941 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
943 if(likely(atmp == dpi->cur))
946 if(dpi->attempt == atmp) {
957 jme_dynamic_pcc(struct jme_adapter *jme)
959 register struct dynpcc_info *dpi = &(jme->dpi);
961 if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
962 jme_attempt_pcc(dpi, PCC_P3);
963 else if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P2_THRESHOLD
964 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
965 jme_attempt_pcc(dpi, PCC_P2);
967 jme_attempt_pcc(dpi, PCC_P1);
969 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 20)) {
970 jme_set_rx_pcc(jme, dpi->attempt);
971 dpi->cur = dpi->attempt;
977 jme_start_pcc_timer(struct jme_adapter *jme)
979 struct dynpcc_info *dpi = &(jme->dpi);
980 dpi->last_bytes = NET_STAT(jme).rx_bytes;
981 dpi->last_pkts = NET_STAT(jme).rx_packets;
983 jwrite32(jme, JME_TMCSR,
984 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
988 jme_stop_pcc_timer(struct jme_adapter *jme)
990 jwrite32(jme, JME_TMCSR, 0);
994 jme_pcc_tasklet(unsigned long arg)
996 struct jme_adapter *jme = (struct jme_adapter*)arg;
997 struct net_device *netdev = jme->dev;
1000 if(unlikely(!netif_carrier_ok(netdev) ||
1001 (atomic_read(&jme->link_changing) != 1)
1003 jme_stop_pcc_timer(jme);
1007 jme_dynamic_pcc(jme);
1008 jme_start_pcc_timer(jme);
1012 jme_link_change_tasklet(unsigned long arg)
1014 struct jme_adapter *jme = (struct jme_adapter*)arg;
1015 struct net_device *netdev = jme->dev;
1016 int timeout = WAIT_TASKLET_TIMEOUT;
1019 if(!atomic_dec_and_test(&jme->link_changing))
1022 if(jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1025 jme->old_mtu = netdev->mtu;
1026 netif_stop_queue(netdev);
1028 while(--timeout > 0 &&
1030 atomic_read(&jme->rx_cleaning) != 1 ||
1031 atomic_read(&jme->tx_cleaning) != 1
1037 if(netif_carrier_ok(netdev)) {
1038 jme_stop_pcc_timer(jme);
1039 jme_reset_mac_processor(jme);
1040 jme_free_rx_resources(jme);
1041 jme_free_tx_resources(jme);
1044 jme_check_link(netdev, 0);
1045 if(netif_carrier_ok(netdev)) {
1046 rc = jme_setup_rx_resources(jme);
1048 jeprintk(netdev->name,
1049 "Allocating resources for RX error"
1050 ", Device STOPPED!\n");
1055 rc = jme_setup_tx_resources(jme);
1057 jeprintk(netdev->name,
1058 "Allocating resources for TX error"
1059 ", Device STOPPED!\n");
1060 goto err_out_free_rx_resources;
1063 jme_enable_rx_engine(jme);
1064 jme_enable_tx_engine(jme);
1066 netif_start_queue(netdev);
1067 jme_start_pcc_timer(jme);
1072 err_out_free_rx_resources:
1073 jme_free_rx_resources(jme);
1075 atomic_inc(&jme->link_changing);
1079 jme_rx_clean_tasklet(unsigned long arg)
1081 struct jme_adapter *jme = (struct jme_adapter*)arg;
1082 struct dynpcc_info *dpi = &(jme->dpi);
1084 if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1087 if(unlikely(atomic_read(&jme->link_changing) != 1))
1090 if(unlikely(!netif_carrier_ok(jme->dev)))
1093 jme_process_receive(jme, jme->rx_ring_size);
1097 atomic_inc(&jme->rx_cleaning);
1101 jme_rx_empty_tasklet(unsigned long arg)
1103 struct jme_adapter *jme = (struct jme_adapter*)arg;
1105 if(unlikely(atomic_read(&jme->link_changing) != 1))
1108 if(unlikely(!netif_carrier_ok(jme->dev)))
1111 queue_dbg(jme->dev->name, "RX Queue Full!\n");
1113 jme_rx_clean_tasklet(arg);
1114 jme_restart_rx_engine(jme);
1118 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1120 struct jme_ring *txring = jme->txring;
1123 if(unlikely(netif_queue_stopped(jme->dev) &&
1124 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1126 queue_dbg(jme->dev->name, "TX Queue Waked.\n");
1127 netif_wake_queue(jme->dev);
1134 jme_tx_clean_tasklet(unsigned long arg)
1136 struct jme_adapter *jme = (struct jme_adapter*)arg;
1137 struct jme_ring *txring = &(jme->txring[0]);
1138 volatile struct txdesc *txdesc = txring->desc;
1139 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1140 int i, j, cnt = 0, max, err, mask;
1142 if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1145 if(unlikely(atomic_read(&jme->link_changing) != 1))
1148 if(unlikely(!netif_carrier_ok(jme->dev)))
1151 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1152 mask = jme->tx_ring_mask;
1154 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1156 for(i = txring->next_to_clean ; cnt < max ; ) {
1160 if(likely(ctxbi->skb &&
1161 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1163 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1165 tx_dbg(jme->dev->name,
1166 "Tx Tasklet: Clean %d+%d\n",
1169 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
1170 ttxbi = txbi + ((i + j) & (mask));
1171 txdesc[(i + j) & (mask)].dw[0] = 0;
1173 pci_unmap_page(jme->pdev,
1182 dev_kfree_skb(ctxbi->skb);
1184 cnt += ctxbi->nr_desc;
1187 ++(NET_STAT(jme).tx_carrier_errors);
1189 ++(NET_STAT(jme).tx_packets);
1190 NET_STAT(jme).tx_bytes += ctxbi->len;
1198 tx_dbg(jme->dev->name,
1200 " Stopped due to no skb.\n");
1202 tx_dbg(jme->dev->name,
1204 "Stopped due to not done.\n");
1208 i = (i + ctxbi->nr_desc) & mask;
1213 tx_dbg(jme->dev->name,
1214 "Tx Tasklet: Stop %d Jiffies %lu\n",
1216 txring->next_to_clean = i;
1218 atomic_add(cnt, &txring->nr_free);
1220 jme_wake_queue_if_stopped(jme);
1223 atomic_inc(&jme->tx_cleaning);
1227 jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
1234 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1237 * Write 1 clear interrupt status
1239 jwrite32f(jme, JME_IEVE, intrstat);
1241 if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1242 tasklet_schedule(&jme->linkch_task);
1246 if(intrstat & INTR_TMINTR)
1247 tasklet_schedule(&jme->pcc_task);
1249 if(intrstat & INTR_RX0EMP)
1250 tasklet_schedule(&jme->rxempty_task);
1252 if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1253 tasklet_schedule(&jme->rxclean_task);
1255 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
1256 tasklet_schedule(&jme->txclean_task);
1258 handled = INTR_ENABLE | INTR_RX0 | INTR_TX0 | INTR_PAUSERCV;
1259 if((intrstat & ~(handled)) != 0) {
1261 * Some interrupt not handled
1262 * but not enabled also (for debug)
1264 dprintk(jme->dev->name,
1265 "UN-handled interrupt.(%08x)\n",
1266 intrstat & ~(handled));
1271 * Re-enable interrupt
1273 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1279 jme_intr(int irq, void *dev_id)
1281 struct net_device *netdev = dev_id;
1282 struct jme_adapter *jme = netdev_priv(netdev);
1285 intrstat = jread32(jme, JME_IEVE);
1288 * Check if it's really an interrupt for us
1290 if(unlikely(intrstat == 0))
1294 * Check if the device still exist
1296 if(unlikely(intrstat == ~((typeof(intrstat))0)))
1299 jme_intr_msi(jme, intrstat);
1305 jme_msi(int irq, void *dev_id)
1307 struct net_device *netdev = dev_id;
1308 struct jme_adapter *jme = netdev_priv(netdev);
1311 pci_dma_sync_single_for_cpu(jme->pdev,
1313 sizeof(__u32) * SHADOW_REG_NR,
1314 PCI_DMA_FROMDEVICE);
1315 intrstat = jme->shadow_regs[SHADOW_IEVE];
1316 jme->shadow_regs[SHADOW_IEVE] = 0;
1318 jme_intr_msi(jme, intrstat);
1325 jme_reset_link(struct jme_adapter *jme)
1327 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1331 jme_restart_an(struct jme_adapter *jme)
1334 unsigned long flags;
1336 spin_lock_irqsave(&jme->phy_lock, flags);
1337 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1338 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1339 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1340 spin_unlock_irqrestore(&jme->phy_lock, flags);
1344 jme_request_irq(struct jme_adapter *jme)
1347 struct net_device *netdev = jme->dev;
1348 irq_handler_t handler = jme_intr;
1349 int irq_flags = IRQF_SHARED;
1351 if (!pci_enable_msi(jme->pdev)) {
1352 jme->flags |= JME_FLAG_MSI;
1357 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1360 jeprintk(netdev->name,
1361 "Unable to request %s interrupt (return: %d)\n",
1362 jme->flags & JME_FLAG_MSI ? "MSI":"INTx", rc);
1364 if(jme->flags & JME_FLAG_MSI) {
1365 pci_disable_msi(jme->pdev);
1366 jme->flags &= ~JME_FLAG_MSI;
1370 netdev->irq = jme->pdev->irq;
1377 jme_free_irq(struct jme_adapter *jme)
1379 free_irq(jme->pdev->irq, jme->dev);
1380 if (jme->flags & JME_FLAG_MSI) {
1381 pci_disable_msi(jme->pdev);
1382 jme->flags &= ~JME_FLAG_MSI;
1383 jme->dev->irq = jme->pdev->irq;
1388 jme_open(struct net_device *netdev)
1390 struct jme_adapter *jme = netdev_priv(netdev);
1391 int rc, timeout = 100;
1396 atomic_read(&jme->link_changing) != 1 ||
1397 atomic_read(&jme->rx_cleaning) != 1 ||
1398 atomic_read(&jme->tx_cleaning) != 1
1409 jme_reset_mac_processor(jme);
1411 rc = jme_request_irq(jme);
1415 jme_enable_shadow(jme);
1418 if(jme->flags & JME_FLAG_SSET)
1419 jme_set_settings(netdev, &jme->old_ecmd);
1421 jme_reset_phy_processor(jme);
1423 jme_reset_link(jme);
1428 netif_stop_queue(netdev);
1429 netif_carrier_off(netdev);
1434 jme_set_100m_half(struct jme_adapter *jme)
1438 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1439 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1440 BMCR_SPEED1000 | BMCR_FULLDPLX);
1441 tmp |= BMCR_SPEED100;
1444 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1446 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1450 jme_phy_off(struct jme_adapter *jme)
1452 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1457 jme_close(struct net_device *netdev)
1459 struct jme_adapter *jme = netdev_priv(netdev);
1461 netif_stop_queue(netdev);
1462 netif_carrier_off(netdev);
1465 jme_disable_shadow(jme);
1468 tasklet_kill(&jme->linkch_task);
1469 tasklet_kill(&jme->txclean_task);
1470 tasklet_kill(&jme->rxclean_task);
1471 tasklet_kill(&jme->rxempty_task);
1473 jme_reset_mac_processor(jme);
1474 jme_free_rx_resources(jme);
1475 jme_free_tx_resources(jme);
1483 jme_alloc_txdesc(struct jme_adapter *jme,
1484 struct sk_buff *skb)
1486 struct jme_ring *txring = jme->txring;
1487 int idx, nr_alloc, mask = jme->tx_ring_mask;
1489 idx = txring->next_to_use;
1490 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1492 if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1495 atomic_sub(nr_alloc, &txring->nr_free);
1497 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1503 jme_fill_tx_map(struct pci_dev *pdev,
1504 volatile struct txdesc *txdesc,
1505 struct jme_buffer_info *txbi,
1513 dmaaddr = pci_map_page(pdev,
1519 pci_dma_sync_single_for_device(pdev,
1526 txdesc->desc2.flags = TXFLAG_OWN;
1527 txdesc->desc2.flags |= (hidma)?TXFLAG_64BIT:0;
1528 txdesc->desc2.datalen = cpu_to_le16(len);
1529 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1530 txdesc->desc2.bufaddrl = cpu_to_le32(
1531 (__u64)dmaaddr & 0xFFFFFFFFUL);
1533 txbi->mapping = dmaaddr;
1538 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1540 struct jme_ring *txring = jme->txring;
1541 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
1542 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1543 __u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1544 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1545 int mask = jme->tx_ring_mask;
1546 struct skb_frag_struct *frag;
1549 for(i = 0 ; i < nr_frags ; ++i) {
1550 frag = &skb_shinfo(skb)->frags[i];
1551 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1552 ctxbi = txbi + ((idx + i + 2) & (mask));
1554 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1555 frag->page_offset, frag->size, hidma);
1558 len = skb_is_nonlinear(skb)?skb_headlen(skb):skb->len;
1559 ctxdesc = txdesc + ((idx + 1) & (mask));
1560 ctxbi = txbi + ((idx + 1) & (mask));
1561 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1562 offset_in_page(skb->data), len, hidma);
1567 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1569 if(unlikely(skb_shinfo(skb)->gso_size &&
1570 skb_header_cloned(skb) &&
1571 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1580 jme_tx_tso(struct sk_buff *skb,
1581 volatile __u16 *mss, __u8 *flags)
1583 if((*mss = (skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT))) {
1584 *flags |= TXFLAG_LSEN;
1586 if(skb->protocol == __constant_htons(ETH_P_IP)) {
1587 struct iphdr *iph = ip_hdr(skb);
1590 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1596 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1598 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1611 jme_tx_csum(struct sk_buff *skb, __u8 *flags)
1613 if(skb->ip_summed == CHECKSUM_PARTIAL) {
1616 switch (skb->protocol) {
1617 case __constant_htons(ETH_P_IP):
1618 ip_proto = ip_hdr(skb)->protocol;
1620 case __constant_htons(ETH_P_IPV6):
1621 ip_proto = ipv6_hdr(skb)->nexthdr;
1630 *flags |= TXFLAG_TCPCS;
1633 *flags |= TXFLAG_UDPCS;
1636 jeprintk("jme", "Error upper layer protocol.\n");
1642 __always_inline static void
1643 jme_tx_vlan(struct sk_buff *skb, volatile __u16 *vlan, __u8 *flags)
1645 if(vlan_tx_tag_present(skb)) {
1646 vlan_dbg("jme", "Tag found!(%04x)\n", vlan_tx_tag_get(skb));
1647 *flags |= TXFLAG_TAGON;
1648 *vlan = vlan_tx_tag_get(skb);
1653 jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1655 struct jme_ring *txring = jme->txring;
1656 volatile struct txdesc *txdesc;
1657 struct jme_buffer_info *txbi;
1660 txdesc = (volatile struct txdesc*)txring->desc + idx;
1661 txbi = txring->bufinf + idx;
1667 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1669 * Set OWN bit at final.
1670 * When kernel transmit faster than NIC.
1671 * And NIC trying to send this descriptor before we tell
1672 * it to start sending this TX queue.
1673 * Other fields are already filled correctly.
1676 flags = TXFLAG_OWN | TXFLAG_INT;
1677 //Set checksum flags while not tso
1678 if(jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1679 jme_tx_csum(skb, &flags);
1680 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1681 txdesc->desc1.flags = flags;
1683 * Set tx buffer info after telling NIC to send
1684 * For better tx_clean timing
1687 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1689 txbi->len = skb->len;
1695 jme_stop_queue_if_full(struct jme_adapter *jme)
1697 struct jme_ring *txring = jme->txring;
1700 if(unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1701 netif_stop_queue(jme->dev);
1702 queue_dbg(jme->dev->name, "TX Queue Paused.\n");
1704 if (atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold)) {
1705 netif_wake_queue(jme->dev);
1706 queue_dbg(jme->dev->name, "TX Queue Fast Waked.\n");
1713 * This function is already protected by netif_tx_lock()
1716 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1718 struct jme_adapter *jme = netdev_priv(netdev);
1721 if(skb_shinfo(skb)->nr_frags) {
1722 tx_dbg(netdev->name, "Frags: %d Headlen: %d Len: %d MSS: %d Sum:%d\n",
1723 skb_shinfo(skb)->nr_frags,
1726 skb_shinfo(skb)->gso_size,
1730 if(unlikely(jme_expand_header(jme, skb))) {
1731 ++(NET_STAT(jme).tx_dropped);
1732 return NETDEV_TX_OK;
1735 idx = jme_alloc_txdesc(jme, skb);
1737 if(unlikely(idx<0)) {
1738 netif_stop_queue(netdev);
1739 jeprintk(netdev->name,
1740 "BUG! Tx ring full when queue awake!\n");
1742 return NETDEV_TX_BUSY;
1745 jme_map_tx_skb(jme, skb, idx);
1746 jme_fill_first_tx_desc(jme, skb, idx);
1748 tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, skb_shinfo(skb)->nr_frags + 2);
1750 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1751 TXCS_SELECT_QUEUE0 |
1754 netdev->trans_start = jiffies;
1756 jme_stop_queue_if_full(jme);
1758 return NETDEV_TX_OK;
1762 jme_set_macaddr(struct net_device *netdev, void *p)
1764 struct jme_adapter *jme = netdev_priv(netdev);
1765 struct sockaddr *addr = p;
1768 if(netif_running(netdev))
1771 spin_lock(&jme->macaddr_lock);
1772 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1774 val = addr->sa_data[3] << 24 |
1775 addr->sa_data[2] << 16 |
1776 addr->sa_data[1] << 8 |
1778 jwrite32(jme, JME_RXUMA_LO, val);
1779 val = addr->sa_data[5] << 8 |
1781 jwrite32(jme, JME_RXUMA_HI, val);
1782 spin_unlock(&jme->macaddr_lock);
1788 jme_set_multi(struct net_device *netdev)
1790 struct jme_adapter *jme = netdev_priv(netdev);
1791 u32 mc_hash[2] = {};
1793 unsigned long flags;
1795 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1797 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1799 if (netdev->flags & IFF_PROMISC) {
1800 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1802 else if (netdev->flags & IFF_ALLMULTI) {
1803 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1805 else if(netdev->flags & IFF_MULTICAST) {
1806 struct dev_mc_list *mclist;
1809 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1810 for (i = 0, mclist = netdev->mc_list;
1811 mclist && i < netdev->mc_count;
1812 ++i, mclist = mclist->next) {
1814 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1815 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
1818 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1819 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
1823 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1825 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1829 jme_change_mtu(struct net_device *netdev, int new_mtu)
1831 struct jme_adapter *jme = netdev_priv(netdev);
1833 if(new_mtu == jme->old_mtu)
1836 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
1837 ((new_mtu) < IPV6_MIN_MTU))
1840 if(new_mtu > 4000) {
1841 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1842 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1843 jme_restart_rx_engine(jme);
1846 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1847 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1848 jme_restart_rx_engine(jme);
1851 if(new_mtu > 1900) {
1852 netdev->features &= ~(NETIF_F_HW_CSUM |
1857 if(jme->flags & JME_FLAG_TXCSUM)
1858 netdev->features |= NETIF_F_HW_CSUM;
1859 if(jme->flags & JME_FLAG_TSO)
1860 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
1863 netdev->mtu = new_mtu;
1864 jme_reset_link(jme);
1870 jme_tx_timeout(struct net_device *netdev)
1872 struct jme_adapter *jme = netdev_priv(netdev);
1876 * And the link change will reinitialize all RX/TX resources
1879 jme_reset_link(jme);
1883 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
1885 struct jme_adapter *jme = netdev_priv(netdev);
1891 jme_get_drvinfo(struct net_device *netdev,
1892 struct ethtool_drvinfo *info)
1894 struct jme_adapter *jme = netdev_priv(netdev);
1896 strcpy(info->driver, DRV_NAME);
1897 strcpy(info->version, DRV_VERSION);
1898 strcpy(info->bus_info, pci_name(jme->pdev));
1902 jme_get_regs_len(struct net_device *netdev)
1908 mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
1912 for(i = 0 ; i < len ; i += 4)
1913 p[i >> 2] = jread32(jme, reg + i);
1918 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
1920 struct jme_adapter *jme = netdev_priv(netdev);
1921 __u32 *p32 = (__u32*)p;
1923 memset(p, 0, 0x400);
1926 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
1929 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
1932 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
1935 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
1940 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1942 struct jme_adapter *jme = netdev_priv(netdev);
1944 ecmd->use_adaptive_rx_coalesce = true;
1945 ecmd->tx_coalesce_usecs = PCC_TX_TO;
1946 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
1948 switch(jme->dpi.cur) {
1950 ecmd->rx_coalesce_usecs = PCC_P1_TO;
1951 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
1954 ecmd->rx_coalesce_usecs = PCC_P2_TO;
1955 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
1958 ecmd->rx_coalesce_usecs = PCC_P3_TO;
1959 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
1969 jme_get_pauseparam(struct net_device *netdev,
1970 struct ethtool_pauseparam *ecmd)
1972 struct jme_adapter *jme = netdev_priv(netdev);
1973 unsigned long flags;
1976 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
1977 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
1979 spin_lock_irqsave(&jme->phy_lock, flags);
1980 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1981 spin_unlock_irqrestore(&jme->phy_lock, flags);
1984 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
1988 jme_set_pauseparam(struct net_device *netdev,
1989 struct ethtool_pauseparam *ecmd)
1991 struct jme_adapter *jme = netdev_priv(netdev);
1992 unsigned long flags;
1995 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
1996 (ecmd->tx_pause != 0)) {
1999 jme->reg_txpfc |= TXPFC_PF_EN;
2001 jme->reg_txpfc &= ~TXPFC_PF_EN;
2003 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2006 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2007 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
2008 (ecmd->rx_pause != 0)) {
2011 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2013 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2015 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2017 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2019 spin_lock_irqsave(&jme->phy_lock, flags);
2020 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2021 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
2022 (ecmd->autoneg != 0)) {
2025 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2027 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2029 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2030 MII_ADVERTISE, val);
2032 spin_unlock_irqrestore(&jme->phy_lock, flags);
2038 jme_get_wol(struct net_device *netdev,
2039 struct ethtool_wolinfo *wol)
2041 struct jme_adapter *jme = netdev_priv(netdev);
2043 wol->supported = WAKE_MAGIC | WAKE_PHY;
2047 if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2048 wol->wolopts |= WAKE_PHY;
2050 if(jme->reg_pmcs & PMCS_MFEN)
2051 wol->wolopts |= WAKE_MAGIC;
2056 jme_set_wol(struct net_device *netdev,
2057 struct ethtool_wolinfo *wol)
2059 struct jme_adapter *jme = netdev_priv(netdev);
2061 if(wol->wolopts & (WAKE_MAGICSECURE |
2070 if(wol->wolopts & WAKE_PHY)
2071 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2073 if(wol->wolopts & WAKE_MAGIC)
2074 jme->reg_pmcs |= PMCS_MFEN;
2081 jme_get_settings(struct net_device *netdev,
2082 struct ethtool_cmd *ecmd)
2084 struct jme_adapter *jme = netdev_priv(netdev);
2086 unsigned long flags;
2088 spin_lock_irqsave(&jme->phy_lock, flags);
2089 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2090 spin_unlock_irqrestore(&jme->phy_lock, flags);
2095 jme_set_settings(struct net_device *netdev,
2096 struct ethtool_cmd *ecmd)
2098 struct jme_adapter *jme = netdev_priv(netdev);
2100 unsigned long flags;
2102 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2105 if(jme->mii_if.force_media &&
2106 ecmd->autoneg != AUTONEG_ENABLE &&
2107 (jme->mii_if.full_duplex != ecmd->duplex))
2110 spin_lock_irqsave(&jme->phy_lock, flags);
2111 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2112 spin_unlock_irqrestore(&jme->phy_lock, flags);
2115 jme_reset_link(jme);
2118 jme->flags |= JME_FLAG_SSET;
2119 jme->old_ecmd = *ecmd;
2126 jme_get_link(struct net_device *netdev)
2128 struct jme_adapter *jme = netdev_priv(netdev);
2129 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2133 jme_get_rx_csum(struct net_device *netdev)
2135 struct jme_adapter *jme = netdev_priv(netdev);
2137 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2141 jme_set_rx_csum(struct net_device *netdev, u32 on)
2143 struct jme_adapter *jme = netdev_priv(netdev);
2144 unsigned long flags;
2146 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2148 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2150 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2151 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2152 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2158 jme_set_tx_csum(struct net_device *netdev, u32 on)
2160 struct jme_adapter *jme = netdev_priv(netdev);
2163 jme->flags |= JME_FLAG_TXCSUM;
2164 if(netdev->mtu <= 1900)
2165 netdev->features |= NETIF_F_HW_CSUM;
2168 jme->flags &= ~JME_FLAG_TXCSUM;
2169 netdev->features &= ~NETIF_F_HW_CSUM;
2176 jme_set_tso(struct net_device *netdev, u32 on)
2178 struct jme_adapter *jme = netdev_priv(netdev);
2181 jme->flags |= JME_FLAG_TSO;
2182 if(netdev->mtu <= 1900)
2183 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2186 jme->flags &= ~JME_FLAG_TSO;
2187 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2194 jme_nway_reset(struct net_device *netdev)
2196 struct jme_adapter *jme = netdev_priv(netdev);
2197 jme_restart_an(jme);
2201 static const struct ethtool_ops jme_ethtool_ops = {
2202 .get_drvinfo = jme_get_drvinfo,
2203 .get_regs_len = jme_get_regs_len,
2204 .get_regs = jme_get_regs,
2205 .get_coalesce = jme_get_coalesce,
2206 .get_pauseparam = jme_get_pauseparam,
2207 .set_pauseparam = jme_set_pauseparam,
2208 .get_wol = jme_get_wol,
2209 .set_wol = jme_set_wol,
2210 .get_settings = jme_get_settings,
2211 .set_settings = jme_set_settings,
2212 .get_link = jme_get_link,
2213 .get_rx_csum = jme_get_rx_csum,
2214 .set_rx_csum = jme_set_rx_csum,
2215 .set_tx_csum = jme_set_tx_csum,
2216 .set_tso = jme_set_tso,
2217 .set_sg = ethtool_op_set_sg,
2218 .nway_reset = jme_nway_reset,
2222 jme_pci_dma64(struct pci_dev *pdev)
2224 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2225 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
2226 dprintk("jme", "64Bit DMA Selected.\n");
2230 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2231 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK)) {
2232 dprintk("jme", "40Bit DMA Selected.\n");
2236 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2237 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
2238 dprintk("jme", "32Bit DMA Selected.\n");
2245 __always_inline static void
2246 jme_set_phy_ps(struct jme_adapter *jme)
2248 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, 0x00001000);
2251 static int __devinit
2252 jme_init_one(struct pci_dev *pdev,
2253 const struct pci_device_id *ent)
2255 int rc = 0, using_dac;
2256 struct net_device *netdev;
2257 struct jme_adapter *jme;
2260 * set up PCI device basics
2262 rc = pci_enable_device(pdev);
2264 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2268 using_dac = jme_pci_dma64(pdev);
2270 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2272 goto err_out_disable_pdev;
2275 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2276 printk(KERN_ERR PFX "No PCI resource region found.\n");
2278 goto err_out_disable_pdev;
2281 rc = pci_request_regions(pdev, DRV_NAME);
2283 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2284 goto err_out_disable_pdev;
2287 pci_set_master(pdev);
2290 * alloc and init net device
2292 netdev = alloc_etherdev(sizeof(*jme));
2294 printk(KERN_ERR PFX "Cannot allocate netdev structure.\n");
2296 goto err_out_release_regions;
2298 netdev->open = jme_open;
2299 netdev->stop = jme_close;
2300 netdev->hard_start_xmit = jme_start_xmit;
2301 netdev->set_mac_address = jme_set_macaddr;
2302 netdev->set_multicast_list = jme_set_multi;
2303 netdev->change_mtu = jme_change_mtu;
2304 netdev->ethtool_ops = &jme_ethtool_ops;
2305 netdev->tx_timeout = jme_tx_timeout;
2306 netdev->watchdog_timeo = TX_TIMEOUT;
2307 netdev->vlan_rx_register = jme_vlan_rx_register;
2308 NETDEV_GET_STATS(netdev, &jme_get_stats);
2309 netdev->features = NETIF_F_HW_CSUM |
2313 NETIF_F_HW_VLAN_TX |
2316 netdev->features |= NETIF_F_HIGHDMA;
2318 SET_NETDEV_DEV(netdev, &pdev->dev);
2319 pci_set_drvdata(pdev, netdev);
2324 jme = netdev_priv(netdev);
2327 jme->old_mtu = netdev->mtu = 1500;
2329 jme->tx_ring_size = 1 << 10;
2330 jme->tx_ring_mask = jme->tx_ring_size - 1;
2331 jme->tx_wake_threshold = 1 << 9;
2332 jme->rx_ring_size = 1 << 9;
2333 jme->rx_ring_mask = jme->rx_ring_size - 1;
2334 jme->regs = ioremap(pci_resource_start(pdev, 0),
2335 pci_resource_len(pdev, 0));
2337 printk(KERN_ERR PFX "Mapping PCI resource region error.\n");
2339 goto err_out_free_netdev;
2341 jme->shadow_regs = pci_alloc_consistent(pdev,
2342 sizeof(__u32) * SHADOW_REG_NR,
2343 &(jme->shadow_dma));
2344 if (!(jme->shadow_regs)) {
2345 printk(KERN_ERR PFX "Allocating shadow register mapping error.\n");
2350 spin_lock_init(&jme->phy_lock);
2351 spin_lock_init(&jme->macaddr_lock);
2352 spin_lock_init(&jme->rxmcs_lock);
2354 atomic_set(&jme->link_changing, 1);
2355 atomic_set(&jme->rx_cleaning, 1);
2356 atomic_set(&jme->tx_cleaning, 1);
2358 tasklet_init(&jme->pcc_task,
2360 (unsigned long) jme);
2361 tasklet_init(&jme->linkch_task,
2362 &jme_link_change_tasklet,
2363 (unsigned long) jme);
2364 tasklet_init(&jme->txclean_task,
2365 &jme_tx_clean_tasklet,
2366 (unsigned long) jme);
2367 tasklet_init(&jme->rxclean_task,
2368 &jme_rx_clean_tasklet,
2369 (unsigned long) jme);
2370 tasklet_init(&jme->rxempty_task,
2371 &jme_rx_empty_tasklet,
2372 (unsigned long) jme);
2373 jme->mii_if.dev = netdev;
2374 jme->mii_if.phy_id = 1;
2375 jme->mii_if.supports_gmii = 1;
2376 jme->mii_if.mdio_read = jme_mdio_read;
2377 jme->mii_if.mdio_write = jme_mdio_write;
2379 jme->dpi.cur = PCC_P1;
2381 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
2382 jme->reg_rxcs = RXCS_DEFAULT;
2383 jme->reg_rxmcs = RXMCS_DEFAULT;
2385 jme->reg_pmcs = PMCS_LFEN | PMCS_LREN | PMCS_MFEN;
2386 jme->flags = JME_FLAG_TXCSUM | JME_FLAG_TSO;
2388 * Get Max Read Req Size from PCI Config Space
2390 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2393 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2396 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2399 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2405 * Reset MAC processor and reload EEPROM for MAC Address
2408 jme_set_phy_ps(jme);
2410 jme_reset_mac_processor(jme);
2411 rc = jme_reload_eeprom(jme);
2414 "Reload eeprom for reading MAC Address error.\n");
2415 goto err_out_free_shadow;
2417 jme_load_macaddr(netdev);
2421 * Tell stack that we are not ready to work until open()
2423 netif_carrier_off(netdev);
2424 netif_stop_queue(netdev);
2429 rc = register_netdev(netdev);
2431 printk(KERN_ERR PFX "Cannot register net device.\n");
2432 goto err_out_free_shadow;
2435 jprintk(netdev->name,
2436 "JMC250 gigabit eth %02x:%02x:%02x:%02x:%02x:%02x\n",
2437 netdev->dev_addr[0],
2438 netdev->dev_addr[1],
2439 netdev->dev_addr[2],
2440 netdev->dev_addr[3],
2441 netdev->dev_addr[4],
2442 netdev->dev_addr[5]);
2446 err_out_free_shadow:
2447 pci_free_consistent(pdev,
2448 sizeof(__u32) * SHADOW_REG_NR,
2453 err_out_free_netdev:
2454 pci_set_drvdata(pdev, NULL);
2455 free_netdev(netdev);
2456 err_out_release_regions:
2457 pci_release_regions(pdev);
2458 err_out_disable_pdev:
2459 pci_disable_device(pdev);
2464 static void __devexit
2465 jme_remove_one(struct pci_dev *pdev)
2467 struct net_device *netdev = pci_get_drvdata(pdev);
2468 struct jme_adapter *jme = netdev_priv(netdev);
2470 unregister_netdev(netdev);
2471 pci_free_consistent(pdev,
2472 sizeof(__u32) * SHADOW_REG_NR,
2476 pci_set_drvdata(pdev, NULL);
2477 free_netdev(netdev);
2478 pci_release_regions(pdev);
2479 pci_disable_device(pdev);
2484 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2486 struct net_device *netdev = pci_get_drvdata(pdev);
2487 struct jme_adapter *jme = netdev_priv(netdev);
2490 atomic_dec(&jme->link_changing);
2492 netif_device_detach(netdev);
2493 netif_stop_queue(netdev);
2497 while(--timeout > 0 &&
2499 atomic_read(&jme->rx_cleaning) != 1 ||
2500 atomic_read(&jme->tx_cleaning) != 1
2505 jeprintk(netdev->name, "Waiting tasklets timeout.\n");
2508 jme_disable_shadow(jme);
2510 if(netif_carrier_ok(netdev)) {
2511 jme_stop_pcc_timer(jme);
2512 jme_reset_mac_processor(jme);
2513 jme_free_rx_resources(jme);
2514 jme_free_tx_resources(jme);
2515 netif_carrier_off(netdev);
2520 pci_save_state(pdev);
2522 jme_set_100m_half(jme);
2523 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2524 pci_enable_wake(pdev, PCI_D3hot, true);
2525 pci_enable_wake(pdev, PCI_D3cold, true);
2529 pci_enable_wake(pdev, PCI_D3hot, false);
2530 pci_enable_wake(pdev, PCI_D3cold, false);
2532 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2538 jme_resume(struct pci_dev *pdev)
2540 struct net_device *netdev = pci_get_drvdata(pdev);
2541 struct jme_adapter *jme = netdev_priv(netdev);
2544 pci_restore_state(pdev);
2546 if(jme->flags & JME_FLAG_SSET)
2547 jme_set_settings(netdev, &jme->old_ecmd);
2549 jme_reset_phy_processor(jme);
2551 jme_reset_mac_processor(jme);
2552 jme_enable_shadow(jme);
2553 jme_request_irq(jme);
2555 netif_device_attach(netdev);
2557 atomic_inc(&jme->link_changing);
2559 jme_reset_link(jme);
2564 static struct pci_device_id jme_pci_tbl[] = {
2565 { PCI_VDEVICE(JMICRON, 0x250) },
2569 static struct pci_driver jme_driver = {
2571 .id_table = jme_pci_tbl,
2572 .probe = jme_init_one,
2573 .remove = __devexit_p(jme_remove_one),
2575 .suspend = jme_suspend,
2576 .resume = jme_resume,
2577 #endif /* CONFIG_PM */
2581 jme_init_module(void)
2583 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2584 "driver version %s\n", DRV_VERSION);
2585 return pci_register_driver(&jme_driver);
2589 jme_cleanup_module(void)
2591 pci_unregister_driver(&jme_driver);
2594 module_init(jme_init_module);
2595 module_exit(jme_cleanup_module);
2597 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
2598 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2599 MODULE_LICENSE("GPL");
2600 MODULE_VERSION(DRV_VERSION);
2601 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);