6b2a5e744255241a572e66b6b8b1298d430894d1
[jme.git] / jme.c
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7  *
8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  *
23  */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/mii.h>
34 #include <linux/crc32.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <linux/ipv6.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/if_vlan.h>
43 #include <linux/slab.h>
44 #include <net/ip6_checksum.h>
45 #include "jme.h"
46
47 static int force_pseudohp = -1;
48 static int no_pseudohp = -1;
49 static int no_extplug = -1;
50 module_param(force_pseudohp, int, 0);
51 MODULE_PARM_DESC(force_pseudohp,
52         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53 module_param(no_pseudohp, int, 0);
54 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55 module_param(no_extplug, int, 0);
56 MODULE_PARM_DESC(no_extplug,
57         "Do not use external plug signal for pseudo hot-plug.");
58
59 static int
60 jme_mdio_read(struct net_device *netdev, int phy, int reg)
61 {
62         struct jme_adapter *jme = netdev_priv(netdev);
63         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
64
65 read_again:
66         jwrite32(jme, JME_SMI, SMI_OP_REQ |
67                                 smi_phy_addr(phy) |
68                                 smi_reg_addr(reg));
69
70         wmb();
71         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72                 udelay(20);
73                 val = jread32(jme, JME_SMI);
74                 if ((val & SMI_OP_REQ) == 0)
75                         break;
76         }
77
78         if (i == 0) {
79                 pr_err("phy(%d) read timeout : %d\n", phy, reg);
80                 return 0;
81         }
82
83         if (again--)
84                 goto read_again;
85
86         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
87 }
88
89 static void
90 jme_mdio_write(struct net_device *netdev,
91                                 int phy, int reg, int val)
92 {
93         struct jme_adapter *jme = netdev_priv(netdev);
94         int i;
95
96         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98                 smi_phy_addr(phy) | smi_reg_addr(reg));
99
100         wmb();
101         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102                 udelay(20);
103                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104                         break;
105         }
106
107         if (i == 0)
108                 pr_err("phy(%d) write timeout : %d\n", phy, reg);
109 }
110
111 static inline void
112 jme_reset_phy_processor(struct jme_adapter *jme)
113 {
114         u32 val;
115
116         jme_mdio_write(jme->dev,
117                         jme->mii_if.phy_id,
118                         MII_ADVERTISE, ADVERTISE_ALL |
119                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120
121         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122                 jme_mdio_write(jme->dev,
123                                 jme->mii_if.phy_id,
124                                 MII_CTRL1000,
125                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126
127         val = jme_mdio_read(jme->dev,
128                                 jme->mii_if.phy_id,
129                                 MII_BMCR);
130
131         jme_mdio_write(jme->dev,
132                         jme->mii_if.phy_id,
133                         MII_BMCR, val | BMCR_RESET);
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138                        const u32 *mask, u32 crc, int fnr)
139 {
140         int i;
141
142         /*
143          * Setup CRC pattern
144          */
145         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146         wmb();
147         jwrite32(jme, JME_WFODP, crc);
148         wmb();
149
150         /*
151          * Setup Mask
152          */
153         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154                 jwrite32(jme, JME_WFOI,
155                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156                                 (fnr & WFOI_FRAME_SEL));
157                 wmb();
158                 jwrite32(jme, JME_WFODP, mask[i]);
159                 wmb();
160         }
161 }
162
163 static inline void
164 jme_mac_rxclk_off(struct jme_adapter *jme)
165 {
166         jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168 }
169
170 static inline void
171 jme_mac_rxclk_on(struct jme_adapter *jme)
172 {
173         jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175 }
176
177 static inline void
178 jme_mac_txclk_off(struct jme_adapter *jme)
179 {
180         jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181         jwrite32f(jme, JME_GHC, jme->reg_ghc);
182 }
183
184 static inline void
185 jme_mac_txclk_on(struct jme_adapter *jme)
186 {
187         u32 speed = jme->reg_ghc & GHC_SPEED;
188         if (speed == GHC_SPEED_1000M)
189                 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190         else
191                 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192         jwrite32f(jme, JME_GHC, jme->reg_ghc);
193 }
194
195 static inline void
196 jme_reset_ghc_speed(struct jme_adapter *jme)
197 {
198         jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199         jwrite32f(jme, JME_GHC, jme->reg_ghc);
200 }
201
202 static inline void
203 jme_reset_250A2_workaround(struct jme_adapter *jme)
204 {
205         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206                              GPREG1_RSSPATCH);
207         jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208 }
209
210 static inline void
211 jme_assert_ghc_reset(struct jme_adapter *jme)
212 {
213         jme->reg_ghc |= GHC_SWRST;
214         jwrite32f(jme, JME_GHC, jme->reg_ghc);
215 }
216
217 static inline void
218 jme_clear_ghc_reset(struct jme_adapter *jme)
219 {
220         jme->reg_ghc &= ~GHC_SWRST;
221         jwrite32f(jme, JME_GHC, jme->reg_ghc);
222 }
223
224 static inline void
225 jme_reset_mac_processor(struct jme_adapter *jme)
226 {
227         static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
228         u32 crc = 0xCDCDCDCD;
229         u32 gpreg0;
230         int i;
231
232         jme_reset_ghc_speed(jme);
233         jme_reset_250A2_workaround(jme);
234
235         jme_mac_rxclk_on(jme);
236         jme_mac_txclk_on(jme);
237         udelay(1);
238         jme_assert_ghc_reset(jme);
239         udelay(1);
240         jme_mac_rxclk_off(jme);
241         jme_mac_txclk_off(jme);
242         udelay(1);
243         jme_clear_ghc_reset(jme);
244         udelay(1);
245         jme_mac_rxclk_on(jme);
246         jme_mac_txclk_on(jme);
247         udelay(1);
248         jme_mac_rxclk_off(jme);
249         jme_mac_txclk_off(jme);
250
251         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253         jwrite32(jme, JME_RXQDC, 0x00000000);
254         jwrite32(jme, JME_RXNDA, 0x00000000);
255         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257         jwrite32(jme, JME_TXQDC, 0x00000000);
258         jwrite32(jme, JME_TXNDA, 0x00000000);
259
260         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
262         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
263                 jme_setup_wakeup_frame(jme, mask, crc, i);
264         if (jme->fpgaver)
265                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266         else
267                 gpreg0 = GPREG0_DEFAULT;
268         jwrite32(jme, JME_GPREG0, gpreg0);
269 }
270
271 static inline void
272 jme_clear_pm(struct jme_adapter *jme)
273 {
274         jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
275 }
276
277 static int
278 jme_reload_eeprom(struct jme_adapter *jme)
279 {
280         u32 val;
281         int i;
282
283         val = jread32(jme, JME_SMBCSR);
284
285         if (val & SMBCSR_EEPROMD) {
286                 val |= SMBCSR_CNACK;
287                 jwrite32(jme, JME_SMBCSR, val);
288                 val |= SMBCSR_RELOAD;
289                 jwrite32(jme, JME_SMBCSR, val);
290                 mdelay(12);
291
292                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
293                         mdelay(1);
294                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
295                                 break;
296                 }
297
298                 if (i == 0) {
299                         pr_err("eeprom reload timeout\n");
300                         return -EIO;
301                 }
302         }
303
304         return 0;
305 }
306
307 static void
308 jme_load_macaddr(struct net_device *netdev)
309 {
310         struct jme_adapter *jme = netdev_priv(netdev);
311         unsigned char macaddr[6];
312         u32 val;
313
314         spin_lock_bh(&jme->macaddr_lock);
315         val = jread32(jme, JME_RXUMA_LO);
316         macaddr[0] = (val >>  0) & 0xFF;
317         macaddr[1] = (val >>  8) & 0xFF;
318         macaddr[2] = (val >> 16) & 0xFF;
319         macaddr[3] = (val >> 24) & 0xFF;
320         val = jread32(jme, JME_RXUMA_HI);
321         macaddr[4] = (val >>  0) & 0xFF;
322         macaddr[5] = (val >>  8) & 0xFF;
323         memcpy(netdev->dev_addr, macaddr, 6);
324         spin_unlock_bh(&jme->macaddr_lock);
325 }
326
327 static inline void
328 jme_set_rx_pcc(struct jme_adapter *jme, int p)
329 {
330         switch (p) {
331         case PCC_OFF:
332                 jwrite32(jme, JME_PCCRX0,
333                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
334                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
335                 break;
336         case PCC_P1:
337                 jwrite32(jme, JME_PCCRX0,
338                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340                 break;
341         case PCC_P2:
342                 jwrite32(jme, JME_PCCRX0,
343                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345                 break;
346         case PCC_P3:
347                 jwrite32(jme, JME_PCCRX0,
348                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350                 break;
351         default:
352                 break;
353         }
354         wmb();
355
356         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
357                 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
358 }
359
360 static void
361 jme_start_irq(struct jme_adapter *jme)
362 {
363         register struct dynpcc_info *dpi = &(jme->dpi);
364
365         jme_set_rx_pcc(jme, PCC_P1);
366         dpi->cur                = PCC_P1;
367         dpi->attempt            = PCC_P1;
368         dpi->cnt                = 0;
369
370         jwrite32(jme, JME_PCCTX,
371                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
372                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
373                         PCCTXQ0_EN
374                 );
375
376         /*
377          * Enable Interrupts
378          */
379         jwrite32(jme, JME_IENS, INTR_ENABLE);
380 }
381
382 static inline void
383 jme_stop_irq(struct jme_adapter *jme)
384 {
385         /*
386          * Disable Interrupts
387          */
388         jwrite32f(jme, JME_IENC, INTR_ENABLE);
389 }
390
391 static u32
392 jme_linkstat_from_phy(struct jme_adapter *jme)
393 {
394         u32 phylink, bmsr;
395
396         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
397         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
398         if (bmsr & BMSR_ANCOMP)
399                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
400
401         return phylink;
402 }
403
404 static inline void
405 jme_set_phyfifo_5level(struct jme_adapter *jme)
406 {
407         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
408 }
409
410 static inline void
411 jme_set_phyfifo_8level(struct jme_adapter *jme)
412 {
413         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
414 }
415
416 static int
417 jme_check_link(struct net_device *netdev, int testonly)
418 {
419         struct jme_adapter *jme = netdev_priv(netdev);
420         u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
421         char linkmsg[64];
422         int rc = 0;
423
424         linkmsg[0] = '\0';
425
426         if (jme->fpgaver)
427                 phylink = jme_linkstat_from_phy(jme);
428         else
429                 phylink = jread32(jme, JME_PHY_LINK);
430
431         if (phylink & PHY_LINK_UP) {
432                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
433                         /*
434                          * If we did not enable AN
435                          * Speed/Duplex Info should be obtained from SMI
436                          */
437                         phylink = PHY_LINK_UP;
438
439                         bmcr = jme_mdio_read(jme->dev,
440                                                 jme->mii_if.phy_id,
441                                                 MII_BMCR);
442
443                         phylink |= ((bmcr & BMCR_SPEED1000) &&
444                                         (bmcr & BMCR_SPEED100) == 0) ?
445                                         PHY_LINK_SPEED_1000M :
446                                         (bmcr & BMCR_SPEED100) ?
447                                         PHY_LINK_SPEED_100M :
448                                         PHY_LINK_SPEED_10M;
449
450                         phylink |= (bmcr & BMCR_FULLDPLX) ?
451                                          PHY_LINK_DUPLEX : 0;
452
453                         strcat(linkmsg, "Forced: ");
454                 } else {
455                         /*
456                          * Keep polling for speed/duplex resolve complete
457                          */
458                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
459                                 --cnt) {
460
461                                 udelay(1);
462
463                                 if (jme->fpgaver)
464                                         phylink = jme_linkstat_from_phy(jme);
465                                 else
466                                         phylink = jread32(jme, JME_PHY_LINK);
467                         }
468                         if (!cnt)
469                                 pr_err("Waiting speed resolve timeout\n");
470
471                         strcat(linkmsg, "ANed: ");
472                 }
473
474                 if (jme->phylink == phylink) {
475                         rc = 1;
476                         goto out;
477                 }
478                 if (testonly)
479                         goto out;
480
481                 jme->phylink = phylink;
482
483                 /*
484                  * The speed/duplex setting of jme->reg_ghc already cleared
485                  * by jme_reset_mac_processor()
486                  */
487                 switch (phylink & PHY_LINK_SPEED_MASK) {
488                 case PHY_LINK_SPEED_10M:
489                         jme->reg_ghc |= GHC_SPEED_10M;
490                         strcat(linkmsg, "10 Mbps, ");
491                         break;
492                 case PHY_LINK_SPEED_100M:
493                         jme->reg_ghc |= GHC_SPEED_100M;
494                         strcat(linkmsg, "100 Mbps, ");
495                         break;
496                 case PHY_LINK_SPEED_1000M:
497                         jme->reg_ghc |= GHC_SPEED_1000M;
498                         strcat(linkmsg, "1000 Mbps, ");
499                         break;
500                 default:
501                         break;
502                 }
503
504                 if (phylink & PHY_LINK_DUPLEX) {
505                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
506                         jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
507                         jme->reg_ghc |= GHC_DPX;
508                 } else {
509                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
510                                                 TXMCS_BACKOFF |
511                                                 TXMCS_CARRIERSENSE |
512                                                 TXMCS_COLLISION);
513                         jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
514                 }
515
516                 jwrite32(jme, JME_GHC, jme->reg_ghc);
517
518                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
519                         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
520                                              GPREG1_RSSPATCH);
521                         if (!(phylink & PHY_LINK_DUPLEX))
522                                 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
523                         switch (phylink & PHY_LINK_SPEED_MASK) {
524                         case PHY_LINK_SPEED_10M:
525                                 jme_set_phyfifo_8level(jme);
526                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
527                                 break;
528                         case PHY_LINK_SPEED_100M:
529                                 jme_set_phyfifo_5level(jme);
530                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
531                                 break;
532                         case PHY_LINK_SPEED_1000M:
533                                 jme_set_phyfifo_8level(jme);
534                                 break;
535                         default:
536                                 break;
537                         }
538                 }
539                 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
540
541                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
542                                         "Full-Duplex, " :
543                                         "Half-Duplex, ");
544                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
545                                         "MDI-X" :
546                                         "MDI");
547                 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
548                 netif_carrier_on(netdev);
549         } else {
550                 if (testonly)
551                         goto out;
552
553                 netif_info(jme, link, jme->dev, "Link is down\n");
554                 jme->phylink = 0;
555                 netif_carrier_off(netdev);
556         }
557
558 out:
559         return rc;
560 }
561
562 static int
563 jme_setup_tx_resources(struct jme_adapter *jme)
564 {
565         struct jme_ring *txring = &(jme->txring[0]);
566
567         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
568                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
569                                    &(txring->dmaalloc),
570                                    GFP_ATOMIC);
571
572         if (!txring->alloc)
573                 goto err_set_null;
574
575         /*
576          * 16 Bytes align
577          */
578         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
579                                                 RING_DESC_ALIGN);
580         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
581         txring->next_to_use     = 0;
582         atomic_set(&txring->next_to_clean, 0);
583         atomic_set(&txring->nr_free, jme->tx_ring_size);
584
585         txring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
586                                         jme->tx_ring_size, GFP_ATOMIC);
587         if (unlikely(!(txring->bufinf)))
588                 goto err_free_txring;
589
590         /*
591          * Initialize Transmit Descriptors
592          */
593         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
594         memset(txring->bufinf, 0,
595                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
596
597         return 0;
598
599 err_free_txring:
600         dma_free_coherent(&(jme->pdev->dev),
601                           TX_RING_ALLOC_SIZE(jme->tx_ring_size),
602                           txring->alloc,
603                           txring->dmaalloc);
604
605 err_set_null:
606         txring->desc = NULL;
607         txring->dmaalloc = 0;
608         txring->dma = 0;
609         txring->bufinf = NULL;
610
611         return -ENOMEM;
612 }
613
614 static void
615 jme_free_tx_resources(struct jme_adapter *jme)
616 {
617         int i;
618         struct jme_ring *txring = &(jme->txring[0]);
619         struct jme_buffer_info *txbi;
620
621         if (txring->alloc) {
622                 if (txring->bufinf) {
623                         for (i = 0 ; i < jme->tx_ring_size ; ++i) {
624                                 txbi = txring->bufinf + i;
625                                 if (txbi->skb) {
626                                         dev_kfree_skb(txbi->skb);
627                                         txbi->skb = NULL;
628                                 }
629                                 txbi->mapping           = 0;
630                                 txbi->len               = 0;
631                                 txbi->nr_desc           = 0;
632                                 txbi->start_xmit        = 0;
633                         }
634                         kfree(txring->bufinf);
635                 }
636
637                 dma_free_coherent(&(jme->pdev->dev),
638                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
639                                   txring->alloc,
640                                   txring->dmaalloc);
641
642                 txring->alloc           = NULL;
643                 txring->desc            = NULL;
644                 txring->dmaalloc        = 0;
645                 txring->dma             = 0;
646                 txring->bufinf          = NULL;
647         }
648         txring->next_to_use     = 0;
649         atomic_set(&txring->next_to_clean, 0);
650         atomic_set(&txring->nr_free, 0);
651 }
652
653 static inline void
654 jme_enable_tx_engine(struct jme_adapter *jme)
655 {
656         /*
657          * Select Queue 0
658          */
659         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
660         wmb();
661
662         /*
663          * Setup TX Queue 0 DMA Bass Address
664          */
665         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
666         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
667         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
668
669         /*
670          * Setup TX Descptor Count
671          */
672         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
673
674         /*
675          * Enable TX Engine
676          */
677         wmb();
678         jwrite32f(jme, JME_TXCS, jme->reg_txcs |
679                                 TXCS_SELECT_QUEUE0 |
680                                 TXCS_ENABLE);
681
682         /*
683          * Start clock for TX MAC Processor
684          */
685         jme_mac_txclk_on(jme);
686 }
687
688 static inline void
689 jme_restart_tx_engine(struct jme_adapter *jme)
690 {
691         /*
692          * Restart TX Engine
693          */
694         jwrite32(jme, JME_TXCS, jme->reg_txcs |
695                                 TXCS_SELECT_QUEUE0 |
696                                 TXCS_ENABLE);
697 }
698
699 static inline void
700 jme_disable_tx_engine(struct jme_adapter *jme)
701 {
702         int i;
703         u32 val;
704
705         /*
706          * Disable TX Engine
707          */
708         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
709         wmb();
710
711         val = jread32(jme, JME_TXCS);
712         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
713                 mdelay(1);
714                 val = jread32(jme, JME_TXCS);
715                 rmb();
716         }
717
718         if (!i)
719                 pr_err("Disable TX engine timeout\n");
720
721         /*
722          * Stop clock for TX MAC Processor
723          */
724         jme_mac_txclk_off(jme);
725 }
726
727 static void
728 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
729 {
730         struct jme_ring *rxring = &(jme->rxring[0]);
731         register struct rxdesc *rxdesc = rxring->desc;
732         struct jme_buffer_info *rxbi = rxring->bufinf;
733         rxdesc += i;
734         rxbi += i;
735
736         rxdesc->dw[0] = 0;
737         rxdesc->dw[1] = 0;
738         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
739         rxdesc->desc1.bufaddrl  = cpu_to_le32(
740                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
741         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
742         if (jme->dev->features & NETIF_F_HIGHDMA)
743                 rxdesc->desc1.flags = RXFLAG_64BIT;
744         wmb();
745         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
746 }
747
748 static int
749 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
750 {
751         struct jme_ring *rxring = &(jme->rxring[0]);
752         struct jme_buffer_info *rxbi = rxring->bufinf + i;
753         struct sk_buff *skb;
754
755         skb = netdev_alloc_skb(jme->dev,
756                 jme->dev->mtu + RX_EXTRA_LEN);
757         if (unlikely(!skb))
758                 return -ENOMEM;
759
760         rxbi->skb = skb;
761         rxbi->len = skb_tailroom(skb);
762         rxbi->mapping = pci_map_page(jme->pdev,
763                                         virt_to_page(skb->data),
764                                         offset_in_page(skb->data),
765                                         rxbi->len,
766                                         PCI_DMA_FROMDEVICE);
767
768         return 0;
769 }
770
771 static void
772 jme_free_rx_buf(struct jme_adapter *jme, int i)
773 {
774         struct jme_ring *rxring = &(jme->rxring[0]);
775         struct jme_buffer_info *rxbi = rxring->bufinf;
776         rxbi += i;
777
778         if (rxbi->skb) {
779                 pci_unmap_page(jme->pdev,
780                                  rxbi->mapping,
781                                  rxbi->len,
782                                  PCI_DMA_FROMDEVICE);
783                 dev_kfree_skb(rxbi->skb);
784                 rxbi->skb = NULL;
785                 rxbi->mapping = 0;
786                 rxbi->len = 0;
787         }
788 }
789
790 static void
791 jme_free_rx_resources(struct jme_adapter *jme)
792 {
793         int i;
794         struct jme_ring *rxring = &(jme->rxring[0]);
795
796         if (rxring->alloc) {
797                 if (rxring->bufinf) {
798                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
799                                 jme_free_rx_buf(jme, i);
800                         kfree(rxring->bufinf);
801                 }
802
803                 dma_free_coherent(&(jme->pdev->dev),
804                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
805                                   rxring->alloc,
806                                   rxring->dmaalloc);
807                 rxring->alloc    = NULL;
808                 rxring->desc     = NULL;
809                 rxring->dmaalloc = 0;
810                 rxring->dma      = 0;
811                 rxring->bufinf   = NULL;
812         }
813         rxring->next_to_use   = 0;
814         atomic_set(&rxring->next_to_clean, 0);
815 }
816
817 static int
818 jme_setup_rx_resources(struct jme_adapter *jme)
819 {
820         int i;
821         struct jme_ring *rxring = &(jme->rxring[0]);
822
823         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
824                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
825                                    &(rxring->dmaalloc),
826                                    GFP_ATOMIC);
827         if (!rxring->alloc)
828                 goto err_set_null;
829
830         /*
831          * 16 Bytes align
832          */
833         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
834                                                 RING_DESC_ALIGN);
835         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
836         rxring->next_to_use     = 0;
837         atomic_set(&rxring->next_to_clean, 0);
838
839         rxring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
840                                         jme->rx_ring_size, GFP_ATOMIC);
841         if (unlikely(!(rxring->bufinf)))
842                 goto err_free_rxring;
843
844         /*
845          * Initiallize Receive Descriptors
846          */
847         memset(rxring->bufinf, 0,
848                 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
849         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
850                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
851                         jme_free_rx_resources(jme);
852                         return -ENOMEM;
853                 }
854
855                 jme_set_clean_rxdesc(jme, i);
856         }
857
858         return 0;
859
860 err_free_rxring:
861         dma_free_coherent(&(jme->pdev->dev),
862                           RX_RING_ALLOC_SIZE(jme->rx_ring_size),
863                           rxring->alloc,
864                           rxring->dmaalloc);
865 err_set_null:
866         rxring->desc = NULL;
867         rxring->dmaalloc = 0;
868         rxring->dma = 0;
869         rxring->bufinf = NULL;
870
871         return -ENOMEM;
872 }
873
874 static inline void
875 jme_enable_rx_engine(struct jme_adapter *jme)
876 {
877         /*
878          * Select Queue 0
879          */
880         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
881                                 RXCS_QUEUESEL_Q0);
882         wmb();
883
884         /*
885          * Setup RX DMA Bass Address
886          */
887         jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
888         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
889         jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
890
891         /*
892          * Setup RX Descriptor Count
893          */
894         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
895
896         /*
897          * Setup Unicast Filter
898          */
899         jme_set_unicastaddr(jme->dev);
900         jme_set_multi(jme->dev);
901
902         /*
903          * Enable RX Engine
904          */
905         wmb();
906         jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
907                                 RXCS_QUEUESEL_Q0 |
908                                 RXCS_ENABLE |
909                                 RXCS_QST);
910
911         /*
912          * Start clock for RX MAC Processor
913          */
914         jme_mac_rxclk_on(jme);
915 }
916
917 static inline void
918 jme_restart_rx_engine(struct jme_adapter *jme)
919 {
920         /*
921          * Start RX Engine
922          */
923         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
924                                 RXCS_QUEUESEL_Q0 |
925                                 RXCS_ENABLE |
926                                 RXCS_QST);
927 }
928
929 static inline void
930 jme_disable_rx_engine(struct jme_adapter *jme)
931 {
932         int i;
933         u32 val;
934
935         /*
936          * Disable RX Engine
937          */
938         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
939         wmb();
940
941         val = jread32(jme, JME_RXCS);
942         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
943                 mdelay(1);
944                 val = jread32(jme, JME_RXCS);
945                 rmb();
946         }
947
948         if (!i)
949                 pr_err("Disable RX engine timeout\n");
950
951         /*
952          * Stop clock for RX MAC Processor
953          */
954         jme_mac_rxclk_off(jme);
955 }
956
957 static u16
958 jme_udpsum(struct sk_buff *skb)
959 {
960         u16 csum = 0xFFFFu;
961
962         if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
963                 return csum;
964         if (skb->protocol != htons(ETH_P_IP))
965                 return csum;
966         skb_set_network_header(skb, ETH_HLEN);
967         if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
968             (skb->len < (ETH_HLEN +
969                         (ip_hdr(skb)->ihl << 2) +
970                         sizeof(struct udphdr)))) {
971                 skb_reset_network_header(skb);
972                 return csum;
973         }
974         skb_set_transport_header(skb,
975                         ETH_HLEN + (ip_hdr(skb)->ihl << 2));
976         csum = udp_hdr(skb)->check;
977         skb_reset_transport_header(skb);
978         skb_reset_network_header(skb);
979
980         return csum;
981 }
982
983 static int
984 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
985 {
986         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
987                 return false;
988
989         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
990                         == RXWBFLAG_TCPON)) {
991                 if (flags & RXWBFLAG_IPV4)
992                         netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
993                 return false;
994         }
995
996         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
997                         == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
998                 if (flags & RXWBFLAG_IPV4)
999                         netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1000                 return false;
1001         }
1002
1003         if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1004                         == RXWBFLAG_IPV4)) {
1005                 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1006                 return false;
1007         }
1008
1009         return true;
1010 }
1011
1012 static void
1013 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1014 {
1015         struct jme_ring *rxring = &(jme->rxring[0]);
1016         struct rxdesc *rxdesc = rxring->desc;
1017         struct jme_buffer_info *rxbi = rxring->bufinf;
1018         struct sk_buff *skb;
1019         int framesize;
1020
1021         rxdesc += idx;
1022         rxbi += idx;
1023
1024         skb = rxbi->skb;
1025         pci_dma_sync_single_for_cpu(jme->pdev,
1026                                         rxbi->mapping,
1027                                         rxbi->len,
1028                                         PCI_DMA_FROMDEVICE);
1029
1030         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1031                 pci_dma_sync_single_for_device(jme->pdev,
1032                                                 rxbi->mapping,
1033                                                 rxbi->len,
1034                                                 PCI_DMA_FROMDEVICE);
1035
1036                 ++(NET_STAT(jme).rx_dropped);
1037         } else {
1038                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1039                                 - RX_PREPAD_SIZE;
1040
1041                 skb_reserve(skb, RX_PREPAD_SIZE);
1042                 skb_put(skb, framesize);
1043                 skb->protocol = eth_type_trans(skb, jme->dev);
1044
1045                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1046                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1047                 else
1048                         skb_checksum_none_assert(skb);
1049
1050                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1051                         if (jme->vlgrp) {
1052                                 jme->jme_vlan_rx(skb, jme->vlgrp,
1053                                         le16_to_cpu(rxdesc->descwb.vlan));
1054                                 NET_STAT(jme).rx_bytes += 4;
1055                         } else {
1056                                 dev_kfree_skb(skb);
1057                         }
1058                 } else {
1059                         jme->jme_rx(skb);
1060                 }
1061
1062                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1063                     cpu_to_le16(RXWBFLAG_DEST_MUL))
1064                         ++(NET_STAT(jme).multicast);
1065
1066                 NET_STAT(jme).rx_bytes += framesize;
1067                 ++(NET_STAT(jme).rx_packets);
1068         }
1069
1070         jme_set_clean_rxdesc(jme, idx);
1071
1072 }
1073
1074 static int
1075 jme_process_receive(struct jme_adapter *jme, int limit)
1076 {
1077         struct jme_ring *rxring = &(jme->rxring[0]);
1078         struct rxdesc *rxdesc = rxring->desc;
1079         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1080
1081         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1082                 goto out_inc;
1083
1084         if (unlikely(atomic_read(&jme->link_changing) != 1))
1085                 goto out_inc;
1086
1087         if (unlikely(!netif_carrier_ok(jme->dev)))
1088                 goto out_inc;
1089
1090         i = atomic_read(&rxring->next_to_clean);
1091         while (limit > 0) {
1092                 rxdesc = rxring->desc;
1093                 rxdesc += i;
1094
1095                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1096                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1097                         goto out;
1098                 --limit;
1099
1100                 rmb();
1101                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1102
1103                 if (unlikely(desccnt > 1 ||
1104                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1105
1106                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1107                                 ++(NET_STAT(jme).rx_crc_errors);
1108                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1109                                 ++(NET_STAT(jme).rx_fifo_errors);
1110                         else
1111                                 ++(NET_STAT(jme).rx_errors);
1112
1113                         if (desccnt > 1)
1114                                 limit -= desccnt - 1;
1115
1116                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1117                                 jme_set_clean_rxdesc(jme, j);
1118                                 j = (j + 1) & (mask);
1119                         }
1120
1121                 } else {
1122                         jme_alloc_and_feed_skb(jme, i);
1123                 }
1124
1125                 i = (i + desccnt) & (mask);
1126         }
1127
1128 out:
1129         atomic_set(&rxring->next_to_clean, i);
1130
1131 out_inc:
1132         atomic_inc(&jme->rx_cleaning);
1133
1134         return limit > 0 ? limit : 0;
1135
1136 }
1137
1138 static void
1139 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1140 {
1141         if (likely(atmp == dpi->cur)) {
1142                 dpi->cnt = 0;
1143                 return;
1144         }
1145
1146         if (dpi->attempt == atmp) {
1147                 ++(dpi->cnt);
1148         } else {
1149                 dpi->attempt = atmp;
1150                 dpi->cnt = 0;
1151         }
1152
1153 }
1154
1155 static void
1156 jme_dynamic_pcc(struct jme_adapter *jme)
1157 {
1158         register struct dynpcc_info *dpi = &(jme->dpi);
1159
1160         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1161                 jme_attempt_pcc(dpi, PCC_P3);
1162         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1163                  dpi->intr_cnt > PCC_INTR_THRESHOLD)
1164                 jme_attempt_pcc(dpi, PCC_P2);
1165         else
1166                 jme_attempt_pcc(dpi, PCC_P1);
1167
1168         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1169                 if (dpi->attempt < dpi->cur)
1170                         tasklet_schedule(&jme->rxclean_task);
1171                 jme_set_rx_pcc(jme, dpi->attempt);
1172                 dpi->cur = dpi->attempt;
1173                 dpi->cnt = 0;
1174         }
1175 }
1176
1177 static void
1178 jme_start_pcc_timer(struct jme_adapter *jme)
1179 {
1180         struct dynpcc_info *dpi = &(jme->dpi);
1181         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1182         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1183         dpi->intr_cnt           = 0;
1184         jwrite32(jme, JME_TMCSR,
1185                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1186 }
1187
1188 static inline void
1189 jme_stop_pcc_timer(struct jme_adapter *jme)
1190 {
1191         jwrite32(jme, JME_TMCSR, 0);
1192 }
1193
1194 static void
1195 jme_shutdown_nic(struct jme_adapter *jme)
1196 {
1197         u32 phylink;
1198
1199         phylink = jme_linkstat_from_phy(jme);
1200
1201         if (!(phylink & PHY_LINK_UP)) {
1202                 /*
1203                  * Disable all interrupt before issue timer
1204                  */
1205                 jme_stop_irq(jme);
1206                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1207         }
1208 }
1209
1210 static void
1211 jme_pcc_tasklet(unsigned long arg)
1212 {
1213         struct jme_adapter *jme = (struct jme_adapter *)arg;
1214         struct net_device *netdev = jme->dev;
1215
1216         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1217                 jme_shutdown_nic(jme);
1218                 return;
1219         }
1220
1221         if (unlikely(!netif_carrier_ok(netdev) ||
1222                 (atomic_read(&jme->link_changing) != 1)
1223         )) {
1224                 jme_stop_pcc_timer(jme);
1225                 return;
1226         }
1227
1228         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1229                 jme_dynamic_pcc(jme);
1230
1231         jme_start_pcc_timer(jme);
1232 }
1233
1234 static inline void
1235 jme_polling_mode(struct jme_adapter *jme)
1236 {
1237         jme_set_rx_pcc(jme, PCC_OFF);
1238 }
1239
1240 static inline void
1241 jme_interrupt_mode(struct jme_adapter *jme)
1242 {
1243         jme_set_rx_pcc(jme, PCC_P1);
1244 }
1245
1246 static inline int
1247 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1248 {
1249         u32 apmc;
1250         apmc = jread32(jme, JME_APMC);
1251         return apmc & JME_APMC_PSEUDO_HP_EN;
1252 }
1253
1254 static void
1255 jme_start_shutdown_timer(struct jme_adapter *jme)
1256 {
1257         u32 apmc;
1258
1259         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1260         apmc &= ~JME_APMC_EPIEN_CTRL;
1261         if (!no_extplug) {
1262                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1263                 wmb();
1264         }
1265         jwrite32f(jme, JME_APMC, apmc);
1266
1267         jwrite32f(jme, JME_TIMER2, 0);
1268         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1269         jwrite32(jme, JME_TMCSR,
1270                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1271 }
1272
1273 static void
1274 jme_stop_shutdown_timer(struct jme_adapter *jme)
1275 {
1276         u32 apmc;
1277
1278         jwrite32f(jme, JME_TMCSR, 0);
1279         jwrite32f(jme, JME_TIMER2, 0);
1280         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1281
1282         apmc = jread32(jme, JME_APMC);
1283         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1284         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1285         wmb();
1286         jwrite32f(jme, JME_APMC, apmc);
1287 }
1288
1289 static void
1290 jme_link_change_tasklet(unsigned long arg)
1291 {
1292         struct jme_adapter *jme = (struct jme_adapter *)arg;
1293         struct net_device *netdev = jme->dev;
1294         int rc;
1295
1296         while (!atomic_dec_and_test(&jme->link_changing)) {
1297                 atomic_inc(&jme->link_changing);
1298                 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1299                 while (atomic_read(&jme->link_changing) != 1)
1300                         netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1301         }
1302
1303         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1304                 goto out;
1305
1306         jme->old_mtu = netdev->mtu;
1307         netif_stop_queue(netdev);
1308         if (jme_pseudo_hotplug_enabled(jme))
1309                 jme_stop_shutdown_timer(jme);
1310
1311         jme_stop_pcc_timer(jme);
1312         tasklet_disable(&jme->txclean_task);
1313         tasklet_disable(&jme->rxclean_task);
1314         tasklet_disable(&jme->rxempty_task);
1315
1316         if (netif_carrier_ok(netdev)) {
1317                 jme_disable_rx_engine(jme);
1318                 jme_disable_tx_engine(jme);
1319                 jme_reset_mac_processor(jme);
1320                 jme_free_rx_resources(jme);
1321                 jme_free_tx_resources(jme);
1322
1323                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1324                         jme_polling_mode(jme);
1325
1326                 netif_carrier_off(netdev);
1327         }
1328
1329         jme_check_link(netdev, 0);
1330         if (netif_carrier_ok(netdev)) {
1331                 rc = jme_setup_rx_resources(jme);
1332                 if (rc) {
1333                         pr_err("Allocating resources for RX error, Device STOPPED!\n");
1334                         goto out_enable_tasklet;
1335                 }
1336
1337                 rc = jme_setup_tx_resources(jme);
1338                 if (rc) {
1339                         pr_err("Allocating resources for TX error, Device STOPPED!\n");
1340                         goto err_out_free_rx_resources;
1341                 }
1342
1343                 jme_enable_rx_engine(jme);
1344                 jme_enable_tx_engine(jme);
1345
1346                 netif_start_queue(netdev);
1347
1348                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1349                         jme_interrupt_mode(jme);
1350
1351                 jme_start_pcc_timer(jme);
1352         } else if (jme_pseudo_hotplug_enabled(jme)) {
1353                 jme_start_shutdown_timer(jme);
1354         }
1355
1356         goto out_enable_tasklet;
1357
1358 err_out_free_rx_resources:
1359         jme_free_rx_resources(jme);
1360 out_enable_tasklet:
1361         tasklet_enable(&jme->txclean_task);
1362         tasklet_hi_enable(&jme->rxclean_task);
1363         tasklet_hi_enable(&jme->rxempty_task);
1364 out:
1365         atomic_inc(&jme->link_changing);
1366 }
1367
1368 static void
1369 jme_rx_clean_tasklet(unsigned long arg)
1370 {
1371         struct jme_adapter *jme = (struct jme_adapter *)arg;
1372         struct dynpcc_info *dpi = &(jme->dpi);
1373
1374         jme_process_receive(jme, jme->rx_ring_size);
1375         ++(dpi->intr_cnt);
1376
1377 }
1378
1379 static int
1380 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1381 {
1382         struct jme_adapter *jme = jme_napi_priv(holder);
1383         int rest;
1384
1385         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1386
1387         while (atomic_read(&jme->rx_empty) > 0) {
1388                 atomic_dec(&jme->rx_empty);
1389                 ++(NET_STAT(jme).rx_dropped);
1390                 jme_restart_rx_engine(jme);
1391         }
1392         atomic_inc(&jme->rx_empty);
1393
1394         if (rest) {
1395                 JME_RX_COMPLETE(netdev, holder);
1396                 jme_interrupt_mode(jme);
1397         }
1398
1399         JME_NAPI_WEIGHT_SET(budget, rest);
1400         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1401 }
1402
1403 static void
1404 jme_rx_empty_tasklet(unsigned long arg)
1405 {
1406         struct jme_adapter *jme = (struct jme_adapter *)arg;
1407
1408         if (unlikely(atomic_read(&jme->link_changing) != 1))
1409                 return;
1410
1411         if (unlikely(!netif_carrier_ok(jme->dev)))
1412                 return;
1413
1414         netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1415
1416         jme_rx_clean_tasklet(arg);
1417
1418         while (atomic_read(&jme->rx_empty) > 0) {
1419                 atomic_dec(&jme->rx_empty);
1420                 ++(NET_STAT(jme).rx_dropped);
1421                 jme_restart_rx_engine(jme);
1422         }
1423         atomic_inc(&jme->rx_empty);
1424 }
1425
1426 static void
1427 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1428 {
1429         struct jme_ring *txring = &(jme->txring[0]);
1430
1431         smp_wmb();
1432         if (unlikely(netif_queue_stopped(jme->dev) &&
1433         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1434                 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1435                 netif_wake_queue(jme->dev);
1436         }
1437
1438 }
1439
1440 static void
1441 jme_tx_clean_tasklet(unsigned long arg)
1442 {
1443         struct jme_adapter *jme = (struct jme_adapter *)arg;
1444         struct jme_ring *txring = &(jme->txring[0]);
1445         struct txdesc *txdesc = txring->desc;
1446         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1447         int i, j, cnt = 0, max, err, mask;
1448
1449         tx_dbg(jme, "Into txclean\n");
1450
1451         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1452                 goto out;
1453
1454         if (unlikely(atomic_read(&jme->link_changing) != 1))
1455                 goto out;
1456
1457         if (unlikely(!netif_carrier_ok(jme->dev)))
1458                 goto out;
1459
1460         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1461         mask = jme->tx_ring_mask;
1462
1463         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1464
1465                 ctxbi = txbi + i;
1466
1467                 if (likely(ctxbi->skb &&
1468                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1469
1470                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1471                                i, ctxbi->nr_desc, jiffies);
1472
1473                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1474
1475                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1476                                 ttxbi = txbi + ((i + j) & (mask));
1477                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1478
1479                                 pci_unmap_page(jme->pdev,
1480                                                  ttxbi->mapping,
1481                                                  ttxbi->len,
1482                                                  PCI_DMA_TODEVICE);
1483
1484                                 ttxbi->mapping = 0;
1485                                 ttxbi->len = 0;
1486                         }
1487
1488                         dev_kfree_skb(ctxbi->skb);
1489
1490                         cnt += ctxbi->nr_desc;
1491
1492                         if (unlikely(err)) {
1493                                 ++(NET_STAT(jme).tx_carrier_errors);
1494                         } else {
1495                                 ++(NET_STAT(jme).tx_packets);
1496                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1497                         }
1498
1499                         ctxbi->skb = NULL;
1500                         ctxbi->len = 0;
1501                         ctxbi->start_xmit = 0;
1502
1503                 } else {
1504                         break;
1505                 }
1506
1507                 i = (i + ctxbi->nr_desc) & mask;
1508
1509                 ctxbi->nr_desc = 0;
1510         }
1511
1512         tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1513         atomic_set(&txring->next_to_clean, i);
1514         atomic_add(cnt, &txring->nr_free);
1515
1516         jme_wake_queue_if_stopped(jme);
1517
1518 out:
1519         atomic_inc(&jme->tx_cleaning);
1520 }
1521
1522 static void
1523 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1524 {
1525         /*
1526          * Disable interrupt
1527          */
1528         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1529
1530         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1531                 /*
1532                  * Link change event is critical
1533                  * all other events are ignored
1534                  */
1535                 jwrite32(jme, JME_IEVE, intrstat);
1536                 tasklet_schedule(&jme->linkch_task);
1537                 goto out_reenable;
1538         }
1539
1540         if (intrstat & INTR_TMINTR) {
1541                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1542                 tasklet_schedule(&jme->pcc_task);
1543         }
1544
1545         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1546                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1547                 tasklet_schedule(&jme->txclean_task);
1548         }
1549
1550         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1551                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1552                                                      INTR_PCCRX0 |
1553                                                      INTR_RX0EMP)) |
1554                                         INTR_RX0);
1555         }
1556
1557         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1558                 if (intrstat & INTR_RX0EMP)
1559                         atomic_inc(&jme->rx_empty);
1560
1561                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1562                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1563                                 jme_polling_mode(jme);
1564                                 JME_RX_SCHEDULE(jme);
1565                         }
1566                 }
1567         } else {
1568                 if (intrstat & INTR_RX0EMP) {
1569                         atomic_inc(&jme->rx_empty);
1570                         tasklet_hi_schedule(&jme->rxempty_task);
1571                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1572                         tasklet_hi_schedule(&jme->rxclean_task);
1573                 }
1574         }
1575
1576 out_reenable:
1577         /*
1578          * Re-enable interrupt
1579          */
1580         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1581 }
1582
1583 static irqreturn_t
1584 jme_intr(int irq, void *dev_id)
1585 {
1586         struct net_device *netdev = dev_id;
1587         struct jme_adapter *jme = netdev_priv(netdev);
1588         u32 intrstat;
1589
1590         intrstat = jread32(jme, JME_IEVE);
1591
1592         /*
1593          * Check if it's really an interrupt for us
1594          */
1595         if (unlikely((intrstat & INTR_ENABLE) == 0))
1596                 return IRQ_NONE;
1597
1598         /*
1599          * Check if the device still exist
1600          */
1601         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1602                 return IRQ_NONE;
1603
1604         jme_intr_msi(jme, intrstat);
1605
1606         return IRQ_HANDLED;
1607 }
1608
1609 static irqreturn_t
1610 jme_msi(int irq, void *dev_id)
1611 {
1612         struct net_device *netdev = dev_id;
1613         struct jme_adapter *jme = netdev_priv(netdev);
1614         u32 intrstat;
1615
1616         intrstat = jread32(jme, JME_IEVE);
1617
1618         jme_intr_msi(jme, intrstat);
1619
1620         return IRQ_HANDLED;
1621 }
1622
1623 static void
1624 jme_reset_link(struct jme_adapter *jme)
1625 {
1626         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1627 }
1628
1629 static void
1630 jme_restart_an(struct jme_adapter *jme)
1631 {
1632         u32 bmcr;
1633
1634         spin_lock_bh(&jme->phy_lock);
1635         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1636         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1637         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1638         spin_unlock_bh(&jme->phy_lock);
1639 }
1640
1641 static int
1642 jme_request_irq(struct jme_adapter *jme)
1643 {
1644         int rc;
1645         struct net_device *netdev = jme->dev;
1646         irq_handler_t handler = jme_intr;
1647         int irq_flags = IRQF_SHARED;
1648
1649         if (!pci_enable_msi(jme->pdev)) {
1650                 set_bit(JME_FLAG_MSI, &jme->flags);
1651                 handler = jme_msi;
1652                 irq_flags = 0;
1653         }
1654
1655         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1656                           netdev);
1657         if (rc) {
1658                 netdev_err(netdev,
1659                            "Unable to request %s interrupt (return: %d)\n",
1660                            test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1661                            rc);
1662
1663                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1664                         pci_disable_msi(jme->pdev);
1665                         clear_bit(JME_FLAG_MSI, &jme->flags);
1666                 }
1667         } else {
1668                 netdev->irq = jme->pdev->irq;
1669         }
1670
1671         return rc;
1672 }
1673
1674 static void
1675 jme_free_irq(struct jme_adapter *jme)
1676 {
1677         free_irq(jme->pdev->irq, jme->dev);
1678         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1679                 pci_disable_msi(jme->pdev);
1680                 clear_bit(JME_FLAG_MSI, &jme->flags);
1681                 jme->dev->irq = jme->pdev->irq;
1682         }
1683 }
1684
1685 static inline void
1686 jme_new_phy_on(struct jme_adapter *jme)
1687 {
1688         u32 reg;
1689
1690         reg = jread32(jme, JME_PHY_PWR);
1691         reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1692                  PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1693         jwrite32(jme, JME_PHY_PWR, reg);
1694
1695         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1696         reg &= ~PE1_GPREG0_PBG;
1697         reg |= PE1_GPREG0_ENBG;
1698         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1699 }
1700
1701 static inline void
1702 jme_new_phy_off(struct jme_adapter *jme)
1703 {
1704         u32 reg;
1705
1706         reg = jread32(jme, JME_PHY_PWR);
1707         reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1708                PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1709         jwrite32(jme, JME_PHY_PWR, reg);
1710
1711         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1712         reg &= ~PE1_GPREG0_PBG;
1713         reg |= PE1_GPREG0_PDD3COLD;
1714         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1715 }
1716
1717 static inline void
1718 jme_phy_on(struct jme_adapter *jme)
1719 {
1720         u32 bmcr;
1721
1722         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1723         bmcr &= ~BMCR_PDOWN;
1724         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1725
1726         if (new_phy_power_ctrl(jme->chip_main_rev))
1727                 jme_new_phy_on(jme);
1728 }
1729
1730 static inline void
1731 jme_phy_off(struct jme_adapter *jme)
1732 {
1733         u32 bmcr;
1734
1735         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1736         bmcr |= BMCR_PDOWN;
1737         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1738
1739         if (new_phy_power_ctrl(jme->chip_main_rev))
1740                 jme_new_phy_off(jme);
1741 }
1742
1743 static int
1744 jme_open(struct net_device *netdev)
1745 {
1746         struct jme_adapter *jme = netdev_priv(netdev);
1747         int rc;
1748
1749         jme_clear_pm(jme);
1750         JME_NAPI_ENABLE(jme);
1751
1752         tasklet_enable(&jme->linkch_task);
1753         tasklet_enable(&jme->txclean_task);
1754         tasklet_hi_enable(&jme->rxclean_task);
1755         tasklet_hi_enable(&jme->rxempty_task);
1756
1757         rc = jme_request_irq(jme);
1758         if (rc)
1759                 goto err_out;
1760
1761         jme_start_irq(jme);
1762
1763         jme_phy_on(jme);
1764         if (test_bit(JME_FLAG_SSET, &jme->flags))
1765                 jme_set_settings(netdev, &jme->old_ecmd);
1766         else
1767                 jme_reset_phy_processor(jme);
1768
1769         jme_reset_link(jme);
1770
1771         return 0;
1772
1773 err_out:
1774         netif_stop_queue(netdev);
1775         netif_carrier_off(netdev);
1776         return rc;
1777 }
1778
1779 static void
1780 jme_set_100m_half(struct jme_adapter *jme)
1781 {
1782         u32 bmcr, tmp;
1783
1784         jme_phy_on(jme);
1785         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1786         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1787                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1788         tmp |= BMCR_SPEED100;
1789
1790         if (bmcr != tmp)
1791                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1792
1793         if (jme->fpgaver)
1794                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1795         else
1796                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1797 }
1798
1799 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1800 static void
1801 jme_wait_link(struct jme_adapter *jme)
1802 {
1803         u32 phylink, to = JME_WAIT_LINK_TIME;
1804
1805         mdelay(1000);
1806         phylink = jme_linkstat_from_phy(jme);
1807         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1808                 mdelay(10);
1809                 phylink = jme_linkstat_from_phy(jme);
1810         }
1811 }
1812
1813 static void
1814 jme_powersave_phy(struct jme_adapter *jme)
1815 {
1816         if (jme->reg_pmcs) {
1817                 jme_set_100m_half(jme);
1818                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1819                         jme_wait_link(jme);
1820                 jme_clear_pm(jme);
1821         } else {
1822                 jme_phy_off(jme);
1823         }
1824 }
1825
1826 static int
1827 jme_close(struct net_device *netdev)
1828 {
1829         struct jme_adapter *jme = netdev_priv(netdev);
1830
1831         netif_stop_queue(netdev);
1832         netif_carrier_off(netdev);
1833
1834         jme_stop_irq(jme);
1835         jme_free_irq(jme);
1836
1837         JME_NAPI_DISABLE(jme);
1838
1839         tasklet_disable(&jme->linkch_task);
1840         tasklet_disable(&jme->txclean_task);
1841         tasklet_disable(&jme->rxclean_task);
1842         tasklet_disable(&jme->rxempty_task);
1843
1844         jme_disable_rx_engine(jme);
1845         jme_disable_tx_engine(jme);
1846         jme_reset_mac_processor(jme);
1847         jme_free_rx_resources(jme);
1848         jme_free_tx_resources(jme);
1849         jme->phylink = 0;
1850         jme_phy_off(jme);
1851
1852         return 0;
1853 }
1854
1855 static int
1856 jme_alloc_txdesc(struct jme_adapter *jme,
1857                         struct sk_buff *skb)
1858 {
1859         struct jme_ring *txring = &(jme->txring[0]);
1860         int idx, nr_alloc, mask = jme->tx_ring_mask;
1861
1862         idx = txring->next_to_use;
1863         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1864
1865         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1866                 return -1;
1867
1868         atomic_sub(nr_alloc, &txring->nr_free);
1869
1870         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1871
1872         return idx;
1873 }
1874
1875 static void
1876 jme_fill_tx_map(struct pci_dev *pdev,
1877                 struct txdesc *txdesc,
1878                 struct jme_buffer_info *txbi,
1879                 struct page *page,
1880                 u32 page_offset,
1881                 u32 len,
1882                 u8 hidma)
1883 {
1884         dma_addr_t dmaaddr;
1885
1886         dmaaddr = pci_map_page(pdev,
1887                                 page,
1888                                 page_offset,
1889                                 len,
1890                                 PCI_DMA_TODEVICE);
1891
1892         pci_dma_sync_single_for_device(pdev,
1893                                        dmaaddr,
1894                                        len,
1895                                        PCI_DMA_TODEVICE);
1896
1897         txdesc->dw[0] = 0;
1898         txdesc->dw[1] = 0;
1899         txdesc->desc2.flags     = TXFLAG_OWN;
1900         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1901         txdesc->desc2.datalen   = cpu_to_le16(len);
1902         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1903         txdesc->desc2.bufaddrl  = cpu_to_le32(
1904                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1905
1906         txbi->mapping = dmaaddr;
1907         txbi->len = len;
1908 }
1909
1910 static void
1911 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1912 {
1913         struct jme_ring *txring = &(jme->txring[0]);
1914         struct txdesc *txdesc = txring->desc, *ctxdesc;
1915         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1916         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1917         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1918         int mask = jme->tx_ring_mask;
1919         struct skb_frag_struct *frag;
1920         u32 len;
1921
1922         for (i = 0 ; i < nr_frags ; ++i) {
1923                 frag = &skb_shinfo(skb)->frags[i];
1924                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1925                 ctxbi = txbi + ((idx + i + 2) & (mask));
1926
1927                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1928                                  frag->page_offset, frag->size, hidma);
1929         }
1930
1931         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1932         ctxdesc = txdesc + ((idx + 1) & (mask));
1933         ctxbi = txbi + ((idx + 1) & (mask));
1934         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1935                         offset_in_page(skb->data), len, hidma);
1936
1937 }
1938
1939 static int
1940 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1941 {
1942         if (unlikely(skb_shinfo(skb)->gso_size &&
1943                         skb_header_cloned(skb) &&
1944                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1945                 dev_kfree_skb(skb);
1946                 return -1;
1947         }
1948
1949         return 0;
1950 }
1951
1952 static int
1953 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1954 {
1955         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1956         if (*mss) {
1957                 *flags |= TXFLAG_LSEN;
1958
1959                 if (skb->protocol == htons(ETH_P_IP)) {
1960                         struct iphdr *iph = ip_hdr(skb);
1961
1962                         iph->check = 0;
1963                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1964                                                                 iph->daddr, 0,
1965                                                                 IPPROTO_TCP,
1966                                                                 0);
1967                 } else {
1968                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1969
1970                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1971                                                                 &ip6h->daddr, 0,
1972                                                                 IPPROTO_TCP,
1973                                                                 0);
1974                 }
1975
1976                 return 0;
1977         }
1978
1979         return 1;
1980 }
1981
1982 static void
1983 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1984 {
1985         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1986                 u8 ip_proto;
1987
1988                 switch (skb->protocol) {
1989                 case htons(ETH_P_IP):
1990                         ip_proto = ip_hdr(skb)->protocol;
1991                         break;
1992                 case htons(ETH_P_IPV6):
1993                         ip_proto = ipv6_hdr(skb)->nexthdr;
1994                         break;
1995                 default:
1996                         ip_proto = 0;
1997                         break;
1998                 }
1999
2000                 switch (ip_proto) {
2001                 case IPPROTO_TCP:
2002                         *flags |= TXFLAG_TCPCS;
2003                         break;
2004                 case IPPROTO_UDP:
2005                         *flags |= TXFLAG_UDPCS;
2006                         break;
2007                 default:
2008                         netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2009                         break;
2010                 }
2011         }
2012 }
2013
2014 static inline void
2015 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2016 {
2017         if (vlan_tx_tag_present(skb)) {
2018                 *flags |= TXFLAG_TAGON;
2019                 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2020         }
2021 }
2022
2023 static int
2024 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2025 {
2026         struct jme_ring *txring = &(jme->txring[0]);
2027         struct txdesc *txdesc;
2028         struct jme_buffer_info *txbi;
2029         u8 flags;
2030
2031         txdesc = (struct txdesc *)txring->desc + idx;
2032         txbi = txring->bufinf + idx;
2033
2034         txdesc->dw[0] = 0;
2035         txdesc->dw[1] = 0;
2036         txdesc->dw[2] = 0;
2037         txdesc->dw[3] = 0;
2038         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2039         /*
2040          * Set OWN bit at final.
2041          * When kernel transmit faster than NIC.
2042          * And NIC trying to send this descriptor before we tell
2043          * it to start sending this TX queue.
2044          * Other fields are already filled correctly.
2045          */
2046         wmb();
2047         flags = TXFLAG_OWN | TXFLAG_INT;
2048         /*
2049          * Set checksum flags while not tso
2050          */
2051         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2052                 jme_tx_csum(jme, skb, &flags);
2053         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2054         jme_map_tx_skb(jme, skb, idx);
2055         txdesc->desc1.flags = flags;
2056         /*
2057          * Set tx buffer info after telling NIC to send
2058          * For better tx_clean timing
2059          */
2060         wmb();
2061         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2062         txbi->skb = skb;
2063         txbi->len = skb->len;
2064         txbi->start_xmit = jiffies;
2065         if (!txbi->start_xmit)
2066                 txbi->start_xmit = (0UL-1);
2067
2068         return 0;
2069 }
2070
2071 static void
2072 jme_stop_queue_if_full(struct jme_adapter *jme)
2073 {
2074         struct jme_ring *txring = &(jme->txring[0]);
2075         struct jme_buffer_info *txbi = txring->bufinf;
2076         int idx = atomic_read(&txring->next_to_clean);
2077
2078         txbi += idx;
2079
2080         smp_wmb();
2081         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2082                 netif_stop_queue(jme->dev);
2083                 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2084                 smp_wmb();
2085                 if (atomic_read(&txring->nr_free)
2086                         >= (jme->tx_wake_threshold)) {
2087                         netif_wake_queue(jme->dev);
2088                         netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2089                 }
2090         }
2091
2092         if (unlikely(txbi->start_xmit &&
2093                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2094                         txbi->skb)) {
2095                 netif_stop_queue(jme->dev);
2096                 netif_info(jme, tx_queued, jme->dev,
2097                            "TX Queue Stopped %d@%lu\n", idx, jiffies);
2098         }
2099 }
2100
2101 /*
2102  * This function is already protected by netif_tx_lock()
2103  */
2104
2105 static netdev_tx_t
2106 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2107 {
2108         struct jme_adapter *jme = netdev_priv(netdev);
2109         int idx;
2110
2111         if (unlikely(jme_expand_header(jme, skb))) {
2112                 ++(NET_STAT(jme).tx_dropped);
2113                 return NETDEV_TX_OK;
2114         }
2115
2116         idx = jme_alloc_txdesc(jme, skb);
2117
2118         if (unlikely(idx < 0)) {
2119                 netif_stop_queue(netdev);
2120                 netif_err(jme, tx_err, jme->dev,
2121                           "BUG! Tx ring full when queue awake!\n");
2122
2123                 return NETDEV_TX_BUSY;
2124         }
2125
2126         jme_fill_tx_desc(jme, skb, idx);
2127
2128         jwrite32(jme, JME_TXCS, jme->reg_txcs |
2129                                 TXCS_SELECT_QUEUE0 |
2130                                 TXCS_QUEUE0S |
2131                                 TXCS_ENABLE);
2132
2133         tx_dbg(jme, "xmit: %d+%d@%lu\n",
2134                idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2135         jme_stop_queue_if_full(jme);
2136
2137         return NETDEV_TX_OK;
2138 }
2139
2140 static void
2141 jme_set_unicastaddr(struct net_device *netdev)
2142 {
2143         struct jme_adapter *jme = netdev_priv(netdev);
2144         u32 val;
2145
2146         val = (netdev->dev_addr[3] & 0xff) << 24 |
2147               (netdev->dev_addr[2] & 0xff) << 16 |
2148               (netdev->dev_addr[1] & 0xff) <<  8 |
2149               (netdev->dev_addr[0] & 0xff);
2150         jwrite32(jme, JME_RXUMA_LO, val);
2151         val = (netdev->dev_addr[5] & 0xff) << 8 |
2152               (netdev->dev_addr[4] & 0xff);
2153         jwrite32(jme, JME_RXUMA_HI, val);
2154 }
2155
2156 static int
2157 jme_set_macaddr(struct net_device *netdev, void *p)
2158 {
2159         struct jme_adapter *jme = netdev_priv(netdev);
2160         struct sockaddr *addr = p;
2161
2162         if (netif_running(netdev))
2163                 return -EBUSY;
2164
2165         spin_lock_bh(&jme->macaddr_lock);
2166         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2167         jme_set_unicastaddr(netdev);
2168         spin_unlock_bh(&jme->macaddr_lock);
2169
2170         return 0;
2171 }
2172
2173 static void
2174 jme_set_multi(struct net_device *netdev)
2175 {
2176         struct jme_adapter *jme = netdev_priv(netdev);
2177         u32 mc_hash[2] = {};
2178
2179         spin_lock_bh(&jme->rxmcs_lock);
2180
2181         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2182
2183         if (netdev->flags & IFF_PROMISC) {
2184                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2185         } else if (netdev->flags & IFF_ALLMULTI) {
2186                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2187         } else if (netdev->flags & IFF_MULTICAST) {
2188                 struct netdev_hw_addr *ha;
2189                 int bit_nr;
2190
2191                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2192                 netdev_for_each_mc_addr(ha, netdev) {
2193                         bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2194                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2195                 }
2196
2197                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2198                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2199         }
2200
2201         wmb();
2202         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2203
2204         spin_unlock_bh(&jme->rxmcs_lock);
2205 }
2206
2207 static int
2208 jme_change_mtu(struct net_device *netdev, int new_mtu)
2209 {
2210         struct jme_adapter *jme = netdev_priv(netdev);
2211
2212         if (new_mtu == jme->old_mtu)
2213                 return 0;
2214
2215         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2216                 ((new_mtu) < IPV6_MIN_MTU))
2217                 return -EINVAL;
2218
2219         if (new_mtu > 4000) {
2220                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2221                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2222                 jme_restart_rx_engine(jme);
2223         } else {
2224                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2225                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2226                 jme_restart_rx_engine(jme);
2227         }
2228
2229         netdev->mtu = new_mtu;
2230         netdev_update_features(netdev);
2231
2232         jme_reset_link(jme);
2233
2234         return 0;
2235 }
2236
2237 static void
2238 jme_tx_timeout(struct net_device *netdev)
2239 {
2240         struct jme_adapter *jme = netdev_priv(netdev);
2241
2242         jme->phylink = 0;
2243         jme_reset_phy_processor(jme);
2244         if (test_bit(JME_FLAG_SSET, &jme->flags))
2245                 jme_set_settings(netdev, &jme->old_ecmd);
2246
2247         /*
2248          * Force to Reset the link again
2249          */
2250         jme_reset_link(jme);
2251 }
2252
2253 static inline void jme_pause_rx(struct jme_adapter *jme)
2254 {
2255         atomic_dec(&jme->link_changing);
2256
2257         jme_set_rx_pcc(jme, PCC_OFF);
2258         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2259                 JME_NAPI_DISABLE(jme);
2260         } else {
2261                 tasklet_disable(&jme->rxclean_task);
2262                 tasklet_disable(&jme->rxempty_task);
2263         }
2264 }
2265
2266 static inline void jme_resume_rx(struct jme_adapter *jme)
2267 {
2268         struct dynpcc_info *dpi = &(jme->dpi);
2269
2270         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2271                 JME_NAPI_ENABLE(jme);
2272         } else {
2273                 tasklet_hi_enable(&jme->rxclean_task);
2274                 tasklet_hi_enable(&jme->rxempty_task);
2275         }
2276         dpi->cur                = PCC_P1;
2277         dpi->attempt            = PCC_P1;
2278         dpi->cnt                = 0;
2279         jme_set_rx_pcc(jme, PCC_P1);
2280
2281         atomic_inc(&jme->link_changing);
2282 }
2283
2284 static void
2285 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2286 {
2287         struct jme_adapter *jme = netdev_priv(netdev);
2288
2289         jme_pause_rx(jme);
2290         jme->vlgrp = grp;
2291         jme_resume_rx(jme);
2292 }
2293
2294 static void
2295 jme_get_drvinfo(struct net_device *netdev,
2296                      struct ethtool_drvinfo *info)
2297 {
2298         struct jme_adapter *jme = netdev_priv(netdev);
2299
2300         strcpy(info->driver, DRV_NAME);
2301         strcpy(info->version, DRV_VERSION);
2302         strcpy(info->bus_info, pci_name(jme->pdev));
2303 }
2304
2305 static int
2306 jme_get_regs_len(struct net_device *netdev)
2307 {
2308         return JME_REG_LEN;
2309 }
2310
2311 static void
2312 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2313 {
2314         int i;
2315
2316         for (i = 0 ; i < len ; i += 4)
2317                 p[i >> 2] = jread32(jme, reg + i);
2318 }
2319
2320 static void
2321 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2322 {
2323         int i;
2324         u16 *p16 = (u16 *)p;
2325
2326         for (i = 0 ; i < reg_nr ; ++i)
2327                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2328 }
2329
2330 static void
2331 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2332 {
2333         struct jme_adapter *jme = netdev_priv(netdev);
2334         u32 *p32 = (u32 *)p;
2335
2336         memset(p, 0xFF, JME_REG_LEN);
2337
2338         regs->version = 1;
2339         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2340
2341         p32 += 0x100 >> 2;
2342         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2343
2344         p32 += 0x100 >> 2;
2345         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2346
2347         p32 += 0x100 >> 2;
2348         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2349
2350         p32 += 0x100 >> 2;
2351         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2352 }
2353
2354 static int
2355 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2356 {
2357         struct jme_adapter *jme = netdev_priv(netdev);
2358
2359         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2360         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2361
2362         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2363                 ecmd->use_adaptive_rx_coalesce = false;
2364                 ecmd->rx_coalesce_usecs = 0;
2365                 ecmd->rx_max_coalesced_frames = 0;
2366                 return 0;
2367         }
2368
2369         ecmd->use_adaptive_rx_coalesce = true;
2370
2371         switch (jme->dpi.cur) {
2372         case PCC_P1:
2373                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2374                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2375                 break;
2376         case PCC_P2:
2377                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2378                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2379                 break;
2380         case PCC_P3:
2381                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2382                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2383                 break;
2384         default:
2385                 break;
2386         }
2387
2388         return 0;
2389 }
2390
2391 static int
2392 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2393 {
2394         struct jme_adapter *jme = netdev_priv(netdev);
2395         struct dynpcc_info *dpi = &(jme->dpi);
2396
2397         if (netif_running(netdev))
2398                 return -EBUSY;
2399
2400         if (ecmd->use_adaptive_rx_coalesce &&
2401             test_bit(JME_FLAG_POLL, &jme->flags)) {
2402                 clear_bit(JME_FLAG_POLL, &jme->flags);
2403                 jme->jme_rx = netif_rx;
2404                 jme->jme_vlan_rx = vlan_hwaccel_rx;
2405                 dpi->cur                = PCC_P1;
2406                 dpi->attempt            = PCC_P1;
2407                 dpi->cnt                = 0;
2408                 jme_set_rx_pcc(jme, PCC_P1);
2409                 jme_interrupt_mode(jme);
2410         } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2411                    !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2412                 set_bit(JME_FLAG_POLL, &jme->flags);
2413                 jme->jme_rx = netif_receive_skb;
2414                 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2415                 jme_interrupt_mode(jme);
2416         }
2417
2418         return 0;
2419 }
2420
2421 static void
2422 jme_get_pauseparam(struct net_device *netdev,
2423                         struct ethtool_pauseparam *ecmd)
2424 {
2425         struct jme_adapter *jme = netdev_priv(netdev);
2426         u32 val;
2427
2428         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2429         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2430
2431         spin_lock_bh(&jme->phy_lock);
2432         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2433         spin_unlock_bh(&jme->phy_lock);
2434
2435         ecmd->autoneg =
2436                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2437 }
2438
2439 static int
2440 jme_set_pauseparam(struct net_device *netdev,
2441                         struct ethtool_pauseparam *ecmd)
2442 {
2443         struct jme_adapter *jme = netdev_priv(netdev);
2444         u32 val;
2445
2446         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2447                 (ecmd->tx_pause != 0)) {
2448
2449                 if (ecmd->tx_pause)
2450                         jme->reg_txpfc |= TXPFC_PF_EN;
2451                 else
2452                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2453
2454                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2455         }
2456
2457         spin_lock_bh(&jme->rxmcs_lock);
2458         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2459                 (ecmd->rx_pause != 0)) {
2460
2461                 if (ecmd->rx_pause)
2462                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2463                 else
2464                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2465
2466                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2467         }
2468         spin_unlock_bh(&jme->rxmcs_lock);
2469
2470         spin_lock_bh(&jme->phy_lock);
2471         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2472         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2473                 (ecmd->autoneg != 0)) {
2474
2475                 if (ecmd->autoneg)
2476                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2477                 else
2478                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2479
2480                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2481                                 MII_ADVERTISE, val);
2482         }
2483         spin_unlock_bh(&jme->phy_lock);
2484
2485         return 0;
2486 }
2487
2488 static void
2489 jme_get_wol(struct net_device *netdev,
2490                 struct ethtool_wolinfo *wol)
2491 {
2492         struct jme_adapter *jme = netdev_priv(netdev);
2493
2494         wol->supported = WAKE_MAGIC | WAKE_PHY;
2495
2496         wol->wolopts = 0;
2497
2498         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2499                 wol->wolopts |= WAKE_PHY;
2500
2501         if (jme->reg_pmcs & PMCS_MFEN)
2502                 wol->wolopts |= WAKE_MAGIC;
2503
2504 }
2505
2506 static int
2507 jme_set_wol(struct net_device *netdev,
2508                 struct ethtool_wolinfo *wol)
2509 {
2510         struct jme_adapter *jme = netdev_priv(netdev);
2511
2512         if (wol->wolopts & (WAKE_MAGICSECURE |
2513                                 WAKE_UCAST |
2514                                 WAKE_MCAST |
2515                                 WAKE_BCAST |
2516                                 WAKE_ARP))
2517                 return -EOPNOTSUPP;
2518
2519         jme->reg_pmcs = 0;
2520
2521         if (wol->wolopts & WAKE_PHY)
2522                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2523
2524         if (wol->wolopts & WAKE_MAGIC)
2525                 jme->reg_pmcs |= PMCS_MFEN;
2526
2527         jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2528         device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2529
2530         return 0;
2531 }
2532
2533 static int
2534 jme_get_settings(struct net_device *netdev,
2535                      struct ethtool_cmd *ecmd)
2536 {
2537         struct jme_adapter *jme = netdev_priv(netdev);
2538         int rc;
2539
2540         spin_lock_bh(&jme->phy_lock);
2541         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2542         spin_unlock_bh(&jme->phy_lock);
2543         return rc;
2544 }
2545
2546 static int
2547 jme_set_settings(struct net_device *netdev,
2548                      struct ethtool_cmd *ecmd)
2549 {
2550         struct jme_adapter *jme = netdev_priv(netdev);
2551         int rc, fdc = 0;
2552
2553         if (ethtool_cmd_speed(ecmd) == SPEED_1000
2554             && ecmd->autoneg != AUTONEG_ENABLE)
2555                 return -EINVAL;
2556
2557         /*
2558          * Check If user changed duplex only while force_media.
2559          * Hardware would not generate link change interrupt.
2560          */
2561         if (jme->mii_if.force_media &&
2562         ecmd->autoneg != AUTONEG_ENABLE &&
2563         (jme->mii_if.full_duplex != ecmd->duplex))
2564                 fdc = 1;
2565
2566         spin_lock_bh(&jme->phy_lock);
2567         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2568         spin_unlock_bh(&jme->phy_lock);
2569
2570         if (!rc) {
2571                 if (fdc)
2572                         jme_reset_link(jme);
2573                 jme->old_ecmd = *ecmd;
2574                 set_bit(JME_FLAG_SSET, &jme->flags);
2575         }
2576
2577         return rc;
2578 }
2579
2580 static int
2581 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2582 {
2583         int rc;
2584         struct jme_adapter *jme = netdev_priv(netdev);
2585         struct mii_ioctl_data *mii_data = if_mii(rq);
2586         unsigned int duplex_chg;
2587
2588         if (cmd == SIOCSMIIREG) {
2589                 u16 val = mii_data->val_in;
2590                 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2591                     (val & BMCR_SPEED1000))
2592                         return -EINVAL;
2593         }
2594
2595         spin_lock_bh(&jme->phy_lock);
2596         rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2597         spin_unlock_bh(&jme->phy_lock);
2598
2599         if (!rc && (cmd == SIOCSMIIREG)) {
2600                 if (duplex_chg)
2601                         jme_reset_link(jme);
2602                 jme_get_settings(netdev, &jme->old_ecmd);
2603                 set_bit(JME_FLAG_SSET, &jme->flags);
2604         }
2605
2606         return rc;
2607 }
2608
2609 static u32
2610 jme_get_link(struct net_device *netdev)
2611 {
2612         struct jme_adapter *jme = netdev_priv(netdev);
2613         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2614 }
2615
2616 static u32
2617 jme_get_msglevel(struct net_device *netdev)
2618 {
2619         struct jme_adapter *jme = netdev_priv(netdev);
2620         return jme->msg_enable;
2621 }
2622
2623 static void
2624 jme_set_msglevel(struct net_device *netdev, u32 value)
2625 {
2626         struct jme_adapter *jme = netdev_priv(netdev);
2627         jme->msg_enable = value;
2628 }
2629
2630 static u32
2631 jme_fix_features(struct net_device *netdev, u32 features)
2632 {
2633         if (netdev->mtu > 1900)
2634                 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2635         return features;
2636 }
2637
2638 static int
2639 jme_set_features(struct net_device *netdev, u32 features)
2640 {
2641         struct jme_adapter *jme = netdev_priv(netdev);
2642
2643         spin_lock_bh(&jme->rxmcs_lock);
2644         if (features & NETIF_F_RXCSUM)
2645                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2646         else
2647                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2648         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2649         spin_unlock_bh(&jme->rxmcs_lock);
2650
2651         return 0;
2652 }
2653
2654 static int
2655 jme_nway_reset(struct net_device *netdev)
2656 {
2657         struct jme_adapter *jme = netdev_priv(netdev);
2658         jme_restart_an(jme);
2659         return 0;
2660 }
2661
2662 static u8
2663 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2664 {
2665         u32 val;
2666         int to;
2667
2668         val = jread32(jme, JME_SMBCSR);
2669         to = JME_SMB_BUSY_TIMEOUT;
2670         while ((val & SMBCSR_BUSY) && --to) {
2671                 msleep(1);
2672                 val = jread32(jme, JME_SMBCSR);
2673         }
2674         if (!to) {
2675                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2676                 return 0xFF;
2677         }
2678
2679         jwrite32(jme, JME_SMBINTF,
2680                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2681                 SMBINTF_HWRWN_READ |
2682                 SMBINTF_HWCMD);
2683
2684         val = jread32(jme, JME_SMBINTF);
2685         to = JME_SMB_BUSY_TIMEOUT;
2686         while ((val & SMBINTF_HWCMD) && --to) {
2687                 msleep(1);
2688                 val = jread32(jme, JME_SMBINTF);
2689         }
2690         if (!to) {
2691                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2692                 return 0xFF;
2693         }
2694
2695         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2696 }
2697
2698 static void
2699 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2700 {
2701         u32 val;
2702         int to;
2703
2704         val = jread32(jme, JME_SMBCSR);
2705         to = JME_SMB_BUSY_TIMEOUT;
2706         while ((val & SMBCSR_BUSY) && --to) {
2707                 msleep(1);
2708                 val = jread32(jme, JME_SMBCSR);
2709         }
2710         if (!to) {
2711                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2712                 return;
2713         }
2714
2715         jwrite32(jme, JME_SMBINTF,
2716                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2717                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2718                 SMBINTF_HWRWN_WRITE |
2719                 SMBINTF_HWCMD);
2720
2721         val = jread32(jme, JME_SMBINTF);
2722         to = JME_SMB_BUSY_TIMEOUT;
2723         while ((val & SMBINTF_HWCMD) && --to) {
2724                 msleep(1);
2725                 val = jread32(jme, JME_SMBINTF);
2726         }
2727         if (!to) {
2728                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2729                 return;
2730         }
2731
2732         mdelay(2);
2733 }
2734
2735 static int
2736 jme_get_eeprom_len(struct net_device *netdev)
2737 {
2738         struct jme_adapter *jme = netdev_priv(netdev);
2739         u32 val;
2740         val = jread32(jme, JME_SMBCSR);
2741         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2742 }
2743
2744 static int
2745 jme_get_eeprom(struct net_device *netdev,
2746                 struct ethtool_eeprom *eeprom, u8 *data)
2747 {
2748         struct jme_adapter *jme = netdev_priv(netdev);
2749         int i, offset = eeprom->offset, len = eeprom->len;
2750
2751         /*
2752          * ethtool will check the boundary for us
2753          */
2754         eeprom->magic = JME_EEPROM_MAGIC;
2755         for (i = 0 ; i < len ; ++i)
2756                 data[i] = jme_smb_read(jme, i + offset);
2757
2758         return 0;
2759 }
2760
2761 static int
2762 jme_set_eeprom(struct net_device *netdev,
2763                 struct ethtool_eeprom *eeprom, u8 *data)
2764 {
2765         struct jme_adapter *jme = netdev_priv(netdev);
2766         int i, offset = eeprom->offset, len = eeprom->len;
2767
2768         if (eeprom->magic != JME_EEPROM_MAGIC)
2769                 return -EINVAL;
2770
2771         /*
2772          * ethtool will check the boundary for us
2773          */
2774         for (i = 0 ; i < len ; ++i)
2775                 jme_smb_write(jme, i + offset, data[i]);
2776
2777         return 0;
2778 }
2779
2780 static const struct ethtool_ops jme_ethtool_ops = {
2781         .get_drvinfo            = jme_get_drvinfo,
2782         .get_regs_len           = jme_get_regs_len,
2783         .get_regs               = jme_get_regs,
2784         .get_coalesce           = jme_get_coalesce,
2785         .set_coalesce           = jme_set_coalesce,
2786         .get_pauseparam         = jme_get_pauseparam,
2787         .set_pauseparam         = jme_set_pauseparam,
2788         .get_wol                = jme_get_wol,
2789         .set_wol                = jme_set_wol,
2790         .get_settings           = jme_get_settings,
2791         .set_settings           = jme_set_settings,
2792         .get_link               = jme_get_link,
2793         .get_msglevel           = jme_get_msglevel,
2794         .set_msglevel           = jme_set_msglevel,
2795         .nway_reset             = jme_nway_reset,
2796         .get_eeprom_len         = jme_get_eeprom_len,
2797         .get_eeprom             = jme_get_eeprom,
2798         .set_eeprom             = jme_set_eeprom,
2799 };
2800
2801 static int
2802 jme_pci_dma64(struct pci_dev *pdev)
2803 {
2804         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2805             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2806                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2807                         return 1;
2808
2809         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2810             !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2811                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2812                         return 1;
2813
2814         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2815                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2816                         return 0;
2817
2818         return -1;
2819 }
2820
2821 static inline void
2822 jme_phy_init(struct jme_adapter *jme)
2823 {
2824         u16 reg26;
2825
2826         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2827         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2828 }
2829
2830 static inline void
2831 jme_check_hw_ver(struct jme_adapter *jme)
2832 {
2833         u32 chipmode;
2834
2835         chipmode = jread32(jme, JME_CHIPMODE);
2836
2837         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2838         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2839         jme->chip_main_rev = jme->chiprev & 0xF;
2840         jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2841 }
2842
2843 static const struct net_device_ops jme_netdev_ops = {
2844         .ndo_open               = jme_open,
2845         .ndo_stop               = jme_close,
2846         .ndo_validate_addr      = eth_validate_addr,
2847         .ndo_do_ioctl           = jme_ioctl,
2848         .ndo_start_xmit         = jme_start_xmit,
2849         .ndo_set_mac_address    = jme_set_macaddr,
2850         .ndo_set_multicast_list = jme_set_multi,
2851         .ndo_change_mtu         = jme_change_mtu,
2852         .ndo_tx_timeout         = jme_tx_timeout,
2853         .ndo_vlan_rx_register   = jme_vlan_rx_register,
2854         .ndo_fix_features       = jme_fix_features,
2855         .ndo_set_features       = jme_set_features,
2856 };
2857
2858 static int __devinit
2859 jme_init_one(struct pci_dev *pdev,
2860              const struct pci_device_id *ent)
2861 {
2862         int rc = 0, using_dac, i;
2863         struct net_device *netdev;
2864         struct jme_adapter *jme;
2865         u16 bmcr, bmsr;
2866         u32 apmc;
2867
2868         /*
2869          * set up PCI device basics
2870          */
2871         rc = pci_enable_device(pdev);
2872         if (rc) {
2873                 pr_err("Cannot enable PCI device\n");
2874                 goto err_out;
2875         }
2876
2877         using_dac = jme_pci_dma64(pdev);
2878         if (using_dac < 0) {
2879                 pr_err("Cannot set PCI DMA Mask\n");
2880                 rc = -EIO;
2881                 goto err_out_disable_pdev;
2882         }
2883
2884         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2885                 pr_err("No PCI resource region found\n");
2886                 rc = -ENOMEM;
2887                 goto err_out_disable_pdev;
2888         }
2889
2890         rc = pci_request_regions(pdev, DRV_NAME);
2891         if (rc) {
2892                 pr_err("Cannot obtain PCI resource region\n");
2893                 goto err_out_disable_pdev;
2894         }
2895
2896         pci_set_master(pdev);
2897
2898         /*
2899          * alloc and init net device
2900          */
2901         netdev = alloc_etherdev(sizeof(*jme));
2902         if (!netdev) {
2903                 pr_err("Cannot allocate netdev structure\n");
2904                 rc = -ENOMEM;
2905                 goto err_out_release_regions;
2906         }
2907         netdev->netdev_ops = &jme_netdev_ops;
2908         netdev->ethtool_ops             = &jme_ethtool_ops;
2909         netdev->watchdog_timeo          = TX_TIMEOUT;
2910         netdev->hw_features             =       NETIF_F_IP_CSUM |
2911                                                 NETIF_F_IPV6_CSUM |
2912                                                 NETIF_F_SG |
2913                                                 NETIF_F_TSO |
2914                                                 NETIF_F_TSO6 |
2915                                                 NETIF_F_RXCSUM;
2916         netdev->features                =       NETIF_F_IP_CSUM |
2917                                                 NETIF_F_IPV6_CSUM |
2918                                                 NETIF_F_SG |
2919                                                 NETIF_F_TSO |
2920                                                 NETIF_F_TSO6 |
2921                                                 NETIF_F_HW_VLAN_TX |
2922                                                 NETIF_F_HW_VLAN_RX;
2923         if (using_dac)
2924                 netdev->features        |=      NETIF_F_HIGHDMA;
2925
2926         SET_NETDEV_DEV(netdev, &pdev->dev);
2927         pci_set_drvdata(pdev, netdev);
2928
2929         /*
2930          * init adapter info
2931          */
2932         jme = netdev_priv(netdev);
2933         jme->pdev = pdev;
2934         jme->dev = netdev;
2935         jme->jme_rx = netif_rx;
2936         jme->jme_vlan_rx = vlan_hwaccel_rx;
2937         jme->old_mtu = netdev->mtu = 1500;
2938         jme->phylink = 0;
2939         jme->tx_ring_size = 1 << 10;
2940         jme->tx_ring_mask = jme->tx_ring_size - 1;
2941         jme->tx_wake_threshold = 1 << 9;
2942         jme->rx_ring_size = 1 << 9;
2943         jme->rx_ring_mask = jme->rx_ring_size - 1;
2944         jme->msg_enable = JME_DEF_MSG_ENABLE;
2945         jme->regs = ioremap(pci_resource_start(pdev, 0),
2946                              pci_resource_len(pdev, 0));
2947         if (!(jme->regs)) {
2948                 pr_err("Mapping PCI resource region error\n");
2949                 rc = -ENOMEM;
2950                 goto err_out_free_netdev;
2951         }
2952
2953         if (no_pseudohp) {
2954                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2955                 jwrite32(jme, JME_APMC, apmc);
2956         } else if (force_pseudohp) {
2957                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2958                 jwrite32(jme, JME_APMC, apmc);
2959         }
2960
2961         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2962
2963         spin_lock_init(&jme->phy_lock);
2964         spin_lock_init(&jme->macaddr_lock);
2965         spin_lock_init(&jme->rxmcs_lock);
2966
2967         atomic_set(&jme->link_changing, 1);
2968         atomic_set(&jme->rx_cleaning, 1);
2969         atomic_set(&jme->tx_cleaning, 1);
2970         atomic_set(&jme->rx_empty, 1);
2971
2972         tasklet_init(&jme->pcc_task,
2973                      jme_pcc_tasklet,
2974                      (unsigned long) jme);
2975         tasklet_init(&jme->linkch_task,
2976                      jme_link_change_tasklet,
2977                      (unsigned long) jme);
2978         tasklet_init(&jme->txclean_task,
2979                      jme_tx_clean_tasklet,
2980                      (unsigned long) jme);
2981         tasklet_init(&jme->rxclean_task,
2982                      jme_rx_clean_tasklet,
2983                      (unsigned long) jme);
2984         tasklet_init(&jme->rxempty_task,
2985                      jme_rx_empty_tasklet,
2986                      (unsigned long) jme);
2987         tasklet_disable_nosync(&jme->linkch_task);
2988         tasklet_disable_nosync(&jme->txclean_task);
2989         tasklet_disable_nosync(&jme->rxclean_task);
2990         tasklet_disable_nosync(&jme->rxempty_task);
2991         jme->dpi.cur = PCC_P1;
2992
2993         jme->reg_ghc = 0;
2994         jme->reg_rxcs = RXCS_DEFAULT;
2995         jme->reg_rxmcs = RXMCS_DEFAULT;
2996         jme->reg_txpfc = 0;
2997         jme->reg_pmcs = PMCS_MFEN;
2998         jme->reg_gpreg1 = GPREG1_DEFAULT;
2999
3000         if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3001                 netdev->features |= NETIF_F_RXCSUM;
3002
3003         /*
3004          * Get Max Read Req Size from PCI Config Space
3005          */
3006         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3007         jme->mrrs &= PCI_DCSR_MRRS_MASK;
3008         switch (jme->mrrs) {
3009         case MRRS_128B:
3010                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3011                 break;
3012         case MRRS_256B:
3013                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3014                 break;
3015         default:
3016                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3017                 break;
3018         }
3019
3020         /*
3021          * Must check before reset_mac_processor
3022          */
3023         jme_check_hw_ver(jme);
3024         jme->mii_if.dev = netdev;
3025         if (jme->fpgaver) {
3026                 jme->mii_if.phy_id = 0;
3027                 for (i = 1 ; i < 32 ; ++i) {
3028                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3029                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3030                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3031                                 jme->mii_if.phy_id = i;
3032                                 break;
3033                         }
3034                 }
3035
3036                 if (!jme->mii_if.phy_id) {
3037                         rc = -EIO;
3038                         pr_err("Can not find phy_id\n");
3039                         goto err_out_unmap;
3040                 }
3041
3042                 jme->reg_ghc |= GHC_LINK_POLL;
3043         } else {
3044                 jme->mii_if.phy_id = 1;
3045         }
3046         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3047                 jme->mii_if.supports_gmii = true;
3048         else
3049                 jme->mii_if.supports_gmii = false;
3050         jme->mii_if.phy_id_mask = 0x1F;
3051         jme->mii_if.reg_num_mask = 0x1F;
3052         jme->mii_if.mdio_read = jme_mdio_read;
3053         jme->mii_if.mdio_write = jme_mdio_write;
3054
3055         jme_clear_pm(jme);
3056         pci_set_power_state(jme->pdev, PCI_D0);
3057         device_set_wakeup_enable(&pdev->dev, true);
3058
3059         jme_set_phyfifo_5level(jme);
3060         jme->pcirev = pdev->revision;
3061         if (!jme->fpgaver)
3062                 jme_phy_init(jme);
3063         jme_phy_off(jme);
3064
3065         /*
3066          * Reset MAC processor and reload EEPROM for MAC Address
3067          */
3068         jme_reset_mac_processor(jme);
3069         rc = jme_reload_eeprom(jme);
3070         if (rc) {
3071                 pr_err("Reload eeprom for reading MAC Address error\n");
3072                 goto err_out_unmap;
3073         }
3074         jme_load_macaddr(netdev);
3075
3076         /*
3077          * Tell stack that we are not ready to work until open()
3078          */
3079         netif_carrier_off(netdev);
3080
3081         rc = register_netdev(netdev);
3082         if (rc) {
3083                 pr_err("Cannot register net device\n");
3084                 goto err_out_unmap;
3085         }
3086
3087         netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3088                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3089                    "JMC250 Gigabit Ethernet" :
3090                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3091                    "JMC260 Fast Ethernet" : "Unknown",
3092                    (jme->fpgaver != 0) ? " (FPGA)" : "",
3093                    (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3094                    jme->pcirev, netdev->dev_addr);
3095
3096         return 0;
3097
3098 err_out_unmap:
3099         iounmap(jme->regs);
3100 err_out_free_netdev:
3101         pci_set_drvdata(pdev, NULL);
3102         free_netdev(netdev);
3103 err_out_release_regions:
3104         pci_release_regions(pdev);
3105 err_out_disable_pdev:
3106         pci_disable_device(pdev);
3107 err_out:
3108         return rc;
3109 }
3110
3111 static void __devexit
3112 jme_remove_one(struct pci_dev *pdev)
3113 {
3114         struct net_device *netdev = pci_get_drvdata(pdev);
3115         struct jme_adapter *jme = netdev_priv(netdev);
3116
3117         unregister_netdev(netdev);
3118         iounmap(jme->regs);
3119         pci_set_drvdata(pdev, NULL);
3120         free_netdev(netdev);
3121         pci_release_regions(pdev);
3122         pci_disable_device(pdev);
3123
3124 }
3125
3126 static void
3127 jme_shutdown(struct pci_dev *pdev)
3128 {
3129         struct net_device *netdev = pci_get_drvdata(pdev);
3130         struct jme_adapter *jme = netdev_priv(netdev);
3131
3132         jme_powersave_phy(jme);
3133         pci_pme_active(pdev, true);
3134 }
3135
3136 #ifdef CONFIG_PM_SLEEP
3137 static int
3138 jme_suspend(struct device *dev)
3139 {
3140         struct pci_dev *pdev = to_pci_dev(dev);
3141         struct net_device *netdev = pci_get_drvdata(pdev);
3142         struct jme_adapter *jme = netdev_priv(netdev);
3143
3144         atomic_dec(&jme->link_changing);
3145
3146         netif_device_detach(netdev);
3147         netif_stop_queue(netdev);
3148         jme_stop_irq(jme);
3149
3150         tasklet_disable(&jme->txclean_task);
3151         tasklet_disable(&jme->rxclean_task);
3152         tasklet_disable(&jme->rxempty_task);
3153
3154         if (netif_carrier_ok(netdev)) {
3155                 if (test_bit(JME_FLAG_POLL, &jme->flags))
3156                         jme_polling_mode(jme);
3157
3158                 jme_stop_pcc_timer(jme);
3159                 jme_disable_rx_engine(jme);
3160                 jme_disable_tx_engine(jme);
3161                 jme_reset_mac_processor(jme);
3162                 jme_free_rx_resources(jme);
3163                 jme_free_tx_resources(jme);
3164                 netif_carrier_off(netdev);
3165                 jme->phylink = 0;
3166         }
3167
3168         tasklet_enable(&jme->txclean_task);
3169         tasklet_hi_enable(&jme->rxclean_task);
3170         tasklet_hi_enable(&jme->rxempty_task);
3171
3172         jme_powersave_phy(jme);
3173
3174         return 0;
3175 }
3176
3177 static int
3178 jme_resume(struct device *dev)
3179 {
3180         struct pci_dev *pdev = to_pci_dev(dev);
3181         struct net_device *netdev = pci_get_drvdata(pdev);
3182         struct jme_adapter *jme = netdev_priv(netdev);
3183
3184         jme_clear_pm(jme);
3185         jme_phy_on(jme);
3186         if (test_bit(JME_FLAG_SSET, &jme->flags))
3187                 jme_set_settings(netdev, &jme->old_ecmd);
3188         else
3189                 jme_reset_phy_processor(jme);
3190
3191         jme_start_irq(jme);
3192         netif_device_attach(netdev);
3193
3194         atomic_inc(&jme->link_changing);
3195
3196         jme_reset_link(jme);
3197
3198         return 0;
3199 }
3200
3201 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3202 #define JME_PM_OPS (&jme_pm_ops)
3203
3204 #else
3205
3206 #define JME_PM_OPS NULL
3207 #endif
3208
3209 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3210         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3211         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3212         { }
3213 };
3214
3215 static struct pci_driver jme_driver = {
3216         .name           = DRV_NAME,
3217         .id_table       = jme_pci_tbl,
3218         .probe          = jme_init_one,
3219         .remove         = __devexit_p(jme_remove_one),
3220         .shutdown       = jme_shutdown,
3221         .driver.pm      = JME_PM_OPS,
3222 };
3223
3224 static int __init
3225 jme_init_module(void)
3226 {
3227         pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3228         return pci_register_driver(&jme_driver);
3229 }
3230
3231 static void __exit
3232 jme_cleanup_module(void)
3233 {
3234         pci_unregister_driver(&jme_driver);
3235 }
3236
3237 module_init(jme_init_module);
3238 module_exit(jme_cleanup_module);
3239
3240 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3241 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3242 MODULE_LICENSE("GPL");
3243 MODULE_VERSION(DRV_VERSION);
3244 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3245