2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
89 struct jme_adapter *jme = netdev_priv(netdev);
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
110 jme_reset_phy_processor(struct jme_adapter *jme)
114 jme_mdio_write(jme->dev,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
125 val = jme_mdio_read(jme->dev,
129 jme_mdio_write(jme->dev,
131 MII_BMCR, val | BMCR_RESET);
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 jwrite32(jme, JME_WFODP, crc);
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
158 jwrite32(jme, JME_WFODP, mask[i]);
164 jme_reset_mac_processor(struct jme_adapter *jme)
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
197 jme_reset_ghc_speed(struct jme_adapter *jme)
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
204 jme_clear_pm(struct jme_adapter *jme)
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
212 jme_reload_eeprom(struct jme_adapter *jme)
217 val = jread32(jme, JME_SMBCSR);
219 if (val & SMBCSR_EEPROMD) {
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
242 jme_load_macaddr(struct net_device *netdev)
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
295 jme_start_irq(struct jme_adapter *jme)
297 register struct dynpcc_info *dpi = &(jme->dpi);
299 jme_set_rx_pcc(jme, PCC_P1);
301 dpi->attempt = PCC_P1;
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
317 jme_stop_irq(struct jme_adapter *jme)
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
326 jme_linkstat_from_phy(struct jme_adapter *jme)
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if (bmsr & BMSR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
339 jme_set_phyfifoa(struct jme_adapter *jme)
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
345 jme_set_phyfifob(struct jme_adapter *jme)
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
351 jme_check_link(struct net_device *netdev, int testonly)
353 struct jme_adapter *jme = netdev_priv(netdev);
354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
361 phylink = jme_linkstat_from_phy(jme);
363 phylink = jread32(jme, JME_PHY_LINK);
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
371 phylink = PHY_LINK_UP;
373 bmcr = jme_mdio_read(jme->dev,
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
387 strcat(linkmsg, "Forced: ");
390 * Keep polling for speed/duplex resolve complete
392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
398 phylink = jme_linkstat_from_phy(jme);
400 phylink = jread32(jme, JME_PHY_LINK);
404 "Waiting speed resolve timeout.\n");
406 strcat(linkmsg, "ANed: ");
409 if (jme->phylink == phylink) {
416 jme->phylink = phylink;
418 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
419 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
420 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
421 switch (phylink & PHY_LINK_SPEED_MASK) {
422 case PHY_LINK_SPEED_10M:
423 ghc |= GHC_SPEED_10M |
424 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
425 strcat(linkmsg, "10 Mbps, ");
427 case PHY_LINK_SPEED_100M:
428 ghc |= GHC_SPEED_100M |
429 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
430 strcat(linkmsg, "100 Mbps, ");
432 case PHY_LINK_SPEED_1000M:
433 ghc |= GHC_SPEED_1000M |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
435 strcat(linkmsg, "1000 Mbps, ");
441 if (phylink & PHY_LINK_DUPLEX) {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifoa(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifob(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifoa(jme);
476 jwrite32(jme, JME_GPREG1, gpreg1);
477 jwrite32(jme, JME_GHC, ghc);
480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
486 msg_link(jme, "Link is up at %s.\n", linkmsg);
487 netif_carrier_on(netdev);
492 msg_link(jme, "Link is down.\n");
494 netif_carrier_off(netdev);
502 jme_setup_tx_resources(struct jme_adapter *jme)
504 struct jme_ring *txring = &(jme->txring[0]);
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
520 txring->next_to_use = 0;
521 atomic_set(&txring->next_to_clean, 0);
522 atomic_set(&txring->nr_free, jme->tx_ring_size);
524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
530 * Initialize Transmit Descriptors
532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
533 memset(txring->bufinf, 0,
534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
546 txring->dmaalloc = 0;
548 txring->bufinf = NULL;
554 jme_free_tx_resources(struct jme_adapter *jme)
557 struct jme_ring *txring = &(jme->txring[0]);
558 struct jme_buffer_info *txbi;
561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
565 dev_kfree_skb(txbi->skb);
571 txbi->start_xmit = 0;
573 kfree(txring->bufinf);
576 dma_free_coherent(&(jme->pdev->dev),
577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
581 txring->alloc = NULL;
583 txring->dmaalloc = 0;
585 txring->bufinf = NULL;
587 txring->next_to_use = 0;
588 atomic_set(&txring->next_to_clean, 0);
589 atomic_set(&txring->nr_free, 0);
593 jme_enable_tx_engine(struct jme_adapter *jme)
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
602 * Setup TX Queue 0 DMA Bass Address
604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
609 * Setup TX Descptor Count
611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
624 jme_restart_tx_engine(struct jme_adapter *jme)
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
635 jme_disable_tx_engine(struct jme_adapter *jme)
643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
646 val = jread32(jme, JME_TXCS);
647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
649 val = jread32(jme, JME_TXCS);
654 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
658 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
660 struct jme_ring *rxring = &(jme->rxring[0]);
661 register struct rxdesc *rxdesc = rxring->desc;
662 struct jme_buffer_info *rxbi = rxring->bufinf;
668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
672 if (jme->dev->features & NETIF_F_HIGHDMA)
673 rxdesc->desc1.flags = RXFLAG_64BIT;
675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
679 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
681 struct jme_ring *rxring = &(jme->rxring[0]);
682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
689 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
694 rxbi->len = skb_tailroom(skb);
695 rxbi->mapping = pci_map_page(jme->pdev,
696 virt_to_page(skb->data),
697 offset_in_page(skb->data),
705 jme_free_rx_buf(struct jme_adapter *jme, int i)
707 struct jme_ring *rxring = &(jme->rxring[0]);
708 struct jme_buffer_info *rxbi = rxring->bufinf;
712 pci_unmap_page(jme->pdev,
716 dev_kfree_skb(rxbi->skb);
724 jme_free_rx_resources(struct jme_adapter *jme)
727 struct jme_ring *rxring = &(jme->rxring[0]);
730 if (rxring->bufinf) {
731 for (i = 0 ; i < jme->rx_ring_size ; ++i)
732 jme_free_rx_buf(jme, i);
733 kfree(rxring->bufinf);
736 dma_free_coherent(&(jme->pdev->dev),
737 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
740 rxring->alloc = NULL;
742 rxring->dmaalloc = 0;
744 rxring->bufinf = NULL;
746 rxring->next_to_use = 0;
747 atomic_set(&rxring->next_to_clean, 0);
751 jme_setup_rx_resources(struct jme_adapter *jme)
754 struct jme_ring *rxring = &(jme->rxring[0]);
756 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
757 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
766 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
768 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
769 rxring->next_to_use = 0;
770 atomic_set(&rxring->next_to_clean, 0);
772 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
773 jme->rx_ring_size, GFP_ATOMIC);
774 if (unlikely(!(rxring->bufinf)))
775 goto err_free_rxring;
778 * Initiallize Receive Descriptors
780 memset(rxring->bufinf, 0,
781 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
782 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
783 if (unlikely(jme_make_new_rx_buf(jme, i))) {
784 jme_free_rx_resources(jme);
788 jme_set_clean_rxdesc(jme, i);
794 dma_free_coherent(&(jme->pdev->dev),
795 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
800 rxring->dmaalloc = 0;
802 rxring->bufinf = NULL;
808 jme_enable_rx_engine(struct jme_adapter *jme)
813 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
818 * Setup RX DMA Bass Address
820 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
821 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
822 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
825 * Setup RX Descriptor Count
827 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
830 * Setup Unicast Filter
832 jme_set_multi(jme->dev);
838 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
845 jme_restart_rx_engine(struct jme_adapter *jme)
850 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
857 jme_disable_rx_engine(struct jme_adapter *jme)
865 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
868 val = jread32(jme, JME_RXCS);
869 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
871 val = jread32(jme, JME_RXCS);
876 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
881 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
883 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
886 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
887 == RXWBFLAG_TCPON)) {
888 if (flags & RXWBFLAG_IPV4)
889 msg_rx_err(jme, "TCP Checksum error\n");
893 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
894 == RXWBFLAG_UDPON)) {
895 if (flags & RXWBFLAG_IPV4)
896 msg_rx_err(jme, "UDP Checksum error.\n");
900 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
902 msg_rx_err(jme, "IPv4 Checksum error.\n");
910 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
912 struct jme_ring *rxring = &(jme->rxring[0]);
913 struct rxdesc *rxdesc = rxring->desc;
914 struct jme_buffer_info *rxbi = rxring->bufinf;
922 pci_dma_sync_single_for_cpu(jme->pdev,
927 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
928 pci_dma_sync_single_for_device(jme->pdev,
933 ++(NET_STAT(jme).rx_dropped);
935 framesize = le16_to_cpu(rxdesc->descwb.framesize)
938 skb_reserve(skb, RX_PREPAD_SIZE);
939 skb_put(skb, framesize);
940 skb->protocol = eth_type_trans(skb, jme->dev);
942 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
943 skb->ip_summed = CHECKSUM_UNNECESSARY;
945 skb->ip_summed = CHECKSUM_NONE;
947 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
949 jme->jme_vlan_rx(skb, jme->vlgrp,
950 le16_to_cpu(rxdesc->descwb.vlan));
951 NET_STAT(jme).rx_bytes += 4;
957 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
958 cpu_to_le16(RXWBFLAG_DEST_MUL))
959 ++(NET_STAT(jme).multicast);
961 NET_STAT(jme).rx_bytes += framesize;
962 ++(NET_STAT(jme).rx_packets);
965 jme_set_clean_rxdesc(jme, idx);
970 jme_process_receive(struct jme_adapter *jme, int limit)
972 struct jme_ring *rxring = &(jme->rxring[0]);
973 struct rxdesc *rxdesc = rxring->desc;
974 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
976 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
979 if (unlikely(atomic_read(&jme->link_changing) != 1))
982 if (unlikely(!netif_carrier_ok(jme->dev)))
985 i = atomic_read(&rxring->next_to_clean);
987 rxdesc = rxring->desc;
990 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
991 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
995 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
997 if (unlikely(desccnt > 1 ||
998 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1000 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1001 ++(NET_STAT(jme).rx_crc_errors);
1002 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1003 ++(NET_STAT(jme).rx_fifo_errors);
1005 ++(NET_STAT(jme).rx_errors);
1008 limit -= desccnt - 1;
1010 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1011 jme_set_clean_rxdesc(jme, j);
1012 j = (j + 1) & (mask);
1016 jme_alloc_and_feed_skb(jme, i);
1019 i = (i + desccnt) & (mask);
1023 atomic_set(&rxring->next_to_clean, i);
1026 atomic_inc(&jme->rx_cleaning);
1028 return limit > 0 ? limit : 0;
1033 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1035 if (likely(atmp == dpi->cur)) {
1040 if (dpi->attempt == atmp) {
1043 dpi->attempt = atmp;
1050 jme_dynamic_pcc(struct jme_adapter *jme)
1052 register struct dynpcc_info *dpi = &(jme->dpi);
1054 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1055 jme_attempt_pcc(dpi, PCC_P3);
1056 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1057 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1058 jme_attempt_pcc(dpi, PCC_P2);
1060 jme_attempt_pcc(dpi, PCC_P1);
1062 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1063 if (dpi->attempt < dpi->cur)
1064 tasklet_schedule(&jme->rxclean_task);
1065 jme_set_rx_pcc(jme, dpi->attempt);
1066 dpi->cur = dpi->attempt;
1072 jme_start_pcc_timer(struct jme_adapter *jme)
1074 struct dynpcc_info *dpi = &(jme->dpi);
1075 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1076 dpi->last_pkts = NET_STAT(jme).rx_packets;
1078 jwrite32(jme, JME_TMCSR,
1079 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1083 jme_stop_pcc_timer(struct jme_adapter *jme)
1085 jwrite32(jme, JME_TMCSR, 0);
1089 jme_shutdown_nic(struct jme_adapter *jme)
1093 phylink = jme_linkstat_from_phy(jme);
1095 if (!(phylink & PHY_LINK_UP)) {
1097 * Disable all interrupt before issue timer
1100 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1105 jme_pcc_tasklet(unsigned long arg)
1107 struct jme_adapter *jme = (struct jme_adapter *)arg;
1108 struct net_device *netdev = jme->dev;
1110 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1111 jme_shutdown_nic(jme);
1115 if (unlikely(!netif_carrier_ok(netdev) ||
1116 (atomic_read(&jme->link_changing) != 1)
1118 jme_stop_pcc_timer(jme);
1122 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1123 jme_dynamic_pcc(jme);
1125 jme_start_pcc_timer(jme);
1129 jme_polling_mode(struct jme_adapter *jme)
1131 jme_set_rx_pcc(jme, PCC_OFF);
1135 jme_interrupt_mode(struct jme_adapter *jme)
1137 jme_set_rx_pcc(jme, PCC_P1);
1141 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1144 apmc = jread32(jme, JME_APMC);
1145 return apmc & JME_APMC_PSEUDO_HP_EN;
1149 jme_start_shutdown_timer(struct jme_adapter *jme)
1153 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1154 apmc &= ~JME_APMC_EPIEN_CTRL;
1156 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1159 jwrite32f(jme, JME_APMC, apmc);
1161 jwrite32f(jme, JME_TIMER2, 0);
1162 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1163 jwrite32(jme, JME_TMCSR,
1164 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1168 jme_stop_shutdown_timer(struct jme_adapter *jme)
1172 jwrite32f(jme, JME_TMCSR, 0);
1173 jwrite32f(jme, JME_TIMER2, 0);
1174 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1176 apmc = jread32(jme, JME_APMC);
1177 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1178 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1180 jwrite32f(jme, JME_APMC, apmc);
1184 jme_link_change_tasklet(unsigned long arg)
1186 struct jme_adapter *jme = (struct jme_adapter *)arg;
1187 struct net_device *netdev = jme->dev;
1190 while (!atomic_dec_and_test(&jme->link_changing)) {
1191 atomic_inc(&jme->link_changing);
1192 msg_intr(jme, "Get link change lock failed.\n");
1193 while (atomic_read(&jme->link_changing) != 1)
1194 msg_intr(jme, "Waiting link change lock.\n");
1197 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1200 jme->old_mtu = netdev->mtu;
1201 netif_stop_queue(netdev);
1202 if (jme_pseudo_hotplug_enabled(jme))
1203 jme_stop_shutdown_timer(jme);
1205 jme_stop_pcc_timer(jme);
1206 tasklet_disable(&jme->txclean_task);
1207 tasklet_disable(&jme->rxclean_task);
1208 tasklet_disable(&jme->rxempty_task);
1210 if (netif_carrier_ok(netdev)) {
1211 jme_reset_ghc_speed(jme);
1212 jme_disable_rx_engine(jme);
1213 jme_disable_tx_engine(jme);
1214 jme_reset_mac_processor(jme);
1215 jme_free_rx_resources(jme);
1216 jme_free_tx_resources(jme);
1218 if (test_bit(JME_FLAG_POLL, &jme->flags))
1219 jme_polling_mode(jme);
1221 netif_carrier_off(netdev);
1224 jme_check_link(netdev, 0);
1225 if (netif_carrier_ok(netdev)) {
1226 rc = jme_setup_rx_resources(jme);
1228 jeprintk(jme->pdev, "Allocating resources for RX error"
1229 ", Device STOPPED!\n");
1230 goto out_enable_tasklet;
1233 rc = jme_setup_tx_resources(jme);
1235 jeprintk(jme->pdev, "Allocating resources for TX error"
1236 ", Device STOPPED!\n");
1237 goto err_out_free_rx_resources;
1240 jme_enable_rx_engine(jme);
1241 jme_enable_tx_engine(jme);
1243 netif_start_queue(netdev);
1245 if (test_bit(JME_FLAG_POLL, &jme->flags))
1246 jme_interrupt_mode(jme);
1248 jme_start_pcc_timer(jme);
1249 } else if (jme_pseudo_hotplug_enabled(jme)) {
1250 jme_start_shutdown_timer(jme);
1253 goto out_enable_tasklet;
1255 err_out_free_rx_resources:
1256 jme_free_rx_resources(jme);
1258 tasklet_enable(&jme->txclean_task);
1259 tasklet_hi_enable(&jme->rxclean_task);
1260 tasklet_hi_enable(&jme->rxempty_task);
1262 atomic_inc(&jme->link_changing);
1266 jme_rx_clean_tasklet(unsigned long arg)
1268 struct jme_adapter *jme = (struct jme_adapter *)arg;
1269 struct dynpcc_info *dpi = &(jme->dpi);
1271 jme_process_receive(jme, jme->rx_ring_size);
1277 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1279 struct jme_adapter *jme = jme_napi_priv(holder);
1283 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1285 while (atomic_read(&jme->rx_empty) > 0) {
1286 atomic_dec(&jme->rx_empty);
1287 ++(NET_STAT(jme).rx_dropped);
1288 jme_restart_rx_engine(jme);
1290 atomic_inc(&jme->rx_empty);
1293 JME_RX_COMPLETE(netdev, holder);
1294 jme_interrupt_mode(jme);
1297 JME_NAPI_WEIGHT_SET(budget, rest);
1298 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1302 jme_rx_empty_tasklet(unsigned long arg)
1304 struct jme_adapter *jme = (struct jme_adapter *)arg;
1306 if (unlikely(atomic_read(&jme->link_changing) != 1))
1309 if (unlikely(!netif_carrier_ok(jme->dev)))
1312 msg_rx_status(jme, "RX Queue Full!\n");
1314 jme_rx_clean_tasklet(arg);
1316 while (atomic_read(&jme->rx_empty) > 0) {
1317 atomic_dec(&jme->rx_empty);
1318 ++(NET_STAT(jme).rx_dropped);
1319 jme_restart_rx_engine(jme);
1321 atomic_inc(&jme->rx_empty);
1325 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1327 struct jme_ring *txring = &(jme->txring[0]);
1330 if (unlikely(netif_queue_stopped(jme->dev) &&
1331 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1332 msg_tx_done(jme, "TX Queue Waked.\n");
1333 netif_wake_queue(jme->dev);
1339 jme_tx_clean_tasklet(unsigned long arg)
1341 struct jme_adapter *jme = (struct jme_adapter *)arg;
1342 struct jme_ring *txring = &(jme->txring[0]);
1343 struct txdesc *txdesc = txring->desc;
1344 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1345 int i, j, cnt = 0, max, err, mask;
1347 tx_dbg(jme, "Into txclean.\n");
1349 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1352 if (unlikely(atomic_read(&jme->link_changing) != 1))
1355 if (unlikely(!netif_carrier_ok(jme->dev)))
1358 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1359 mask = jme->tx_ring_mask;
1361 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1365 if (likely(ctxbi->skb &&
1366 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1368 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1369 i, ctxbi->nr_desc, jiffies);
1371 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1373 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1374 ttxbi = txbi + ((i + j) & (mask));
1375 txdesc[(i + j) & (mask)].dw[0] = 0;
1377 pci_unmap_page(jme->pdev,
1386 dev_kfree_skb(ctxbi->skb);
1388 cnt += ctxbi->nr_desc;
1390 if (unlikely(err)) {
1391 ++(NET_STAT(jme).tx_carrier_errors);
1393 ++(NET_STAT(jme).tx_packets);
1394 NET_STAT(jme).tx_bytes += ctxbi->len;
1399 ctxbi->start_xmit = 0;
1405 i = (i + ctxbi->nr_desc) & mask;
1410 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1411 atomic_set(&txring->next_to_clean, i);
1412 atomic_add(cnt, &txring->nr_free);
1414 jme_wake_queue_if_stopped(jme);
1417 atomic_inc(&jme->tx_cleaning);
1421 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1426 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1428 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1430 * Link change event is critical
1431 * all other events are ignored
1433 jwrite32(jme, JME_IEVE, intrstat);
1434 tasklet_schedule(&jme->linkch_task);
1438 if (intrstat & INTR_TMINTR) {
1439 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1440 tasklet_schedule(&jme->pcc_task);
1443 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1444 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1445 tasklet_schedule(&jme->txclean_task);
1448 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1449 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1455 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1456 if (intrstat & INTR_RX0EMP)
1457 atomic_inc(&jme->rx_empty);
1459 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1460 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1461 jme_polling_mode(jme);
1462 JME_RX_SCHEDULE(jme);
1466 if (intrstat & INTR_RX0EMP) {
1467 atomic_inc(&jme->rx_empty);
1468 tasklet_hi_schedule(&jme->rxempty_task);
1469 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1470 tasklet_hi_schedule(&jme->rxclean_task);
1476 * Re-enable interrupt
1478 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1481 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1483 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1486 jme_intr(int irq, void *dev_id)
1489 struct net_device *netdev = dev_id;
1490 struct jme_adapter *jme = netdev_priv(netdev);
1493 intrstat = jread32(jme, JME_IEVE);
1496 * Check if it's really an interrupt for us
1498 if (unlikely((intrstat & INTR_ENABLE) == 0))
1502 * Check if the device still exist
1504 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1507 jme_intr_msi(jme, intrstat);
1512 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1514 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1517 jme_msi(int irq, void *dev_id)
1520 struct net_device *netdev = dev_id;
1521 struct jme_adapter *jme = netdev_priv(netdev);
1524 intrstat = jread32(jme, JME_IEVE);
1526 jme_intr_msi(jme, intrstat);
1532 jme_reset_link(struct jme_adapter *jme)
1534 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1538 jme_restart_an(struct jme_adapter *jme)
1542 spin_lock_bh(&jme->phy_lock);
1543 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1544 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1545 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1546 spin_unlock_bh(&jme->phy_lock);
1550 jme_request_irq(struct jme_adapter *jme)
1553 struct net_device *netdev = jme->dev;
1554 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1555 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1556 int irq_flags = SA_SHIRQ;
1558 irq_handler_t handler = jme_intr;
1559 int irq_flags = IRQF_SHARED;
1562 if (!pci_enable_msi(jme->pdev)) {
1563 set_bit(JME_FLAG_MSI, &jme->flags);
1568 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1572 "Unable to request %s interrupt (return: %d)\n",
1573 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1576 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1577 pci_disable_msi(jme->pdev);
1578 clear_bit(JME_FLAG_MSI, &jme->flags);
1581 netdev->irq = jme->pdev->irq;
1588 jme_free_irq(struct jme_adapter *jme)
1590 free_irq(jme->pdev->irq, jme->dev);
1591 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1592 pci_disable_msi(jme->pdev);
1593 clear_bit(JME_FLAG_MSI, &jme->flags);
1594 jme->dev->irq = jme->pdev->irq;
1599 jme_open(struct net_device *netdev)
1601 struct jme_adapter *jme = netdev_priv(netdev);
1605 JME_NAPI_ENABLE(jme);
1607 tasklet_enable(&jme->linkch_task);
1608 tasklet_enable(&jme->txclean_task);
1609 tasklet_hi_enable(&jme->rxclean_task);
1610 tasklet_hi_enable(&jme->rxempty_task);
1612 rc = jme_request_irq(jme);
1618 if (test_bit(JME_FLAG_SSET, &jme->flags))
1619 jme_set_settings(netdev, &jme->old_ecmd);
1621 jme_reset_phy_processor(jme);
1623 jme_reset_link(jme);
1628 netif_stop_queue(netdev);
1629 netif_carrier_off(netdev);
1635 jme_set_100m_half(struct jme_adapter *jme)
1639 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1640 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1641 BMCR_SPEED1000 | BMCR_FULLDPLX);
1642 tmp |= BMCR_SPEED100;
1645 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1648 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1650 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1653 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1655 jme_wait_link(struct jme_adapter *jme)
1657 u32 phylink, to = JME_WAIT_LINK_TIME;
1660 phylink = jme_linkstat_from_phy(jme);
1661 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1663 phylink = jme_linkstat_from_phy(jme);
1669 jme_phy_off(struct jme_adapter *jme)
1671 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1675 jme_close(struct net_device *netdev)
1677 struct jme_adapter *jme = netdev_priv(netdev);
1679 netif_stop_queue(netdev);
1680 netif_carrier_off(netdev);
1685 JME_NAPI_DISABLE(jme);
1687 tasklet_disable(&jme->linkch_task);
1688 tasklet_disable(&jme->txclean_task);
1689 tasklet_disable(&jme->rxclean_task);
1690 tasklet_disable(&jme->rxempty_task);
1692 jme_reset_ghc_speed(jme);
1693 jme_disable_rx_engine(jme);
1694 jme_disable_tx_engine(jme);
1695 jme_reset_mac_processor(jme);
1696 jme_free_rx_resources(jme);
1697 jme_free_tx_resources(jme);
1705 jme_alloc_txdesc(struct jme_adapter *jme,
1706 struct sk_buff *skb)
1708 struct jme_ring *txring = &(jme->txring[0]);
1709 int idx, nr_alloc, mask = jme->tx_ring_mask;
1711 idx = txring->next_to_use;
1712 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1714 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1717 atomic_sub(nr_alloc, &txring->nr_free);
1719 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1725 jme_fill_tx_map(struct pci_dev *pdev,
1726 struct txdesc *txdesc,
1727 struct jme_buffer_info *txbi,
1735 dmaaddr = pci_map_page(pdev,
1741 pci_dma_sync_single_for_device(pdev,
1748 txdesc->desc2.flags = TXFLAG_OWN;
1749 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1750 txdesc->desc2.datalen = cpu_to_le16(len);
1751 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1752 txdesc->desc2.bufaddrl = cpu_to_le32(
1753 (__u64)dmaaddr & 0xFFFFFFFFUL);
1755 txbi->mapping = dmaaddr;
1760 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1762 struct jme_ring *txring = &(jme->txring[0]);
1763 struct txdesc *txdesc = txring->desc, *ctxdesc;
1764 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1765 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1766 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1767 int mask = jme->tx_ring_mask;
1768 struct skb_frag_struct *frag;
1771 for (i = 0 ; i < nr_frags ; ++i) {
1772 frag = &skb_shinfo(skb)->frags[i];
1773 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1774 ctxbi = txbi + ((idx + i + 2) & (mask));
1776 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1777 frag->page_offset, frag->size, hidma);
1780 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1781 ctxdesc = txdesc + ((idx + 1) & (mask));
1782 ctxbi = txbi + ((idx + 1) & (mask));
1783 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1784 offset_in_page(skb->data), len, hidma);
1789 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1792 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1793 skb_shinfo(skb)->tso_size
1795 skb_shinfo(skb)->gso_size
1797 && skb_header_cloned(skb) &&
1798 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1807 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1809 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1810 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1812 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1815 *flags |= TXFLAG_LSEN;
1817 if (skb->protocol == htons(ETH_P_IP)) {
1818 struct iphdr *iph = ip_hdr(skb);
1821 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1826 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1828 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1841 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1843 #ifdef CHECKSUM_PARTIAL
1844 if (skb->ip_summed == CHECKSUM_PARTIAL)
1846 if (skb->ip_summed == CHECKSUM_HW)
1851 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1852 if (skb->protocol == htons(ETH_P_IP))
1853 ip_proto = ip_hdr(skb)->protocol;
1854 else if (skb->protocol == htons(ETH_P_IPV6))
1855 ip_proto = ipv6_hdr(skb)->nexthdr;
1859 switch (skb->protocol) {
1860 case htons(ETH_P_IP):
1861 ip_proto = ip_hdr(skb)->protocol;
1863 case htons(ETH_P_IPV6):
1864 ip_proto = ipv6_hdr(skb)->nexthdr;
1874 *flags |= TXFLAG_TCPCS;
1877 *flags |= TXFLAG_UDPCS;
1880 msg_tx_err(jme, "Error upper layer protocol.\n");
1887 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1889 if (vlan_tx_tag_present(skb)) {
1890 *flags |= TXFLAG_TAGON;
1891 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1896 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1898 struct jme_ring *txring = &(jme->txring[0]);
1899 struct txdesc *txdesc;
1900 struct jme_buffer_info *txbi;
1903 txdesc = (struct txdesc *)txring->desc + idx;
1904 txbi = txring->bufinf + idx;
1910 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1912 * Set OWN bit at final.
1913 * When kernel transmit faster than NIC.
1914 * And NIC trying to send this descriptor before we tell
1915 * it to start sending this TX queue.
1916 * Other fields are already filled correctly.
1919 flags = TXFLAG_OWN | TXFLAG_INT;
1921 * Set checksum flags while not tso
1923 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1924 jme_tx_csum(jme, skb, &flags);
1925 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1926 jme_map_tx_skb(jme, skb, idx);
1927 txdesc->desc1.flags = flags;
1929 * Set tx buffer info after telling NIC to send
1930 * For better tx_clean timing
1933 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1935 txbi->len = skb->len;
1936 txbi->start_xmit = jiffies;
1937 if (!txbi->start_xmit)
1938 txbi->start_xmit = (0UL-1);
1944 jme_stop_queue_if_full(struct jme_adapter *jme)
1946 struct jme_ring *txring = &(jme->txring[0]);
1947 struct jme_buffer_info *txbi = txring->bufinf;
1948 int idx = atomic_read(&txring->next_to_clean);
1953 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1954 netif_stop_queue(jme->dev);
1955 msg_tx_queued(jme, "TX Queue Paused.\n");
1957 if (atomic_read(&txring->nr_free)
1958 >= (jme->tx_wake_threshold)) {
1959 netif_wake_queue(jme->dev);
1960 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1964 if (unlikely(txbi->start_xmit &&
1965 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1967 netif_stop_queue(jme->dev);
1968 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1973 * This function is already protected by netif_tx_lock()
1977 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1979 struct jme_adapter *jme = netdev_priv(netdev);
1982 if (unlikely(jme_expand_header(jme, skb))) {
1983 ++(NET_STAT(jme).tx_dropped);
1984 return NETDEV_TX_OK;
1987 idx = jme_alloc_txdesc(jme, skb);
1989 if (unlikely(idx < 0)) {
1990 netif_stop_queue(netdev);
1991 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1993 return NETDEV_TX_BUSY;
1996 jme_fill_tx_desc(jme, skb, idx);
1998 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1999 TXCS_SELECT_QUEUE0 |
2002 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2003 netdev->trans_start = jiffies;
2006 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
2007 skb_shinfo(skb)->nr_frags + 2,
2009 jme_stop_queue_if_full(jme);
2011 return NETDEV_TX_OK;
2015 jme_set_macaddr(struct net_device *netdev, void *p)
2017 struct jme_adapter *jme = netdev_priv(netdev);
2018 struct sockaddr *addr = p;
2021 if (netif_running(netdev))
2024 spin_lock_bh(&jme->macaddr_lock);
2025 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2027 val = (addr->sa_data[3] & 0xff) << 24 |
2028 (addr->sa_data[2] & 0xff) << 16 |
2029 (addr->sa_data[1] & 0xff) << 8 |
2030 (addr->sa_data[0] & 0xff);
2031 jwrite32(jme, JME_RXUMA_LO, val);
2032 val = (addr->sa_data[5] & 0xff) << 8 |
2033 (addr->sa_data[4] & 0xff);
2034 jwrite32(jme, JME_RXUMA_HI, val);
2035 spin_unlock_bh(&jme->macaddr_lock);
2041 jme_set_multi(struct net_device *netdev)
2043 struct jme_adapter *jme = netdev_priv(netdev);
2044 u32 mc_hash[2] = {};
2047 spin_lock_bh(&jme->rxmcs_lock);
2049 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2051 if (netdev->flags & IFF_PROMISC) {
2052 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2053 } else if (netdev->flags & IFF_ALLMULTI) {
2054 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2055 } else if (netdev->flags & IFF_MULTICAST) {
2056 struct dev_mc_list *mclist;
2059 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2060 for (i = 0, mclist = netdev->mc_list;
2061 mclist && i < netdev->mc_count;
2062 ++i, mclist = mclist->next) {
2064 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2065 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2068 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2069 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2073 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2075 spin_unlock_bh(&jme->rxmcs_lock);
2079 jme_change_mtu(struct net_device *netdev, int new_mtu)
2081 struct jme_adapter *jme = netdev_priv(netdev);
2083 if (new_mtu == jme->old_mtu)
2086 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2087 ((new_mtu) < IPV6_MIN_MTU))
2090 if (new_mtu > 4000) {
2091 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2092 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2093 jme_restart_rx_engine(jme);
2095 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2096 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2097 jme_restart_rx_engine(jme);
2100 if (new_mtu > 1900) {
2101 netdev->features &= ~(NETIF_F_HW_CSUM |
2108 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2109 netdev->features |= NETIF_F_HW_CSUM;
2110 if (test_bit(JME_FLAG_TSO, &jme->flags))
2111 netdev->features |= NETIF_F_TSO
2118 netdev->mtu = new_mtu;
2119 jme_reset_link(jme);
2125 jme_tx_timeout(struct net_device *netdev)
2127 struct jme_adapter *jme = netdev_priv(netdev);
2130 jme_reset_phy_processor(jme);
2131 if (test_bit(JME_FLAG_SSET, &jme->flags))
2132 jme_set_settings(netdev, &jme->old_ecmd);
2135 * Force to Reset the link again
2137 jme_reset_link(jme);
2141 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2143 struct jme_adapter *jme = netdev_priv(netdev);
2149 jme_get_drvinfo(struct net_device *netdev,
2150 struct ethtool_drvinfo *info)
2152 struct jme_adapter *jme = netdev_priv(netdev);
2154 strcpy(info->driver, DRV_NAME);
2155 strcpy(info->version, DRV_VERSION);
2156 strcpy(info->bus_info, pci_name(jme->pdev));
2160 jme_get_regs_len(struct net_device *netdev)
2166 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2170 for (i = 0 ; i < len ; i += 4)
2171 p[i >> 2] = jread32(jme, reg + i);
2175 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2178 u16 *p16 = (u16 *)p;
2180 for (i = 0 ; i < reg_nr ; ++i)
2181 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2185 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2187 struct jme_adapter *jme = netdev_priv(netdev);
2188 u32 *p32 = (u32 *)p;
2190 memset(p, 0xFF, JME_REG_LEN);
2193 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2196 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2199 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2202 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2205 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2209 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2211 struct jme_adapter *jme = netdev_priv(netdev);
2213 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2214 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2216 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2217 ecmd->use_adaptive_rx_coalesce = false;
2218 ecmd->rx_coalesce_usecs = 0;
2219 ecmd->rx_max_coalesced_frames = 0;
2223 ecmd->use_adaptive_rx_coalesce = true;
2225 switch (jme->dpi.cur) {
2227 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2228 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2231 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2232 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2235 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2236 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2246 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2248 struct jme_adapter *jme = netdev_priv(netdev);
2249 struct dynpcc_info *dpi = &(jme->dpi);
2251 if (netif_running(netdev))
2254 if (ecmd->use_adaptive_rx_coalesce
2255 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2256 clear_bit(JME_FLAG_POLL, &jme->flags);
2257 jme->jme_rx = netif_rx;
2258 jme->jme_vlan_rx = vlan_hwaccel_rx;
2260 dpi->attempt = PCC_P1;
2262 jme_set_rx_pcc(jme, PCC_P1);
2263 jme_interrupt_mode(jme);
2264 } else if (!(ecmd->use_adaptive_rx_coalesce)
2265 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2266 set_bit(JME_FLAG_POLL, &jme->flags);
2267 jme->jme_rx = netif_receive_skb;
2268 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2269 jme_interrupt_mode(jme);
2276 jme_get_pauseparam(struct net_device *netdev,
2277 struct ethtool_pauseparam *ecmd)
2279 struct jme_adapter *jme = netdev_priv(netdev);
2282 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2283 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2285 spin_lock_bh(&jme->phy_lock);
2286 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2287 spin_unlock_bh(&jme->phy_lock);
2290 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2294 jme_set_pauseparam(struct net_device *netdev,
2295 struct ethtool_pauseparam *ecmd)
2297 struct jme_adapter *jme = netdev_priv(netdev);
2300 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2301 (ecmd->tx_pause != 0)) {
2304 jme->reg_txpfc |= TXPFC_PF_EN;
2306 jme->reg_txpfc &= ~TXPFC_PF_EN;
2308 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2311 spin_lock_bh(&jme->rxmcs_lock);
2312 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2313 (ecmd->rx_pause != 0)) {
2316 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2318 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2320 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2322 spin_unlock_bh(&jme->rxmcs_lock);
2324 spin_lock_bh(&jme->phy_lock);
2325 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2326 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2327 (ecmd->autoneg != 0)) {
2330 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2332 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2334 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2335 MII_ADVERTISE, val);
2337 spin_unlock_bh(&jme->phy_lock);
2343 jme_get_wol(struct net_device *netdev,
2344 struct ethtool_wolinfo *wol)
2346 struct jme_adapter *jme = netdev_priv(netdev);
2348 wol->supported = WAKE_MAGIC | WAKE_PHY;
2352 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2353 wol->wolopts |= WAKE_PHY;
2355 if (jme->reg_pmcs & PMCS_MFEN)
2356 wol->wolopts |= WAKE_MAGIC;
2361 jme_set_wol(struct net_device *netdev,
2362 struct ethtool_wolinfo *wol)
2364 struct jme_adapter *jme = netdev_priv(netdev);
2366 if (wol->wolopts & (WAKE_MAGICSECURE |
2375 if (wol->wolopts & WAKE_PHY)
2376 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2378 if (wol->wolopts & WAKE_MAGIC)
2379 jme->reg_pmcs |= PMCS_MFEN;
2381 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2387 jme_get_settings(struct net_device *netdev,
2388 struct ethtool_cmd *ecmd)
2390 struct jme_adapter *jme = netdev_priv(netdev);
2393 spin_lock_bh(&jme->phy_lock);
2394 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2395 spin_unlock_bh(&jme->phy_lock);
2400 jme_set_settings(struct net_device *netdev,
2401 struct ethtool_cmd *ecmd)
2403 struct jme_adapter *jme = netdev_priv(netdev);
2406 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2409 if (jme->mii_if.force_media &&
2410 ecmd->autoneg != AUTONEG_ENABLE &&
2411 (jme->mii_if.full_duplex != ecmd->duplex))
2414 spin_lock_bh(&jme->phy_lock);
2415 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2416 spin_unlock_bh(&jme->phy_lock);
2419 jme_reset_link(jme);
2422 set_bit(JME_FLAG_SSET, &jme->flags);
2423 jme->old_ecmd = *ecmd;
2430 jme_get_link(struct net_device *netdev)
2432 struct jme_adapter *jme = netdev_priv(netdev);
2433 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2437 jme_get_msglevel(struct net_device *netdev)
2439 struct jme_adapter *jme = netdev_priv(netdev);
2440 return jme->msg_enable;
2444 jme_set_msglevel(struct net_device *netdev, u32 value)
2446 struct jme_adapter *jme = netdev_priv(netdev);
2447 jme->msg_enable = value;
2451 jme_get_rx_csum(struct net_device *netdev)
2453 struct jme_adapter *jme = netdev_priv(netdev);
2454 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2458 jme_set_rx_csum(struct net_device *netdev, u32 on)
2460 struct jme_adapter *jme = netdev_priv(netdev);
2462 spin_lock_bh(&jme->rxmcs_lock);
2464 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2466 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2467 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2468 spin_unlock_bh(&jme->rxmcs_lock);
2474 jme_set_tx_csum(struct net_device *netdev, u32 on)
2476 struct jme_adapter *jme = netdev_priv(netdev);
2479 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2480 if (netdev->mtu <= 1900)
2481 netdev->features |= NETIF_F_HW_CSUM;
2483 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2484 netdev->features &= ~NETIF_F_HW_CSUM;
2491 jme_set_tso(struct net_device *netdev, u32 on)
2493 struct jme_adapter *jme = netdev_priv(netdev);
2496 set_bit(JME_FLAG_TSO, &jme->flags);
2497 if (netdev->mtu <= 1900)
2498 netdev->features |= NETIF_F_TSO
2504 clear_bit(JME_FLAG_TSO, &jme->flags);
2505 netdev->features &= ~(NETIF_F_TSO
2516 jme_nway_reset(struct net_device *netdev)
2518 struct jme_adapter *jme = netdev_priv(netdev);
2519 jme_restart_an(jme);
2524 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2529 val = jread32(jme, JME_SMBCSR);
2530 to = JME_SMB_BUSY_TIMEOUT;
2531 while ((val & SMBCSR_BUSY) && --to) {
2533 val = jread32(jme, JME_SMBCSR);
2536 msg_hw(jme, "SMB Bus Busy.\n");
2540 jwrite32(jme, JME_SMBINTF,
2541 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2542 SMBINTF_HWRWN_READ |
2545 val = jread32(jme, JME_SMBINTF);
2546 to = JME_SMB_BUSY_TIMEOUT;
2547 while ((val & SMBINTF_HWCMD) && --to) {
2549 val = jread32(jme, JME_SMBINTF);
2552 msg_hw(jme, "SMB Bus Busy.\n");
2556 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2560 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2565 val = jread32(jme, JME_SMBCSR);
2566 to = JME_SMB_BUSY_TIMEOUT;
2567 while ((val & SMBCSR_BUSY) && --to) {
2569 val = jread32(jme, JME_SMBCSR);
2572 msg_hw(jme, "SMB Bus Busy.\n");
2576 jwrite32(jme, JME_SMBINTF,
2577 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2578 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2579 SMBINTF_HWRWN_WRITE |
2582 val = jread32(jme, JME_SMBINTF);
2583 to = JME_SMB_BUSY_TIMEOUT;
2584 while ((val & SMBINTF_HWCMD) && --to) {
2586 val = jread32(jme, JME_SMBINTF);
2589 msg_hw(jme, "SMB Bus Busy.\n");
2597 jme_get_eeprom_len(struct net_device *netdev)
2599 struct jme_adapter *jme = netdev_priv(netdev);
2601 val = jread32(jme, JME_SMBCSR);
2602 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2606 jme_get_eeprom(struct net_device *netdev,
2607 struct ethtool_eeprom *eeprom, u8 *data)
2609 struct jme_adapter *jme = netdev_priv(netdev);
2610 int i, offset = eeprom->offset, len = eeprom->len;
2613 * ethtool will check the boundary for us
2615 eeprom->magic = JME_EEPROM_MAGIC;
2616 for (i = 0 ; i < len ; ++i)
2617 data[i] = jme_smb_read(jme, i + offset);
2623 jme_set_eeprom(struct net_device *netdev,
2624 struct ethtool_eeprom *eeprom, u8 *data)
2626 struct jme_adapter *jme = netdev_priv(netdev);
2627 int i, offset = eeprom->offset, len = eeprom->len;
2629 if (eeprom->magic != JME_EEPROM_MAGIC)
2633 * ethtool will check the boundary for us
2635 for (i = 0 ; i < len ; ++i)
2636 jme_smb_write(jme, i + offset, data[i]);
2641 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2642 static struct ethtool_ops jme_ethtool_ops = {
2644 static const struct ethtool_ops jme_ethtool_ops = {
2646 .get_drvinfo = jme_get_drvinfo,
2647 .get_regs_len = jme_get_regs_len,
2648 .get_regs = jme_get_regs,
2649 .get_coalesce = jme_get_coalesce,
2650 .set_coalesce = jme_set_coalesce,
2651 .get_pauseparam = jme_get_pauseparam,
2652 .set_pauseparam = jme_set_pauseparam,
2653 .get_wol = jme_get_wol,
2654 .set_wol = jme_set_wol,
2655 .get_settings = jme_get_settings,
2656 .set_settings = jme_set_settings,
2657 .get_link = jme_get_link,
2658 .get_msglevel = jme_get_msglevel,
2659 .set_msglevel = jme_set_msglevel,
2660 .get_rx_csum = jme_get_rx_csum,
2661 .set_rx_csum = jme_set_rx_csum,
2662 .set_tx_csum = jme_set_tx_csum,
2663 .set_tso = jme_set_tso,
2664 .set_sg = ethtool_op_set_sg,
2665 .nway_reset = jme_nway_reset,
2666 .get_eeprom_len = jme_get_eeprom_len,
2667 .get_eeprom = jme_get_eeprom,
2668 .set_eeprom = jme_set_eeprom,
2672 jme_pci_dma64(struct pci_dev *pdev)
2674 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2675 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2676 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2678 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2681 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2682 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2684 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2688 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2689 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2690 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2692 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2695 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2696 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2698 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2702 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2703 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2704 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2706 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2707 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2715 jme_phy_init(struct jme_adapter *jme)
2719 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2720 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2724 jme_check_hw_ver(struct jme_adapter *jme)
2728 chipmode = jread32(jme, JME_CHIPMODE);
2730 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2731 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2734 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2735 static const struct net_device_ops jme_netdev_ops = {
2736 .ndo_open = jme_open,
2737 .ndo_stop = jme_close,
2738 .ndo_validate_addr = eth_validate_addr,
2739 .ndo_start_xmit = jme_start_xmit,
2740 .ndo_set_mac_address = jme_set_macaddr,
2741 .ndo_set_multicast_list = jme_set_multi,
2742 .ndo_change_mtu = jme_change_mtu,
2743 .ndo_tx_timeout = jme_tx_timeout,
2744 .ndo_vlan_rx_register = jme_vlan_rx_register,
2748 static int __devinit
2749 jme_init_one(struct pci_dev *pdev,
2750 const struct pci_device_id *ent)
2752 int rc = 0, using_dac, i;
2753 struct net_device *netdev;
2754 struct jme_adapter *jme;
2759 * set up PCI device basics
2761 rc = pci_enable_device(pdev);
2763 jeprintk(pdev, "Cannot enable PCI device.\n");
2767 using_dac = jme_pci_dma64(pdev);
2768 if (using_dac < 0) {
2769 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2771 goto err_out_disable_pdev;
2774 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2775 jeprintk(pdev, "No PCI resource region found.\n");
2777 goto err_out_disable_pdev;
2780 rc = pci_request_regions(pdev, DRV_NAME);
2782 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2783 goto err_out_disable_pdev;
2786 pci_set_master(pdev);
2789 * alloc and init net device
2791 netdev = alloc_etherdev(sizeof(*jme));
2793 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2795 goto err_out_release_regions;
2797 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2798 netdev->netdev_ops = &jme_netdev_ops;
2800 netdev->open = jme_open;
2801 netdev->stop = jme_close;
2802 netdev->hard_start_xmit = jme_start_xmit;
2803 netdev->set_mac_address = jme_set_macaddr;
2804 netdev->set_multicast_list = jme_set_multi;
2805 netdev->change_mtu = jme_change_mtu;
2806 netdev->tx_timeout = jme_tx_timeout;
2807 netdev->vlan_rx_register = jme_vlan_rx_register;
2808 NETDEV_GET_STATS(netdev, &jme_get_stats);
2810 netdev->ethtool_ops = &jme_ethtool_ops;
2811 netdev->watchdog_timeo = TX_TIMEOUT;
2812 netdev->features = NETIF_F_HW_CSUM |
2818 NETIF_F_HW_VLAN_TX |
2821 netdev->features |= NETIF_F_HIGHDMA;
2823 SET_NETDEV_DEV(netdev, &pdev->dev);
2824 pci_set_drvdata(pdev, netdev);
2829 jme = netdev_priv(netdev);
2832 jme->jme_rx = netif_rx;
2833 jme->jme_vlan_rx = vlan_hwaccel_rx;
2834 jme->old_mtu = netdev->mtu = 1500;
2836 jme->tx_ring_size = 1 << 10;
2837 jme->tx_ring_mask = jme->tx_ring_size - 1;
2838 jme->tx_wake_threshold = 1 << 9;
2839 jme->rx_ring_size = 1 << 9;
2840 jme->rx_ring_mask = jme->rx_ring_size - 1;
2841 jme->msg_enable = JME_DEF_MSG_ENABLE;
2842 jme->regs = ioremap(pci_resource_start(pdev, 0),
2843 pci_resource_len(pdev, 0));
2845 jeprintk(pdev, "Mapping PCI resource region error.\n");
2847 goto err_out_free_netdev;
2851 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2852 jwrite32(jme, JME_APMC, apmc);
2853 } else if (force_pseudohp) {
2854 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2855 jwrite32(jme, JME_APMC, apmc);
2858 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2860 spin_lock_init(&jme->phy_lock);
2861 spin_lock_init(&jme->macaddr_lock);
2862 spin_lock_init(&jme->rxmcs_lock);
2864 atomic_set(&jme->link_changing, 1);
2865 atomic_set(&jme->rx_cleaning, 1);
2866 atomic_set(&jme->tx_cleaning, 1);
2867 atomic_set(&jme->rx_empty, 1);
2869 tasklet_init(&jme->pcc_task,
2871 (unsigned long) jme);
2872 tasklet_init(&jme->linkch_task,
2873 &jme_link_change_tasklet,
2874 (unsigned long) jme);
2875 tasklet_init(&jme->txclean_task,
2876 &jme_tx_clean_tasklet,
2877 (unsigned long) jme);
2878 tasklet_init(&jme->rxclean_task,
2879 &jme_rx_clean_tasklet,
2880 (unsigned long) jme);
2881 tasklet_init(&jme->rxempty_task,
2882 &jme_rx_empty_tasklet,
2883 (unsigned long) jme);
2884 tasklet_disable_nosync(&jme->linkch_task);
2885 tasklet_disable_nosync(&jme->txclean_task);
2886 tasklet_disable_nosync(&jme->rxclean_task);
2887 tasklet_disable_nosync(&jme->rxempty_task);
2888 jme->dpi.cur = PCC_P1;
2891 jme->reg_rxcs = RXCS_DEFAULT;
2892 jme->reg_rxmcs = RXMCS_DEFAULT;
2894 jme->reg_pmcs = PMCS_MFEN;
2895 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2896 set_bit(JME_FLAG_TSO, &jme->flags);
2899 * Get Max Read Req Size from PCI Config Space
2901 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2902 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2903 switch (jme->mrrs) {
2905 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2908 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2911 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2916 * Must check before reset_mac_processor
2918 jme_check_hw_ver(jme);
2919 jme->mii_if.dev = netdev;
2921 jme->mii_if.phy_id = 0;
2922 for (i = 1 ; i < 32 ; ++i) {
2923 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2924 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2925 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2926 jme->mii_if.phy_id = i;
2931 if (!jme->mii_if.phy_id) {
2933 jeprintk(pdev, "Can not find phy_id.\n");
2937 jme->reg_ghc |= GHC_LINK_POLL;
2939 jme->mii_if.phy_id = 1;
2941 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2942 jme->mii_if.supports_gmii = true;
2944 jme->mii_if.supports_gmii = false;
2945 jme->mii_if.mdio_read = jme_mdio_read;
2946 jme->mii_if.mdio_write = jme_mdio_write;
2949 jme_set_phyfifoa(jme);
2950 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2956 * Reset MAC processor and reload EEPROM for MAC Address
2958 jme_reset_mac_processor(jme);
2959 rc = jme_reload_eeprom(jme);
2962 "Reload eeprom for reading MAC Address error.\n");
2965 jme_load_macaddr(netdev);
2968 * Tell stack that we are not ready to work until open()
2970 netif_carrier_off(netdev);
2971 netif_stop_queue(netdev);
2976 rc = register_netdev(netdev);
2978 jeprintk(pdev, "Cannot register net device.\n");
2982 msg_probe(jme, "%s%s ver:%x rev:%x "
2983 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
2984 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2985 "JMC250 Gigabit Ethernet" :
2986 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2987 "JMC260 Fast Ethernet" : "Unknown",
2988 (jme->fpgaver != 0) ? " (FPGA)" : "",
2989 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2991 netdev->dev_addr[0],
2992 netdev->dev_addr[1],
2993 netdev->dev_addr[2],
2994 netdev->dev_addr[3],
2995 netdev->dev_addr[4],
2996 netdev->dev_addr[5]);
3002 err_out_free_netdev:
3003 pci_set_drvdata(pdev, NULL);
3004 free_netdev(netdev);
3005 err_out_release_regions:
3006 pci_release_regions(pdev);
3007 err_out_disable_pdev:
3008 pci_disable_device(pdev);
3013 static void __devexit
3014 jme_remove_one(struct pci_dev *pdev)
3016 struct net_device *netdev = pci_get_drvdata(pdev);
3017 struct jme_adapter *jme = netdev_priv(netdev);
3019 unregister_netdev(netdev);
3021 pci_set_drvdata(pdev, NULL);
3022 free_netdev(netdev);
3023 pci_release_regions(pdev);
3024 pci_disable_device(pdev);
3030 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3032 struct net_device *netdev = pci_get_drvdata(pdev);
3033 struct jme_adapter *jme = netdev_priv(netdev);
3035 atomic_dec(&jme->link_changing);
3037 netif_device_detach(netdev);
3038 netif_stop_queue(netdev);
3041 tasklet_disable(&jme->txclean_task);
3042 tasklet_disable(&jme->rxclean_task);
3043 tasklet_disable(&jme->rxempty_task);
3045 if (netif_carrier_ok(netdev)) {
3046 if (test_bit(JME_FLAG_POLL, &jme->flags))
3047 jme_polling_mode(jme);
3049 jme_stop_pcc_timer(jme);
3050 jme_reset_ghc_speed(jme);
3051 jme_disable_rx_engine(jme);
3052 jme_disable_tx_engine(jme);
3053 jme_reset_mac_processor(jme);
3054 jme_free_rx_resources(jme);
3055 jme_free_tx_resources(jme);
3056 netif_carrier_off(netdev);
3060 tasklet_enable(&jme->txclean_task);
3061 tasklet_hi_enable(&jme->rxclean_task);
3062 tasklet_hi_enable(&jme->rxempty_task);
3064 pci_save_state(pdev);
3065 if (jme->reg_pmcs) {
3066 jme_set_100m_half(jme);
3068 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3071 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3073 pci_enable_wake(pdev, PCI_D3cold, true);
3077 pci_set_power_state(pdev, PCI_D3cold);
3083 jme_resume(struct pci_dev *pdev)
3085 struct net_device *netdev = pci_get_drvdata(pdev);
3086 struct jme_adapter *jme = netdev_priv(netdev);
3089 pci_restore_state(pdev);
3091 if (test_bit(JME_FLAG_SSET, &jme->flags))
3092 jme_set_settings(netdev, &jme->old_ecmd);
3094 jme_reset_phy_processor(jme);
3097 netif_device_attach(netdev);
3099 atomic_inc(&jme->link_changing);
3101 jme_reset_link(jme);
3107 static struct pci_device_id jme_pci_tbl[] = {
3108 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3109 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3113 static struct pci_driver jme_driver = {
3115 .id_table = jme_pci_tbl,
3116 .probe = jme_init_one,
3117 .remove = __devexit_p(jme_remove_one),
3119 .suspend = jme_suspend,
3120 .resume = jme_resume,
3121 #endif /* CONFIG_PM */
3125 jme_init_module(void)
3127 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3128 "driver version %s\n", DRV_VERSION);
3129 return pci_register_driver(&jme_driver);
3133 jme_cleanup_module(void)
3135 pci_unregister_driver(&jme_driver);
3138 module_init(jme_init_module);
3139 module_exit(jme_cleanup_module);
3141 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3142 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3143 MODULE_LICENSE("GPL");
3144 MODULE_VERSION(DRV_VERSION);
3145 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);