2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/version.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/pci.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/mii.h>
32 #include <linux/crc32.h>
33 #include <linux/delay.h>
34 #include <linux/spinlock.h>
37 #include <linux/ipv6.h>
38 #include <linux/tcp.h>
39 #include <linux/udp.h>
40 #include <linux/if_vlan.h>
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
89 struct jme_adapter *jme = netdev_priv(netdev);
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
110 jme_spi_start(struct pci_dev *pdev, struct jme_spi_op *spiop)
113 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
114 ndelay(spiop->halfclk << 2);
115 if (spiop->mode & SPI_MODE_CPOL) {
116 spiop->sr |= SPI_SCLK;
117 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
118 ndelay(spiop->halfclk << 2);
120 spiop->sr &= ~SPI_CS;
121 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
122 ndelay(spiop->halfclk);
126 jme_spi_write(struct pci_dev *pdev, struct jme_spi_op *spiop, u8 byte)
130 for (bit = 0 ; bit < 8 ; ++bit) {
132 spiop->sr |= SPI_MOSI;
134 spiop->sr &= ~SPI_MOSI;
135 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
138 ndelay(spiop->halfclk);
139 spiop->sr ^= SPI_SCLK;
140 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
142 ndelay(spiop->halfclk);
143 spiop->sr ^= SPI_SCLK;
144 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
149 jme_spi_read(struct pci_dev *pdev, struct jme_spi_op *spiop, u8 *byte)
154 spiop->sr &= ~SPI_MOSI;
155 for (bit = 0 ; bit < 8 ; ++bit) {
157 ndelay(spiop->halfclk);
158 spiop->sr ^= SPI_SCLK;
159 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
161 ndelay(spiop->halfclk);
162 pci_read_config_byte(pdev, PCI_SPI, &b);
163 *byte |= !!(b & SPI_MISO);
164 spiop->sr ^= SPI_SCLK;
165 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
170 jme_spi_stop(struct pci_dev *pdev, struct jme_spi_op *spiop)
172 spiop->sr &= ~SPI_EN;
174 pci_write_config_byte(pdev, PCI_SPI, spiop->sr);
178 * jme_spi_io - SPI Access helper function.
179 * @jme: Adapter informations
180 * @spiop: SPI operation.
182 * We have a SPI SW Access register in PCI configuration space,
183 * which directly connect to flash controller with SPI interface.
184 * This function is used to communicate with it in SPI protocol.
187 jme_spi_op(struct jme_adapter *jme, struct jme_spi_op *spiop)
192 * Only support 8 bits for now
194 if (spiop->bitn != 8)
198 * Only support half-duplex for now
200 if (spiop->mode & SPI_MODE_DUP)
203 spiop->halfclk = HALF_US / spiop->spd;
205 jme_spi_start(jme->pdev, spiop);
207 for (i = 0 ; i < spiop->wn ; ++i)
208 jme_spi_write(jme->pdev, spiop, spiop->kwbuf[i]);
210 for (i = 0 ; i < spiop->rn ; ++i)
211 jme_spi_read(jme->pdev, spiop, spiop->krbuf + i);
213 jme_spi_stop(jme->pdev, spiop);
219 jme_reset_phy_processor(struct jme_adapter *jme)
223 jme_mdio_write(jme->dev,
225 MII_ADVERTISE, ADVERTISE_ALL |
226 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
228 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
229 jme_mdio_write(jme->dev,
232 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
234 val = jme_mdio_read(jme->dev,
238 jme_mdio_write(jme->dev,
240 MII_BMCR, val | BMCR_RESET);
246 jme_setup_wakeup_frame(struct jme_adapter *jme,
247 u32 *mask, u32 crc, int fnr)
254 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
256 jwrite32(jme, JME_WFODP, crc);
262 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
263 jwrite32(jme, JME_WFOI,
264 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
265 (fnr & WFOI_FRAME_SEL));
267 jwrite32(jme, JME_WFODP, mask[i]);
273 jme_reset_mac_processor(struct jme_adapter *jme)
275 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
276 u32 crc = 0xCDCDCDCD;
280 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
282 jwrite32(jme, JME_GHC, jme->reg_ghc);
284 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
285 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
286 jwrite32(jme, JME_RXQDC, 0x00000000);
287 jwrite32(jme, JME_RXNDA, 0x00000000);
288 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
289 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
290 jwrite32(jme, JME_TXQDC, 0x00000000);
291 jwrite32(jme, JME_TXNDA, 0x00000000);
293 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
294 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
295 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
296 jme_setup_wakeup_frame(jme, mask, crc, i);
298 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
300 gpreg0 = GPREG0_DEFAULT;
301 jwrite32(jme, JME_GPREG0, gpreg0);
302 jwrite32(jme, JME_GPREG1, 0);
306 jme_reset_ghc_speed(struct jme_adapter *jme)
308 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
309 jwrite32(jme, JME_GHC, jme->reg_ghc);
313 jme_clear_pm(struct jme_adapter *jme)
315 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
316 pci_set_power_state(jme->pdev, PCI_D0);
317 pci_enable_wake(jme->pdev, PCI_D0, false);
321 jme_reload_eeprom(struct jme_adapter *jme)
326 val = jread32(jme, JME_SMBCSR);
328 if (val & SMBCSR_EEPROMD) {
330 jwrite32(jme, JME_SMBCSR, val);
331 val |= SMBCSR_RELOAD;
332 jwrite32(jme, JME_SMBCSR, val);
335 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
337 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
342 jeprintk(jme->pdev, "eeprom reload timeout\n");
351 jme_load_macaddr(struct net_device *netdev)
353 struct jme_adapter *jme = netdev_priv(netdev);
354 unsigned char macaddr[6];
357 spin_lock_bh(&jme->macaddr_lock);
358 val = jread32(jme, JME_RXUMA_LO);
359 macaddr[0] = (val >> 0) & 0xFF;
360 macaddr[1] = (val >> 8) & 0xFF;
361 macaddr[2] = (val >> 16) & 0xFF;
362 macaddr[3] = (val >> 24) & 0xFF;
363 val = jread32(jme, JME_RXUMA_HI);
364 macaddr[4] = (val >> 0) & 0xFF;
365 macaddr[5] = (val >> 8) & 0xFF;
366 memcpy(netdev->dev_addr, macaddr, 6);
367 spin_unlock_bh(&jme->macaddr_lock);
371 jme_set_rx_pcc(struct jme_adapter *jme, int p)
375 jwrite32(jme, JME_PCCRX0,
376 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
377 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
380 jwrite32(jme, JME_PCCRX0,
381 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
382 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
385 jwrite32(jme, JME_PCCRX0,
386 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
387 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
390 jwrite32(jme, JME_PCCRX0,
391 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
392 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
399 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
400 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
404 jme_start_irq(struct jme_adapter *jme)
406 register struct dynpcc_info *dpi = &(jme->dpi);
408 jme_set_rx_pcc(jme, PCC_P1);
410 dpi->attempt = PCC_P1;
413 jwrite32(jme, JME_PCCTX,
414 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
415 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
422 jwrite32(jme, JME_IENS, INTR_ENABLE);
426 jme_stop_irq(struct jme_adapter *jme)
431 jwrite32f(jme, JME_IENC, INTR_ENABLE);
435 jme_enable_shadow(struct jme_adapter *jme)
439 ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
443 jme_disable_shadow(struct jme_adapter *jme)
445 jwrite32(jme, JME_SHBA_LO, 0x0);
449 jme_linkstat_from_phy(struct jme_adapter *jme)
453 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
454 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
455 if (bmsr & BMSR_ANCOMP)
456 phylink |= PHY_LINK_AUTONEG_COMPLETE;
462 jme_set_gmii(struct jme_adapter *jme)
464 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
468 jme_set_rgmii(struct jme_adapter *jme)
470 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
474 jme_check_link(struct net_device *netdev, int testonly)
476 struct jme_adapter *jme = netdev_priv(netdev);
477 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
484 phylink = jme_linkstat_from_phy(jme);
486 phylink = jread32(jme, JME_PHY_LINK);
488 if (phylink & PHY_LINK_UP) {
489 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
491 * If we did not enable AN
492 * Speed/Duplex Info should be obtained from SMI
494 phylink = PHY_LINK_UP;
496 bmcr = jme_mdio_read(jme->dev,
500 phylink |= ((bmcr & BMCR_SPEED1000) &&
501 (bmcr & BMCR_SPEED100) == 0) ?
502 PHY_LINK_SPEED_1000M :
503 (bmcr & BMCR_SPEED100) ?
504 PHY_LINK_SPEED_100M :
507 phylink |= (bmcr & BMCR_FULLDPLX) ?
510 strcat(linkmsg, "Forced: ");
513 * Keep polling for speed/duplex resolve complete
515 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
521 phylink = jme_linkstat_from_phy(jme);
523 phylink = jread32(jme, JME_PHY_LINK);
527 "Waiting speed resolve timeout.\n");
529 strcat(linkmsg, "ANed: ");
532 if (jme->phylink == phylink) {
539 jme->phylink = phylink;
541 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
545 switch (phylink & PHY_LINK_SPEED_MASK) {
546 case PHY_LINK_SPEED_10M:
547 ghc |= GHC_SPEED_10M;
548 strcat(linkmsg, "10 Mbps, ");
549 if (jme->rev == 0x11)
552 case PHY_LINK_SPEED_100M:
553 ghc |= GHC_SPEED_100M;
554 strcat(linkmsg, "100 Mbps, ");
555 if (jme->rev == 0x11)
558 case PHY_LINK_SPEED_1000M:
559 ghc |= GHC_SPEED_1000M;
560 strcat(linkmsg, "1000 Mbps, ");
561 if (jme->rev == 0x11)
567 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
569 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
573 if (phylink & PHY_LINK_MDI_STAT)
574 strcat(linkmsg, "MDI-X");
576 strcat(linkmsg, "MDI");
578 if (phylink & PHY_LINK_DUPLEX) {
579 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
581 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
585 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
586 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
588 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
592 jwrite32(jme, JME_GHC, ghc);
594 msg_link(jme, "Link is up at %s.\n", linkmsg);
595 netif_carrier_on(netdev);
600 msg_link(jme, "Link is down.\n");
602 netif_carrier_off(netdev);
610 jme_setup_tx_resources(struct jme_adapter *jme)
612 struct jme_ring *txring = &(jme->txring[0]);
614 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
615 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
619 if (!txring->alloc) {
621 txring->dmaalloc = 0;
629 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
631 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
632 txring->next_to_use = 0;
633 atomic_set(&txring->next_to_clean, 0);
634 atomic_set(&txring->nr_free, jme->tx_ring_size);
637 * Initialize Transmit Descriptors
639 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
640 memset(txring->bufinf, 0,
641 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
647 jme_free_tx_resources(struct jme_adapter *jme)
650 struct jme_ring *txring = &(jme->txring[0]);
651 struct jme_buffer_info *txbi = txring->bufinf;
654 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
655 txbi = txring->bufinf + i;
657 dev_kfree_skb(txbi->skb);
663 txbi->start_xmit = 0;
666 dma_free_coherent(&(jme->pdev->dev),
667 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
671 txring->alloc = NULL;
673 txring->dmaalloc = 0;
676 txring->next_to_use = 0;
677 atomic_set(&txring->next_to_clean, 0);
678 atomic_set(&txring->nr_free, 0);
683 jme_enable_tx_engine(struct jme_adapter *jme)
688 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
692 * Setup TX Queue 0 DMA Bass Address
694 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
695 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
696 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
699 * Setup TX Descptor Count
701 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
707 jwrite32(jme, JME_TXCS, jme->reg_txcs |
714 jme_restart_tx_engine(struct jme_adapter *jme)
719 jwrite32(jme, JME_TXCS, jme->reg_txcs |
725 jme_disable_tx_engine(struct jme_adapter *jme)
733 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
736 val = jread32(jme, JME_TXCS);
737 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
739 val = jread32(jme, JME_TXCS);
744 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
748 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
750 struct jme_ring *rxring = jme->rxring;
751 register struct rxdesc *rxdesc = rxring->desc;
752 struct jme_buffer_info *rxbi = rxring->bufinf;
758 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
759 rxdesc->desc1.bufaddrl = cpu_to_le32(
760 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
761 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
762 if (jme->dev->features & NETIF_F_HIGHDMA)
763 rxdesc->desc1.flags = RXFLAG_64BIT;
765 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
769 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
771 struct jme_ring *rxring = &(jme->rxring[0]);
772 struct jme_buffer_info *rxbi = rxring->bufinf + i;
775 skb = netdev_alloc_skb(jme->dev,
776 jme->dev->mtu + RX_EXTRA_LEN);
781 rxbi->len = skb_tailroom(skb);
782 rxbi->mapping = pci_map_page(jme->pdev,
783 virt_to_page(skb->data),
784 offset_in_page(skb->data),
792 jme_free_rx_buf(struct jme_adapter *jme, int i)
794 struct jme_ring *rxring = &(jme->rxring[0]);
795 struct jme_buffer_info *rxbi = rxring->bufinf;
799 pci_unmap_page(jme->pdev,
803 dev_kfree_skb(rxbi->skb);
811 jme_free_rx_resources(struct jme_adapter *jme)
814 struct jme_ring *rxring = &(jme->rxring[0]);
817 for (i = 0 ; i < jme->rx_ring_size ; ++i)
818 jme_free_rx_buf(jme, i);
820 dma_free_coherent(&(jme->pdev->dev),
821 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
824 rxring->alloc = NULL;
826 rxring->dmaalloc = 0;
829 rxring->next_to_use = 0;
830 atomic_set(&rxring->next_to_clean, 0);
834 jme_setup_rx_resources(struct jme_adapter *jme)
837 struct jme_ring *rxring = &(jme->rxring[0]);
839 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
840 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
843 if (!rxring->alloc) {
845 rxring->dmaalloc = 0;
853 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
855 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
856 rxring->next_to_use = 0;
857 atomic_set(&rxring->next_to_clean, 0);
860 * Initiallize Receive Descriptors
862 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
863 if (unlikely(jme_make_new_rx_buf(jme, i))) {
864 jme_free_rx_resources(jme);
868 jme_set_clean_rxdesc(jme, i);
875 jme_enable_rx_engine(struct jme_adapter *jme)
880 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
885 * Setup RX DMA Bass Address
887 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
888 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
889 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
892 * Setup RX Descriptor Count
894 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
897 * Setup Unicast Filter
899 jme_set_multi(jme->dev);
905 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
912 jme_restart_rx_engine(struct jme_adapter *jme)
917 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
924 jme_disable_rx_engine(struct jme_adapter *jme)
932 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
935 val = jread32(jme, JME_RXCS);
936 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
938 val = jread32(jme, JME_RXCS);
943 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
948 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
950 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
953 if (unlikely(!(flags & RXWBFLAG_MF) &&
954 (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
955 msg_rx_err(jme, "TCP Checksum error.\n");
959 if (unlikely(!(flags & RXWBFLAG_MF) &&
960 (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
961 msg_rx_err(jme, "UDP Checksum error.\n");
965 if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
966 msg_rx_err(jme, "IPv4 Checksum error.\n");
977 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
979 struct jme_ring *rxring = &(jme->rxring[0]);
980 struct rxdesc *rxdesc = rxring->desc;
981 struct jme_buffer_info *rxbi = rxring->bufinf;
989 pci_dma_sync_single_for_cpu(jme->pdev,
994 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
995 pci_dma_sync_single_for_device(jme->pdev,
1000 ++(NET_STAT(jme).rx_dropped);
1002 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1005 skb_reserve(skb, RX_PREPAD_SIZE);
1006 skb_put(skb, framesize);
1007 skb->protocol = eth_type_trans(skb, jme->dev);
1009 if (jme_rxsum_ok(jme, rxdesc->descwb.flags))
1010 skb->ip_summed = CHECKSUM_UNNECESSARY;
1012 skb->ip_summed = CHECKSUM_NONE;
1014 if (rxdesc->descwb.flags & RXWBFLAG_TAGON) {
1016 jme->jme_vlan_rx(skb, jme->vlgrp,
1017 le32_to_cpu(rxdesc->descwb.vlan));
1018 NET_STAT(jme).rx_bytes += 4;
1024 if ((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
1026 ++(NET_STAT(jme).multicast);
1028 jme->dev->last_rx = jiffies;
1029 NET_STAT(jme).rx_bytes += framesize;
1030 ++(NET_STAT(jme).rx_packets);
1033 jme_set_clean_rxdesc(jme, idx);
1038 jme_process_receive(struct jme_adapter *jme, int limit)
1040 struct jme_ring *rxring = &(jme->rxring[0]);
1041 struct rxdesc *rxdesc = rxring->desc;
1042 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1044 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1047 if (unlikely(atomic_read(&jme->link_changing) != 1))
1050 if (unlikely(!netif_carrier_ok(jme->dev)))
1053 i = atomic_read(&rxring->next_to_clean);
1054 while (limit-- > 0) {
1055 rxdesc = rxring->desc;
1058 if ((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
1059 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1062 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1064 if (unlikely(desccnt > 1 ||
1065 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1067 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1068 ++(NET_STAT(jme).rx_crc_errors);
1069 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1070 ++(NET_STAT(jme).rx_fifo_errors);
1072 ++(NET_STAT(jme).rx_errors);
1075 limit -= desccnt - 1;
1077 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1078 jme_set_clean_rxdesc(jme, j);
1079 j = (j + 1) & (mask);
1083 jme_alloc_and_feed_skb(jme, i);
1086 i = (i + desccnt) & (mask);
1090 atomic_set(&rxring->next_to_clean, i);
1093 atomic_inc(&jme->rx_cleaning);
1095 return limit > 0 ? limit : 0;
1100 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1102 if (likely(atmp == dpi->cur)) {
1107 if (dpi->attempt == atmp) {
1110 dpi->attempt = atmp;
1117 jme_dynamic_pcc(struct jme_adapter *jme)
1119 register struct dynpcc_info *dpi = &(jme->dpi);
1121 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1122 jme_attempt_pcc(dpi, PCC_P3);
1123 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1124 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1125 jme_attempt_pcc(dpi, PCC_P2);
1127 jme_attempt_pcc(dpi, PCC_P1);
1129 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1130 if (dpi->attempt < dpi->cur)
1131 tasklet_schedule(&jme->rxclean_task);
1132 jme_set_rx_pcc(jme, dpi->attempt);
1133 dpi->cur = dpi->attempt;
1139 jme_start_pcc_timer(struct jme_adapter *jme)
1141 struct dynpcc_info *dpi = &(jme->dpi);
1142 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1143 dpi->last_pkts = NET_STAT(jme).rx_packets;
1145 jwrite32(jme, JME_TMCSR,
1146 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1150 jme_stop_pcc_timer(struct jme_adapter *jme)
1152 jwrite32(jme, JME_TMCSR, 0);
1156 jme_shutdown_nic(struct jme_adapter *jme)
1160 phylink = jme_linkstat_from_phy(jme);
1162 if (!(phylink & PHY_LINK_UP)) {
1164 * Disable all interrupt before issue timer
1167 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1172 jme_pcc_tasklet(unsigned long arg)
1174 struct jme_adapter *jme = (struct jme_adapter *)arg;
1175 struct net_device *netdev = jme->dev;
1177 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1178 jme_shutdown_nic(jme);
1182 if (unlikely(!netif_carrier_ok(netdev) ||
1183 (atomic_read(&jme->link_changing) != 1)
1185 jme_stop_pcc_timer(jme);
1189 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1190 jme_dynamic_pcc(jme);
1192 jme_start_pcc_timer(jme);
1196 jme_polling_mode(struct jme_adapter *jme)
1198 jme_set_rx_pcc(jme, PCC_OFF);
1202 jme_interrupt_mode(struct jme_adapter *jme)
1204 jme_set_rx_pcc(jme, PCC_P1);
1208 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1211 apmc = jread32(jme, JME_APMC);
1212 return apmc & JME_APMC_PSEUDO_HP_EN;
1216 jme_start_shutdown_timer(struct jme_adapter *jme)
1220 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1221 apmc &= ~JME_APMC_EPIEN_CTRL;
1223 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1226 jwrite32f(jme, JME_APMC, apmc);
1228 jwrite32f(jme, JME_TIMER2, 0);
1229 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1230 jwrite32(jme, JME_TMCSR,
1231 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1235 jme_stop_shutdown_timer(struct jme_adapter *jme)
1239 jwrite32f(jme, JME_TMCSR, 0);
1240 jwrite32f(jme, JME_TIMER2, 0);
1241 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1243 apmc = jread32(jme, JME_APMC);
1244 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1245 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1247 jwrite32f(jme, JME_APMC, apmc);
1251 jme_link_change_tasklet(unsigned long arg)
1253 struct jme_adapter *jme = (struct jme_adapter *)arg;
1254 struct net_device *netdev = jme->dev;
1257 while (!atomic_dec_and_test(&jme->link_changing)) {
1258 atomic_inc(&jme->link_changing);
1259 msg_intr(jme, "Get link change lock failed.\n");
1260 while(atomic_read(&jme->link_changing) != 1)
1261 msg_intr(jme, "Waiting link change lock.\n");
1264 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1267 jme->old_mtu = netdev->mtu;
1268 netif_stop_queue(netdev);
1269 if (jme_pseudo_hotplug_enabled(jme))
1270 jme_stop_shutdown_timer(jme);
1272 jme_stop_pcc_timer(jme);
1273 tasklet_disable(&jme->txclean_task);
1274 tasklet_disable(&jme->rxclean_task);
1275 tasklet_disable(&jme->rxempty_task);
1277 if (netif_carrier_ok(netdev)) {
1278 jme_reset_ghc_speed(jme);
1279 jme_disable_rx_engine(jme);
1280 jme_disable_tx_engine(jme);
1281 jme_reset_mac_processor(jme);
1282 jme_free_rx_resources(jme);
1283 jme_free_tx_resources(jme);
1285 if (test_bit(JME_FLAG_POLL, &jme->flags))
1286 jme_polling_mode(jme);
1288 netif_carrier_off(netdev);
1291 jme_check_link(netdev, 0);
1292 if (netif_carrier_ok(netdev)) {
1293 rc = jme_setup_rx_resources(jme);
1295 jeprintk(jme->pdev, "Allocating resources for RX error"
1296 ", Device STOPPED!\n");
1297 goto out_enable_tasklet;
1300 rc = jme_setup_tx_resources(jme);
1302 jeprintk(jme->pdev, "Allocating resources for TX error"
1303 ", Device STOPPED!\n");
1304 goto err_out_free_rx_resources;
1307 jme_enable_rx_engine(jme);
1308 jme_enable_tx_engine(jme);
1310 netif_start_queue(netdev);
1312 if (test_bit(JME_FLAG_POLL, &jme->flags))
1313 jme_interrupt_mode(jme);
1315 jme_start_pcc_timer(jme);
1316 } else if (jme_pseudo_hotplug_enabled(jme)) {
1317 jme_start_shutdown_timer(jme);
1320 goto out_enable_tasklet;
1322 err_out_free_rx_resources:
1323 jme_free_rx_resources(jme);
1325 tasklet_enable(&jme->txclean_task);
1326 tasklet_hi_enable(&jme->rxclean_task);
1327 tasklet_hi_enable(&jme->rxempty_task);
1329 atomic_inc(&jme->link_changing);
1333 jme_rx_clean_tasklet(unsigned long arg)
1335 struct jme_adapter *jme = (struct jme_adapter *)arg;
1336 struct dynpcc_info *dpi = &(jme->dpi);
1338 jme_process_receive(jme, jme->rx_ring_size);
1344 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1346 struct jme_adapter *jme = jme_napi_priv(holder);
1347 struct net_device *netdev = jme->dev;
1350 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1352 while (atomic_read(&jme->rx_empty) > 0) {
1353 atomic_dec(&jme->rx_empty);
1354 ++(NET_STAT(jme).rx_dropped);
1355 jme_restart_rx_engine(jme);
1357 atomic_inc(&jme->rx_empty);
1360 JME_RX_COMPLETE(netdev, holder);
1361 jme_interrupt_mode(jme);
1364 JME_NAPI_WEIGHT_SET(budget, rest);
1365 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1369 jme_rx_empty_tasklet(unsigned long arg)
1371 struct jme_adapter *jme = (struct jme_adapter *)arg;
1373 if (unlikely(atomic_read(&jme->link_changing) != 1))
1376 if (unlikely(!netif_carrier_ok(jme->dev)))
1379 msg_rx_status(jme, "RX Queue Full!\n");
1381 jme_rx_clean_tasklet(arg);
1383 while (atomic_read(&jme->rx_empty) > 0) {
1384 atomic_dec(&jme->rx_empty);
1385 ++(NET_STAT(jme).rx_dropped);
1386 jme_restart_rx_engine(jme);
1388 atomic_inc(&jme->rx_empty);
1392 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1394 struct jme_ring *txring = jme->txring;
1397 if (unlikely(netif_queue_stopped(jme->dev) &&
1398 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1399 msg_tx_done(jme, "TX Queue Waked.\n");
1400 netif_wake_queue(jme->dev);
1406 jme_tx_clean_tasklet(unsigned long arg)
1408 struct jme_adapter *jme = (struct jme_adapter *)arg;
1409 struct jme_ring *txring = &(jme->txring[0]);
1410 struct txdesc *txdesc = txring->desc;
1411 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1412 int i, j, cnt = 0, max, err, mask;
1414 tx_dbg(jme, "Into txclean.\n");
1416 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1419 if (unlikely(atomic_read(&jme->link_changing) != 1))
1422 if (unlikely(!netif_carrier_ok(jme->dev)))
1425 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1426 mask = jme->tx_ring_mask;
1428 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1432 if (likely(ctxbi->skb &&
1433 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1435 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1436 i, ctxbi->nr_desc, jiffies);
1438 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1440 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1441 ttxbi = txbi + ((i + j) & (mask));
1442 txdesc[(i + j) & (mask)].dw[0] = 0;
1444 pci_unmap_page(jme->pdev,
1453 dev_kfree_skb(ctxbi->skb);
1455 cnt += ctxbi->nr_desc;
1457 if (unlikely(err)) {
1458 ++(NET_STAT(jme).tx_carrier_errors);
1460 ++(NET_STAT(jme).tx_packets);
1461 NET_STAT(jme).tx_bytes += ctxbi->len;
1466 ctxbi->start_xmit = 0;
1472 i = (i + ctxbi->nr_desc) & mask;
1477 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1478 atomic_set(&txring->next_to_clean, i);
1479 atomic_add(cnt, &txring->nr_free);
1481 jme_wake_queue_if_stopped(jme);
1484 atomic_inc(&jme->tx_cleaning);
1488 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1493 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1495 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1497 * Link change event is critical
1498 * all other events are ignored
1500 jwrite32(jme, JME_IEVE, intrstat);
1501 tasklet_schedule(&jme->linkch_task);
1505 if (intrstat & INTR_TMINTR) {
1506 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1507 tasklet_schedule(&jme->pcc_task);
1510 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1511 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1512 tasklet_schedule(&jme->txclean_task);
1515 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1516 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1522 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1523 if (intrstat & INTR_RX0EMP)
1524 atomic_inc(&jme->rx_empty);
1526 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1527 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1528 jme_polling_mode(jme);
1529 JME_RX_SCHEDULE(jme);
1533 if (intrstat & INTR_RX0EMP) {
1534 atomic_inc(&jme->rx_empty);
1535 tasklet_hi_schedule(&jme->rxempty_task);
1536 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1537 tasklet_hi_schedule(&jme->rxclean_task);
1543 * Re-enable interrupt
1545 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1549 jme_intr(int irq, void *dev_id)
1551 struct net_device *netdev = dev_id;
1552 struct jme_adapter *jme = netdev_priv(netdev);
1555 intrstat = jread32(jme, JME_IEVE);
1558 * Check if it's really an interrupt for us
1560 if (unlikely(intrstat == 0))
1564 * Check if the device still exist
1566 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1569 jme_intr_msi(jme, intrstat);
1575 jme_msi(int irq, void *dev_id)
1577 struct net_device *netdev = dev_id;
1578 struct jme_adapter *jme = netdev_priv(netdev);
1581 pci_dma_sync_single_for_cpu(jme->pdev,
1583 sizeof(u32) * SHADOW_REG_NR,
1584 PCI_DMA_FROMDEVICE);
1585 intrstat = jme->shadow_regs[SHADOW_IEVE];
1586 jme->shadow_regs[SHADOW_IEVE] = 0;
1588 jme_intr_msi(jme, intrstat);
1594 jme_reset_link(struct jme_adapter *jme)
1596 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1600 jme_restart_an(struct jme_adapter *jme)
1604 spin_lock_bh(&jme->phy_lock);
1605 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1606 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1607 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1608 spin_unlock_bh(&jme->phy_lock);
1612 jme_request_irq(struct jme_adapter *jme)
1615 struct net_device *netdev = jme->dev;
1616 irq_handler_t handler = jme_intr;
1617 int irq_flags = IRQF_SHARED;
1619 if (!pci_enable_msi(jme->pdev)) {
1620 set_bit(JME_FLAG_MSI, &jme->flags);
1625 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1629 "Unable to request %s interrupt (return: %d)\n",
1630 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1633 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1634 pci_disable_msi(jme->pdev);
1635 clear_bit(JME_FLAG_MSI, &jme->flags);
1638 netdev->irq = jme->pdev->irq;
1645 jme_free_irq(struct jme_adapter *jme)
1647 free_irq(jme->pdev->irq, jme->dev);
1648 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1649 pci_disable_msi(jme->pdev);
1650 clear_bit(JME_FLAG_MSI, &jme->flags);
1651 jme->dev->irq = jme->pdev->irq;
1656 jme_open(struct net_device *netdev)
1658 struct jme_adapter *jme = netdev_priv(netdev);
1662 JME_NAPI_ENABLE(jme);
1664 tasklet_enable(&jme->txclean_task);
1665 tasklet_hi_enable(&jme->rxclean_task);
1666 tasklet_hi_enable(&jme->rxempty_task);
1668 rc = jme_request_irq(jme);
1672 jme_enable_shadow(jme);
1675 if (test_bit(JME_FLAG_SSET, &jme->flags))
1676 jme_set_settings(netdev, &jme->old_ecmd);
1678 jme_reset_phy_processor(jme);
1680 jme_reset_link(jme);
1685 netif_stop_queue(netdev);
1686 netif_carrier_off(netdev);
1691 jme_set_100m_half(struct jme_adapter *jme)
1695 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1696 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1697 BMCR_SPEED1000 | BMCR_FULLDPLX);
1698 tmp |= BMCR_SPEED100;
1701 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1704 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1706 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1709 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1711 jme_wait_link(struct jme_adapter *jme)
1713 u32 phylink, to = JME_WAIT_LINK_TIME;
1716 phylink = jme_linkstat_from_phy(jme);
1717 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1719 phylink = jme_linkstat_from_phy(jme);
1724 jme_phy_off(struct jme_adapter *jme)
1726 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1730 jme_close(struct net_device *netdev)
1732 struct jme_adapter *jme = netdev_priv(netdev);
1734 netif_stop_queue(netdev);
1735 netif_carrier_off(netdev);
1738 jme_disable_shadow(jme);
1741 JME_NAPI_DISABLE(jme);
1743 tasklet_kill(&jme->linkch_task);
1744 tasklet_kill(&jme->txclean_task);
1745 tasklet_kill(&jme->rxclean_task);
1746 tasklet_kill(&jme->rxempty_task);
1748 jme_reset_ghc_speed(jme);
1749 jme_disable_rx_engine(jme);
1750 jme_disable_tx_engine(jme);
1751 jme_reset_mac_processor(jme);
1752 jme_free_rx_resources(jme);
1753 jme_free_tx_resources(jme);
1761 jme_alloc_txdesc(struct jme_adapter *jme,
1762 struct sk_buff *skb)
1764 struct jme_ring *txring = jme->txring;
1765 int idx, nr_alloc, mask = jme->tx_ring_mask;
1767 idx = txring->next_to_use;
1768 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1770 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1773 atomic_sub(nr_alloc, &txring->nr_free);
1775 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1781 jme_fill_tx_map(struct pci_dev *pdev,
1782 struct txdesc *txdesc,
1783 struct jme_buffer_info *txbi,
1791 dmaaddr = pci_map_page(pdev,
1797 pci_dma_sync_single_for_device(pdev,
1804 txdesc->desc2.flags = TXFLAG_OWN;
1805 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1806 txdesc->desc2.datalen = cpu_to_le16(len);
1807 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1808 txdesc->desc2.bufaddrl = cpu_to_le32(
1809 (__u64)dmaaddr & 0xFFFFFFFFUL);
1811 txbi->mapping = dmaaddr;
1816 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1818 struct jme_ring *txring = jme->txring;
1819 struct txdesc *txdesc = txring->desc, *ctxdesc;
1820 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1821 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1822 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1823 int mask = jme->tx_ring_mask;
1824 struct skb_frag_struct *frag;
1827 for (i = 0 ; i < nr_frags ; ++i) {
1828 frag = &skb_shinfo(skb)->frags[i];
1829 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1830 ctxbi = txbi + ((idx + i + 2) & (mask));
1832 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1833 frag->page_offset, frag->size, hidma);
1836 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1837 ctxdesc = txdesc + ((idx + 1) & (mask));
1838 ctxbi = txbi + ((idx + 1) & (mask));
1839 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1840 offset_in_page(skb->data), len, hidma);
1845 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1847 if (unlikely(skb_shinfo(skb)->gso_size &&
1848 skb_header_cloned(skb) &&
1849 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1858 jme_tx_tso(struct sk_buff *skb,
1859 u16 *mss, u8 *flags)
1861 *mss = skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT;
1863 *flags |= TXFLAG_LSEN;
1865 if (skb->protocol == htons(ETH_P_IP)) {
1866 struct iphdr *iph = ip_hdr(skb);
1869 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1874 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1876 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1889 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1891 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1894 switch (skb->protocol) {
1895 case htons(ETH_P_IP):
1896 ip_proto = ip_hdr(skb)->protocol;
1898 case htons(ETH_P_IPV6):
1899 ip_proto = ipv6_hdr(skb)->nexthdr;
1908 *flags |= TXFLAG_TCPCS;
1911 *flags |= TXFLAG_UDPCS;
1914 msg_tx_err(jme, "Error upper layer protocol.\n");
1921 jme_tx_vlan(struct sk_buff *skb, u16 *vlan, u8 *flags)
1923 if (vlan_tx_tag_present(skb)) {
1924 *flags |= TXFLAG_TAGON;
1925 *vlan = vlan_tx_tag_get(skb);
1930 jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1932 struct jme_ring *txring = jme->txring;
1933 struct txdesc *txdesc;
1934 struct jme_buffer_info *txbi;
1937 txdesc = (struct txdesc *)txring->desc + idx;
1938 txbi = txring->bufinf + idx;
1944 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1946 * Set OWN bit at final.
1947 * When kernel transmit faster than NIC.
1948 * And NIC trying to send this descriptor before we tell
1949 * it to start sending this TX queue.
1950 * Other fields are already filled correctly.
1953 flags = TXFLAG_OWN | TXFLAG_INT;
1955 * Set checksum flags while not tso
1957 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1958 jme_tx_csum(jme, skb, &flags);
1959 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1960 txdesc->desc1.flags = flags;
1962 * Set tx buffer info after telling NIC to send
1963 * For better tx_clean timing
1966 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1968 txbi->len = skb->len;
1969 txbi->start_xmit = jiffies;
1970 if (!txbi->start_xmit)
1971 txbi->start_xmit = (0UL-1);
1977 jme_stop_queue_if_full(struct jme_adapter *jme)
1979 struct jme_ring *txring = jme->txring;
1980 struct jme_buffer_info *txbi = txring->bufinf;
1981 int idx = atomic_read(&txring->next_to_clean);
1986 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1987 netif_stop_queue(jme->dev);
1988 msg_tx_queued(jme, "TX Queue Paused.\n");
1990 if (atomic_read(&txring->nr_free)
1991 >= (jme->tx_wake_threshold)) {
1992 netif_wake_queue(jme->dev);
1993 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1997 if (unlikely(txbi->start_xmit &&
1998 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2000 netif_stop_queue(jme->dev);
2001 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
2006 * This function is already protected by netif_tx_lock()
2010 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2012 struct jme_adapter *jme = netdev_priv(netdev);
2015 if (unlikely(jme_expand_header(jme, skb))) {
2016 ++(NET_STAT(jme).tx_dropped);
2017 return NETDEV_TX_OK;
2020 idx = jme_alloc_txdesc(jme, skb);
2022 if (unlikely(idx < 0)) {
2023 netif_stop_queue(netdev);
2024 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
2026 return NETDEV_TX_BUSY;
2029 jme_map_tx_skb(jme, skb, idx);
2030 jme_fill_first_tx_desc(jme, skb, idx);
2032 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2033 TXCS_SELECT_QUEUE0 |
2036 netdev->trans_start = jiffies;
2038 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
2039 skb_shinfo(skb)->nr_frags + 2,
2041 jme_stop_queue_if_full(jme);
2043 return NETDEV_TX_OK;
2047 jme_set_macaddr(struct net_device *netdev, void *p)
2049 struct jme_adapter *jme = netdev_priv(netdev);
2050 struct sockaddr *addr = p;
2053 if (netif_running(netdev))
2056 spin_lock_bh(&jme->macaddr_lock);
2057 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2059 val = (addr->sa_data[3] & 0xff) << 24 |
2060 (addr->sa_data[2] & 0xff) << 16 |
2061 (addr->sa_data[1] & 0xff) << 8 |
2062 (addr->sa_data[0] & 0xff);
2063 jwrite32(jme, JME_RXUMA_LO, val);
2064 val = (addr->sa_data[5] & 0xff) << 8 |
2065 (addr->sa_data[4] & 0xff);
2066 jwrite32(jme, JME_RXUMA_HI, val);
2067 spin_unlock_bh(&jme->macaddr_lock);
2073 jme_set_multi(struct net_device *netdev)
2075 struct jme_adapter *jme = netdev_priv(netdev);
2076 u32 mc_hash[2] = {};
2079 spin_lock_bh(&jme->rxmcs_lock);
2081 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2083 if (netdev->flags & IFF_PROMISC) {
2084 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2085 } else if (netdev->flags & IFF_ALLMULTI) {
2086 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2087 } else if (netdev->flags & IFF_MULTICAST) {
2088 struct dev_mc_list *mclist;
2091 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2092 for (i = 0, mclist = netdev->mc_list;
2093 mclist && i < netdev->mc_count;
2094 ++i, mclist = mclist->next) {
2096 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2097 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2100 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2101 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2105 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2107 spin_unlock_bh(&jme->rxmcs_lock);
2111 jme_change_mtu(struct net_device *netdev, int new_mtu)
2113 struct jme_adapter *jme = netdev_priv(netdev);
2115 if (new_mtu == jme->old_mtu)
2118 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2119 ((new_mtu) < IPV6_MIN_MTU))
2122 if (new_mtu > 4000) {
2123 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2124 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2125 jme_restart_rx_engine(jme);
2127 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2128 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2129 jme_restart_rx_engine(jme);
2132 if (new_mtu > 1900) {
2133 netdev->features &= ~(NETIF_F_HW_CSUM |
2137 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2138 netdev->features |= NETIF_F_HW_CSUM;
2139 if (test_bit(JME_FLAG_TSO, &jme->flags))
2140 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2143 netdev->mtu = new_mtu;
2144 jme_reset_link(jme);
2150 jme_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2152 struct jme_adapter *jme = netdev_priv(netdev);
2153 struct jme_spi_op spiop;
2158 if (!capable(CAP_NET_ADMIN))
2161 copy_from_user(&spiop, ifr->ifr_data,
2162 sizeof(struct jme_spi_op));
2163 spiop.kwbuf = kmalloc(spiop.wn, GFP_KERNEL);
2168 spiop.krbuf = kmalloc(spiop.rn, GFP_KERNEL);
2173 copy_from_user(spiop.kwbuf, spiop.uwbuf, spiop.wn);
2174 rc = jme_spi_op(jme, &spiop);
2177 copy_to_user(spiop.urbuf, spiop.krbuf, spiop.rn);
2192 jme_tx_timeout(struct net_device *netdev)
2194 struct jme_adapter *jme = netdev_priv(netdev);
2197 jme_reset_phy_processor(jme);
2198 if (test_bit(JME_FLAG_SSET, &jme->flags))
2199 jme_set_settings(netdev, &jme->old_ecmd);
2202 * Force to Reset the link again
2204 jme_reset_link(jme);
2208 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2210 struct jme_adapter *jme = netdev_priv(netdev);
2216 jme_get_drvinfo(struct net_device *netdev,
2217 struct ethtool_drvinfo *info)
2219 struct jme_adapter *jme = netdev_priv(netdev);
2221 strcpy(info->driver, DRV_NAME);
2222 strcpy(info->version, DRV_VERSION);
2223 strcpy(info->bus_info, pci_name(jme->pdev));
2227 jme_get_regs_len(struct net_device *netdev)
2233 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2237 for (i = 0 ; i < len ; i += 4)
2238 p[i >> 2] = jread32(jme, reg + i);
2242 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2245 u16 *p16 = (u16 *)p;
2247 for (i = 0 ; i < reg_nr ; ++i)
2248 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2252 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2254 struct jme_adapter *jme = netdev_priv(netdev);
2255 u32 *p32 = (u32 *)p;
2257 memset(p, 0xFF, JME_REG_LEN);
2260 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2263 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2266 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2269 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2272 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2276 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2278 struct jme_adapter *jme = netdev_priv(netdev);
2280 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2281 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2283 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2284 ecmd->use_adaptive_rx_coalesce = false;
2285 ecmd->rx_coalesce_usecs = 0;
2286 ecmd->rx_max_coalesced_frames = 0;
2290 ecmd->use_adaptive_rx_coalesce = true;
2292 switch (jme->dpi.cur) {
2294 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2295 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2298 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2299 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2302 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2303 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2313 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2315 struct jme_adapter *jme = netdev_priv(netdev);
2316 struct dynpcc_info *dpi = &(jme->dpi);
2318 if (netif_running(netdev))
2321 if (ecmd->use_adaptive_rx_coalesce
2322 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2323 clear_bit(JME_FLAG_POLL, &jme->flags);
2324 jme->jme_rx = netif_rx;
2325 jme->jme_vlan_rx = vlan_hwaccel_rx;
2327 dpi->attempt = PCC_P1;
2329 jme_set_rx_pcc(jme, PCC_P1);
2330 jme_interrupt_mode(jme);
2331 } else if (!(ecmd->use_adaptive_rx_coalesce)
2332 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2333 set_bit(JME_FLAG_POLL, &jme->flags);
2334 jme->jme_rx = netif_receive_skb;
2335 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2336 jme_interrupt_mode(jme);
2343 jme_get_pauseparam(struct net_device *netdev,
2344 struct ethtool_pauseparam *ecmd)
2346 struct jme_adapter *jme = netdev_priv(netdev);
2349 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2350 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2352 spin_lock_bh(&jme->phy_lock);
2353 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2354 spin_unlock_bh(&jme->phy_lock);
2357 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2361 jme_set_pauseparam(struct net_device *netdev,
2362 struct ethtool_pauseparam *ecmd)
2364 struct jme_adapter *jme = netdev_priv(netdev);
2367 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2368 (ecmd->tx_pause != 0)) {
2371 jme->reg_txpfc |= TXPFC_PF_EN;
2373 jme->reg_txpfc &= ~TXPFC_PF_EN;
2375 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2378 spin_lock_bh(&jme->rxmcs_lock);
2379 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2380 (ecmd->rx_pause != 0)) {
2383 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2385 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2387 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2389 spin_unlock_bh(&jme->rxmcs_lock);
2391 spin_lock_bh(&jme->phy_lock);
2392 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2393 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2394 (ecmd->autoneg != 0)) {
2397 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2399 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2401 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2402 MII_ADVERTISE, val);
2404 spin_unlock_bh(&jme->phy_lock);
2410 jme_get_wol(struct net_device *netdev,
2411 struct ethtool_wolinfo *wol)
2413 struct jme_adapter *jme = netdev_priv(netdev);
2415 wol->supported = WAKE_MAGIC | WAKE_PHY;
2419 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2420 wol->wolopts |= WAKE_PHY;
2422 if (jme->reg_pmcs & PMCS_MFEN)
2423 wol->wolopts |= WAKE_MAGIC;
2428 jme_set_wol(struct net_device *netdev,
2429 struct ethtool_wolinfo *wol)
2431 struct jme_adapter *jme = netdev_priv(netdev);
2433 if (wol->wolopts & (WAKE_MAGICSECURE |
2442 if (wol->wolopts & WAKE_PHY)
2443 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2445 if (wol->wolopts & WAKE_MAGIC)
2446 jme->reg_pmcs |= PMCS_MFEN;
2448 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2454 jme_get_settings(struct net_device *netdev,
2455 struct ethtool_cmd *ecmd)
2457 struct jme_adapter *jme = netdev_priv(netdev);
2460 spin_lock_bh(&jme->phy_lock);
2461 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2462 spin_unlock_bh(&jme->phy_lock);
2467 jme_set_settings(struct net_device *netdev,
2468 struct ethtool_cmd *ecmd)
2470 struct jme_adapter *jme = netdev_priv(netdev);
2473 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2476 if (jme->mii_if.force_media &&
2477 ecmd->autoneg != AUTONEG_ENABLE &&
2478 (jme->mii_if.full_duplex != ecmd->duplex))
2481 spin_lock_bh(&jme->phy_lock);
2482 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2483 spin_unlock_bh(&jme->phy_lock);
2486 jme_reset_link(jme);
2489 set_bit(JME_FLAG_SSET, &jme->flags);
2490 jme->old_ecmd = *ecmd;
2497 jme_get_link(struct net_device *netdev)
2499 struct jme_adapter *jme = netdev_priv(netdev);
2500 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2504 jme_get_msglevel(struct net_device *netdev)
2506 struct jme_adapter *jme = netdev_priv(netdev);
2507 return jme->msg_enable;
2511 jme_set_msglevel(struct net_device *netdev, u32 value)
2513 struct jme_adapter *jme = netdev_priv(netdev);
2514 jme->msg_enable = value;
2518 jme_get_rx_csum(struct net_device *netdev)
2520 struct jme_adapter *jme = netdev_priv(netdev);
2521 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2525 jme_set_rx_csum(struct net_device *netdev, u32 on)
2527 struct jme_adapter *jme = netdev_priv(netdev);
2529 spin_lock_bh(&jme->rxmcs_lock);
2531 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2533 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2534 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2535 spin_unlock_bh(&jme->rxmcs_lock);
2541 jme_set_tx_csum(struct net_device *netdev, u32 on)
2543 struct jme_adapter *jme = netdev_priv(netdev);
2546 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2547 if (netdev->mtu <= 1900)
2548 netdev->features |= NETIF_F_HW_CSUM;
2550 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2551 netdev->features &= ~NETIF_F_HW_CSUM;
2558 jme_set_tso(struct net_device *netdev, u32 on)
2560 struct jme_adapter *jme = netdev_priv(netdev);
2563 set_bit(JME_FLAG_TSO, &jme->flags);
2564 if (netdev->mtu <= 1900)
2565 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2567 clear_bit(JME_FLAG_TSO, &jme->flags);
2568 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2575 jme_nway_reset(struct net_device *netdev)
2577 struct jme_adapter *jme = netdev_priv(netdev);
2578 jme_restart_an(jme);
2583 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2588 val = jread32(jme, JME_SMBCSR);
2589 to = JME_SMB_BUSY_TIMEOUT;
2590 while ((val & SMBCSR_BUSY) && --to) {
2592 val = jread32(jme, JME_SMBCSR);
2595 msg_hw(jme, "SMB Bus Busy.\n");
2599 jwrite32(jme, JME_SMBINTF,
2600 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2601 SMBINTF_HWRWN_READ |
2604 val = jread32(jme, JME_SMBINTF);
2605 to = JME_SMB_BUSY_TIMEOUT;
2606 while ((val & SMBINTF_HWCMD) && --to) {
2608 val = jread32(jme, JME_SMBINTF);
2611 msg_hw(jme, "SMB Bus Busy.\n");
2615 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2619 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2624 val = jread32(jme, JME_SMBCSR);
2625 to = JME_SMB_BUSY_TIMEOUT;
2626 while ((val & SMBCSR_BUSY) && --to) {
2628 val = jread32(jme, JME_SMBCSR);
2631 msg_hw(jme, "SMB Bus Busy.\n");
2635 jwrite32(jme, JME_SMBINTF,
2636 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2637 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2638 SMBINTF_HWRWN_WRITE |
2641 val = jread32(jme, JME_SMBINTF);
2642 to = JME_SMB_BUSY_TIMEOUT;
2643 while ((val & SMBINTF_HWCMD) && --to) {
2645 val = jread32(jme, JME_SMBINTF);
2648 msg_hw(jme, "SMB Bus Busy.\n");
2656 jme_get_eeprom_len(struct net_device *netdev)
2658 struct jme_adapter *jme = netdev_priv(netdev);
2660 val = jread32(jme, JME_SMBCSR);
2661 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2665 jme_get_eeprom(struct net_device *netdev,
2666 struct ethtool_eeprom *eeprom, u8 *data)
2668 struct jme_adapter *jme = netdev_priv(netdev);
2669 int i, offset = eeprom->offset, len = eeprom->len;
2672 * ethtool will check the boundary for us
2674 eeprom->magic = JME_EEPROM_MAGIC;
2675 for (i = 0 ; i < len ; ++i)
2676 data[i] = jme_smb_read(jme, i + offset);
2682 jme_set_eeprom(struct net_device *netdev,
2683 struct ethtool_eeprom *eeprom, u8 *data)
2685 struct jme_adapter *jme = netdev_priv(netdev);
2686 int i, offset = eeprom->offset, len = eeprom->len;
2688 if (eeprom->magic != JME_EEPROM_MAGIC)
2692 * ethtool will check the boundary for us
2694 for (i = 0 ; i < len ; ++i)
2695 jme_smb_write(jme, i + offset, data[i]);
2700 static const struct ethtool_ops jme_ethtool_ops = {
2701 .get_drvinfo = jme_get_drvinfo,
2702 .get_regs_len = jme_get_regs_len,
2703 .get_regs = jme_get_regs,
2704 .get_coalesce = jme_get_coalesce,
2705 .set_coalesce = jme_set_coalesce,
2706 .get_pauseparam = jme_get_pauseparam,
2707 .set_pauseparam = jme_set_pauseparam,
2708 .get_wol = jme_get_wol,
2709 .set_wol = jme_set_wol,
2710 .get_settings = jme_get_settings,
2711 .set_settings = jme_set_settings,
2712 .get_link = jme_get_link,
2713 .get_msglevel = jme_get_msglevel,
2714 .set_msglevel = jme_set_msglevel,
2715 .get_rx_csum = jme_get_rx_csum,
2716 .set_rx_csum = jme_set_rx_csum,
2717 .set_tx_csum = jme_set_tx_csum,
2718 .set_tso = jme_set_tso,
2719 .set_sg = ethtool_op_set_sg,
2720 .nway_reset = jme_nway_reset,
2721 .get_eeprom_len = jme_get_eeprom_len,
2722 .get_eeprom = jme_get_eeprom,
2723 .set_eeprom = jme_set_eeprom,
2727 jme_pci_dma64(struct pci_dev *pdev)
2729 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2730 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2733 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2734 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2737 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2738 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2745 jme_phy_init(struct jme_adapter *jme)
2749 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2750 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2754 jme_check_hw_ver(struct jme_adapter *jme)
2758 chipmode = jread32(jme, JME_CHIPMODE);
2760 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2761 jme->chipver = (chipmode & CM_CHIPVER_MASK) >> CM_CHIPVER_SHIFT;
2764 static int __devinit
2765 jme_init_one(struct pci_dev *pdev,
2766 const struct pci_device_id *ent)
2768 int rc = 0, using_dac, i;
2769 struct net_device *netdev;
2770 struct jme_adapter *jme;
2775 * set up PCI device basics
2777 rc = pci_enable_device(pdev);
2779 jeprintk(pdev, "Cannot enable PCI device.\n");
2783 using_dac = jme_pci_dma64(pdev);
2784 if (using_dac < 0) {
2785 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2787 goto err_out_disable_pdev;
2790 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2791 jeprintk(pdev, "No PCI resource region found.\n");
2793 goto err_out_disable_pdev;
2796 rc = pci_request_regions(pdev, DRV_NAME);
2798 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2799 goto err_out_disable_pdev;
2802 pci_set_master(pdev);
2805 * alloc and init net device
2807 netdev = alloc_etherdev(sizeof(*jme));
2809 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2811 goto err_out_release_regions;
2813 netdev->open = jme_open;
2814 netdev->stop = jme_close;
2815 netdev->hard_start_xmit = jme_start_xmit;
2816 netdev->set_mac_address = jme_set_macaddr;
2817 netdev->set_multicast_list = jme_set_multi;
2818 netdev->change_mtu = jme_change_mtu;
2819 netdev->do_ioctl = jme_ioctl;
2820 netdev->ethtool_ops = &jme_ethtool_ops;
2821 netdev->tx_timeout = jme_tx_timeout;
2822 netdev->watchdog_timeo = TX_TIMEOUT;
2823 netdev->vlan_rx_register = jme_vlan_rx_register;
2824 NETDEV_GET_STATS(netdev, &jme_get_stats);
2825 netdev->features = NETIF_F_HW_CSUM |
2829 NETIF_F_HW_VLAN_TX |
2832 netdev->features |= NETIF_F_HIGHDMA;
2834 SET_NETDEV_DEV(netdev, &pdev->dev);
2835 pci_set_drvdata(pdev, netdev);
2840 jme = netdev_priv(netdev);
2843 jme->jme_rx = netif_rx;
2844 jme->jme_vlan_rx = vlan_hwaccel_rx;
2845 jme->old_mtu = netdev->mtu = 1500;
2847 jme->tx_ring_size = 1 << 10;
2848 jme->tx_ring_mask = jme->tx_ring_size - 1;
2849 jme->tx_wake_threshold = 1 << 9;
2850 jme->rx_ring_size = 1 << 9;
2851 jme->rx_ring_mask = jme->rx_ring_size - 1;
2852 jme->msg_enable = JME_DEF_MSG_ENABLE;
2853 jme->regs = ioremap(pci_resource_start(pdev, 0),
2854 pci_resource_len(pdev, 0));
2856 jeprintk(pdev, "Mapping PCI resource region error.\n");
2858 goto err_out_free_netdev;
2860 jme->shadow_regs = pci_alloc_consistent(pdev,
2861 sizeof(u32) * SHADOW_REG_NR,
2862 &(jme->shadow_dma));
2863 if (!(jme->shadow_regs)) {
2864 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2870 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2871 jwrite32(jme, JME_APMC, apmc);
2872 } else if (force_pseudohp) {
2873 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2874 jwrite32(jme, JME_APMC, apmc);
2877 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2879 spin_lock_init(&jme->phy_lock);
2880 spin_lock_init(&jme->macaddr_lock);
2881 spin_lock_init(&jme->rxmcs_lock);
2883 atomic_set(&jme->link_changing, 1);
2884 atomic_set(&jme->rx_cleaning, 1);
2885 atomic_set(&jme->tx_cleaning, 1);
2886 atomic_set(&jme->rx_empty, 1);
2888 tasklet_init(&jme->pcc_task,
2890 (unsigned long) jme);
2891 tasklet_init(&jme->linkch_task,
2892 &jme_link_change_tasklet,
2893 (unsigned long) jme);
2894 tasklet_init(&jme->txclean_task,
2895 &jme_tx_clean_tasklet,
2896 (unsigned long) jme);
2897 tasklet_init(&jme->rxclean_task,
2898 &jme_rx_clean_tasklet,
2899 (unsigned long) jme);
2900 tasklet_init(&jme->rxempty_task,
2901 &jme_rx_empty_tasklet,
2902 (unsigned long) jme);
2903 tasklet_disable_nosync(&jme->txclean_task);
2904 tasklet_disable_nosync(&jme->rxclean_task);
2905 tasklet_disable_nosync(&jme->rxempty_task);
2906 jme->dpi.cur = PCC_P1;
2909 jme->reg_rxcs = RXCS_DEFAULT;
2910 jme->reg_rxmcs = RXMCS_DEFAULT;
2912 jme->reg_pmcs = PMCS_MFEN;
2913 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2914 set_bit(JME_FLAG_TSO, &jme->flags);
2917 * Get Max Read Req Size from PCI Config Space
2919 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2920 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2921 switch (jme->mrrs) {
2923 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2926 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2929 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2934 * Must check before reset_mac_processor
2936 jme_check_hw_ver(jme);
2937 jme->mii_if.dev = netdev;
2939 jme->mii_if.phy_id = 0;
2940 for (i = 1 ; i < 32 ; ++i) {
2941 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2942 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2943 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2944 jme->mii_if.phy_id = i;
2949 if (!jme->mii_if.phy_id) {
2951 jeprintk(pdev, "Can not find phy_id.\n");
2952 goto err_out_free_shadow;
2955 jme->reg_ghc |= GHC_LINK_POLL;
2957 jme->mii_if.phy_id = 1;
2959 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2960 jme->mii_if.supports_gmii = true;
2962 jme->mii_if.supports_gmii = false;
2963 jme->mii_if.mdio_read = jme_mdio_read;
2964 jme->mii_if.mdio_write = jme_mdio_write;
2968 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2974 * Reset MAC processor and reload EEPROM for MAC Address
2976 jme_reset_mac_processor(jme);
2977 rc = jme_reload_eeprom(jme);
2980 "Reload eeprom for reading MAC Address error.\n");
2981 goto err_out_free_shadow;
2983 jme_load_macaddr(netdev);
2986 * Tell stack that we are not ready to work until open()
2988 netif_carrier_off(netdev);
2989 netif_stop_queue(netdev);
2994 rc = register_netdev(netdev);
2996 jeprintk(pdev, "Cannot register net device.\n");
2997 goto err_out_free_shadow;
3001 "JMC250 gigabit%s ver:%u rev:%1x.%1x "
3002 "macaddr:%02x:%02x:%02x:%02x:%02x:%02x\n",
3003 (jme->fpgaver != 0) ? " (FPGA)" : "",
3004 (jme->fpgaver != 0) ? jme->fpgaver : jme->chipver,
3005 jme->rev & 0xf, (jme->rev >> 4) & 0xf,
3006 netdev->dev_addr[0],
3007 netdev->dev_addr[1],
3008 netdev->dev_addr[2],
3009 netdev->dev_addr[3],
3010 netdev->dev_addr[4],
3011 netdev->dev_addr[5]);
3015 err_out_free_shadow:
3016 pci_free_consistent(pdev,
3017 sizeof(u32) * SHADOW_REG_NR,
3022 err_out_free_netdev:
3023 pci_set_drvdata(pdev, NULL);
3024 free_netdev(netdev);
3025 err_out_release_regions:
3026 pci_release_regions(pdev);
3027 err_out_disable_pdev:
3028 pci_disable_device(pdev);
3033 static void __devexit
3034 jme_remove_one(struct pci_dev *pdev)
3036 struct net_device *netdev = pci_get_drvdata(pdev);
3037 struct jme_adapter *jme = netdev_priv(netdev);
3039 unregister_netdev(netdev);
3040 pci_free_consistent(pdev,
3041 sizeof(u32) * SHADOW_REG_NR,
3045 pci_set_drvdata(pdev, NULL);
3046 free_netdev(netdev);
3047 pci_release_regions(pdev);
3048 pci_disable_device(pdev);
3053 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3055 struct net_device *netdev = pci_get_drvdata(pdev);
3056 struct jme_adapter *jme = netdev_priv(netdev);
3058 atomic_dec(&jme->link_changing);
3060 netif_device_detach(netdev);
3061 netif_stop_queue(netdev);
3064 tasklet_disable(&jme->txclean_task);
3065 tasklet_disable(&jme->rxclean_task);
3066 tasklet_disable(&jme->rxempty_task);
3068 jme_disable_shadow(jme);
3070 if (netif_carrier_ok(netdev)) {
3071 if (test_bit(JME_FLAG_POLL, &jme->flags))
3072 jme_polling_mode(jme);
3074 jme_stop_pcc_timer(jme);
3075 jme_reset_ghc_speed(jme);
3076 jme_disable_rx_engine(jme);
3077 jme_disable_tx_engine(jme);
3078 jme_reset_mac_processor(jme);
3079 jme_free_rx_resources(jme);
3080 jme_free_tx_resources(jme);
3081 netif_carrier_off(netdev);
3085 tasklet_enable(&jme->txclean_task);
3086 tasklet_hi_enable(&jme->rxclean_task);
3087 tasklet_hi_enable(&jme->rxempty_task);
3089 pci_save_state(pdev);
3090 if (jme->reg_pmcs) {
3091 jme_set_100m_half(jme);
3093 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3096 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3098 pci_enable_wake(pdev, PCI_D3cold, true);
3102 pci_set_power_state(pdev, PCI_D3cold);
3108 jme_resume(struct pci_dev *pdev)
3110 struct net_device *netdev = pci_get_drvdata(pdev);
3111 struct jme_adapter *jme = netdev_priv(netdev);
3114 pci_restore_state(pdev);
3116 if (test_bit(JME_FLAG_SSET, &jme->flags))
3117 jme_set_settings(netdev, &jme->old_ecmd);
3119 jme_reset_phy_processor(jme);
3121 jme_enable_shadow(jme);
3123 netif_device_attach(netdev);
3125 atomic_inc(&jme->link_changing);
3127 jme_reset_link(jme);
3132 static struct pci_device_id jme_pci_tbl[] = {
3133 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3134 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3138 static struct pci_driver jme_driver = {
3140 .id_table = jme_pci_tbl,
3141 .probe = jme_init_one,
3142 .remove = __devexit_p(jme_remove_one),
3144 .suspend = jme_suspend,
3145 .resume = jme_resume,
3146 #endif /* CONFIG_PM */
3150 jme_init_module(void)
3152 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
3153 "driver version %s\n", DRV_VERSION);
3154 return pci_register_driver(&jme_driver);
3158 jme_cleanup_module(void)
3160 pci_unregister_driver(&jme_driver);
3163 module_init(jme_init_module);
3164 module_exit(jme_cleanup_module);
3166 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3167 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3168 MODULE_LICENSE("GPL");
3169 MODULE_VERSION(DRV_VERSION);
3170 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);