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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#ifndef __JME_H_INCLUDED__
26#define __JME_H_INCLUDED__
27#include <linux/interrupt.h>
28
29#define DRV_NAME "jme"
30#define DRV_VERSION "1.0.8.1-jmmod"
31#define PFX DRV_NAME ": "
32
33#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
34#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35
36/*
37 * Message related definitions
38 */
39#define JME_DEF_MSG_ENABLE \
40 (NETIF_MSG_PROBE | \
41 NETIF_MSG_LINK | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR | \
44 NETIF_MSG_HW)
45
46#ifndef pr_err
47#define pr_err(fmt, arg...) \
48 printk(KERN_ERR fmt, ##arg)
49#endif
50#ifndef netdev_err
51#define netdev_err(netdev, fmt, arg...) \
52 pr_err(fmt, ##arg)
53#endif
54
55#ifdef TX_DEBUG
56#define tx_dbg(priv, fmt, args...) \
57 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
58#else
59#define tx_dbg(priv, fmt, args...) \
60do { \
61 if (0) \
62 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
63} while (0)
64#endif
65
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
67#define jme_msg(msglvl, type, priv, fmt, args...) \
68 if (netif_msg_##type(priv)) \
69 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
70
71#define msg_probe(priv, fmt, args...) \
72 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
73
74#define msg_link(priv, fmt, args...) \
75 jme_msg(KERN_INFO, link, priv, fmt, ## args)
76
77#define msg_intr(priv, fmt, args...) \
78 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
79
80#define msg_rx_err(priv, fmt, args...) \
81 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
82
83#define msg_rx_status(priv, fmt, args...) \
84 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
85
86#define msg_tx_err(priv, fmt, args...) \
87 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
88
89#define msg_tx_done(priv, fmt, args...) \
90 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
91
92#define msg_tx_queued(priv, fmt, args...) \
93 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
94
95#define msg_hw(priv, fmt, args...) \
96 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
97
98#ifndef netif_info
99#define netif_info(priv, type, dev, fmt, args...) \
100 msg_ ## type(priv, fmt, ## args)
101#endif
102#ifndef netif_err
103#define netif_err(priv, type, dev, fmt, args...) \
104 msg_ ## type(priv, fmt, ## args)
105#endif
106#endif
107
108#ifndef NETIF_F_TSO6
109#define NETIF_F_TSO6 0
110#endif
111#ifndef NETIF_F_IPV6_CSUM
112#define NETIF_F_IPV6_CSUM 0
113#endif
114
115/*
116 * Extra PCI Configuration space interface
117 */
118#define PCI_DCSR_MRRS 0x59
119#define PCI_DCSR_MRRS_MASK 0x70
120
121enum pci_dcsr_mrrs_vals {
122 MRRS_128B = 0x00,
123 MRRS_256B = 0x10,
124 MRRS_512B = 0x20,
125 MRRS_1024B = 0x30,
126 MRRS_2048B = 0x40,
127 MRRS_4096B = 0x50,
128};
129
130#define PCI_SPI 0xB0
131
132enum pci_spi_bits {
133 SPI_EN = 0x10,
134 SPI_MISO = 0x08,
135 SPI_MOSI = 0x04,
136 SPI_SCLK = 0x02,
137 SPI_CS = 0x01,
138};
139
140struct jme_spi_op {
141 void __user *uwbuf;
142 void __user *urbuf;
143 __u8 wn; /* Number of write actions */
144 __u8 rn; /* Number of read actions */
145 __u8 bitn; /* Number of bits per action */
146 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
147 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
148
149 /* Internal use only */
150 u8 *kwbuf;
151 u8 *krbuf;
152 u8 sr;
153 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
154};
155
156enum jme_spi_op_bits {
157 SPI_MODE_CPHA = 0x01,
158 SPI_MODE_CPOL = 0x02,
159 SPI_MODE_DUP = 0x80,
160};
161
162#define HALF_US 500 /* 500 ns */
163#define JMESPIIOCTL SIOCDEVPRIVATE
164
165#define PCI_PRIV_PE1 0xE4
166
167enum pci_priv_pe1_bit_masks {
168 PE1_ASPMSUPRT = 0x00000003, /*
169 * RW:
170 * Aspm_support[1:0]
171 * (R/W Port of 5C[11:10])
172 */
173 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
174 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
175 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
176 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
177 PE1_GPREG0 = 0x0000FF00, /*
178 * SRW:
179 * Cfg_gp_reg0
180 * [7:6] phy_giga BG control
181 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
182 * [4:0] Reserved
183 */
184 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
185 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
186 PE1_REVID = 0xFF000000, /* RO: Rev ID */
187};
188
189enum pci_priv_pe1_values {
190 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
191 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
192 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
193 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
194};
195
196/*
197 * Dynamic(adaptive)/Static PCC values
198 */
199enum dynamic_pcc_values {
200 PCC_OFF = 0,
201 PCC_P1 = 1,
202 PCC_P2 = 2,
203 PCC_P3 = 3,
204
205 PCC_OFF_TO = 0,
206 PCC_P1_TO = 1,
207 PCC_P2_TO = 64,
208 PCC_P3_TO = 128,
209
210 PCC_OFF_CNT = 0,
211 PCC_P1_CNT = 1,
212 PCC_P2_CNT = 16,
213 PCC_P3_CNT = 32,
214};
215struct dynpcc_info {
216 unsigned long last_bytes;
217 unsigned long last_pkts;
218 unsigned long intr_cnt;
219 unsigned char cur;
220 unsigned char attempt;
221 unsigned char cnt;
222};
223#define PCC_INTERVAL_US 100000
224#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
225#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
226#define PCC_P2_THRESHOLD 800
227#define PCC_INTR_THRESHOLD 800
228#define PCC_TX_TO 1000
229#define PCC_TX_CNT 8
230
231/*
232 * TX/RX Descriptors
233 *
234 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
235 */
236#define RING_DESC_ALIGN 16 /* Descriptor alignment */
237#define TX_DESC_SIZE 16
238#define TX_RING_NR 8
239#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
240
241struct txdesc {
242 union {
243 __u8 all[16];
244 __le32 dw[4];
245 struct {
246 /* DW0 */
247 __le16 vlan;
248 __u8 rsv1;
249 __u8 flags;
250
251 /* DW1 */
252 __le16 datalen;
253 __le16 mss;
254
255 /* DW2 */
256 __le16 pktsize;
257 __le16 rsv2;
258
259 /* DW3 */
260 __le32 bufaddr;
261 } desc1;
262 struct {
263 /* DW0 */
264 __le16 rsv1;
265 __u8 rsv2;
266 __u8 flags;
267
268 /* DW1 */
269 __le16 datalen;
270 __le16 rsv3;
271
272 /* DW2 */
273 __le32 bufaddrh;
274
275 /* DW3 */
276 __le32 bufaddrl;
277 } desc2;
278 struct {
279 /* DW0 */
280 __u8 ehdrsz;
281 __u8 rsv1;
282 __u8 rsv2;
283 __u8 flags;
284
285 /* DW1 */
286 __le16 trycnt;
287 __le16 segcnt;
288
289 /* DW2 */
290 __le16 pktsz;
291 __le16 rsv3;
292
293 /* DW3 */
294 __le32 bufaddrl;
295 } descwb;
296 };
297};
298
299enum jme_txdesc_flags_bits {
300 TXFLAG_OWN = 0x80,
301 TXFLAG_INT = 0x40,
302 TXFLAG_64BIT = 0x20,
303 TXFLAG_TCPCS = 0x10,
304 TXFLAG_UDPCS = 0x08,
305 TXFLAG_IPCS = 0x04,
306 TXFLAG_LSEN = 0x02,
307 TXFLAG_TAGON = 0x01,
308};
309
310#define TXDESC_MSS_SHIFT 2
311enum jme_txwbdesc_flags_bits {
312 TXWBFLAG_OWN = 0x80,
313 TXWBFLAG_INT = 0x40,
314 TXWBFLAG_TMOUT = 0x20,
315 TXWBFLAG_TRYOUT = 0x10,
316 TXWBFLAG_COL = 0x08,
317
318 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
319 TXWBFLAG_TRYOUT |
320 TXWBFLAG_COL,
321};
322
323#define RX_DESC_SIZE 16
324#define RX_RING_NR 4
325#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
326#define RX_BUF_DMA_ALIGN 8
327#define RX_PREPAD_SIZE 10
328#define ETH_CRC_LEN 2
329#define RX_VLANHDR_LEN 2
330#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
331 ETH_HLEN + \
332 ETH_CRC_LEN + \
333 RX_VLANHDR_LEN + \
334 RX_BUF_DMA_ALIGN)
335
336struct rxdesc {
337 union {
338 __u8 all[16];
339 __le32 dw[4];
340 struct {
341 /* DW0 */
342 __le16 rsv2;
343 __u8 rsv1;
344 __u8 flags;
345
346 /* DW1 */
347 __le16 datalen;
348 __le16 wbcpl;
349
350 /* DW2 */
351 __le32 bufaddrh;
352
353 /* DW3 */
354 __le32 bufaddrl;
355 } desc1;
356 struct {
357 /* DW0 */
358 __le16 vlan;
359 __le16 flags;
360
361 /* DW1 */
362 __le16 framesize;
363 __u8 errstat;
364 __u8 desccnt;
365
366 /* DW2 */
367 __le32 rsshash;
368
369 /* DW3 */
370 __u8 hashfun;
371 __u8 hashtype;
372 __le16 resrv;
373 } descwb;
374 };
375};
376
377enum jme_rxdesc_flags_bits {
378 RXFLAG_OWN = 0x80,
379 RXFLAG_INT = 0x40,
380 RXFLAG_64BIT = 0x20,
381};
382
383enum jme_rxwbdesc_flags_bits {
384 RXWBFLAG_OWN = 0x8000,
385 RXWBFLAG_INT = 0x4000,
386 RXWBFLAG_MF = 0x2000,
387 RXWBFLAG_64BIT = 0x2000,
388 RXWBFLAG_TCPON = 0x1000,
389 RXWBFLAG_UDPON = 0x0800,
390 RXWBFLAG_IPCS = 0x0400,
391 RXWBFLAG_TCPCS = 0x0200,
392 RXWBFLAG_UDPCS = 0x0100,
393 RXWBFLAG_TAGON = 0x0080,
394 RXWBFLAG_IPV4 = 0x0040,
395 RXWBFLAG_IPV6 = 0x0020,
396 RXWBFLAG_PAUSE = 0x0010,
397 RXWBFLAG_MAGIC = 0x0008,
398 RXWBFLAG_WAKEUP = 0x0004,
399 RXWBFLAG_DEST = 0x0003,
400 RXWBFLAG_DEST_UNI = 0x0001,
401 RXWBFLAG_DEST_MUL = 0x0002,
402 RXWBFLAG_DEST_BRO = 0x0003,
403};
404
405enum jme_rxwbdesc_desccnt_mask {
406 RXWBDCNT_WBCPL = 0x80,
407 RXWBDCNT_DCNT = 0x7F,
408};
409
410enum jme_rxwbdesc_errstat_bits {
411 RXWBERR_LIMIT = 0x80,
412 RXWBERR_MIIER = 0x40,
413 RXWBERR_NIBON = 0x20,
414 RXWBERR_COLON = 0x10,
415 RXWBERR_ABORT = 0x08,
416 RXWBERR_SHORT = 0x04,
417 RXWBERR_OVERUN = 0x02,
418 RXWBERR_CRCERR = 0x01,
419 RXWBERR_ALLERR = 0xFF,
420};
421
422/*
423 * Buffer information corresponding to ring descriptors.
424 */
425struct jme_buffer_info {
426 struct sk_buff *skb;
427 dma_addr_t mapping;
428 int len;
429 int nr_desc;
430 unsigned long start_xmit;
431};
432
433/*
434 * The structure holding buffer information and ring descriptors all together.
435 */
436struct jme_ring {
437 void *alloc; /* pointer to allocated memory */
438 void *desc; /* pointer to ring memory */
439 dma_addr_t dmaalloc; /* phys address of ring alloc */
440 dma_addr_t dma; /* phys address for ring dma */
441
442 /* Buffer information corresponding to each descriptor */
443 struct jme_buffer_info *bufinf;
444
445 int next_to_use;
446 atomic_t next_to_clean;
447 atomic_t nr_free;
448};
449
450#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
451#define false 0
452#define true 0
453#define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
454#define PCI_VENDOR_ID_JMICRON 0x197B
455#endif
456
457#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
458#define PCI_VDEVICE(vendor, device) \
459 PCI_VENDOR_ID_##vendor, (device), \
460 PCI_ANY_ID, PCI_ANY_ID, 0, 0
461#endif
462
463#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
464#define NET_STAT(priv) priv->stats
465#define NETDEV_GET_STATS(netdev, fun_ptr) \
466 netdev->get_stats = fun_ptr
467#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
468/*
469 * CentOS 5.2 have *_hdr helpers back-ported
470 */
471#ifdef RHEL_RELEASE_CODE
472#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2)
473#define __DEFINE_IPHDR_HELPERS__
474#endif
475#else
476#define __DEFINE_IPHDR_HELPERS__
477#endif
478#else
479#define NET_STAT(priv) (priv->dev->stats)
480#define NETDEV_GET_STATS(netdev, fun_ptr)
481#define DECLARE_NET_DEVICE_STATS
482#endif
483
484#ifdef __DEFINE_IPHDR_HELPERS__
485static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
486{
487 return skb->nh.iph;
488}
489
490static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
491{
492 return skb->nh.ipv6h;
493}
494
495static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
496{
497 return skb->h.th;
498}
499#endif
500
501#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
502#define DECLARE_NAPI_STRUCT
503#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
504 dev->poll = pollfn; \
505 dev->weight = q;
506#define JME_NAPI_HOLDER(holder) struct net_device *holder
507#define JME_NAPI_WEIGHT(w) int *w
508#define JME_NAPI_WEIGHT_VAL(w) *w
509#define JME_NAPI_WEIGHT_SET(w, r) *w = r
510#define DECLARE_NETDEV struct net_device *netdev = jme->dev;
511#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
512#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
513#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
514#define JME_RX_SCHEDULE_PREP(priv) \
515 netif_rx_schedule_prep(priv->dev)
516#define JME_RX_SCHEDULE(priv) \
517 __netif_rx_schedule(priv->dev);
518#else
519#define DECLARE_NAPI_STRUCT struct napi_struct napi;
520#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
521 netif_napi_add(dev, napis, pollfn, q);
522#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
523#define JME_NAPI_WEIGHT(w) int w
524#define JME_NAPI_WEIGHT_VAL(w) w
525#define JME_NAPI_WEIGHT_SET(w, r)
526#define DECLARE_NETDEV
527#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
528#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
529#define JME_NAPI_DISABLE(priv) \
530 if (!napi_disable_pending(&priv->napi)) \
531 napi_disable(&priv->napi);
532#define JME_RX_SCHEDULE_PREP(priv) \
533 napi_schedule_prep(&priv->napi)
534#define JME_RX_SCHEDULE(priv) \
535 __napi_schedule(&priv->napi);
536#endif
537
538#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
539#define JME_NEW_PM_API
540#endif
541
542#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)
543static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
544{
545 return ep->speed;
546}
547#endif
548
549/*
550 * Jmac Adapter Private data
551 */
552struct jme_adapter {
553 struct pci_dev *pdev;
554 struct net_device *dev;
555 void __iomem *regs;
556 struct mii_if_info mii_if;
557 struct jme_ring rxring[RX_RING_NR];
558 struct jme_ring txring[TX_RING_NR];
559 spinlock_t phy_lock;
560 spinlock_t macaddr_lock;
561 spinlock_t rxmcs_lock;
562 struct tasklet_struct rxempty_task;
563 struct tasklet_struct rxclean_task;
564 struct tasklet_struct txclean_task;
565 struct tasklet_struct linkch_task;
566 struct tasklet_struct pcc_task;
567 unsigned long flags;
568 u32 reg_txcs;
569 u32 reg_txpfc;
570 u32 reg_rxcs;
571 u32 reg_rxmcs;
572 u32 reg_ghc;
573 u32 reg_pmcs;
574 u32 reg_gpreg1;
575 u32 phylink;
576 u32 tx_ring_size;
577 u32 tx_ring_mask;
578 u32 tx_wake_threshold;
579 u32 rx_ring_size;
580 u32 rx_ring_mask;
581 u8 mrrs;
582 unsigned int fpgaver;
583 u8 chiprev;
584 u8 chip_main_rev;
585 u8 chip_sub_rev;
586 u8 pcirev;
587 u32 msg_enable;
588 struct ethtool_cmd old_ecmd;
589 unsigned int old_mtu;
590 struct vlan_group *vlgrp;
591 struct dynpcc_info dpi;
592 atomic_t intr_sem;
593 atomic_t link_changing;
594 atomic_t tx_cleaning;
595 atomic_t rx_cleaning;
596 atomic_t rx_empty;
597 int (*jme_rx)(struct sk_buff *skb);
598 int (*jme_vlan_rx)(struct sk_buff *skb,
599 struct vlan_group *grp,
600 unsigned short vlan_tag);
601 DECLARE_NAPI_STRUCT
602 DECLARE_NET_DEVICE_STATS
603};
604
605#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
606static struct net_device_stats *
607jme_get_stats(struct net_device *netdev)
608{
609 struct jme_adapter *jme = netdev_priv(netdev);
610 return &jme->stats;
611}
612#endif
613
614enum jme_flags_bits {
615 JME_FLAG_MSI = 1,
616 JME_FLAG_SSET = 2,
617 JME_FLAG_TXCSUM = 3,
618 JME_FLAG_TSO = 4,
619 JME_FLAG_POLL = 5,
620 JME_FLAG_SHUTDOWN = 6,
621};
622
623#define TX_TIMEOUT (5 * HZ)
624#define JME_REG_LEN 0x500
625#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
626
627#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
628static inline struct jme_adapter*
629jme_napi_priv(struct net_device *holder)
630{
631 struct jme_adapter *jme;
632 jme = netdev_priv(holder);
633 return jme;
634}
635#else
636static inline struct jme_adapter*
637jme_napi_priv(struct napi_struct *napi)
638{
639 struct jme_adapter *jme;
640 jme = container_of(napi, struct jme_adapter, napi);
641 return jme;
642}
643#endif
644
645/*
646 * MMaped I/O Resters
647 */
648enum jme_iomap_offsets {
649 JME_MAC = 0x0000,
650 JME_PHY = 0x0400,
651 JME_MISC = 0x0800,
652 JME_RSS = 0x0C00,
653};
654
655enum jme_iomap_lens {
656 JME_MAC_LEN = 0x80,
657 JME_PHY_LEN = 0x58,
658 JME_MISC_LEN = 0x98,
659 JME_RSS_LEN = 0xFF,
660};
661
662enum jme_iomap_regs {
663 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
664 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
665 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
666 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
667 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
668 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
669 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
670 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
671
672 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
673 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
674 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
675 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
676 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
677 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
678 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
679 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
680 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
681 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
682 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
683 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
684
685 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
686 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
687 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
688
689
690 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
691 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
692 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
693 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
694 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
695
696
697 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
698 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
699 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
700 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
701 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
702 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
703 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
704 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
705 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
706 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
707 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
708 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
709 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
710 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
711 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
712 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
713};
714
715/*
716 * TX Control/Status Bits
717 */
718enum jme_txcs_bits {
719 TXCS_QUEUE7S = 0x00008000,
720 TXCS_QUEUE6S = 0x00004000,
721 TXCS_QUEUE5S = 0x00002000,
722 TXCS_QUEUE4S = 0x00001000,
723 TXCS_QUEUE3S = 0x00000800,
724 TXCS_QUEUE2S = 0x00000400,
725 TXCS_QUEUE1S = 0x00000200,
726 TXCS_QUEUE0S = 0x00000100,
727 TXCS_FIFOTH = 0x000000C0,
728 TXCS_DMASIZE = 0x00000030,
729 TXCS_BURST = 0x00000004,
730 TXCS_ENABLE = 0x00000001,
731};
732
733enum jme_txcs_value {
734 TXCS_FIFOTH_16QW = 0x000000C0,
735 TXCS_FIFOTH_12QW = 0x00000080,
736 TXCS_FIFOTH_8QW = 0x00000040,
737 TXCS_FIFOTH_4QW = 0x00000000,
738
739 TXCS_DMASIZE_64B = 0x00000000,
740 TXCS_DMASIZE_128B = 0x00000010,
741 TXCS_DMASIZE_256B = 0x00000020,
742 TXCS_DMASIZE_512B = 0x00000030,
743
744 TXCS_SELECT_QUEUE0 = 0x00000000,
745 TXCS_SELECT_QUEUE1 = 0x00010000,
746 TXCS_SELECT_QUEUE2 = 0x00020000,
747 TXCS_SELECT_QUEUE3 = 0x00030000,
748 TXCS_SELECT_QUEUE4 = 0x00040000,
749 TXCS_SELECT_QUEUE5 = 0x00050000,
750 TXCS_SELECT_QUEUE6 = 0x00060000,
751 TXCS_SELECT_QUEUE7 = 0x00070000,
752
753 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
754 TXCS_BURST,
755};
756
757#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
758
759/*
760 * TX MAC Control/Status Bits
761 */
762enum jme_txmcs_bit_masks {
763 TXMCS_IFG2 = 0xC0000000,
764 TXMCS_IFG1 = 0x30000000,
765 TXMCS_TTHOLD = 0x00000300,
766 TXMCS_FBURST = 0x00000080,
767 TXMCS_CARRIEREXT = 0x00000040,
768 TXMCS_DEFER = 0x00000020,
769 TXMCS_BACKOFF = 0x00000010,
770 TXMCS_CARRIERSENSE = 0x00000008,
771 TXMCS_COLLISION = 0x00000004,
772 TXMCS_CRC = 0x00000002,
773 TXMCS_PADDING = 0x00000001,
774};
775
776enum jme_txmcs_values {
777 TXMCS_IFG2_6_4 = 0x00000000,
778 TXMCS_IFG2_8_5 = 0x40000000,
779 TXMCS_IFG2_10_6 = 0x80000000,
780 TXMCS_IFG2_12_7 = 0xC0000000,
781
782 TXMCS_IFG1_8_4 = 0x00000000,
783 TXMCS_IFG1_12_6 = 0x10000000,
784 TXMCS_IFG1_16_8 = 0x20000000,
785 TXMCS_IFG1_20_10 = 0x30000000,
786
787 TXMCS_TTHOLD_1_8 = 0x00000000,
788 TXMCS_TTHOLD_1_4 = 0x00000100,
789 TXMCS_TTHOLD_1_2 = 0x00000200,
790 TXMCS_TTHOLD_FULL = 0x00000300,
791
792 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
793 TXMCS_IFG1_16_8 |
794 TXMCS_TTHOLD_FULL |
795 TXMCS_DEFER |
796 TXMCS_CRC |
797 TXMCS_PADDING,
798};
799
800enum jme_txpfc_bits_masks {
801 TXPFC_VLAN_TAG = 0xFFFF0000,
802 TXPFC_VLAN_EN = 0x00008000,
803 TXPFC_PF_EN = 0x00000001,
804};
805
806enum jme_txtrhd_bits_masks {
807 TXTRHD_TXPEN = 0x80000000,
808 TXTRHD_TXP = 0x7FFFFF00,
809 TXTRHD_TXREN = 0x00000080,
810 TXTRHD_TXRL = 0x0000007F,
811};
812
813enum jme_txtrhd_shifts {
814 TXTRHD_TXP_SHIFT = 8,
815 TXTRHD_TXRL_SHIFT = 0,
816};
817
818enum jme_txtrhd_values {
819 TXTRHD_FULLDUPLEX = 0x00000000,
820 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
821 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
822 TXTRHD_TXREN |
823 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
824};
825
826/*
827 * RX Control/Status Bits
828 */
829enum jme_rxcs_bit_masks {
830 /* FIFO full threshold for transmitting Tx Pause Packet */
831 RXCS_FIFOTHTP = 0x30000000,
832 /* FIFO threshold for processing next packet */
833 RXCS_FIFOTHNP = 0x0C000000,
834 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
835 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
836 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
837 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
838 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
839 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
840 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
841 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
842 RXCS_QST = 0x00000004, /* Receive queue start */
843 RXCS_SUSPEND = 0x00000002,
844 RXCS_ENABLE = 0x00000001,
845};
846
847enum jme_rxcs_values {
848 RXCS_FIFOTHTP_16T = 0x00000000,
849 RXCS_FIFOTHTP_32T = 0x10000000,
850 RXCS_FIFOTHTP_64T = 0x20000000,
851 RXCS_FIFOTHTP_128T = 0x30000000,
852
853 RXCS_FIFOTHNP_16QW = 0x00000000,
854 RXCS_FIFOTHNP_32QW = 0x04000000,
855 RXCS_FIFOTHNP_64QW = 0x08000000,
856 RXCS_FIFOTHNP_128QW = 0x0C000000,
857
858 RXCS_DMAREQSZ_16B = 0x00000000,
859 RXCS_DMAREQSZ_32B = 0x01000000,
860 RXCS_DMAREQSZ_64B = 0x02000000,
861 RXCS_DMAREQSZ_128B = 0x03000000,
862
863 RXCS_QUEUESEL_Q0 = 0x00000000,
864 RXCS_QUEUESEL_Q1 = 0x00010000,
865 RXCS_QUEUESEL_Q2 = 0x00020000,
866 RXCS_QUEUESEL_Q3 = 0x00030000,
867
868 RXCS_RETRYGAP_256ns = 0x00000000,
869 RXCS_RETRYGAP_512ns = 0x00001000,
870 RXCS_RETRYGAP_1024ns = 0x00002000,
871 RXCS_RETRYGAP_2048ns = 0x00003000,
872 RXCS_RETRYGAP_4096ns = 0x00004000,
873 RXCS_RETRYGAP_8192ns = 0x00005000,
874 RXCS_RETRYGAP_16384ns = 0x00006000,
875 RXCS_RETRYGAP_32768ns = 0x00007000,
876
877 RXCS_RETRYCNT_0 = 0x00000000,
878 RXCS_RETRYCNT_4 = 0x00000100,
879 RXCS_RETRYCNT_8 = 0x00000200,
880 RXCS_RETRYCNT_12 = 0x00000300,
881 RXCS_RETRYCNT_16 = 0x00000400,
882 RXCS_RETRYCNT_20 = 0x00000500,
883 RXCS_RETRYCNT_24 = 0x00000600,
884 RXCS_RETRYCNT_28 = 0x00000700,
885 RXCS_RETRYCNT_32 = 0x00000800,
886 RXCS_RETRYCNT_36 = 0x00000900,
887 RXCS_RETRYCNT_40 = 0x00000A00,
888 RXCS_RETRYCNT_44 = 0x00000B00,
889 RXCS_RETRYCNT_48 = 0x00000C00,
890 RXCS_RETRYCNT_52 = 0x00000D00,
891 RXCS_RETRYCNT_56 = 0x00000E00,
892 RXCS_RETRYCNT_60 = 0x00000F00,
893
894 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
895 RXCS_FIFOTHNP_128QW |
896 RXCS_DMAREQSZ_128B |
897 RXCS_RETRYGAP_256ns |
898 RXCS_RETRYCNT_32,
899};
900
901#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
902
903/*
904 * RX MAC Control/Status Bits
905 */
906enum jme_rxmcs_bits {
907 RXMCS_ALLFRAME = 0x00000800,
908 RXMCS_BRDFRAME = 0x00000400,
909 RXMCS_MULFRAME = 0x00000200,
910 RXMCS_UNIFRAME = 0x00000100,
911 RXMCS_ALLMULFRAME = 0x00000080,
912 RXMCS_MULFILTERED = 0x00000040,
913 RXMCS_RXCOLLDEC = 0x00000020,
914 RXMCS_FLOWCTRL = 0x00000008,
915 RXMCS_VTAGRM = 0x00000004,
916 RXMCS_PREPAD = 0x00000002,
917 RXMCS_CHECKSUM = 0x00000001,
918
919 RXMCS_DEFAULT = RXMCS_VTAGRM |
920 RXMCS_PREPAD |
921 RXMCS_FLOWCTRL |
922 RXMCS_CHECKSUM,
923};
924
925/*
926 * Wakeup Frame setup interface registers
927 */
928#define WAKEUP_FRAME_NR 8
929#define WAKEUP_FRAME_MASK_DWNR 4
930
931enum jme_wfoi_bit_masks {
932 WFOI_MASK_SEL = 0x00000070,
933 WFOI_CRC_SEL = 0x00000008,
934 WFOI_FRAME_SEL = 0x00000007,
935};
936
937enum jme_wfoi_shifts {
938 WFOI_MASK_SHIFT = 4,
939};
940
941/*
942 * SMI Related definitions
943 */
944enum jme_smi_bit_mask {
945 SMI_DATA_MASK = 0xFFFF0000,
946 SMI_REG_ADDR_MASK = 0x0000F800,
947 SMI_PHY_ADDR_MASK = 0x000007C0,
948 SMI_OP_WRITE = 0x00000020,
949 /* Set to 1, after req done it'll be cleared to 0 */
950 SMI_OP_REQ = 0x00000010,
951 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
952 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
953 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
954 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
955};
956
957enum jme_smi_bit_shift {
958 SMI_DATA_SHIFT = 16,
959 SMI_REG_ADDR_SHIFT = 11,
960 SMI_PHY_ADDR_SHIFT = 6,
961};
962
963static inline u32 smi_reg_addr(int x)
964{
965 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
966}
967
968static inline u32 smi_phy_addr(int x)
969{
970 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
971}
972
973#define JME_PHY_TIMEOUT 100 /* 100 msec */
974#define JME_PHY_REG_NR 32
975
976/*
977 * Global Host Control
978 */
979enum jme_ghc_bit_mask {
980 GHC_SWRST = 0x40000000,
981 GHC_TO_CLK_SRC = 0x00C00000,
982 GHC_TXMAC_CLK_SRC = 0x00300000,
983 GHC_DPX = 0x00000040,
984 GHC_SPEED = 0x00000030,
985 GHC_LINK_POLL = 0x00000001,
986};
987
988enum jme_ghc_speed_val {
989 GHC_SPEED_10M = 0x00000010,
990 GHC_SPEED_100M = 0x00000020,
991 GHC_SPEED_1000M = 0x00000030,
992};
993
994enum jme_ghc_to_clk {
995 GHC_TO_CLK_OFF = 0x00000000,
996 GHC_TO_CLK_GPHY = 0x00400000,
997 GHC_TO_CLK_PCIE = 0x00800000,
998 GHC_TO_CLK_INVALID = 0x00C00000,
999};
1000
1001enum jme_ghc_txmac_clk {
1002 GHC_TXMAC_CLK_OFF = 0x00000000,
1003 GHC_TXMAC_CLK_GPHY = 0x00100000,
1004 GHC_TXMAC_CLK_PCIE = 0x00200000,
1005 GHC_TXMAC_CLK_INVALID = 0x00300000,
1006};
1007
1008/*
1009 * Power management control and status register
1010 */
1011enum jme_pmcs_bit_masks {
1012 PMCS_STMASK = 0xFFFF0000,
1013 PMCS_WF7DET = 0x80000000,
1014 PMCS_WF6DET = 0x40000000,
1015 PMCS_WF5DET = 0x20000000,
1016 PMCS_WF4DET = 0x10000000,
1017 PMCS_WF3DET = 0x08000000,
1018 PMCS_WF2DET = 0x04000000,
1019 PMCS_WF1DET = 0x02000000,
1020 PMCS_WF0DET = 0x01000000,
1021 PMCS_LFDET = 0x00040000,
1022 PMCS_LRDET = 0x00020000,
1023 PMCS_MFDET = 0x00010000,
1024 PMCS_ENMASK = 0x0000FFFF,
1025 PMCS_WF7EN = 0x00008000,
1026 PMCS_WF6EN = 0x00004000,
1027 PMCS_WF5EN = 0x00002000,
1028 PMCS_WF4EN = 0x00001000,
1029 PMCS_WF3EN = 0x00000800,
1030 PMCS_WF2EN = 0x00000400,
1031 PMCS_WF1EN = 0x00000200,
1032 PMCS_WF0EN = 0x00000100,
1033 PMCS_LFEN = 0x00000004,
1034 PMCS_LREN = 0x00000002,
1035 PMCS_MFEN = 0x00000001,
1036};
1037
1038/*
1039 * New PHY Power Control Register
1040 */
1041enum jme_phy_pwr_bit_masks {
1042 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1043 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1044 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1045 PHY_PWR_CLKSEL = 0x08000000, /*
1046 * XTL_OUT Clock select
1047 * (an internal free-running clock)
1048 * 0: xtl_out = phy_giga.A_XTL25_O
1049 * 1: xtl_out = phy_giga.PD_OSC
1050 */
1051};
1052
1053/*
1054 * Giga PHY Status Registers
1055 */
1056enum jme_phy_link_bit_mask {
1057 PHY_LINK_SPEED_MASK = 0x0000C000,
1058 PHY_LINK_DUPLEX = 0x00002000,
1059 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
1060 PHY_LINK_UP = 0x00000400,
1061 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
1062 PHY_LINK_MDI_STAT = 0x00000040,
1063};
1064
1065enum jme_phy_link_speed_val {
1066 PHY_LINK_SPEED_10M = 0x00000000,
1067 PHY_LINK_SPEED_100M = 0x00004000,
1068 PHY_LINK_SPEED_1000M = 0x00008000,
1069};
1070
1071#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
1072
1073/*
1074 * SMB Control and Status
1075 */
1076enum jme_smbcsr_bit_mask {
1077 SMBCSR_CNACK = 0x00020000,
1078 SMBCSR_RELOAD = 0x00010000,
1079 SMBCSR_EEPROMD = 0x00000020,
1080 SMBCSR_INITDONE = 0x00000010,
1081 SMBCSR_BUSY = 0x0000000F,
1082};
1083
1084enum jme_smbintf_bit_mask {
1085 SMBINTF_HWDATR = 0xFF000000,
1086 SMBINTF_HWDATW = 0x00FF0000,
1087 SMBINTF_HWADDR = 0x0000FF00,
1088 SMBINTF_HWRWN = 0x00000020,
1089 SMBINTF_HWCMD = 0x00000010,
1090 SMBINTF_FASTM = 0x00000008,
1091 SMBINTF_GPIOSCL = 0x00000004,
1092 SMBINTF_GPIOSDA = 0x00000002,
1093 SMBINTF_GPIOEN = 0x00000001,
1094};
1095
1096enum jme_smbintf_vals {
1097 SMBINTF_HWRWN_READ = 0x00000020,
1098 SMBINTF_HWRWN_WRITE = 0x00000000,
1099};
1100
1101enum jme_smbintf_shifts {
1102 SMBINTF_HWDATR_SHIFT = 24,
1103 SMBINTF_HWDATW_SHIFT = 16,
1104 SMBINTF_HWADDR_SHIFT = 8,
1105};
1106
1107#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1108#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1109#define JME_SMB_LEN 256
1110#define JME_EEPROM_MAGIC 0x250
1111
1112/*
1113 * Timer Control/Status Register
1114 */
1115enum jme_tmcsr_bit_masks {
1116 TMCSR_SWIT = 0x80000000,
1117 TMCSR_EN = 0x01000000,
1118 TMCSR_CNT = 0x00FFFFFF,
1119};
1120
1121/*
1122 * General Purpose REG-0
1123 */
1124enum jme_gpreg0_masks {
1125 GPREG0_DISSH = 0xFF000000,
1126 GPREG0_PCIRLMT = 0x00300000,
1127 GPREG0_PCCNOMUTCLR = 0x00040000,
1128 GPREG0_LNKINTPOLL = 0x00001000,
1129 GPREG0_PCCTMR = 0x00000300,
1130 GPREG0_PHYADDR = 0x0000001F,
1131};
1132
1133enum jme_gpreg0_vals {
1134 GPREG0_DISSH_DW7 = 0x80000000,
1135 GPREG0_DISSH_DW6 = 0x40000000,
1136 GPREG0_DISSH_DW5 = 0x20000000,
1137 GPREG0_DISSH_DW4 = 0x10000000,
1138 GPREG0_DISSH_DW3 = 0x08000000,
1139 GPREG0_DISSH_DW2 = 0x04000000,
1140 GPREG0_DISSH_DW1 = 0x02000000,
1141 GPREG0_DISSH_DW0 = 0x01000000,
1142 GPREG0_DISSH_ALL = 0xFF000000,
1143
1144 GPREG0_PCIRLMT_8 = 0x00000000,
1145 GPREG0_PCIRLMT_6 = 0x00100000,
1146 GPREG0_PCIRLMT_5 = 0x00200000,
1147 GPREG0_PCIRLMT_4 = 0x00300000,
1148
1149 GPREG0_PCCTMR_16ns = 0x00000000,
1150 GPREG0_PCCTMR_256ns = 0x00000100,
1151 GPREG0_PCCTMR_1us = 0x00000200,
1152 GPREG0_PCCTMR_1ms = 0x00000300,
1153
1154 GPREG0_PHYADDR_1 = 0x00000001,
1155
1156 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1157 GPREG0_PCCTMR_1us |
1158 GPREG0_PHYADDR_1,
1159};
1160
1161/*
1162 * General Purpose REG-1
1163 */
1164enum jme_gpreg1_bit_masks {
1165 GPREG1_RXCLKOFF = 0x04000000,
1166 GPREG1_PCREQN = 0x00020000,
1167 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1168 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1169 GPREG1_INTRDELAYUNIT = 0x00000018,
1170 GPREG1_INTRDELAYENABLE = 0x00000007,
1171};
1172
1173enum jme_gpreg1_vals {
1174 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1175 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1176 GPREG1_INTDLYUNIT_1US = 0x00000010,
1177 GPREG1_INTDLYUNIT_16US = 0x00000018,
1178
1179 GPREG1_INTDLYEN_1U = 0x00000001,
1180 GPREG1_INTDLYEN_2U = 0x00000002,
1181 GPREG1_INTDLYEN_3U = 0x00000003,
1182 GPREG1_INTDLYEN_4U = 0x00000004,
1183 GPREG1_INTDLYEN_5U = 0x00000005,
1184 GPREG1_INTDLYEN_6U = 0x00000006,
1185 GPREG1_INTDLYEN_7U = 0x00000007,
1186
1187 GPREG1_DEFAULT = GPREG1_PCREQN,
1188};
1189
1190/*
1191 * Interrupt Status Bits
1192 */
1193enum jme_interrupt_bits {
1194 INTR_SWINTR = 0x80000000,
1195 INTR_TMINTR = 0x40000000,
1196 INTR_LINKCH = 0x20000000,
1197 INTR_PAUSERCV = 0x10000000,
1198 INTR_MAGICRCV = 0x08000000,
1199 INTR_WAKERCV = 0x04000000,
1200 INTR_PCCRX0TO = 0x02000000,
1201 INTR_PCCRX1TO = 0x01000000,
1202 INTR_PCCRX2TO = 0x00800000,
1203 INTR_PCCRX3TO = 0x00400000,
1204 INTR_PCCTXTO = 0x00200000,
1205 INTR_PCCRX0 = 0x00100000,
1206 INTR_PCCRX1 = 0x00080000,
1207 INTR_PCCRX2 = 0x00040000,
1208 INTR_PCCRX3 = 0x00020000,
1209 INTR_PCCTX = 0x00010000,
1210 INTR_RX3EMP = 0x00008000,
1211 INTR_RX2EMP = 0x00004000,
1212 INTR_RX1EMP = 0x00002000,
1213 INTR_RX0EMP = 0x00001000,
1214 INTR_RX3 = 0x00000800,
1215 INTR_RX2 = 0x00000400,
1216 INTR_RX1 = 0x00000200,
1217 INTR_RX0 = 0x00000100,
1218 INTR_TX7 = 0x00000080,
1219 INTR_TX6 = 0x00000040,
1220 INTR_TX5 = 0x00000020,
1221 INTR_TX4 = 0x00000010,
1222 INTR_TX3 = 0x00000008,
1223 INTR_TX2 = 0x00000004,
1224 INTR_TX1 = 0x00000002,
1225 INTR_TX0 = 0x00000001,
1226};
1227
1228static const u32 INTR_ENABLE = INTR_SWINTR |
1229 INTR_TMINTR |
1230 INTR_LINKCH |
1231 INTR_PCCRX0TO |
1232 INTR_PCCRX0 |
1233 INTR_PCCTXTO |
1234 INTR_PCCTX |
1235 INTR_RX0EMP;
1236
1237/*
1238 * PCC Control Registers
1239 */
1240enum jme_pccrx_masks {
1241 PCCRXTO_MASK = 0xFFFF0000,
1242 PCCRX_MASK = 0x0000FF00,
1243};
1244
1245enum jme_pcctx_masks {
1246 PCCTXTO_MASK = 0xFFFF0000,
1247 PCCTX_MASK = 0x0000FF00,
1248 PCCTX_QS_MASK = 0x000000FF,
1249};
1250
1251enum jme_pccrx_shifts {
1252 PCCRXTO_SHIFT = 16,
1253 PCCRX_SHIFT = 8,
1254};
1255
1256enum jme_pcctx_shifts {
1257 PCCTXTO_SHIFT = 16,
1258 PCCTX_SHIFT = 8,
1259};
1260
1261enum jme_pcctx_bits {
1262 PCCTXQ0_EN = 0x00000001,
1263 PCCTXQ1_EN = 0x00000002,
1264 PCCTXQ2_EN = 0x00000004,
1265 PCCTXQ3_EN = 0x00000008,
1266 PCCTXQ4_EN = 0x00000010,
1267 PCCTXQ5_EN = 0x00000020,
1268 PCCTXQ6_EN = 0x00000040,
1269 PCCTXQ7_EN = 0x00000080,
1270};
1271
1272/*
1273 * Chip Mode Register
1274 */
1275enum jme_chipmode_bit_masks {
1276 CM_FPGAVER_MASK = 0xFFFF0000,
1277 CM_CHIPREV_MASK = 0x0000FF00,
1278 CM_CHIPMODE_MASK = 0x0000000F,
1279};
1280
1281enum jme_chipmode_shifts {
1282 CM_FPGAVER_SHIFT = 16,
1283 CM_CHIPREV_SHIFT = 8,
1284};
1285
1286/*
1287 * Aggressive Power Mode Control
1288 */
1289enum jme_apmc_bits {
1290 JME_APMC_PCIE_SD_EN = 0x40000000,
1291 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1292 JME_APMC_EPIEN = 0x04000000,
1293 JME_APMC_EPIEN_CTRL = 0x03000000,
1294};
1295
1296enum jme_apmc_values {
1297 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1298 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1299};
1300
1301#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1302
1303#ifdef REG_DEBUG
1304static char *MAC_REG_NAME[] = {
1305 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1306 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1307 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1308 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1309 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1310 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1311 "JME_PMCS"};
1312
1313static char *PE_REG_NAME[] = {
1314 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1315 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1316 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1317 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1318 "JME_SMBCSR", "JME_SMBINTF"};
1319
1320static char *MISC_REG_NAME[] = {
1321 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1322 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1323 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1324 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1325 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1326 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1327 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1328 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1329 "JME_PCCSRX0"};
1330
1331static inline void reg_dbg(const struct jme_adapter *jme,
1332 const char *msg, u32 val, u32 reg)
1333{
1334 const char *regname;
1335 switch (reg & 0xF00) {
1336 case 0x000:
1337 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1338 break;
1339 case 0x400:
1340 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1341 break;
1342 case 0x800:
1343 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1344 break;
1345 default:
1346 regname = PE_REG_NAME[0];
1347 }
1348 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1349 msg, val, regname);
1350}
1351#else
1352static inline void reg_dbg(const struct jme_adapter *jme,
1353 const char *msg, u32 val, u32 reg) {}
1354#endif
1355
1356/*
1357 * Read/Write MMaped I/O Registers
1358 */
1359static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1360{
1361 return readl(jme->regs + reg);
1362}
1363
1364static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1365{
1366 reg_dbg(jme, "REG WRITE", val, reg);
1367 writel(val, jme->regs + reg);
1368 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1369}
1370
1371static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1372{
1373 /*
1374 * Read after write should cause flush
1375 */
1376 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1377 writel(val, jme->regs + reg);
1378 readl(jme->regs + reg);
1379 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1380}
1381
1382/*
1383 * PHY Regs
1384 */
1385enum jme_phy_reg17_bit_masks {
1386 PREG17_SPEED = 0xC000,
1387 PREG17_DUPLEX = 0x2000,
1388 PREG17_SPDRSV = 0x0800,
1389 PREG17_LNKUP = 0x0400,
1390 PREG17_MDI = 0x0040,
1391};
1392
1393enum jme_phy_reg17_vals {
1394 PREG17_SPEED_10M = 0x0000,
1395 PREG17_SPEED_100M = 0x4000,
1396 PREG17_SPEED_1000M = 0x8000,
1397};
1398
1399#define BMSR_ANCOMP 0x0020
1400
1401/*
1402 * Workaround
1403 */
1404static inline int is_buggy250(unsigned short device, u8 chiprev)
1405{
1406 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1407}
1408
1409static inline int new_phy_power_ctrl(u8 chip_main_rev)
1410{
1411 return chip_main_rev >= 5;
1412}
1413
1414/*
1415 * Function prototypes
1416 */
1417static int jme_set_settings(struct net_device *netdev,
1418 struct ethtool_cmd *ecmd);
1419static void jme_set_unicastaddr(struct net_device *netdev);
1420static void jme_set_multi(struct net_device *netdev);
1421
1422#endif
1423
JMicron Ethernet Linux driver