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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#ifndef __JME_H_INCLUDED__
26#define __JME_H_INCLUDED__
27#include <linux/interrupt.h>
28
29#define DRV_NAME "jme"
30#define DRV_VERSION "1.0.8-jmmod"
31#define PFX DRV_NAME ": "
32
33#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
34#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35
36/*
37 * Message related definitions
38 */
39#define JME_DEF_MSG_ENABLE \
40 (NETIF_MSG_PROBE | \
41 NETIF_MSG_LINK | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR | \
44 NETIF_MSG_HW)
45
46#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
47#define pr_err(fmt, arg...) \
48 printk(KERN_ERR fmt, ##arg)
49#endif
50#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
51#define netdev_err(netdev, fmt, arg...) \
52 pr_err(fmt, ##arg)
53#endif
54
55#ifdef TX_DEBUG
56#define tx_dbg(priv, fmt, args...) \
57 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
58#else
59#define tx_dbg(priv, fmt, args...) \
60do { \
61 if (0) \
62 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
63} while (0)
64#endif
65
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
67#define jme_msg(msglvl, type, priv, fmt, args...) \
68 if (netif_msg_##type(priv)) \
69 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
70
71#define msg_probe(priv, fmt, args...) \
72 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
73
74#define msg_link(priv, fmt, args...) \
75 jme_msg(KERN_INFO, link, priv, fmt, ## args)
76
77#define msg_intr(priv, fmt, args...) \
78 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
79
80#define msg_rx_err(priv, fmt, args...) \
81 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
82
83#define msg_rx_status(priv, fmt, args...) \
84 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
85
86#define msg_tx_err(priv, fmt, args...) \
87 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
88
89#define msg_tx_done(priv, fmt, args...) \
90 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
91
92#define msg_tx_queued(priv, fmt, args...) \
93 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
94
95#define msg_hw(priv, fmt, args...) \
96 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
97
98#define netif_info(priv, type, dev, fmt, args...) \
99 msg_ ## type(priv, fmt, ## args)
100#define netif_err(priv, type, dev, fmt, args...) \
101 msg_ ## type(priv, fmt, ## args)
102#endif
103
104#ifndef NETIF_F_TSO6
105#define NETIF_F_TSO6 0
106#endif
107#ifndef NETIF_F_IPV6_CSUM
108#define NETIF_F_IPV6_CSUM 0
109#endif
110
111/*
112 * Extra PCI Configuration space interface
113 */
114#define PCI_DCSR_MRRS 0x59
115#define PCI_DCSR_MRRS_MASK 0x70
116
117enum pci_dcsr_mrrs_vals {
118 MRRS_128B = 0x00,
119 MRRS_256B = 0x10,
120 MRRS_512B = 0x20,
121 MRRS_1024B = 0x30,
122 MRRS_2048B = 0x40,
123 MRRS_4096B = 0x50,
124};
125
126#define PCI_SPI 0xB0
127
128enum pci_spi_bits {
129 SPI_EN = 0x10,
130 SPI_MISO = 0x08,
131 SPI_MOSI = 0x04,
132 SPI_SCLK = 0x02,
133 SPI_CS = 0x01,
134};
135
136struct jme_spi_op {
137 void __user *uwbuf;
138 void __user *urbuf;
139 __u8 wn; /* Number of write actions */
140 __u8 rn; /* Number of read actions */
141 __u8 bitn; /* Number of bits per action */
142 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
143 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
144
145 /* Internal use only */
146 u8 *kwbuf;
147 u8 *krbuf;
148 u8 sr;
149 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
150};
151
152enum jme_spi_op_bits {
153 SPI_MODE_CPHA = 0x01,
154 SPI_MODE_CPOL = 0x02,
155 SPI_MODE_DUP = 0x80,
156};
157
158#define HALF_US 500 /* 500 ns */
159#define JMESPIIOCTL SIOCDEVPRIVATE
160
161#define PCI_PRIV_PE1 0xE4
162
163enum pci_priv_pe1_bit_masks {
164 PE1_ASPMSUPRT = 0x00000003, /*
165 * RW:
166 * Aspm_support[1:0]
167 * (R/W Port of 5C[11:10])
168 */
169 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
170 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
171 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
172 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
173 PE1_GPREG0 = 0x0000FF00, /*
174 * SRW:
175 * Cfg_gp_reg0
176 * [7:6] phy_giga BG control
177 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
178 * [4:0] Reserved
179 */
180 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
181 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
182 PE1_REVID = 0xFF000000, /* RO: Rev ID */
183};
184
185enum pci_priv_pe1_values {
186 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
187 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
188 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
189 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
190};
191
192/*
193 * Dynamic(adaptive)/Static PCC values
194 */
195enum dynamic_pcc_values {
196 PCC_OFF = 0,
197 PCC_P1 = 1,
198 PCC_P2 = 2,
199 PCC_P3 = 3,
200
201 PCC_OFF_TO = 0,
202 PCC_P1_TO = 1,
203 PCC_P2_TO = 64,
204 PCC_P3_TO = 128,
205
206 PCC_OFF_CNT = 0,
207 PCC_P1_CNT = 1,
208 PCC_P2_CNT = 16,
209 PCC_P3_CNT = 32,
210};
211struct dynpcc_info {
212 unsigned long last_bytes;
213 unsigned long last_pkts;
214 unsigned long intr_cnt;
215 unsigned char cur;
216 unsigned char attempt;
217 unsigned char cnt;
218};
219#define PCC_INTERVAL_US 100000
220#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
221#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
222#define PCC_P2_THRESHOLD 800
223#define PCC_INTR_THRESHOLD 800
224#define PCC_TX_TO 1000
225#define PCC_TX_CNT 8
226
227/*
228 * TX/RX Descriptors
229 *
230 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
231 */
232#define RING_DESC_ALIGN 16 /* Descriptor alignment */
233#define TX_DESC_SIZE 16
234#define TX_RING_NR 8
235#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
236
237struct txdesc {
238 union {
239 __u8 all[16];
240 __le32 dw[4];
241 struct {
242 /* DW0 */
243 __le16 vlan;
244 __u8 rsv1;
245 __u8 flags;
246
247 /* DW1 */
248 __le16 datalen;
249 __le16 mss;
250
251 /* DW2 */
252 __le16 pktsize;
253 __le16 rsv2;
254
255 /* DW3 */
256 __le32 bufaddr;
257 } desc1;
258 struct {
259 /* DW0 */
260 __le16 rsv1;
261 __u8 rsv2;
262 __u8 flags;
263
264 /* DW1 */
265 __le16 datalen;
266 __le16 rsv3;
267
268 /* DW2 */
269 __le32 bufaddrh;
270
271 /* DW3 */
272 __le32 bufaddrl;
273 } desc2;
274 struct {
275 /* DW0 */
276 __u8 ehdrsz;
277 __u8 rsv1;
278 __u8 rsv2;
279 __u8 flags;
280
281 /* DW1 */
282 __le16 trycnt;
283 __le16 segcnt;
284
285 /* DW2 */
286 __le16 pktsz;
287 __le16 rsv3;
288
289 /* DW3 */
290 __le32 bufaddrl;
291 } descwb;
292 };
293};
294
295enum jme_txdesc_flags_bits {
296 TXFLAG_OWN = 0x80,
297 TXFLAG_INT = 0x40,
298 TXFLAG_64BIT = 0x20,
299 TXFLAG_TCPCS = 0x10,
300 TXFLAG_UDPCS = 0x08,
301 TXFLAG_IPCS = 0x04,
302 TXFLAG_LSEN = 0x02,
303 TXFLAG_TAGON = 0x01,
304};
305
306#define TXDESC_MSS_SHIFT 2
307enum jme_txwbdesc_flags_bits {
308 TXWBFLAG_OWN = 0x80,
309 TXWBFLAG_INT = 0x40,
310 TXWBFLAG_TMOUT = 0x20,
311 TXWBFLAG_TRYOUT = 0x10,
312 TXWBFLAG_COL = 0x08,
313
314 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
315 TXWBFLAG_TRYOUT |
316 TXWBFLAG_COL,
317};
318
319#define RX_DESC_SIZE 16
320#define RX_RING_NR 4
321#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
322#define RX_BUF_DMA_ALIGN 8
323#define RX_PREPAD_SIZE 10
324#define ETH_CRC_LEN 2
325#define RX_VLANHDR_LEN 2
326#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
327 ETH_HLEN + \
328 ETH_CRC_LEN + \
329 RX_VLANHDR_LEN + \
330 RX_BUF_DMA_ALIGN)
331
332struct rxdesc {
333 union {
334 __u8 all[16];
335 __le32 dw[4];
336 struct {
337 /* DW0 */
338 __le16 rsv2;
339 __u8 rsv1;
340 __u8 flags;
341
342 /* DW1 */
343 __le16 datalen;
344 __le16 wbcpl;
345
346 /* DW2 */
347 __le32 bufaddrh;
348
349 /* DW3 */
350 __le32 bufaddrl;
351 } desc1;
352 struct {
353 /* DW0 */
354 __le16 vlan;
355 __le16 flags;
356
357 /* DW1 */
358 __le16 framesize;
359 __u8 errstat;
360 __u8 desccnt;
361
362 /* DW2 */
363 __le32 rsshash;
364
365 /* DW3 */
366 __u8 hashfun;
367 __u8 hashtype;
368 __le16 resrv;
369 } descwb;
370 };
371};
372
373enum jme_rxdesc_flags_bits {
374 RXFLAG_OWN = 0x80,
375 RXFLAG_INT = 0x40,
376 RXFLAG_64BIT = 0x20,
377};
378
379enum jme_rxwbdesc_flags_bits {
380 RXWBFLAG_OWN = 0x8000,
381 RXWBFLAG_INT = 0x4000,
382 RXWBFLAG_MF = 0x2000,
383 RXWBFLAG_64BIT = 0x2000,
384 RXWBFLAG_TCPON = 0x1000,
385 RXWBFLAG_UDPON = 0x0800,
386 RXWBFLAG_IPCS = 0x0400,
387 RXWBFLAG_TCPCS = 0x0200,
388 RXWBFLAG_UDPCS = 0x0100,
389 RXWBFLAG_TAGON = 0x0080,
390 RXWBFLAG_IPV4 = 0x0040,
391 RXWBFLAG_IPV6 = 0x0020,
392 RXWBFLAG_PAUSE = 0x0010,
393 RXWBFLAG_MAGIC = 0x0008,
394 RXWBFLAG_WAKEUP = 0x0004,
395 RXWBFLAG_DEST = 0x0003,
396 RXWBFLAG_DEST_UNI = 0x0001,
397 RXWBFLAG_DEST_MUL = 0x0002,
398 RXWBFLAG_DEST_BRO = 0x0003,
399};
400
401enum jme_rxwbdesc_desccnt_mask {
402 RXWBDCNT_WBCPL = 0x80,
403 RXWBDCNT_DCNT = 0x7F,
404};
405
406enum jme_rxwbdesc_errstat_bits {
407 RXWBERR_LIMIT = 0x80,
408 RXWBERR_MIIER = 0x40,
409 RXWBERR_NIBON = 0x20,
410 RXWBERR_COLON = 0x10,
411 RXWBERR_ABORT = 0x08,
412 RXWBERR_SHORT = 0x04,
413 RXWBERR_OVERUN = 0x02,
414 RXWBERR_CRCERR = 0x01,
415 RXWBERR_ALLERR = 0xFF,
416};
417
418/*
419 * Buffer information corresponding to ring descriptors.
420 */
421struct jme_buffer_info {
422 struct sk_buff *skb;
423 dma_addr_t mapping;
424 int len;
425 int nr_desc;
426 unsigned long start_xmit;
427};
428
429/*
430 * The structure holding buffer information and ring descriptors all together.
431 */
432struct jme_ring {
433 void *alloc; /* pointer to allocated memory */
434 void *desc; /* pointer to ring memory */
435 dma_addr_t dmaalloc; /* phys address of ring alloc */
436 dma_addr_t dma; /* phys address for ring dma */
437
438 /* Buffer information corresponding to each descriptor */
439 struct jme_buffer_info *bufinf;
440
441 int next_to_use;
442 atomic_t next_to_clean;
443 atomic_t nr_free;
444};
445
446#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
447#define false 0
448#define true 0
449#define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
450#define PCI_VENDOR_ID_JMICRON 0x197B
451#endif
452
453#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
454#define PCI_VDEVICE(vendor, device) \
455 PCI_VENDOR_ID_##vendor, (device), \
456 PCI_ANY_ID, PCI_ANY_ID, 0, 0
457#endif
458
459#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
460#define NET_STAT(priv) priv->stats
461#define NETDEV_GET_STATS(netdev, fun_ptr) \
462 netdev->get_stats = fun_ptr
463#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
464/*
465 * CentOS 5.2 have *_hdr helpers back-ported
466 */
467#ifdef RHEL_RELEASE_CODE
468#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2)
469#define __DEFINE_IPHDR_HELPERS__
470#endif
471#else
472#define __DEFINE_IPHDR_HELPERS__
473#endif
474#else
475#define NET_STAT(priv) (priv->dev->stats)
476#define NETDEV_GET_STATS(netdev, fun_ptr)
477#define DECLARE_NET_DEVICE_STATS
478#endif
479
480#ifdef __DEFINE_IPHDR_HELPERS__
481static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
482{
483 return skb->nh.iph;
484}
485
486static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
487{
488 return skb->nh.ipv6h;
489}
490
491static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
492{
493 return skb->h.th;
494}
495#endif
496
497#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
498#define DECLARE_NAPI_STRUCT
499#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
500 dev->poll = pollfn; \
501 dev->weight = q;
502#define JME_NAPI_HOLDER(holder) struct net_device *holder
503#define JME_NAPI_WEIGHT(w) int *w
504#define JME_NAPI_WEIGHT_VAL(w) *w
505#define JME_NAPI_WEIGHT_SET(w, r) *w = r
506#define DECLARE_NETDEV struct net_device *netdev = jme->dev;
507#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
508#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
509#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
510#define JME_RX_SCHEDULE_PREP(priv) \
511 netif_rx_schedule_prep(priv->dev)
512#define JME_RX_SCHEDULE(priv) \
513 __netif_rx_schedule(priv->dev);
514#else
515#define DECLARE_NAPI_STRUCT struct napi_struct napi;
516#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
517 netif_napi_add(dev, napis, pollfn, q);
518#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
519#define JME_NAPI_WEIGHT(w) int w
520#define JME_NAPI_WEIGHT_VAL(w) w
521#define JME_NAPI_WEIGHT_SET(w, r)
522#define DECLARE_NETDEV
523#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
524#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
525#define JME_NAPI_DISABLE(priv) \
526 if (!napi_disable_pending(&priv->napi)) \
527 napi_disable(&priv->napi);
528#define JME_RX_SCHEDULE_PREP(priv) \
529 napi_schedule_prep(&priv->napi)
530#define JME_RX_SCHEDULE(priv) \
531 __napi_schedule(&priv->napi);
532#endif
533
534#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
535#define JME_NEW_PM_API
536#endif
537
538/*
539 * Jmac Adapter Private data
540 */
541struct jme_adapter {
542 struct pci_dev *pdev;
543 struct net_device *dev;
544 void __iomem *regs;
545 struct mii_if_info mii_if;
546 struct jme_ring rxring[RX_RING_NR];
547 struct jme_ring txring[TX_RING_NR];
548 spinlock_t phy_lock;
549 spinlock_t macaddr_lock;
550 spinlock_t rxmcs_lock;
551 struct tasklet_struct rxempty_task;
552 struct tasklet_struct rxclean_task;
553 struct tasklet_struct txclean_task;
554 struct tasklet_struct linkch_task;
555 struct tasklet_struct pcc_task;
556 unsigned long flags;
557 u32 reg_txcs;
558 u32 reg_txpfc;
559 u32 reg_rxcs;
560 u32 reg_rxmcs;
561 u32 reg_ghc;
562 u32 reg_pmcs;
563 u32 reg_gpreg1;
564 u32 phylink;
565 u32 tx_ring_size;
566 u32 tx_ring_mask;
567 u32 tx_wake_threshold;
568 u32 rx_ring_size;
569 u32 rx_ring_mask;
570 u8 mrrs;
571 unsigned int fpgaver;
572 u8 chiprev;
573 u8 chip_main_rev;
574 u8 chip_sub_rev;
575 u8 pcirev;
576 u32 msg_enable;
577 struct ethtool_cmd old_ecmd;
578 unsigned int old_mtu;
579 struct vlan_group *vlgrp;
580 struct dynpcc_info dpi;
581 atomic_t intr_sem;
582 atomic_t link_changing;
583 atomic_t tx_cleaning;
584 atomic_t rx_cleaning;
585 atomic_t rx_empty;
586 int (*jme_rx)(struct sk_buff *skb);
587 int (*jme_vlan_rx)(struct sk_buff *skb,
588 struct vlan_group *grp,
589 unsigned short vlan_tag);
590 DECLARE_NAPI_STRUCT
591 DECLARE_NET_DEVICE_STATS
592};
593
594#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
595static struct net_device_stats *
596jme_get_stats(struct net_device *netdev)
597{
598 struct jme_adapter *jme = netdev_priv(netdev);
599 return &jme->stats;
600}
601#endif
602
603enum jme_flags_bits {
604 JME_FLAG_MSI = 1,
605 JME_FLAG_SSET = 2,
606 JME_FLAG_TXCSUM = 3,
607 JME_FLAG_TSO = 4,
608 JME_FLAG_POLL = 5,
609 JME_FLAG_SHUTDOWN = 6,
610};
611
612#define TX_TIMEOUT (5 * HZ)
613#define JME_REG_LEN 0x500
614#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
615
616#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
617static inline struct jme_adapter*
618jme_napi_priv(struct net_device *holder)
619{
620 struct jme_adapter *jme;
621 jme = netdev_priv(holder);
622 return jme;
623}
624#else
625static inline struct jme_adapter*
626jme_napi_priv(struct napi_struct *napi)
627{
628 struct jme_adapter *jme;
629 jme = container_of(napi, struct jme_adapter, napi);
630 return jme;
631}
632#endif
633
634/*
635 * MMaped I/O Resters
636 */
637enum jme_iomap_offsets {
638 JME_MAC = 0x0000,
639 JME_PHY = 0x0400,
640 JME_MISC = 0x0800,
641 JME_RSS = 0x0C00,
642};
643
644enum jme_iomap_lens {
645 JME_MAC_LEN = 0x80,
646 JME_PHY_LEN = 0x58,
647 JME_MISC_LEN = 0x98,
648 JME_RSS_LEN = 0xFF,
649};
650
651enum jme_iomap_regs {
652 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
653 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
654 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
655 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
656 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
657 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
658 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
659 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
660
661 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
662 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
663 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
664 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
665 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
666 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
667 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
668 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
669 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
670 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
671 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
672 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
673
674 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
675 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
676 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
677
678
679 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
680 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
681 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
682 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
683 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
684
685
686 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
687 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
688 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
689 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
690 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
691 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
692 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
693 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
694 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
695 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
696 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
697 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
698 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
699 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
700 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
701 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
702};
703
704/*
705 * TX Control/Status Bits
706 */
707enum jme_txcs_bits {
708 TXCS_QUEUE7S = 0x00008000,
709 TXCS_QUEUE6S = 0x00004000,
710 TXCS_QUEUE5S = 0x00002000,
711 TXCS_QUEUE4S = 0x00001000,
712 TXCS_QUEUE3S = 0x00000800,
713 TXCS_QUEUE2S = 0x00000400,
714 TXCS_QUEUE1S = 0x00000200,
715 TXCS_QUEUE0S = 0x00000100,
716 TXCS_FIFOTH = 0x000000C0,
717 TXCS_DMASIZE = 0x00000030,
718 TXCS_BURST = 0x00000004,
719 TXCS_ENABLE = 0x00000001,
720};
721
722enum jme_txcs_value {
723 TXCS_FIFOTH_16QW = 0x000000C0,
724 TXCS_FIFOTH_12QW = 0x00000080,
725 TXCS_FIFOTH_8QW = 0x00000040,
726 TXCS_FIFOTH_4QW = 0x00000000,
727
728 TXCS_DMASIZE_64B = 0x00000000,
729 TXCS_DMASIZE_128B = 0x00000010,
730 TXCS_DMASIZE_256B = 0x00000020,
731 TXCS_DMASIZE_512B = 0x00000030,
732
733 TXCS_SELECT_QUEUE0 = 0x00000000,
734 TXCS_SELECT_QUEUE1 = 0x00010000,
735 TXCS_SELECT_QUEUE2 = 0x00020000,
736 TXCS_SELECT_QUEUE3 = 0x00030000,
737 TXCS_SELECT_QUEUE4 = 0x00040000,
738 TXCS_SELECT_QUEUE5 = 0x00050000,
739 TXCS_SELECT_QUEUE6 = 0x00060000,
740 TXCS_SELECT_QUEUE7 = 0x00070000,
741
742 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
743 TXCS_BURST,
744};
745
746#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
747
748/*
749 * TX MAC Control/Status Bits
750 */
751enum jme_txmcs_bit_masks {
752 TXMCS_IFG2 = 0xC0000000,
753 TXMCS_IFG1 = 0x30000000,
754 TXMCS_TTHOLD = 0x00000300,
755 TXMCS_FBURST = 0x00000080,
756 TXMCS_CARRIEREXT = 0x00000040,
757 TXMCS_DEFER = 0x00000020,
758 TXMCS_BACKOFF = 0x00000010,
759 TXMCS_CARRIERSENSE = 0x00000008,
760 TXMCS_COLLISION = 0x00000004,
761 TXMCS_CRC = 0x00000002,
762 TXMCS_PADDING = 0x00000001,
763};
764
765enum jme_txmcs_values {
766 TXMCS_IFG2_6_4 = 0x00000000,
767 TXMCS_IFG2_8_5 = 0x40000000,
768 TXMCS_IFG2_10_6 = 0x80000000,
769 TXMCS_IFG2_12_7 = 0xC0000000,
770
771 TXMCS_IFG1_8_4 = 0x00000000,
772 TXMCS_IFG1_12_6 = 0x10000000,
773 TXMCS_IFG1_16_8 = 0x20000000,
774 TXMCS_IFG1_20_10 = 0x30000000,
775
776 TXMCS_TTHOLD_1_8 = 0x00000000,
777 TXMCS_TTHOLD_1_4 = 0x00000100,
778 TXMCS_TTHOLD_1_2 = 0x00000200,
779 TXMCS_TTHOLD_FULL = 0x00000300,
780
781 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
782 TXMCS_IFG1_16_8 |
783 TXMCS_TTHOLD_FULL |
784 TXMCS_DEFER |
785 TXMCS_CRC |
786 TXMCS_PADDING,
787};
788
789enum jme_txpfc_bits_masks {
790 TXPFC_VLAN_TAG = 0xFFFF0000,
791 TXPFC_VLAN_EN = 0x00008000,
792 TXPFC_PF_EN = 0x00000001,
793};
794
795enum jme_txtrhd_bits_masks {
796 TXTRHD_TXPEN = 0x80000000,
797 TXTRHD_TXP = 0x7FFFFF00,
798 TXTRHD_TXREN = 0x00000080,
799 TXTRHD_TXRL = 0x0000007F,
800};
801
802enum jme_txtrhd_shifts {
803 TXTRHD_TXP_SHIFT = 8,
804 TXTRHD_TXRL_SHIFT = 0,
805};
806
807enum jme_txtrhd_values {
808 TXTRHD_FULLDUPLEX = 0x00000000,
809 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
810 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
811 TXTRHD_TXREN |
812 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
813};
814
815/*
816 * RX Control/Status Bits
817 */
818enum jme_rxcs_bit_masks {
819 /* FIFO full threshold for transmitting Tx Pause Packet */
820 RXCS_FIFOTHTP = 0x30000000,
821 /* FIFO threshold for processing next packet */
822 RXCS_FIFOTHNP = 0x0C000000,
823 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
824 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
825 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
826 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
827 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
828 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
829 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
830 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
831 RXCS_QST = 0x00000004, /* Receive queue start */
832 RXCS_SUSPEND = 0x00000002,
833 RXCS_ENABLE = 0x00000001,
834};
835
836enum jme_rxcs_values {
837 RXCS_FIFOTHTP_16T = 0x00000000,
838 RXCS_FIFOTHTP_32T = 0x10000000,
839 RXCS_FIFOTHTP_64T = 0x20000000,
840 RXCS_FIFOTHTP_128T = 0x30000000,
841
842 RXCS_FIFOTHNP_16QW = 0x00000000,
843 RXCS_FIFOTHNP_32QW = 0x04000000,
844 RXCS_FIFOTHNP_64QW = 0x08000000,
845 RXCS_FIFOTHNP_128QW = 0x0C000000,
846
847 RXCS_DMAREQSZ_16B = 0x00000000,
848 RXCS_DMAREQSZ_32B = 0x01000000,
849 RXCS_DMAREQSZ_64B = 0x02000000,
850 RXCS_DMAREQSZ_128B = 0x03000000,
851
852 RXCS_QUEUESEL_Q0 = 0x00000000,
853 RXCS_QUEUESEL_Q1 = 0x00010000,
854 RXCS_QUEUESEL_Q2 = 0x00020000,
855 RXCS_QUEUESEL_Q3 = 0x00030000,
856
857 RXCS_RETRYGAP_256ns = 0x00000000,
858 RXCS_RETRYGAP_512ns = 0x00001000,
859 RXCS_RETRYGAP_1024ns = 0x00002000,
860 RXCS_RETRYGAP_2048ns = 0x00003000,
861 RXCS_RETRYGAP_4096ns = 0x00004000,
862 RXCS_RETRYGAP_8192ns = 0x00005000,
863 RXCS_RETRYGAP_16384ns = 0x00006000,
864 RXCS_RETRYGAP_32768ns = 0x00007000,
865
866 RXCS_RETRYCNT_0 = 0x00000000,
867 RXCS_RETRYCNT_4 = 0x00000100,
868 RXCS_RETRYCNT_8 = 0x00000200,
869 RXCS_RETRYCNT_12 = 0x00000300,
870 RXCS_RETRYCNT_16 = 0x00000400,
871 RXCS_RETRYCNT_20 = 0x00000500,
872 RXCS_RETRYCNT_24 = 0x00000600,
873 RXCS_RETRYCNT_28 = 0x00000700,
874 RXCS_RETRYCNT_32 = 0x00000800,
875 RXCS_RETRYCNT_36 = 0x00000900,
876 RXCS_RETRYCNT_40 = 0x00000A00,
877 RXCS_RETRYCNT_44 = 0x00000B00,
878 RXCS_RETRYCNT_48 = 0x00000C00,
879 RXCS_RETRYCNT_52 = 0x00000D00,
880 RXCS_RETRYCNT_56 = 0x00000E00,
881 RXCS_RETRYCNT_60 = 0x00000F00,
882
883 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
884 RXCS_FIFOTHNP_128QW |
885 RXCS_DMAREQSZ_128B |
886 RXCS_RETRYGAP_256ns |
887 RXCS_RETRYCNT_32,
888};
889
890#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
891
892/*
893 * RX MAC Control/Status Bits
894 */
895enum jme_rxmcs_bits {
896 RXMCS_ALLFRAME = 0x00000800,
897 RXMCS_BRDFRAME = 0x00000400,
898 RXMCS_MULFRAME = 0x00000200,
899 RXMCS_UNIFRAME = 0x00000100,
900 RXMCS_ALLMULFRAME = 0x00000080,
901 RXMCS_MULFILTERED = 0x00000040,
902 RXMCS_RXCOLLDEC = 0x00000020,
903 RXMCS_FLOWCTRL = 0x00000008,
904 RXMCS_VTAGRM = 0x00000004,
905 RXMCS_PREPAD = 0x00000002,
906 RXMCS_CHECKSUM = 0x00000001,
907
908 RXMCS_DEFAULT = RXMCS_VTAGRM |
909 RXMCS_PREPAD |
910 RXMCS_FLOWCTRL |
911 RXMCS_CHECKSUM,
912};
913
914/*
915 * Wakeup Frame setup interface registers
916 */
917#define WAKEUP_FRAME_NR 8
918#define WAKEUP_FRAME_MASK_DWNR 4
919
920enum jme_wfoi_bit_masks {
921 WFOI_MASK_SEL = 0x00000070,
922 WFOI_CRC_SEL = 0x00000008,
923 WFOI_FRAME_SEL = 0x00000007,
924};
925
926enum jme_wfoi_shifts {
927 WFOI_MASK_SHIFT = 4,
928};
929
930/*
931 * SMI Related definitions
932 */
933enum jme_smi_bit_mask {
934 SMI_DATA_MASK = 0xFFFF0000,
935 SMI_REG_ADDR_MASK = 0x0000F800,
936 SMI_PHY_ADDR_MASK = 0x000007C0,
937 SMI_OP_WRITE = 0x00000020,
938 /* Set to 1, after req done it'll be cleared to 0 */
939 SMI_OP_REQ = 0x00000010,
940 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
941 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
942 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
943 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
944};
945
946enum jme_smi_bit_shift {
947 SMI_DATA_SHIFT = 16,
948 SMI_REG_ADDR_SHIFT = 11,
949 SMI_PHY_ADDR_SHIFT = 6,
950};
951
952static inline u32 smi_reg_addr(int x)
953{
954 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
955}
956
957static inline u32 smi_phy_addr(int x)
958{
959 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
960}
961
962#define JME_PHY_TIMEOUT 100 /* 100 msec */
963#define JME_PHY_REG_NR 32
964
965/*
966 * Global Host Control
967 */
968enum jme_ghc_bit_mask {
969 GHC_SWRST = 0x40000000,
970 GHC_TO_CLK_SRC = 0x00C00000,
971 GHC_TXMAC_CLK_SRC = 0x00300000,
972 GHC_DPX = 0x00000040,
973 GHC_SPEED = 0x00000030,
974 GHC_LINK_POLL = 0x00000001,
975};
976
977enum jme_ghc_speed_val {
978 GHC_SPEED_10M = 0x00000010,
979 GHC_SPEED_100M = 0x00000020,
980 GHC_SPEED_1000M = 0x00000030,
981};
982
983enum jme_ghc_to_clk {
984 GHC_TO_CLK_OFF = 0x00000000,
985 GHC_TO_CLK_GPHY = 0x00400000,
986 GHC_TO_CLK_PCIE = 0x00800000,
987 GHC_TO_CLK_INVALID = 0x00C00000,
988};
989
990enum jme_ghc_txmac_clk {
991 GHC_TXMAC_CLK_OFF = 0x00000000,
992 GHC_TXMAC_CLK_GPHY = 0x00100000,
993 GHC_TXMAC_CLK_PCIE = 0x00200000,
994 GHC_TXMAC_CLK_INVALID = 0x00300000,
995};
996
997/*
998 * Power management control and status register
999 */
1000enum jme_pmcs_bit_masks {
1001 PMCS_STMASK = 0xFFFF0000,
1002 PMCS_WF7DET = 0x80000000,
1003 PMCS_WF6DET = 0x40000000,
1004 PMCS_WF5DET = 0x20000000,
1005 PMCS_WF4DET = 0x10000000,
1006 PMCS_WF3DET = 0x08000000,
1007 PMCS_WF2DET = 0x04000000,
1008 PMCS_WF1DET = 0x02000000,
1009 PMCS_WF0DET = 0x01000000,
1010 PMCS_LFDET = 0x00040000,
1011 PMCS_LRDET = 0x00020000,
1012 PMCS_MFDET = 0x00010000,
1013 PMCS_ENMASK = 0x0000FFFF,
1014 PMCS_WF7EN = 0x00008000,
1015 PMCS_WF6EN = 0x00004000,
1016 PMCS_WF5EN = 0x00002000,
1017 PMCS_WF4EN = 0x00001000,
1018 PMCS_WF3EN = 0x00000800,
1019 PMCS_WF2EN = 0x00000400,
1020 PMCS_WF1EN = 0x00000200,
1021 PMCS_WF0EN = 0x00000100,
1022 PMCS_LFEN = 0x00000004,
1023 PMCS_LREN = 0x00000002,
1024 PMCS_MFEN = 0x00000001,
1025};
1026
1027/*
1028 * New PHY Power Control Register
1029 */
1030enum jme_phy_pwr_bit_masks {
1031 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1032 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1033 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1034 PHY_PWR_CLKSEL = 0x08000000, /*
1035 * XTL_OUT Clock select
1036 * (an internal free-running clock)
1037 * 0: xtl_out = phy_giga.A_XTL25_O
1038 * 1: xtl_out = phy_giga.PD_OSC
1039 */
1040};
1041
1042/*
1043 * Giga PHY Status Registers
1044 */
1045enum jme_phy_link_bit_mask {
1046 PHY_LINK_SPEED_MASK = 0x0000C000,
1047 PHY_LINK_DUPLEX = 0x00002000,
1048 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
1049 PHY_LINK_UP = 0x00000400,
1050 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
1051 PHY_LINK_MDI_STAT = 0x00000040,
1052};
1053
1054enum jme_phy_link_speed_val {
1055 PHY_LINK_SPEED_10M = 0x00000000,
1056 PHY_LINK_SPEED_100M = 0x00004000,
1057 PHY_LINK_SPEED_1000M = 0x00008000,
1058};
1059
1060#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
1061
1062/*
1063 * SMB Control and Status
1064 */
1065enum jme_smbcsr_bit_mask {
1066 SMBCSR_CNACK = 0x00020000,
1067 SMBCSR_RELOAD = 0x00010000,
1068 SMBCSR_EEPROMD = 0x00000020,
1069 SMBCSR_INITDONE = 0x00000010,
1070 SMBCSR_BUSY = 0x0000000F,
1071};
1072
1073enum jme_smbintf_bit_mask {
1074 SMBINTF_HWDATR = 0xFF000000,
1075 SMBINTF_HWDATW = 0x00FF0000,
1076 SMBINTF_HWADDR = 0x0000FF00,
1077 SMBINTF_HWRWN = 0x00000020,
1078 SMBINTF_HWCMD = 0x00000010,
1079 SMBINTF_FASTM = 0x00000008,
1080 SMBINTF_GPIOSCL = 0x00000004,
1081 SMBINTF_GPIOSDA = 0x00000002,
1082 SMBINTF_GPIOEN = 0x00000001,
1083};
1084
1085enum jme_smbintf_vals {
1086 SMBINTF_HWRWN_READ = 0x00000020,
1087 SMBINTF_HWRWN_WRITE = 0x00000000,
1088};
1089
1090enum jme_smbintf_shifts {
1091 SMBINTF_HWDATR_SHIFT = 24,
1092 SMBINTF_HWDATW_SHIFT = 16,
1093 SMBINTF_HWADDR_SHIFT = 8,
1094};
1095
1096#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1097#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1098#define JME_SMB_LEN 256
1099#define JME_EEPROM_MAGIC 0x250
1100
1101/*
1102 * Timer Control/Status Register
1103 */
1104enum jme_tmcsr_bit_masks {
1105 TMCSR_SWIT = 0x80000000,
1106 TMCSR_EN = 0x01000000,
1107 TMCSR_CNT = 0x00FFFFFF,
1108};
1109
1110/*
1111 * General Purpose REG-0
1112 */
1113enum jme_gpreg0_masks {
1114 GPREG0_DISSH = 0xFF000000,
1115 GPREG0_PCIRLMT = 0x00300000,
1116 GPREG0_PCCNOMUTCLR = 0x00040000,
1117 GPREG0_LNKINTPOLL = 0x00001000,
1118 GPREG0_PCCTMR = 0x00000300,
1119 GPREG0_PHYADDR = 0x0000001F,
1120};
1121
1122enum jme_gpreg0_vals {
1123 GPREG0_DISSH_DW7 = 0x80000000,
1124 GPREG0_DISSH_DW6 = 0x40000000,
1125 GPREG0_DISSH_DW5 = 0x20000000,
1126 GPREG0_DISSH_DW4 = 0x10000000,
1127 GPREG0_DISSH_DW3 = 0x08000000,
1128 GPREG0_DISSH_DW2 = 0x04000000,
1129 GPREG0_DISSH_DW1 = 0x02000000,
1130 GPREG0_DISSH_DW0 = 0x01000000,
1131 GPREG0_DISSH_ALL = 0xFF000000,
1132
1133 GPREG0_PCIRLMT_8 = 0x00000000,
1134 GPREG0_PCIRLMT_6 = 0x00100000,
1135 GPREG0_PCIRLMT_5 = 0x00200000,
1136 GPREG0_PCIRLMT_4 = 0x00300000,
1137
1138 GPREG0_PCCTMR_16ns = 0x00000000,
1139 GPREG0_PCCTMR_256ns = 0x00000100,
1140 GPREG0_PCCTMR_1us = 0x00000200,
1141 GPREG0_PCCTMR_1ms = 0x00000300,
1142
1143 GPREG0_PHYADDR_1 = 0x00000001,
1144
1145 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1146 GPREG0_PCCTMR_1us |
1147 GPREG0_PHYADDR_1,
1148};
1149
1150/*
1151 * General Purpose REG-1
1152 */
1153enum jme_gpreg1_bit_masks {
1154 GPREG1_RXCLKOFF = 0x04000000,
1155 GPREG1_PCREQN = 0x00020000,
1156 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1157 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1158 GPREG1_INTRDELAYUNIT = 0x00000018,
1159 GPREG1_INTRDELAYENABLE = 0x00000007,
1160};
1161
1162enum jme_gpreg1_vals {
1163 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1164 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1165 GPREG1_INTDLYUNIT_1US = 0x00000010,
1166 GPREG1_INTDLYUNIT_16US = 0x00000018,
1167
1168 GPREG1_INTDLYEN_1U = 0x00000001,
1169 GPREG1_INTDLYEN_2U = 0x00000002,
1170 GPREG1_INTDLYEN_3U = 0x00000003,
1171 GPREG1_INTDLYEN_4U = 0x00000004,
1172 GPREG1_INTDLYEN_5U = 0x00000005,
1173 GPREG1_INTDLYEN_6U = 0x00000006,
1174 GPREG1_INTDLYEN_7U = 0x00000007,
1175
1176 GPREG1_DEFAULT = GPREG1_PCREQN,
1177};
1178
1179/*
1180 * Interrupt Status Bits
1181 */
1182enum jme_interrupt_bits {
1183 INTR_SWINTR = 0x80000000,
1184 INTR_TMINTR = 0x40000000,
1185 INTR_LINKCH = 0x20000000,
1186 INTR_PAUSERCV = 0x10000000,
1187 INTR_MAGICRCV = 0x08000000,
1188 INTR_WAKERCV = 0x04000000,
1189 INTR_PCCRX0TO = 0x02000000,
1190 INTR_PCCRX1TO = 0x01000000,
1191 INTR_PCCRX2TO = 0x00800000,
1192 INTR_PCCRX3TO = 0x00400000,
1193 INTR_PCCTXTO = 0x00200000,
1194 INTR_PCCRX0 = 0x00100000,
1195 INTR_PCCRX1 = 0x00080000,
1196 INTR_PCCRX2 = 0x00040000,
1197 INTR_PCCRX3 = 0x00020000,
1198 INTR_PCCTX = 0x00010000,
1199 INTR_RX3EMP = 0x00008000,
1200 INTR_RX2EMP = 0x00004000,
1201 INTR_RX1EMP = 0x00002000,
1202 INTR_RX0EMP = 0x00001000,
1203 INTR_RX3 = 0x00000800,
1204 INTR_RX2 = 0x00000400,
1205 INTR_RX1 = 0x00000200,
1206 INTR_RX0 = 0x00000100,
1207 INTR_TX7 = 0x00000080,
1208 INTR_TX6 = 0x00000040,
1209 INTR_TX5 = 0x00000020,
1210 INTR_TX4 = 0x00000010,
1211 INTR_TX3 = 0x00000008,
1212 INTR_TX2 = 0x00000004,
1213 INTR_TX1 = 0x00000002,
1214 INTR_TX0 = 0x00000001,
1215};
1216
1217static const u32 INTR_ENABLE = INTR_SWINTR |
1218 INTR_TMINTR |
1219 INTR_LINKCH |
1220 INTR_PCCRX0TO |
1221 INTR_PCCRX0 |
1222 INTR_PCCTXTO |
1223 INTR_PCCTX |
1224 INTR_RX0EMP;
1225
1226/*
1227 * PCC Control Registers
1228 */
1229enum jme_pccrx_masks {
1230 PCCRXTO_MASK = 0xFFFF0000,
1231 PCCRX_MASK = 0x0000FF00,
1232};
1233
1234enum jme_pcctx_masks {
1235 PCCTXTO_MASK = 0xFFFF0000,
1236 PCCTX_MASK = 0x0000FF00,
1237 PCCTX_QS_MASK = 0x000000FF,
1238};
1239
1240enum jme_pccrx_shifts {
1241 PCCRXTO_SHIFT = 16,
1242 PCCRX_SHIFT = 8,
1243};
1244
1245enum jme_pcctx_shifts {
1246 PCCTXTO_SHIFT = 16,
1247 PCCTX_SHIFT = 8,
1248};
1249
1250enum jme_pcctx_bits {
1251 PCCTXQ0_EN = 0x00000001,
1252 PCCTXQ1_EN = 0x00000002,
1253 PCCTXQ2_EN = 0x00000004,
1254 PCCTXQ3_EN = 0x00000008,
1255 PCCTXQ4_EN = 0x00000010,
1256 PCCTXQ5_EN = 0x00000020,
1257 PCCTXQ6_EN = 0x00000040,
1258 PCCTXQ7_EN = 0x00000080,
1259};
1260
1261/*
1262 * Chip Mode Register
1263 */
1264enum jme_chipmode_bit_masks {
1265 CM_FPGAVER_MASK = 0xFFFF0000,
1266 CM_CHIPREV_MASK = 0x0000FF00,
1267 CM_CHIPMODE_MASK = 0x0000000F,
1268};
1269
1270enum jme_chipmode_shifts {
1271 CM_FPGAVER_SHIFT = 16,
1272 CM_CHIPREV_SHIFT = 8,
1273};
1274
1275/*
1276 * Aggressive Power Mode Control
1277 */
1278enum jme_apmc_bits {
1279 JME_APMC_PCIE_SD_EN = 0x40000000,
1280 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1281 JME_APMC_EPIEN = 0x04000000,
1282 JME_APMC_EPIEN_CTRL = 0x03000000,
1283};
1284
1285enum jme_apmc_values {
1286 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1287 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1288};
1289
1290#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1291
1292#ifdef REG_DEBUG
1293static char *MAC_REG_NAME[] = {
1294 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1295 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1296 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1297 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1298 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1299 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1300 "JME_PMCS"};
1301
1302static char *PE_REG_NAME[] = {
1303 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1304 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1305 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1306 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1307 "JME_SMBCSR", "JME_SMBINTF"};
1308
1309static char *MISC_REG_NAME[] = {
1310 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1311 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1312 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1313 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1314 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1315 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1316 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1317 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1318 "JME_PCCSRX0"};
1319
1320static inline void reg_dbg(const struct jme_adapter *jme,
1321 const char *msg, u32 val, u32 reg)
1322{
1323 const char *regname;
1324 switch (reg & 0xF00) {
1325 case 0x000:
1326 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1327 break;
1328 case 0x400:
1329 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1330 break;
1331 case 0x800:
1332 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1333 break;
1334 default:
1335 regname = PE_REG_NAME[0];
1336 }
1337 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1338 msg, val, regname);
1339}
1340#else
1341static inline void reg_dbg(const struct jme_adapter *jme,
1342 const char *msg, u32 val, u32 reg) {}
1343#endif
1344
1345/*
1346 * Read/Write MMaped I/O Registers
1347 */
1348static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1349{
1350 return readl(jme->regs + reg);
1351}
1352
1353static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1354{
1355 reg_dbg(jme, "REG WRITE", val, reg);
1356 writel(val, jme->regs + reg);
1357 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1358}
1359
1360static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1361{
1362 /*
1363 * Read after write should cause flush
1364 */
1365 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1366 writel(val, jme->regs + reg);
1367 readl(jme->regs + reg);
1368 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1369}
1370
1371/*
1372 * PHY Regs
1373 */
1374enum jme_phy_reg17_bit_masks {
1375 PREG17_SPEED = 0xC000,
1376 PREG17_DUPLEX = 0x2000,
1377 PREG17_SPDRSV = 0x0800,
1378 PREG17_LNKUP = 0x0400,
1379 PREG17_MDI = 0x0040,
1380};
1381
1382enum jme_phy_reg17_vals {
1383 PREG17_SPEED_10M = 0x0000,
1384 PREG17_SPEED_100M = 0x4000,
1385 PREG17_SPEED_1000M = 0x8000,
1386};
1387
1388#define BMSR_ANCOMP 0x0020
1389
1390/*
1391 * Workaround
1392 */
1393static inline int is_buggy250(unsigned short device, u8 chiprev)
1394{
1395 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1396}
1397
1398static inline int new_phy_power_ctrl(u8 chip_main_rev)
1399{
1400 return chip_main_rev >= 5;
1401}
1402
1403/*
1404 * Function prototypes
1405 */
1406static int jme_set_settings(struct net_device *netdev,
1407 struct ethtool_cmd *ecmd);
1408static void jme_set_unicastaddr(struct net_device *netdev);
1409static void jme_set_multi(struct net_device *netdev);
1410
1411#endif
1412
JMicron Ethernet Linux driver