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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/version.h>
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
38#include <linux/delay.h>
39#include <linux/spinlock.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/if_vlan.h>
46#include <linux/slab.h>
47#include <net/ip6_checksum.h>
48#include "jme.h"
49
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
61
62static int
63jme_mdio_read(struct net_device *netdev, int phy, int reg)
64{
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
67
68read_again:
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
70 smi_phy_addr(phy) |
71 smi_reg_addr(reg));
72
73 wmb();
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
75 udelay(20);
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
78 break;
79 }
80
81 if (i == 0) {
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
83 return 0;
84 }
85
86 if (again--)
87 goto read_again;
88
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
90}
91
92static void
93jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
95{
96 struct jme_adapter *jme = netdev_priv(netdev);
97 int i;
98
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
102
103 wmb();
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 udelay(20);
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
107 break;
108 }
109
110 if (i == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
112}
113
114static inline void
115jme_reset_phy_processor(struct jme_adapter *jme)
116{
117 u32 val;
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
123
124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
125 jme_mdio_write(jme->dev,
126 jme->mii_if.phy_id,
127 MII_CTRL1000,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
129
130 val = jme_mdio_read(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR);
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_BMCR, val | BMCR_RESET);
137}
138
139static void
140jme_setup_wakeup_frame(struct jme_adapter *jme,
141 const u32 *mask, u32 crc, int fnr)
142{
143 int i;
144
145 /*
146 * Setup CRC pattern
147 */
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 wmb();
150 jwrite32(jme, JME_WFODP, crc);
151 wmb();
152
153 /*
154 * Setup Mask
155 */
156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
160 wmb();
161 jwrite32(jme, JME_WFODP, mask[i]);
162 wmb();
163 }
164}
165
166static inline void
167jme_reset_mac_processor(struct jme_adapter *jme)
168{
169 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
170 u32 crc = 0xCDCDCDCD;
171 u32 gpreg0;
172 int i;
173
174 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
175 udelay(2);
176 jwrite32(jme, JME_GHC, jme->reg_ghc);
177
178 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_RXQDC, 0x00000000);
181 jwrite32(jme, JME_RXNDA, 0x00000000);
182 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
183 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
184 jwrite32(jme, JME_TXQDC, 0x00000000);
185 jwrite32(jme, JME_TXNDA, 0x00000000);
186
187 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
188 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
189 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
190 jme_setup_wakeup_frame(jme, mask, crc, i);
191 if (jme->fpgaver)
192 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
193 else
194 gpreg0 = GPREG0_DEFAULT;
195 jwrite32(jme, JME_GPREG0, gpreg0);
196 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
197}
198
199static inline void
200jme_reset_ghc_speed(struct jme_adapter *jme)
201{
202 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
203 jwrite32(jme, JME_GHC, jme->reg_ghc);
204}
205
206static inline void
207jme_clear_pm(struct jme_adapter *jme)
208{
209 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
210 pci_set_power_state(jme->pdev, PCI_D0);
211 pci_enable_wake(jme->pdev, PCI_D0, false);
212}
213
214static int
215jme_reload_eeprom(struct jme_adapter *jme)
216{
217 u32 val;
218 int i;
219
220 val = jread32(jme, JME_SMBCSR);
221
222 if (val & SMBCSR_EEPROMD) {
223 val |= SMBCSR_CNACK;
224 jwrite32(jme, JME_SMBCSR, val);
225 val |= SMBCSR_RELOAD;
226 jwrite32(jme, JME_SMBCSR, val);
227 mdelay(12);
228
229 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
230 mdelay(1);
231 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
232 break;
233 }
234
235 if (i == 0) {
236 pr_err("eeprom reload timeout\n");
237 return -EIO;
238 }
239 }
240
241 return 0;
242}
243
244static void
245jme_load_macaddr(struct net_device *netdev)
246{
247 struct jme_adapter *jme = netdev_priv(netdev);
248 unsigned char macaddr[6];
249 u32 val;
250
251 spin_lock_bh(&jme->macaddr_lock);
252 val = jread32(jme, JME_RXUMA_LO);
253 macaddr[0] = (val >> 0) & 0xFF;
254 macaddr[1] = (val >> 8) & 0xFF;
255 macaddr[2] = (val >> 16) & 0xFF;
256 macaddr[3] = (val >> 24) & 0xFF;
257 val = jread32(jme, JME_RXUMA_HI);
258 macaddr[4] = (val >> 0) & 0xFF;
259 macaddr[5] = (val >> 8) & 0xFF;
260 memcpy(netdev->dev_addr, macaddr, 6);
261 spin_unlock_bh(&jme->macaddr_lock);
262}
263
264static inline void
265jme_set_rx_pcc(struct jme_adapter *jme, int p)
266{
267 switch (p) {
268 case PCC_OFF:
269 jwrite32(jme, JME_PCCRX0,
270 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
271 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
272 break;
273 case PCC_P1:
274 jwrite32(jme, JME_PCCRX0,
275 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
276 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
277 break;
278 case PCC_P2:
279 jwrite32(jme, JME_PCCRX0,
280 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
281 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
282 break;
283 case PCC_P3:
284 jwrite32(jme, JME_PCCRX0,
285 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
286 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
287 break;
288 default:
289 break;
290 }
291 wmb();
292
293 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
294 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
295}
296
297static void
298jme_start_irq(struct jme_adapter *jme)
299{
300 register struct dynpcc_info *dpi = &(jme->dpi);
301
302 jme_set_rx_pcc(jme, PCC_P1);
303 dpi->cur = PCC_P1;
304 dpi->attempt = PCC_P1;
305 dpi->cnt = 0;
306
307 jwrite32(jme, JME_PCCTX,
308 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
309 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
310 PCCTXQ0_EN
311 );
312
313 /*
314 * Enable Interrupts
315 */
316 jwrite32(jme, JME_IENS, INTR_ENABLE);
317}
318
319static inline void
320jme_stop_irq(struct jme_adapter *jme)
321{
322 /*
323 * Disable Interrupts
324 */
325 jwrite32f(jme, JME_IENC, INTR_ENABLE);
326}
327
328static u32
329jme_linkstat_from_phy(struct jme_adapter *jme)
330{
331 u32 phylink, bmsr;
332
333 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
334 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
335 if (bmsr & BMSR_ANCOMP)
336 phylink |= PHY_LINK_AUTONEG_COMPLETE;
337
338 return phylink;
339}
340
341static inline void
342jme_set_phyfifoa(struct jme_adapter *jme)
343{
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
345}
346
347static inline void
348jme_set_phyfifob(struct jme_adapter *jme)
349{
350 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
351}
352
353static int
354jme_check_link(struct net_device *netdev, int testonly)
355{
356 struct jme_adapter *jme = netdev_priv(netdev);
357 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
358 char linkmsg[64];
359 int rc = 0;
360
361 linkmsg[0] = '\0';
362
363 if (jme->fpgaver)
364 phylink = jme_linkstat_from_phy(jme);
365 else
366 phylink = jread32(jme, JME_PHY_LINK);
367
368 if (phylink & PHY_LINK_UP) {
369 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
370 /*
371 * If we did not enable AN
372 * Speed/Duplex Info should be obtained from SMI
373 */
374 phylink = PHY_LINK_UP;
375
376 bmcr = jme_mdio_read(jme->dev,
377 jme->mii_if.phy_id,
378 MII_BMCR);
379
380 phylink |= ((bmcr & BMCR_SPEED1000) &&
381 (bmcr & BMCR_SPEED100) == 0) ?
382 PHY_LINK_SPEED_1000M :
383 (bmcr & BMCR_SPEED100) ?
384 PHY_LINK_SPEED_100M :
385 PHY_LINK_SPEED_10M;
386
387 phylink |= (bmcr & BMCR_FULLDPLX) ?
388 PHY_LINK_DUPLEX : 0;
389
390 strcat(linkmsg, "Forced: ");
391 } else {
392 /*
393 * Keep polling for speed/duplex resolve complete
394 */
395 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
396 --cnt) {
397
398 udelay(1);
399
400 if (jme->fpgaver)
401 phylink = jme_linkstat_from_phy(jme);
402 else
403 phylink = jread32(jme, JME_PHY_LINK);
404 }
405 if (!cnt)
406 pr_err("Waiting speed resolve timeout\n");
407
408 strcat(linkmsg, "ANed: ");
409 }
410
411 if (jme->phylink == phylink) {
412 rc = 1;
413 goto out;
414 }
415 if (testonly)
416 goto out;
417
418 jme->phylink = phylink;
419
420 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
422 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
423 switch (phylink & PHY_LINK_SPEED_MASK) {
424 case PHY_LINK_SPEED_10M:
425 ghc |= GHC_SPEED_10M |
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
427 strcat(linkmsg, "10 Mbps, ");
428 break;
429 case PHY_LINK_SPEED_100M:
430 ghc |= GHC_SPEED_100M |
431 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
432 strcat(linkmsg, "100 Mbps, ");
433 break;
434 case PHY_LINK_SPEED_1000M:
435 ghc |= GHC_SPEED_1000M |
436 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
437 strcat(linkmsg, "1000 Mbps, ");
438 break;
439 default:
440 break;
441 }
442
443 if (phylink & PHY_LINK_DUPLEX) {
444 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
445 ghc |= GHC_DPX;
446 } else {
447 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
448 TXMCS_BACKOFF |
449 TXMCS_CARRIERSENSE |
450 TXMCS_COLLISION);
451 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
452 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
453 TXTRHD_TXREN |
454 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
455 }
456
457 gpreg1 = GPREG1_DEFAULT;
458 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
459 if (!(phylink & PHY_LINK_DUPLEX))
460 gpreg1 |= GPREG1_HALFMODEPATCH;
461 switch (phylink & PHY_LINK_SPEED_MASK) {
462 case PHY_LINK_SPEED_10M:
463 jme_set_phyfifoa(jme);
464 gpreg1 |= GPREG1_RSSPATCH;
465 break;
466 case PHY_LINK_SPEED_100M:
467 jme_set_phyfifob(jme);
468 gpreg1 |= GPREG1_RSSPATCH;
469 break;
470 case PHY_LINK_SPEED_1000M:
471 jme_set_phyfifoa(jme);
472 break;
473 default:
474 break;
475 }
476 }
477
478 jwrite32(jme, JME_GPREG1, gpreg1);
479 jwrite32(jme, JME_GHC, ghc);
480 jme->reg_ghc = ghc;
481
482 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
483 "Full-Duplex, " :
484 "Half-Duplex, ");
485 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
486 "MDI-X" :
487 "MDI");
488 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
489 netif_carrier_on(netdev);
490 } else {
491 if (testonly)
492 goto out;
493
494 netif_info(jme, link, jme->dev, "Link is down\n");
495 jme->phylink = 0;
496 netif_carrier_off(netdev);
497 }
498
499out:
500 return rc;
501}
502
503static int
504jme_setup_tx_resources(struct jme_adapter *jme)
505{
506 struct jme_ring *txring = &(jme->txring[0]);
507
508 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
509 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
510 &(txring->dmaalloc),
511 GFP_ATOMIC);
512
513 if (!txring->alloc)
514 goto err_set_null;
515
516 /*
517 * 16 Bytes align
518 */
519 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
520 RING_DESC_ALIGN);
521 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
522 txring->next_to_use = 0;
523 atomic_set(&txring->next_to_clean, 0);
524 atomic_set(&txring->nr_free, jme->tx_ring_size);
525
526 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
527 jme->tx_ring_size, GFP_ATOMIC);
528 if (unlikely(!(txring->bufinf)))
529 goto err_free_txring;
530
531 /*
532 * Initialize Transmit Descriptors
533 */
534 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
535 memset(txring->bufinf, 0,
536 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
537
538 return 0;
539
540err_free_txring:
541 dma_free_coherent(&(jme->pdev->dev),
542 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
543 txring->alloc,
544 txring->dmaalloc);
545
546err_set_null:
547 txring->desc = NULL;
548 txring->dmaalloc = 0;
549 txring->dma = 0;
550 txring->bufinf = NULL;
551
552 return -ENOMEM;
553}
554
555static void
556jme_free_tx_resources(struct jme_adapter *jme)
557{
558 int i;
559 struct jme_ring *txring = &(jme->txring[0]);
560 struct jme_buffer_info *txbi;
561
562 if (txring->alloc) {
563 if (txring->bufinf) {
564 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
565 txbi = txring->bufinf + i;
566 if (txbi->skb) {
567 dev_kfree_skb(txbi->skb);
568 txbi->skb = NULL;
569 }
570 txbi->mapping = 0;
571 txbi->len = 0;
572 txbi->nr_desc = 0;
573 txbi->start_xmit = 0;
574 }
575 kfree(txring->bufinf);
576 }
577
578 dma_free_coherent(&(jme->pdev->dev),
579 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
580 txring->alloc,
581 txring->dmaalloc);
582
583 txring->alloc = NULL;
584 txring->desc = NULL;
585 txring->dmaalloc = 0;
586 txring->dma = 0;
587 txring->bufinf = NULL;
588 }
589 txring->next_to_use = 0;
590 atomic_set(&txring->next_to_clean, 0);
591 atomic_set(&txring->nr_free, 0);
592}
593
594static inline void
595jme_enable_tx_engine(struct jme_adapter *jme)
596{
597 /*
598 * Select Queue 0
599 */
600 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
601 wmb();
602
603 /*
604 * Setup TX Queue 0 DMA Bass Address
605 */
606 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
607 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
608 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
609
610 /*
611 * Setup TX Descptor Count
612 */
613 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
614
615 /*
616 * Enable TX Engine
617 */
618 wmb();
619 jwrite32(jme, JME_TXCS, jme->reg_txcs |
620 TXCS_SELECT_QUEUE0 |
621 TXCS_ENABLE);
622
623}
624
625static inline void
626jme_restart_tx_engine(struct jme_adapter *jme)
627{
628 /*
629 * Restart TX Engine
630 */
631 jwrite32(jme, JME_TXCS, jme->reg_txcs |
632 TXCS_SELECT_QUEUE0 |
633 TXCS_ENABLE);
634}
635
636static inline void
637jme_disable_tx_engine(struct jme_adapter *jme)
638{
639 int i;
640 u32 val;
641
642 /*
643 * Disable TX Engine
644 */
645 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
646 wmb();
647
648 val = jread32(jme, JME_TXCS);
649 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
650 mdelay(1);
651 val = jread32(jme, JME_TXCS);
652 rmb();
653 }
654
655 if (!i)
656 pr_err("Disable TX engine timeout\n");
657}
658
659static void
660jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
661{
662 struct jme_ring *rxring = &(jme->rxring[0]);
663 register struct rxdesc *rxdesc = rxring->desc;
664 struct jme_buffer_info *rxbi = rxring->bufinf;
665 rxdesc += i;
666 rxbi += i;
667
668 rxdesc->dw[0] = 0;
669 rxdesc->dw[1] = 0;
670 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
671 rxdesc->desc1.bufaddrl = cpu_to_le32(
672 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
673 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
674 if (jme->dev->features & NETIF_F_HIGHDMA)
675 rxdesc->desc1.flags = RXFLAG_64BIT;
676 wmb();
677 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
678}
679
680static int
681jme_make_new_rx_buf(struct jme_adapter *jme, int i)
682{
683 struct jme_ring *rxring = &(jme->rxring[0]);
684 struct jme_buffer_info *rxbi = rxring->bufinf + i;
685 struct sk_buff *skb;
686
687 skb = netdev_alloc_skb(jme->dev,
688 jme->dev->mtu + RX_EXTRA_LEN);
689 if (unlikely(!skb))
690 return -ENOMEM;
691#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
692 skb->dev = jme->dev;
693#endif
694
695 rxbi->skb = skb;
696 rxbi->len = skb_tailroom(skb);
697 rxbi->mapping = pci_map_page(jme->pdev,
698 virt_to_page(skb->data),
699 offset_in_page(skb->data),
700 rxbi->len,
701 PCI_DMA_FROMDEVICE);
702
703 return 0;
704}
705
706static void
707jme_free_rx_buf(struct jme_adapter *jme, int i)
708{
709 struct jme_ring *rxring = &(jme->rxring[0]);
710 struct jme_buffer_info *rxbi = rxring->bufinf;
711 rxbi += i;
712
713 if (rxbi->skb) {
714 pci_unmap_page(jme->pdev,
715 rxbi->mapping,
716 rxbi->len,
717 PCI_DMA_FROMDEVICE);
718 dev_kfree_skb(rxbi->skb);
719 rxbi->skb = NULL;
720 rxbi->mapping = 0;
721 rxbi->len = 0;
722 }
723}
724
725static void
726jme_free_rx_resources(struct jme_adapter *jme)
727{
728 int i;
729 struct jme_ring *rxring = &(jme->rxring[0]);
730
731 if (rxring->alloc) {
732 if (rxring->bufinf) {
733 for (i = 0 ; i < jme->rx_ring_size ; ++i)
734 jme_free_rx_buf(jme, i);
735 kfree(rxring->bufinf);
736 }
737
738 dma_free_coherent(&(jme->pdev->dev),
739 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
740 rxring->alloc,
741 rxring->dmaalloc);
742 rxring->alloc = NULL;
743 rxring->desc = NULL;
744 rxring->dmaalloc = 0;
745 rxring->dma = 0;
746 rxring->bufinf = NULL;
747 }
748 rxring->next_to_use = 0;
749 atomic_set(&rxring->next_to_clean, 0);
750}
751
752static int
753jme_setup_rx_resources(struct jme_adapter *jme)
754{
755 int i;
756 struct jme_ring *rxring = &(jme->rxring[0]);
757
758 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
759 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
760 &(rxring->dmaalloc),
761 GFP_ATOMIC);
762 if (!rxring->alloc)
763 goto err_set_null;
764
765 /*
766 * 16 Bytes align
767 */
768 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
769 RING_DESC_ALIGN);
770 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
771 rxring->next_to_use = 0;
772 atomic_set(&rxring->next_to_clean, 0);
773
774 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
775 jme->rx_ring_size, GFP_ATOMIC);
776 if (unlikely(!(rxring->bufinf)))
777 goto err_free_rxring;
778
779 /*
780 * Initiallize Receive Descriptors
781 */
782 memset(rxring->bufinf, 0,
783 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
784 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
785 if (unlikely(jme_make_new_rx_buf(jme, i))) {
786 jme_free_rx_resources(jme);
787 return -ENOMEM;
788 }
789
790 jme_set_clean_rxdesc(jme, i);
791 }
792
793 return 0;
794
795err_free_rxring:
796 dma_free_coherent(&(jme->pdev->dev),
797 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
798 rxring->alloc,
799 rxring->dmaalloc);
800err_set_null:
801 rxring->desc = NULL;
802 rxring->dmaalloc = 0;
803 rxring->dma = 0;
804 rxring->bufinf = NULL;
805
806 return -ENOMEM;
807}
808
809static inline void
810jme_enable_rx_engine(struct jme_adapter *jme)
811{
812 /*
813 * Select Queue 0
814 */
815 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
816 RXCS_QUEUESEL_Q0);
817 wmb();
818
819 /*
820 * Setup RX DMA Bass Address
821 */
822 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
823 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
824 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
825
826 /*
827 * Setup RX Descriptor Count
828 */
829 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
830
831 /*
832 * Setup Unicast Filter
833 */
834 jme_set_multi(jme->dev);
835
836 /*
837 * Enable RX Engine
838 */
839 wmb();
840 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
841 RXCS_QUEUESEL_Q0 |
842 RXCS_ENABLE |
843 RXCS_QST);
844}
845
846static inline void
847jme_restart_rx_engine(struct jme_adapter *jme)
848{
849 /*
850 * Start RX Engine
851 */
852 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
853 RXCS_QUEUESEL_Q0 |
854 RXCS_ENABLE |
855 RXCS_QST);
856}
857
858static inline void
859jme_disable_rx_engine(struct jme_adapter *jme)
860{
861 int i;
862 u32 val;
863
864 /*
865 * Disable RX Engine
866 */
867 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
868 wmb();
869
870 val = jread32(jme, JME_RXCS);
871 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
872 mdelay(1);
873 val = jread32(jme, JME_RXCS);
874 rmb();
875 }
876
877 if (!i)
878 pr_err("Disable RX engine timeout\n");
879
880}
881
882static int
883jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
884{
885 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
886 return false;
887
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
889 == RXWBFLAG_TCPON)) {
890 if (flags & RXWBFLAG_IPV4)
891 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
892 return false;
893 }
894
895 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
896 == RXWBFLAG_UDPON)) {
897 if (flags & RXWBFLAG_IPV4)
898 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
899 return false;
900 }
901
902 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
903 == RXWBFLAG_IPV4)) {
904 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
905 return false;
906 }
907
908 return true;
909}
910
911static void
912jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
913{
914 struct jme_ring *rxring = &(jme->rxring[0]);
915 struct rxdesc *rxdesc = rxring->desc;
916 struct jme_buffer_info *rxbi = rxring->bufinf;
917 struct sk_buff *skb;
918 int framesize;
919
920 rxdesc += idx;
921 rxbi += idx;
922
923 skb = rxbi->skb;
924 pci_dma_sync_single_for_cpu(jme->pdev,
925 rxbi->mapping,
926 rxbi->len,
927 PCI_DMA_FROMDEVICE);
928
929 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
930 pci_dma_sync_single_for_device(jme->pdev,
931 rxbi->mapping,
932 rxbi->len,
933 PCI_DMA_FROMDEVICE);
934
935 ++(NET_STAT(jme).rx_dropped);
936 } else {
937 framesize = le16_to_cpu(rxdesc->descwb.framesize)
938 - RX_PREPAD_SIZE;
939
940 skb_reserve(skb, RX_PREPAD_SIZE);
941 skb_put(skb, framesize);
942 skb->protocol = eth_type_trans(skb, jme->dev);
943
944 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
945 skb->ip_summed = CHECKSUM_UNNECESSARY;
946 else
947#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
948 skb->ip_summed = CHECKSUM_NONE;
949#else
950 skb_checksum_none_assert(skb);
951#endif
952
953 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
954 if (jme->vlgrp) {
955 jme->jme_vlan_rx(skb, jme->vlgrp,
956 le16_to_cpu(rxdesc->descwb.vlan));
957 NET_STAT(jme).rx_bytes += 4;
958 } else {
959 dev_kfree_skb(skb);
960 }
961 } else {
962 jme->jme_rx(skb);
963 }
964
965 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
966 cpu_to_le16(RXWBFLAG_DEST_MUL))
967 ++(NET_STAT(jme).multicast);
968
969 NET_STAT(jme).rx_bytes += framesize;
970 ++(NET_STAT(jme).rx_packets);
971 }
972
973 jme_set_clean_rxdesc(jme, idx);
974
975}
976
977static int
978jme_process_receive(struct jme_adapter *jme, int limit)
979{
980 struct jme_ring *rxring = &(jme->rxring[0]);
981 struct rxdesc *rxdesc = rxring->desc;
982 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
983
984 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
985 goto out_inc;
986
987 if (unlikely(atomic_read(&jme->link_changing) != 1))
988 goto out_inc;
989
990 if (unlikely(!netif_carrier_ok(jme->dev)))
991 goto out_inc;
992
993 i = atomic_read(&rxring->next_to_clean);
994 while (limit > 0) {
995 rxdesc = rxring->desc;
996 rxdesc += i;
997
998 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
999 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1000 goto out;
1001 --limit;
1002
1003 rmb();
1004 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1005
1006 if (unlikely(desccnt > 1 ||
1007 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1008
1009 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1010 ++(NET_STAT(jme).rx_crc_errors);
1011 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1012 ++(NET_STAT(jme).rx_fifo_errors);
1013 else
1014 ++(NET_STAT(jme).rx_errors);
1015
1016 if (desccnt > 1)
1017 limit -= desccnt - 1;
1018
1019 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1020 jme_set_clean_rxdesc(jme, j);
1021 j = (j + 1) & (mask);
1022 }
1023
1024 } else {
1025 jme_alloc_and_feed_skb(jme, i);
1026 }
1027
1028 i = (i + desccnt) & (mask);
1029 }
1030
1031out:
1032 atomic_set(&rxring->next_to_clean, i);
1033
1034out_inc:
1035 atomic_inc(&jme->rx_cleaning);
1036
1037 return limit > 0 ? limit : 0;
1038
1039}
1040
1041static void
1042jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1043{
1044 if (likely(atmp == dpi->cur)) {
1045 dpi->cnt = 0;
1046 return;
1047 }
1048
1049 if (dpi->attempt == atmp) {
1050 ++(dpi->cnt);
1051 } else {
1052 dpi->attempt = atmp;
1053 dpi->cnt = 0;
1054 }
1055
1056}
1057
1058static void
1059jme_dynamic_pcc(struct jme_adapter *jme)
1060{
1061 register struct dynpcc_info *dpi = &(jme->dpi);
1062
1063 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1064 jme_attempt_pcc(dpi, PCC_P3);
1065 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1066 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1067 jme_attempt_pcc(dpi, PCC_P2);
1068 else
1069 jme_attempt_pcc(dpi, PCC_P1);
1070
1071 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1072 if (dpi->attempt < dpi->cur)
1073 tasklet_schedule(&jme->rxclean_task);
1074 jme_set_rx_pcc(jme, dpi->attempt);
1075 dpi->cur = dpi->attempt;
1076 dpi->cnt = 0;
1077 }
1078}
1079
1080static void
1081jme_start_pcc_timer(struct jme_adapter *jme)
1082{
1083 struct dynpcc_info *dpi = &(jme->dpi);
1084 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1085 dpi->last_pkts = NET_STAT(jme).rx_packets;
1086 dpi->intr_cnt = 0;
1087 jwrite32(jme, JME_TMCSR,
1088 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1089}
1090
1091static inline void
1092jme_stop_pcc_timer(struct jme_adapter *jme)
1093{
1094 jwrite32(jme, JME_TMCSR, 0);
1095}
1096
1097static void
1098jme_shutdown_nic(struct jme_adapter *jme)
1099{
1100 u32 phylink;
1101
1102 phylink = jme_linkstat_from_phy(jme);
1103
1104 if (!(phylink & PHY_LINK_UP)) {
1105 /*
1106 * Disable all interrupt before issue timer
1107 */
1108 jme_stop_irq(jme);
1109 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1110 }
1111}
1112
1113static void
1114jme_pcc_tasklet(unsigned long arg)
1115{
1116 struct jme_adapter *jme = (struct jme_adapter *)arg;
1117 struct net_device *netdev = jme->dev;
1118
1119 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1120 jme_shutdown_nic(jme);
1121 return;
1122 }
1123
1124 if (unlikely(!netif_carrier_ok(netdev) ||
1125 (atomic_read(&jme->link_changing) != 1)
1126 )) {
1127 jme_stop_pcc_timer(jme);
1128 return;
1129 }
1130
1131 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1132 jme_dynamic_pcc(jme);
1133
1134 jme_start_pcc_timer(jme);
1135}
1136
1137static inline void
1138jme_polling_mode(struct jme_adapter *jme)
1139{
1140 jme_set_rx_pcc(jme, PCC_OFF);
1141}
1142
1143static inline void
1144jme_interrupt_mode(struct jme_adapter *jme)
1145{
1146 jme_set_rx_pcc(jme, PCC_P1);
1147}
1148
1149static inline int
1150jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1151{
1152 u32 apmc;
1153 apmc = jread32(jme, JME_APMC);
1154 return apmc & JME_APMC_PSEUDO_HP_EN;
1155}
1156
1157static void
1158jme_start_shutdown_timer(struct jme_adapter *jme)
1159{
1160 u32 apmc;
1161
1162 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1163 apmc &= ~JME_APMC_EPIEN_CTRL;
1164 if (!no_extplug) {
1165 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1166 wmb();
1167 }
1168 jwrite32f(jme, JME_APMC, apmc);
1169
1170 jwrite32f(jme, JME_TIMER2, 0);
1171 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1172 jwrite32(jme, JME_TMCSR,
1173 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1174}
1175
1176static void
1177jme_stop_shutdown_timer(struct jme_adapter *jme)
1178{
1179 u32 apmc;
1180
1181 jwrite32f(jme, JME_TMCSR, 0);
1182 jwrite32f(jme, JME_TIMER2, 0);
1183 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1184
1185 apmc = jread32(jme, JME_APMC);
1186 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1187 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1188 wmb();
1189 jwrite32f(jme, JME_APMC, apmc);
1190}
1191
1192static void
1193jme_link_change_tasklet(unsigned long arg)
1194{
1195 struct jme_adapter *jme = (struct jme_adapter *)arg;
1196 struct net_device *netdev = jme->dev;
1197 int rc;
1198
1199 while (!atomic_dec_and_test(&jme->link_changing)) {
1200 atomic_inc(&jme->link_changing);
1201 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1202 while (atomic_read(&jme->link_changing) != 1)
1203 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1204 }
1205
1206 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1207 goto out;
1208
1209 jme->old_mtu = netdev->mtu;
1210 netif_stop_queue(netdev);
1211 if (jme_pseudo_hotplug_enabled(jme))
1212 jme_stop_shutdown_timer(jme);
1213
1214 jme_stop_pcc_timer(jme);
1215 tasklet_disable(&jme->txclean_task);
1216 tasklet_disable(&jme->rxclean_task);
1217 tasklet_disable(&jme->rxempty_task);
1218
1219 if (netif_carrier_ok(netdev)) {
1220 jme_reset_ghc_speed(jme);
1221 jme_disable_rx_engine(jme);
1222 jme_disable_tx_engine(jme);
1223 jme_reset_mac_processor(jme);
1224 jme_free_rx_resources(jme);
1225 jme_free_tx_resources(jme);
1226
1227 if (test_bit(JME_FLAG_POLL, &jme->flags))
1228 jme_polling_mode(jme);
1229
1230 netif_carrier_off(netdev);
1231 }
1232
1233 jme_check_link(netdev, 0);
1234 if (netif_carrier_ok(netdev)) {
1235 rc = jme_setup_rx_resources(jme);
1236 if (rc) {
1237 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1238 goto out_enable_tasklet;
1239 }
1240
1241 rc = jme_setup_tx_resources(jme);
1242 if (rc) {
1243 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1244 goto err_out_free_rx_resources;
1245 }
1246
1247 jme_enable_rx_engine(jme);
1248 jme_enable_tx_engine(jme);
1249
1250 netif_start_queue(netdev);
1251
1252 if (test_bit(JME_FLAG_POLL, &jme->flags))
1253 jme_interrupt_mode(jme);
1254
1255 jme_start_pcc_timer(jme);
1256 } else if (jme_pseudo_hotplug_enabled(jme)) {
1257 jme_start_shutdown_timer(jme);
1258 }
1259
1260 goto out_enable_tasklet;
1261
1262err_out_free_rx_resources:
1263 jme_free_rx_resources(jme);
1264out_enable_tasklet:
1265 tasklet_enable(&jme->txclean_task);
1266 tasklet_hi_enable(&jme->rxclean_task);
1267 tasklet_hi_enable(&jme->rxempty_task);
1268out:
1269 atomic_inc(&jme->link_changing);
1270}
1271
1272static void
1273jme_rx_clean_tasklet(unsigned long arg)
1274{
1275 struct jme_adapter *jme = (struct jme_adapter *)arg;
1276 struct dynpcc_info *dpi = &(jme->dpi);
1277
1278 jme_process_receive(jme, jme->rx_ring_size);
1279 ++(dpi->intr_cnt);
1280
1281}
1282
1283static int
1284jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1285{
1286 struct jme_adapter *jme = jme_napi_priv(holder);
1287 DECLARE_NETDEV
1288 int rest;
1289
1290 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1291
1292 while (atomic_read(&jme->rx_empty) > 0) {
1293 atomic_dec(&jme->rx_empty);
1294 ++(NET_STAT(jme).rx_dropped);
1295 jme_restart_rx_engine(jme);
1296 }
1297 atomic_inc(&jme->rx_empty);
1298
1299 if (rest) {
1300 JME_RX_COMPLETE(netdev, holder);
1301 jme_interrupt_mode(jme);
1302 }
1303
1304 JME_NAPI_WEIGHT_SET(budget, rest);
1305 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1306}
1307
1308static void
1309jme_rx_empty_tasklet(unsigned long arg)
1310{
1311 struct jme_adapter *jme = (struct jme_adapter *)arg;
1312
1313 if (unlikely(atomic_read(&jme->link_changing) != 1))
1314 return;
1315
1316 if (unlikely(!netif_carrier_ok(jme->dev)))
1317 return;
1318
1319 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1320
1321 jme_rx_clean_tasklet(arg);
1322
1323 while (atomic_read(&jme->rx_empty) > 0) {
1324 atomic_dec(&jme->rx_empty);
1325 ++(NET_STAT(jme).rx_dropped);
1326 jme_restart_rx_engine(jme);
1327 }
1328 atomic_inc(&jme->rx_empty);
1329}
1330
1331static void
1332jme_wake_queue_if_stopped(struct jme_adapter *jme)
1333{
1334 struct jme_ring *txring = &(jme->txring[0]);
1335
1336 smp_wmb();
1337 if (unlikely(netif_queue_stopped(jme->dev) &&
1338 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1339 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1340 netif_wake_queue(jme->dev);
1341 }
1342
1343}
1344
1345static void
1346jme_tx_clean_tasklet(unsigned long arg)
1347{
1348 struct jme_adapter *jme = (struct jme_adapter *)arg;
1349 struct jme_ring *txring = &(jme->txring[0]);
1350 struct txdesc *txdesc = txring->desc;
1351 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1352 int i, j, cnt = 0, max, err, mask;
1353
1354 tx_dbg(jme, "Into txclean\n");
1355
1356 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1357 goto out;
1358
1359 if (unlikely(atomic_read(&jme->link_changing) != 1))
1360 goto out;
1361
1362 if (unlikely(!netif_carrier_ok(jme->dev)))
1363 goto out;
1364
1365 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1366 mask = jme->tx_ring_mask;
1367
1368 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1369
1370 ctxbi = txbi + i;
1371
1372 if (likely(ctxbi->skb &&
1373 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1374
1375 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1376 i, ctxbi->nr_desc, jiffies);
1377
1378 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1379
1380 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1381 ttxbi = txbi + ((i + j) & (mask));
1382 txdesc[(i + j) & (mask)].dw[0] = 0;
1383
1384 pci_unmap_page(jme->pdev,
1385 ttxbi->mapping,
1386 ttxbi->len,
1387 PCI_DMA_TODEVICE);
1388
1389 ttxbi->mapping = 0;
1390 ttxbi->len = 0;
1391 }
1392
1393 dev_kfree_skb(ctxbi->skb);
1394
1395 cnt += ctxbi->nr_desc;
1396
1397 if (unlikely(err)) {
1398 ++(NET_STAT(jme).tx_carrier_errors);
1399 } else {
1400 ++(NET_STAT(jme).tx_packets);
1401 NET_STAT(jme).tx_bytes += ctxbi->len;
1402 }
1403
1404 ctxbi->skb = NULL;
1405 ctxbi->len = 0;
1406 ctxbi->start_xmit = 0;
1407
1408 } else {
1409 break;
1410 }
1411
1412 i = (i + ctxbi->nr_desc) & mask;
1413
1414 ctxbi->nr_desc = 0;
1415 }
1416
1417 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1418 atomic_set(&txring->next_to_clean, i);
1419 atomic_add(cnt, &txring->nr_free);
1420
1421 jme_wake_queue_if_stopped(jme);
1422
1423out:
1424 atomic_inc(&jme->tx_cleaning);
1425}
1426
1427static void
1428jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1429{
1430 /*
1431 * Disable interrupt
1432 */
1433 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1434
1435 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1436 /*
1437 * Link change event is critical
1438 * all other events are ignored
1439 */
1440 jwrite32(jme, JME_IEVE, intrstat);
1441 tasklet_schedule(&jme->linkch_task);
1442 goto out_reenable;
1443 }
1444
1445 if (intrstat & INTR_TMINTR) {
1446 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1447 tasklet_schedule(&jme->pcc_task);
1448 }
1449
1450 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1451 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1452 tasklet_schedule(&jme->txclean_task);
1453 }
1454
1455 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1456 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1457 INTR_PCCRX0 |
1458 INTR_RX0EMP)) |
1459 INTR_RX0);
1460 }
1461
1462 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1463 if (intrstat & INTR_RX0EMP)
1464 atomic_inc(&jme->rx_empty);
1465
1466 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1467 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1468 jme_polling_mode(jme);
1469 JME_RX_SCHEDULE(jme);
1470 }
1471 }
1472 } else {
1473 if (intrstat & INTR_RX0EMP) {
1474 atomic_inc(&jme->rx_empty);
1475 tasklet_hi_schedule(&jme->rxempty_task);
1476 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1477 tasklet_hi_schedule(&jme->rxclean_task);
1478 }
1479 }
1480
1481out_reenable:
1482 /*
1483 * Re-enable interrupt
1484 */
1485 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1486}
1487
1488#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1489static irqreturn_t
1490jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1491#else
1492static irqreturn_t
1493jme_intr(int irq, void *dev_id)
1494#endif
1495{
1496 struct net_device *netdev = dev_id;
1497 struct jme_adapter *jme = netdev_priv(netdev);
1498 u32 intrstat;
1499
1500 intrstat = jread32(jme, JME_IEVE);
1501
1502 /*
1503 * Check if it's really an interrupt for us
1504 */
1505 if (unlikely((intrstat & INTR_ENABLE) == 0))
1506 return IRQ_NONE;
1507
1508 /*
1509 * Check if the device still exist
1510 */
1511 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1512 return IRQ_NONE;
1513
1514 jme_intr_msi(jme, intrstat);
1515
1516 return IRQ_HANDLED;
1517}
1518
1519#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1520static irqreturn_t
1521jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1522#else
1523static irqreturn_t
1524jme_msi(int irq, void *dev_id)
1525#endif
1526{
1527 struct net_device *netdev = dev_id;
1528 struct jme_adapter *jme = netdev_priv(netdev);
1529 u32 intrstat;
1530
1531 intrstat = jread32(jme, JME_IEVE);
1532
1533 jme_intr_msi(jme, intrstat);
1534
1535 return IRQ_HANDLED;
1536}
1537
1538static void
1539jme_reset_link(struct jme_adapter *jme)
1540{
1541 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1542}
1543
1544static void
1545jme_restart_an(struct jme_adapter *jme)
1546{
1547 u32 bmcr;
1548
1549 spin_lock_bh(&jme->phy_lock);
1550 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1551 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1552 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1553 spin_unlock_bh(&jme->phy_lock);
1554}
1555
1556static int
1557jme_request_irq(struct jme_adapter *jme)
1558{
1559 int rc;
1560 struct net_device *netdev = jme->dev;
1561#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1562 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1563 int irq_flags = SA_SHIRQ;
1564#else
1565 irq_handler_t handler = jme_intr;
1566 int irq_flags = IRQF_SHARED;
1567#endif
1568
1569 if (!pci_enable_msi(jme->pdev)) {
1570 set_bit(JME_FLAG_MSI, &jme->flags);
1571 handler = jme_msi;
1572 irq_flags = 0;
1573 }
1574
1575 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1576 netdev);
1577 if (rc) {
1578 netdev_err(netdev,
1579 "Unable to request %s interrupt (return: %d)\n",
1580 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1581 rc);
1582
1583 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1584 pci_disable_msi(jme->pdev);
1585 clear_bit(JME_FLAG_MSI, &jme->flags);
1586 }
1587 } else {
1588 netdev->irq = jme->pdev->irq;
1589 }
1590
1591 return rc;
1592}
1593
1594static void
1595jme_free_irq(struct jme_adapter *jme)
1596{
1597 free_irq(jme->pdev->irq, jme->dev);
1598 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1599 pci_disable_msi(jme->pdev);
1600 clear_bit(JME_FLAG_MSI, &jme->flags);
1601 jme->dev->irq = jme->pdev->irq;
1602 }
1603}
1604
1605static inline void
1606jme_phy_on(struct jme_adapter *jme)
1607{
1608 u32 bmcr;
1609
1610 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1611 bmcr &= ~BMCR_PDOWN;
1612 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1613}
1614
1615static int
1616jme_open(struct net_device *netdev)
1617{
1618 struct jme_adapter *jme = netdev_priv(netdev);
1619 int rc;
1620
1621 jme_clear_pm(jme);
1622 JME_NAPI_ENABLE(jme);
1623
1624 tasklet_enable(&jme->linkch_task);
1625 tasklet_enable(&jme->txclean_task);
1626 tasklet_hi_enable(&jme->rxclean_task);
1627 tasklet_hi_enable(&jme->rxempty_task);
1628
1629 rc = jme_request_irq(jme);
1630 if (rc)
1631 goto err_out;
1632
1633 jme_start_irq(jme);
1634
1635 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1636 jme_phy_on(jme);
1637 jme_set_settings(netdev, &jme->old_ecmd);
1638 } else {
1639 jme_reset_phy_processor(jme);
1640 }
1641
1642 jme_reset_link(jme);
1643
1644 return 0;
1645
1646err_out:
1647 netif_stop_queue(netdev);
1648 netif_carrier_off(netdev);
1649 return rc;
1650}
1651
1652static void
1653jme_set_100m_half(struct jme_adapter *jme)
1654{
1655 u32 bmcr, tmp;
1656
1657 jme_phy_on(jme);
1658 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1659 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1660 BMCR_SPEED1000 | BMCR_FULLDPLX);
1661 tmp |= BMCR_SPEED100;
1662
1663 if (bmcr != tmp)
1664 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1665
1666 if (jme->fpgaver)
1667 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1668 else
1669 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1670}
1671
1672#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1673static void
1674jme_wait_link(struct jme_adapter *jme)
1675{
1676 u32 phylink, to = JME_WAIT_LINK_TIME;
1677
1678 mdelay(1000);
1679 phylink = jme_linkstat_from_phy(jme);
1680 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1681 mdelay(10);
1682 phylink = jme_linkstat_from_phy(jme);
1683 }
1684}
1685
1686static inline void
1687jme_phy_off(struct jme_adapter *jme)
1688{
1689 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1690}
1691
1692static void
1693jme_powersave_phy(struct jme_adapter *jme)
1694{
1695 if (jme->reg_pmcs) {
1696 jme_set_100m_half(jme);
1697
1698 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1699 jme_wait_link(jme);
1700
1701 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1702 } else {
1703 jme_phy_off(jme);
1704 }
1705}
1706
1707static int
1708jme_close(struct net_device *netdev)
1709{
1710 struct jme_adapter *jme = netdev_priv(netdev);
1711
1712 netif_stop_queue(netdev);
1713 netif_carrier_off(netdev);
1714
1715 jme_stop_irq(jme);
1716 jme_free_irq(jme);
1717
1718 JME_NAPI_DISABLE(jme);
1719
1720 tasklet_disable(&jme->linkch_task);
1721 tasklet_disable(&jme->txclean_task);
1722 tasklet_disable(&jme->rxclean_task);
1723 tasklet_disable(&jme->rxempty_task);
1724
1725 jme_reset_ghc_speed(jme);
1726 jme_disable_rx_engine(jme);
1727 jme_disable_tx_engine(jme);
1728 jme_reset_mac_processor(jme);
1729 jme_free_rx_resources(jme);
1730 jme_free_tx_resources(jme);
1731 jme->phylink = 0;
1732 jme_phy_off(jme);
1733
1734 return 0;
1735}
1736
1737static int
1738jme_alloc_txdesc(struct jme_adapter *jme,
1739 struct sk_buff *skb)
1740{
1741 struct jme_ring *txring = &(jme->txring[0]);
1742 int idx, nr_alloc, mask = jme->tx_ring_mask;
1743
1744 idx = txring->next_to_use;
1745 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1746
1747 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1748 return -1;
1749
1750 atomic_sub(nr_alloc, &txring->nr_free);
1751
1752 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1753
1754 return idx;
1755}
1756
1757static void
1758jme_fill_tx_map(struct pci_dev *pdev,
1759 struct txdesc *txdesc,
1760 struct jme_buffer_info *txbi,
1761 struct page *page,
1762 u32 page_offset,
1763 u32 len,
1764 u8 hidma)
1765{
1766 dma_addr_t dmaaddr;
1767
1768 dmaaddr = pci_map_page(pdev,
1769 page,
1770 page_offset,
1771 len,
1772 PCI_DMA_TODEVICE);
1773
1774 pci_dma_sync_single_for_device(pdev,
1775 dmaaddr,
1776 len,
1777 PCI_DMA_TODEVICE);
1778
1779 txdesc->dw[0] = 0;
1780 txdesc->dw[1] = 0;
1781 txdesc->desc2.flags = TXFLAG_OWN;
1782 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1783 txdesc->desc2.datalen = cpu_to_le16(len);
1784 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1785 txdesc->desc2.bufaddrl = cpu_to_le32(
1786 (__u64)dmaaddr & 0xFFFFFFFFUL);
1787
1788 txbi->mapping = dmaaddr;
1789 txbi->len = len;
1790}
1791
1792static void
1793jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1794{
1795 struct jme_ring *txring = &(jme->txring[0]);
1796 struct txdesc *txdesc = txring->desc, *ctxdesc;
1797 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1798 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1799 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1800 int mask = jme->tx_ring_mask;
1801 struct skb_frag_struct *frag;
1802 u32 len;
1803
1804 for (i = 0 ; i < nr_frags ; ++i) {
1805 frag = &skb_shinfo(skb)->frags[i];
1806 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1807 ctxbi = txbi + ((idx + i + 2) & (mask));
1808
1809 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1810 frag->page_offset, frag->size, hidma);
1811 }
1812
1813 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1814 ctxdesc = txdesc + ((idx + 1) & (mask));
1815 ctxbi = txbi + ((idx + 1) & (mask));
1816 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1817 offset_in_page(skb->data), len, hidma);
1818
1819}
1820
1821static int
1822jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1823{
1824 if (unlikely(
1825#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1826 skb_shinfo(skb)->tso_size
1827#else
1828 skb_shinfo(skb)->gso_size
1829#endif
1830 && skb_header_cloned(skb) &&
1831 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1832 dev_kfree_skb(skb);
1833 return -1;
1834 }
1835
1836 return 0;
1837}
1838
1839static int
1840jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1841{
1842#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1843 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1844#else
1845 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1846#endif
1847 if (*mss) {
1848 *flags |= TXFLAG_LSEN;
1849
1850 if (skb->protocol == htons(ETH_P_IP)) {
1851 struct iphdr *iph = ip_hdr(skb);
1852
1853 iph->check = 0;
1854 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1855 iph->daddr, 0,
1856 IPPROTO_TCP,
1857 0);
1858 } else {
1859 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1860
1861 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1862 &ip6h->daddr, 0,
1863 IPPROTO_TCP,
1864 0);
1865 }
1866
1867 return 0;
1868 }
1869
1870 return 1;
1871}
1872
1873static void
1874jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1875{
1876#ifdef CHECKSUM_PARTIAL
1877 if (skb->ip_summed == CHECKSUM_PARTIAL)
1878#else
1879 if (skb->ip_summed == CHECKSUM_HW)
1880#endif
1881 {
1882 u8 ip_proto;
1883
1884#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1885 if (skb->protocol == htons(ETH_P_IP))
1886 ip_proto = ip_hdr(skb)->protocol;
1887 else if (skb->protocol == htons(ETH_P_IPV6))
1888 ip_proto = ipv6_hdr(skb)->nexthdr;
1889 else
1890 ip_proto = 0;
1891#else
1892 switch (skb->protocol) {
1893 case htons(ETH_P_IP):
1894 ip_proto = ip_hdr(skb)->protocol;
1895 break;
1896 case htons(ETH_P_IPV6):
1897 ip_proto = ipv6_hdr(skb)->nexthdr;
1898 break;
1899 default:
1900 ip_proto = 0;
1901 break;
1902 }
1903#endif
1904
1905 switch (ip_proto) {
1906 case IPPROTO_TCP:
1907 *flags |= TXFLAG_TCPCS;
1908 break;
1909 case IPPROTO_UDP:
1910 *flags |= TXFLAG_UDPCS;
1911 break;
1912 default:
1913 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1914 break;
1915 }
1916 }
1917}
1918
1919static inline void
1920jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1921{
1922 if (vlan_tx_tag_present(skb)) {
1923 *flags |= TXFLAG_TAGON;
1924 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1925 }
1926}
1927
1928static int
1929jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1930{
1931 struct jme_ring *txring = &(jme->txring[0]);
1932 struct txdesc *txdesc;
1933 struct jme_buffer_info *txbi;
1934 u8 flags;
1935
1936 txdesc = (struct txdesc *)txring->desc + idx;
1937 txbi = txring->bufinf + idx;
1938
1939 txdesc->dw[0] = 0;
1940 txdesc->dw[1] = 0;
1941 txdesc->dw[2] = 0;
1942 txdesc->dw[3] = 0;
1943 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1944 /*
1945 * Set OWN bit at final.
1946 * When kernel transmit faster than NIC.
1947 * And NIC trying to send this descriptor before we tell
1948 * it to start sending this TX queue.
1949 * Other fields are already filled correctly.
1950 */
1951 wmb();
1952 flags = TXFLAG_OWN | TXFLAG_INT;
1953 /*
1954 * Set checksum flags while not tso
1955 */
1956 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1957 jme_tx_csum(jme, skb, &flags);
1958 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1959 jme_map_tx_skb(jme, skb, idx);
1960 txdesc->desc1.flags = flags;
1961 /*
1962 * Set tx buffer info after telling NIC to send
1963 * For better tx_clean timing
1964 */
1965 wmb();
1966 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1967 txbi->skb = skb;
1968 txbi->len = skb->len;
1969 txbi->start_xmit = jiffies;
1970 if (!txbi->start_xmit)
1971 txbi->start_xmit = (0UL-1);
1972
1973 return 0;
1974}
1975
1976static void
1977jme_stop_queue_if_full(struct jme_adapter *jme)
1978{
1979 struct jme_ring *txring = &(jme->txring[0]);
1980 struct jme_buffer_info *txbi = txring->bufinf;
1981 int idx = atomic_read(&txring->next_to_clean);
1982
1983 txbi += idx;
1984
1985 smp_wmb();
1986 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1987 netif_stop_queue(jme->dev);
1988 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1989 smp_wmb();
1990 if (atomic_read(&txring->nr_free)
1991 >= (jme->tx_wake_threshold)) {
1992 netif_wake_queue(jme->dev);
1993 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1994 }
1995 }
1996
1997 if (unlikely(txbi->start_xmit &&
1998 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1999 txbi->skb)) {
2000 netif_stop_queue(jme->dev);
2001 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2002 }
2003}
2004
2005/*
2006 * This function is already protected by netif_tx_lock()
2007 */
2008
2009#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2010static int
2011#else
2012static netdev_tx_t
2013#endif
2014jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2015{
2016 struct jme_adapter *jme = netdev_priv(netdev);
2017 int idx;
2018
2019 if (unlikely(jme_expand_header(jme, skb))) {
2020 ++(NET_STAT(jme).tx_dropped);
2021 return NETDEV_TX_OK;
2022 }
2023
2024 idx = jme_alloc_txdesc(jme, skb);
2025
2026 if (unlikely(idx < 0)) {
2027 netif_stop_queue(netdev);
2028 netif_err(jme, tx_err, jme->dev,
2029 "BUG! Tx ring full when queue awake!\n");
2030
2031 return NETDEV_TX_BUSY;
2032 }
2033
2034 jme_fill_tx_desc(jme, skb, idx);
2035
2036 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2037 TXCS_SELECT_QUEUE0 |
2038 TXCS_QUEUE0S |
2039 TXCS_ENABLE);
2040#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2041 netdev->trans_start = jiffies;
2042#endif
2043
2044 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2045 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2046 jme_stop_queue_if_full(jme);
2047
2048 return NETDEV_TX_OK;
2049}
2050
2051static int
2052jme_set_macaddr(struct net_device *netdev, void *p)
2053{
2054 struct jme_adapter *jme = netdev_priv(netdev);
2055 struct sockaddr *addr = p;
2056 u32 val;
2057
2058 if (netif_running(netdev))
2059 return -EBUSY;
2060
2061 spin_lock_bh(&jme->macaddr_lock);
2062 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2063
2064 val = (addr->sa_data[3] & 0xff) << 24 |
2065 (addr->sa_data[2] & 0xff) << 16 |
2066 (addr->sa_data[1] & 0xff) << 8 |
2067 (addr->sa_data[0] & 0xff);
2068 jwrite32(jme, JME_RXUMA_LO, val);
2069 val = (addr->sa_data[5] & 0xff) << 8 |
2070 (addr->sa_data[4] & 0xff);
2071 jwrite32(jme, JME_RXUMA_HI, val);
2072 spin_unlock_bh(&jme->macaddr_lock);
2073
2074 return 0;
2075}
2076
2077static void
2078jme_set_multi(struct net_device *netdev)
2079{
2080 struct jme_adapter *jme = netdev_priv(netdev);
2081 u32 mc_hash[2] = {};
2082#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2083 int i;
2084#endif
2085
2086 spin_lock_bh(&jme->rxmcs_lock);
2087
2088 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2089
2090 if (netdev->flags & IFF_PROMISC) {
2091 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2092 } else if (netdev->flags & IFF_ALLMULTI) {
2093 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2094 } else if (netdev->flags & IFF_MULTICAST) {
2095#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2096 struct dev_mc_list *mclist;
2097#else
2098 struct netdev_hw_addr *ha;
2099#endif
2100 int bit_nr;
2101
2102 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2103#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2104 for (i = 0, mclist = netdev->mc_list;
2105 mclist && i < netdev->mc_count;
2106 ++i, mclist = mclist->next) {
2107#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2108 netdev_for_each_mc_addr(mclist, netdev) {
2109#else
2110 netdev_for_each_mc_addr(ha, netdev) {
2111#endif
2112#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2113 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2114#else
2115 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2116#endif
2117 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2118 }
2119
2120 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2121 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2122 }
2123
2124 wmb();
2125 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2126
2127 spin_unlock_bh(&jme->rxmcs_lock);
2128}
2129
2130static int
2131jme_change_mtu(struct net_device *netdev, int new_mtu)
2132{
2133 struct jme_adapter *jme = netdev_priv(netdev);
2134
2135 if (new_mtu == jme->old_mtu)
2136 return 0;
2137
2138 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2139 ((new_mtu) < IPV6_MIN_MTU))
2140 return -EINVAL;
2141
2142 if (new_mtu > 4000) {
2143 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2144 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2145 jme_restart_rx_engine(jme);
2146 } else {
2147 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2148 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2149 jme_restart_rx_engine(jme);
2150 }
2151
2152 if (new_mtu > 1900) {
2153 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2154 NETIF_F_TSO | NETIF_F_TSO6);
2155 } else {
2156 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2157 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2158 if (test_bit(JME_FLAG_TSO, &jme->flags))
2159 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2160 }
2161
2162 netdev->mtu = new_mtu;
2163 jme_reset_link(jme);
2164
2165 return 0;
2166}
2167
2168static void
2169jme_tx_timeout(struct net_device *netdev)
2170{
2171 struct jme_adapter *jme = netdev_priv(netdev);
2172
2173 jme->phylink = 0;
2174 jme_reset_phy_processor(jme);
2175 if (test_bit(JME_FLAG_SSET, &jme->flags))
2176 jme_set_settings(netdev, &jme->old_ecmd);
2177
2178 /*
2179 * Force to Reset the link again
2180 */
2181 jme_reset_link(jme);
2182}
2183
2184static inline void jme_pause_rx(struct jme_adapter *jme)
2185{
2186 atomic_dec(&jme->link_changing);
2187
2188 jme_set_rx_pcc(jme, PCC_OFF);
2189 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2190 JME_NAPI_DISABLE(jme);
2191 } else {
2192 tasklet_disable(&jme->rxclean_task);
2193 tasklet_disable(&jme->rxempty_task);
2194 }
2195}
2196
2197static inline void jme_resume_rx(struct jme_adapter *jme)
2198{
2199 struct dynpcc_info *dpi = &(jme->dpi);
2200
2201 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2202 JME_NAPI_ENABLE(jme);
2203 } else {
2204 tasklet_hi_enable(&jme->rxclean_task);
2205 tasklet_hi_enable(&jme->rxempty_task);
2206 }
2207 dpi->cur = PCC_P1;
2208 dpi->attempt = PCC_P1;
2209 dpi->cnt = 0;
2210 jme_set_rx_pcc(jme, PCC_P1);
2211
2212 atomic_inc(&jme->link_changing);
2213}
2214
2215static void
2216jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2217{
2218 struct jme_adapter *jme = netdev_priv(netdev);
2219
2220 jme_pause_rx(jme);
2221 jme->vlgrp = grp;
2222 jme_resume_rx(jme);
2223}
2224
2225#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2226static void
2227jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2228{
2229 struct jme_adapter *jme = netdev_priv(netdev);
2230
2231 if(jme->vlgrp) {
2232 jme_pause_rx(jme);
2233#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2234 jme->vlgrp->vlan_devices[vid] = NULL;
2235#else
2236 vlan_group_set_device(jme->vlgrp, vid, NULL);
2237#endif
2238 jme_resume_rx(jme);
2239 }
2240}
2241#endif
2242
2243static void
2244jme_get_drvinfo(struct net_device *netdev,
2245 struct ethtool_drvinfo *info)
2246{
2247 struct jme_adapter *jme = netdev_priv(netdev);
2248
2249 strcpy(info->driver, DRV_NAME);
2250 strcpy(info->version, DRV_VERSION);
2251 strcpy(info->bus_info, pci_name(jme->pdev));
2252}
2253
2254static int
2255jme_get_regs_len(struct net_device *netdev)
2256{
2257 return JME_REG_LEN;
2258}
2259
2260static void
2261mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2262{
2263 int i;
2264
2265 for (i = 0 ; i < len ; i += 4)
2266 p[i >> 2] = jread32(jme, reg + i);
2267}
2268
2269static void
2270mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2271{
2272 int i;
2273 u16 *p16 = (u16 *)p;
2274
2275 for (i = 0 ; i < reg_nr ; ++i)
2276 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2277}
2278
2279static void
2280jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2281{
2282 struct jme_adapter *jme = netdev_priv(netdev);
2283 u32 *p32 = (u32 *)p;
2284
2285 memset(p, 0xFF, JME_REG_LEN);
2286
2287 regs->version = 1;
2288 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2289
2290 p32 += 0x100 >> 2;
2291 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2292
2293 p32 += 0x100 >> 2;
2294 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2295
2296 p32 += 0x100 >> 2;
2297 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2298
2299 p32 += 0x100 >> 2;
2300 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2301}
2302
2303static int
2304jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2305{
2306 struct jme_adapter *jme = netdev_priv(netdev);
2307
2308 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2309 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2310
2311 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2312 ecmd->use_adaptive_rx_coalesce = false;
2313 ecmd->rx_coalesce_usecs = 0;
2314 ecmd->rx_max_coalesced_frames = 0;
2315 return 0;
2316 }
2317
2318 ecmd->use_adaptive_rx_coalesce = true;
2319
2320 switch (jme->dpi.cur) {
2321 case PCC_P1:
2322 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2323 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2324 break;
2325 case PCC_P2:
2326 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2327 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2328 break;
2329 case PCC_P3:
2330 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2331 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2332 break;
2333 default:
2334 break;
2335 }
2336
2337 return 0;
2338}
2339
2340static int
2341jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2342{
2343 struct jme_adapter *jme = netdev_priv(netdev);
2344 struct dynpcc_info *dpi = &(jme->dpi);
2345
2346 if (netif_running(netdev))
2347 return -EBUSY;
2348
2349 if (ecmd->use_adaptive_rx_coalesce &&
2350 test_bit(JME_FLAG_POLL, &jme->flags)) {
2351 clear_bit(JME_FLAG_POLL, &jme->flags);
2352 jme->jme_rx = netif_rx;
2353 jme->jme_vlan_rx = vlan_hwaccel_rx;
2354 dpi->cur = PCC_P1;
2355 dpi->attempt = PCC_P1;
2356 dpi->cnt = 0;
2357 jme_set_rx_pcc(jme, PCC_P1);
2358 jme_interrupt_mode(jme);
2359 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2360 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2361 set_bit(JME_FLAG_POLL, &jme->flags);
2362 jme->jme_rx = netif_receive_skb;
2363 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2364 jme_interrupt_mode(jme);
2365 }
2366
2367 return 0;
2368}
2369
2370static void
2371jme_get_pauseparam(struct net_device *netdev,
2372 struct ethtool_pauseparam *ecmd)
2373{
2374 struct jme_adapter *jme = netdev_priv(netdev);
2375 u32 val;
2376
2377 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2378 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2379
2380 spin_lock_bh(&jme->phy_lock);
2381 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2382 spin_unlock_bh(&jme->phy_lock);
2383
2384 ecmd->autoneg =
2385 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2386}
2387
2388static int
2389jme_set_pauseparam(struct net_device *netdev,
2390 struct ethtool_pauseparam *ecmd)
2391{
2392 struct jme_adapter *jme = netdev_priv(netdev);
2393 u32 val;
2394
2395 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2396 (ecmd->tx_pause != 0)) {
2397
2398 if (ecmd->tx_pause)
2399 jme->reg_txpfc |= TXPFC_PF_EN;
2400 else
2401 jme->reg_txpfc &= ~TXPFC_PF_EN;
2402
2403 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2404 }
2405
2406 spin_lock_bh(&jme->rxmcs_lock);
2407 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2408 (ecmd->rx_pause != 0)) {
2409
2410 if (ecmd->rx_pause)
2411 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2412 else
2413 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2414
2415 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2416 }
2417 spin_unlock_bh(&jme->rxmcs_lock);
2418
2419 spin_lock_bh(&jme->phy_lock);
2420 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2421 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2422 (ecmd->autoneg != 0)) {
2423
2424 if (ecmd->autoneg)
2425 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2426 else
2427 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2428
2429 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2430 MII_ADVERTISE, val);
2431 }
2432 spin_unlock_bh(&jme->phy_lock);
2433
2434 return 0;
2435}
2436
2437static void
2438jme_get_wol(struct net_device *netdev,
2439 struct ethtool_wolinfo *wol)
2440{
2441 struct jme_adapter *jme = netdev_priv(netdev);
2442
2443 wol->supported = WAKE_MAGIC | WAKE_PHY;
2444
2445 wol->wolopts = 0;
2446
2447 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2448 wol->wolopts |= WAKE_PHY;
2449
2450 if (jme->reg_pmcs & PMCS_MFEN)
2451 wol->wolopts |= WAKE_MAGIC;
2452
2453}
2454
2455static int
2456jme_set_wol(struct net_device *netdev,
2457 struct ethtool_wolinfo *wol)
2458{
2459 struct jme_adapter *jme = netdev_priv(netdev);
2460
2461 if (wol->wolopts & (WAKE_MAGICSECURE |
2462 WAKE_UCAST |
2463 WAKE_MCAST |
2464 WAKE_BCAST |
2465 WAKE_ARP))
2466 return -EOPNOTSUPP;
2467
2468 jme->reg_pmcs = 0;
2469
2470 if (wol->wolopts & WAKE_PHY)
2471 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2472
2473 if (wol->wolopts & WAKE_MAGIC)
2474 jme->reg_pmcs |= PMCS_MFEN;
2475
2476 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2477
2478 return 0;
2479}
2480
2481static int
2482jme_get_settings(struct net_device *netdev,
2483 struct ethtool_cmd *ecmd)
2484{
2485 struct jme_adapter *jme = netdev_priv(netdev);
2486 int rc;
2487
2488 spin_lock_bh(&jme->phy_lock);
2489 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2490 spin_unlock_bh(&jme->phy_lock);
2491 return rc;
2492}
2493
2494static int
2495jme_set_settings(struct net_device *netdev,
2496 struct ethtool_cmd *ecmd)
2497{
2498 struct jme_adapter *jme = netdev_priv(netdev);
2499 int rc, fdc = 0;
2500
2501 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2502 return -EINVAL;
2503
2504 /*
2505 * Check If user changed duplex only while force_media.
2506 * Hardware would not generate link change interrupt.
2507 */
2508 if (jme->mii_if.force_media &&
2509 ecmd->autoneg != AUTONEG_ENABLE &&
2510 (jme->mii_if.full_duplex != ecmd->duplex))
2511 fdc = 1;
2512
2513 spin_lock_bh(&jme->phy_lock);
2514 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2515 spin_unlock_bh(&jme->phy_lock);
2516
2517 if (!rc) {
2518 if (fdc)
2519 jme_reset_link(jme);
2520 jme->old_ecmd = *ecmd;
2521 set_bit(JME_FLAG_SSET, &jme->flags);
2522 }
2523
2524 return rc;
2525}
2526
2527static int
2528jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2529{
2530 int rc;
2531 struct jme_adapter *jme = netdev_priv(netdev);
2532 struct mii_ioctl_data *mii_data = if_mii(rq);
2533 unsigned int duplex_chg;
2534
2535 if (cmd == SIOCSMIIREG) {
2536 u16 val = mii_data->val_in;
2537 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2538 (val & BMCR_SPEED1000))
2539 return -EINVAL;
2540 }
2541
2542 spin_lock_bh(&jme->phy_lock);
2543 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2544 spin_unlock_bh(&jme->phy_lock);
2545
2546 if (!rc && (cmd == SIOCSMIIREG)) {
2547 if (duplex_chg)
2548 jme_reset_link(jme);
2549 jme_get_settings(netdev, &jme->old_ecmd);
2550 set_bit(JME_FLAG_SSET, &jme->flags);
2551 }
2552
2553 return rc;
2554}
2555
2556static u32
2557jme_get_link(struct net_device *netdev)
2558{
2559 struct jme_adapter *jme = netdev_priv(netdev);
2560 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2561}
2562
2563static u32
2564jme_get_msglevel(struct net_device *netdev)
2565{
2566 struct jme_adapter *jme = netdev_priv(netdev);
2567 return jme->msg_enable;
2568}
2569
2570static void
2571jme_set_msglevel(struct net_device *netdev, u32 value)
2572{
2573 struct jme_adapter *jme = netdev_priv(netdev);
2574 jme->msg_enable = value;
2575}
2576
2577static u32
2578jme_get_rx_csum(struct net_device *netdev)
2579{
2580 struct jme_adapter *jme = netdev_priv(netdev);
2581 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2582}
2583
2584static int
2585jme_set_rx_csum(struct net_device *netdev, u32 on)
2586{
2587 struct jme_adapter *jme = netdev_priv(netdev);
2588
2589 spin_lock_bh(&jme->rxmcs_lock);
2590 if (on)
2591 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2592 else
2593 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2594 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2595 spin_unlock_bh(&jme->rxmcs_lock);
2596
2597 return 0;
2598}
2599
2600static int
2601jme_set_tx_csum(struct net_device *netdev, u32 on)
2602{
2603 struct jme_adapter *jme = netdev_priv(netdev);
2604
2605 if (on) {
2606 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2607 if (netdev->mtu <= 1900)
2608 netdev->features |=
2609 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2610 } else {
2611 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2612 netdev->features &=
2613 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2614 }
2615
2616 return 0;
2617}
2618
2619static int
2620jme_set_tso(struct net_device *netdev, u32 on)
2621{
2622 struct jme_adapter *jme = netdev_priv(netdev);
2623
2624 if (on) {
2625 set_bit(JME_FLAG_TSO, &jme->flags);
2626 if (netdev->mtu <= 1900)
2627 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2628 } else {
2629 clear_bit(JME_FLAG_TSO, &jme->flags);
2630 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2631 }
2632
2633 return 0;
2634}
2635
2636static int
2637jme_nway_reset(struct net_device *netdev)
2638{
2639 struct jme_adapter *jme = netdev_priv(netdev);
2640 jme_restart_an(jme);
2641 return 0;
2642}
2643
2644static u8
2645jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2646{
2647 u32 val;
2648 int to;
2649
2650 val = jread32(jme, JME_SMBCSR);
2651 to = JME_SMB_BUSY_TIMEOUT;
2652 while ((val & SMBCSR_BUSY) && --to) {
2653 msleep(1);
2654 val = jread32(jme, JME_SMBCSR);
2655 }
2656 if (!to) {
2657 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2658 return 0xFF;
2659 }
2660
2661 jwrite32(jme, JME_SMBINTF,
2662 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2663 SMBINTF_HWRWN_READ |
2664 SMBINTF_HWCMD);
2665
2666 val = jread32(jme, JME_SMBINTF);
2667 to = JME_SMB_BUSY_TIMEOUT;
2668 while ((val & SMBINTF_HWCMD) && --to) {
2669 msleep(1);
2670 val = jread32(jme, JME_SMBINTF);
2671 }
2672 if (!to) {
2673 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2674 return 0xFF;
2675 }
2676
2677 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2678}
2679
2680static void
2681jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2682{
2683 u32 val;
2684 int to;
2685
2686 val = jread32(jme, JME_SMBCSR);
2687 to = JME_SMB_BUSY_TIMEOUT;
2688 while ((val & SMBCSR_BUSY) && --to) {
2689 msleep(1);
2690 val = jread32(jme, JME_SMBCSR);
2691 }
2692 if (!to) {
2693 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2694 return;
2695 }
2696
2697 jwrite32(jme, JME_SMBINTF,
2698 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2699 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2700 SMBINTF_HWRWN_WRITE |
2701 SMBINTF_HWCMD);
2702
2703 val = jread32(jme, JME_SMBINTF);
2704 to = JME_SMB_BUSY_TIMEOUT;
2705 while ((val & SMBINTF_HWCMD) && --to) {
2706 msleep(1);
2707 val = jread32(jme, JME_SMBINTF);
2708 }
2709 if (!to) {
2710 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2711 return;
2712 }
2713
2714 mdelay(2);
2715}
2716
2717static int
2718jme_get_eeprom_len(struct net_device *netdev)
2719{
2720 struct jme_adapter *jme = netdev_priv(netdev);
2721 u32 val;
2722 val = jread32(jme, JME_SMBCSR);
2723 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2724}
2725
2726static int
2727jme_get_eeprom(struct net_device *netdev,
2728 struct ethtool_eeprom *eeprom, u8 *data)
2729{
2730 struct jme_adapter *jme = netdev_priv(netdev);
2731 int i, offset = eeprom->offset, len = eeprom->len;
2732
2733 /*
2734 * ethtool will check the boundary for us
2735 */
2736 eeprom->magic = JME_EEPROM_MAGIC;
2737 for (i = 0 ; i < len ; ++i)
2738 data[i] = jme_smb_read(jme, i + offset);
2739
2740 return 0;
2741}
2742
2743static int
2744jme_set_eeprom(struct net_device *netdev,
2745 struct ethtool_eeprom *eeprom, u8 *data)
2746{
2747 struct jme_adapter *jme = netdev_priv(netdev);
2748 int i, offset = eeprom->offset, len = eeprom->len;
2749
2750 if (eeprom->magic != JME_EEPROM_MAGIC)
2751 return -EINVAL;
2752
2753 /*
2754 * ethtool will check the boundary for us
2755 */
2756 for (i = 0 ; i < len ; ++i)
2757 jme_smb_write(jme, i + offset, data[i]);
2758
2759 return 0;
2760}
2761
2762#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2763static struct ethtool_ops jme_ethtool_ops = {
2764#else
2765static const struct ethtool_ops jme_ethtool_ops = {
2766#endif
2767 .get_drvinfo = jme_get_drvinfo,
2768 .get_regs_len = jme_get_regs_len,
2769 .get_regs = jme_get_regs,
2770 .get_coalesce = jme_get_coalesce,
2771 .set_coalesce = jme_set_coalesce,
2772 .get_pauseparam = jme_get_pauseparam,
2773 .set_pauseparam = jme_set_pauseparam,
2774 .get_wol = jme_get_wol,
2775 .set_wol = jme_set_wol,
2776 .get_settings = jme_get_settings,
2777 .set_settings = jme_set_settings,
2778 .get_link = jme_get_link,
2779 .get_msglevel = jme_get_msglevel,
2780 .set_msglevel = jme_set_msglevel,
2781 .get_rx_csum = jme_get_rx_csum,
2782 .set_rx_csum = jme_set_rx_csum,
2783 .set_tx_csum = jme_set_tx_csum,
2784 .set_tso = jme_set_tso,
2785 .set_sg = ethtool_op_set_sg,
2786 .nway_reset = jme_nway_reset,
2787 .get_eeprom_len = jme_get_eeprom_len,
2788 .get_eeprom = jme_get_eeprom,
2789 .set_eeprom = jme_set_eeprom,
2790};
2791
2792static int
2793jme_pci_dma64(struct pci_dev *pdev)
2794{
2795 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2796#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2797 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2798#else
2799 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2800#endif
2801 )
2802#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2803 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2804#else
2805 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2806#endif
2807 return 1;
2808
2809 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2810#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2811 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2812#else
2813 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2814#endif
2815 )
2816#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2817 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2818#else
2819 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2820#endif
2821 return 1;
2822
2823#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2824 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2825 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2826#else
2827 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2828 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2829#endif
2830 return 0;
2831
2832 return -1;
2833}
2834
2835static inline void
2836jme_phy_init(struct jme_adapter *jme)
2837{
2838 u16 reg26;
2839
2840 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2841 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2842}
2843
2844static inline void
2845jme_check_hw_ver(struct jme_adapter *jme)
2846{
2847 u32 chipmode;
2848
2849 chipmode = jread32(jme, JME_CHIPMODE);
2850
2851 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2852 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2853}
2854
2855#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2856static const struct net_device_ops jme_netdev_ops = {
2857 .ndo_open = jme_open,
2858 .ndo_stop = jme_close,
2859 .ndo_validate_addr = eth_validate_addr,
2860 .ndo_do_ioctl = jme_ioctl,
2861 .ndo_start_xmit = jme_start_xmit,
2862 .ndo_set_mac_address = jme_set_macaddr,
2863 .ndo_set_multicast_list = jme_set_multi,
2864 .ndo_change_mtu = jme_change_mtu,
2865 .ndo_tx_timeout = jme_tx_timeout,
2866 .ndo_vlan_rx_register = jme_vlan_rx_register,
2867};
2868#endif
2869
2870static int __devinit
2871jme_init_one(struct pci_dev *pdev,
2872 const struct pci_device_id *ent)
2873{
2874 int rc = 0, using_dac, i;
2875 struct net_device *netdev;
2876 struct jme_adapter *jme;
2877 u16 bmcr, bmsr;
2878 u32 apmc;
2879
2880 /*
2881 * set up PCI device basics
2882 */
2883 rc = pci_enable_device(pdev);
2884 if (rc) {
2885 pr_err("Cannot enable PCI device\n");
2886 goto err_out;
2887 }
2888
2889 using_dac = jme_pci_dma64(pdev);
2890 if (using_dac < 0) {
2891 pr_err("Cannot set PCI DMA Mask\n");
2892 rc = -EIO;
2893 goto err_out_disable_pdev;
2894 }
2895
2896 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2897 pr_err("No PCI resource region found\n");
2898 rc = -ENOMEM;
2899 goto err_out_disable_pdev;
2900 }
2901
2902 rc = pci_request_regions(pdev, DRV_NAME);
2903 if (rc) {
2904 pr_err("Cannot obtain PCI resource region\n");
2905 goto err_out_disable_pdev;
2906 }
2907
2908 pci_set_master(pdev);
2909
2910 /*
2911 * alloc and init net device
2912 */
2913 netdev = alloc_etherdev(sizeof(*jme));
2914 if (!netdev) {
2915 pr_err("Cannot allocate netdev structure\n");
2916 rc = -ENOMEM;
2917 goto err_out_release_regions;
2918 }
2919#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2920 netdev->netdev_ops = &jme_netdev_ops;
2921#else
2922 netdev->open = jme_open;
2923 netdev->stop = jme_close;
2924 netdev->do_ioctl = jme_ioctl;
2925 netdev->hard_start_xmit = jme_start_xmit;
2926 netdev->set_mac_address = jme_set_macaddr;
2927 netdev->set_multicast_list = jme_set_multi;
2928 netdev->change_mtu = jme_change_mtu;
2929 netdev->tx_timeout = jme_tx_timeout;
2930 netdev->vlan_rx_register = jme_vlan_rx_register;
2931#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2932 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
2933#endif
2934 NETDEV_GET_STATS(netdev, &jme_get_stats);
2935#endif
2936 netdev->ethtool_ops = &jme_ethtool_ops;
2937 netdev->watchdog_timeo = TX_TIMEOUT;
2938 netdev->features = NETIF_F_IP_CSUM |
2939 NETIF_F_IPV6_CSUM |
2940 NETIF_F_SG |
2941 NETIF_F_TSO |
2942 NETIF_F_TSO6 |
2943 NETIF_F_HW_VLAN_TX |
2944 NETIF_F_HW_VLAN_RX;
2945 if (using_dac)
2946 netdev->features |= NETIF_F_HIGHDMA;
2947
2948 SET_NETDEV_DEV(netdev, &pdev->dev);
2949 pci_set_drvdata(pdev, netdev);
2950
2951 /*
2952 * init adapter info
2953 */
2954 jme = netdev_priv(netdev);
2955 jme->pdev = pdev;
2956 jme->dev = netdev;
2957 jme->jme_rx = netif_rx;
2958 jme->jme_vlan_rx = vlan_hwaccel_rx;
2959 jme->old_mtu = netdev->mtu = 1500;
2960 jme->phylink = 0;
2961 jme->tx_ring_size = 1 << 10;
2962 jme->tx_ring_mask = jme->tx_ring_size - 1;
2963 jme->tx_wake_threshold = 1 << 9;
2964 jme->rx_ring_size = 1 << 9;
2965 jme->rx_ring_mask = jme->rx_ring_size - 1;
2966 jme->msg_enable = JME_DEF_MSG_ENABLE;
2967 jme->regs = ioremap(pci_resource_start(pdev, 0),
2968 pci_resource_len(pdev, 0));
2969 if (!(jme->regs)) {
2970 pr_err("Mapping PCI resource region error\n");
2971 rc = -ENOMEM;
2972 goto err_out_free_netdev;
2973 }
2974
2975 if (no_pseudohp) {
2976 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2977 jwrite32(jme, JME_APMC, apmc);
2978 } else if (force_pseudohp) {
2979 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2980 jwrite32(jme, JME_APMC, apmc);
2981 }
2982
2983 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2984
2985 spin_lock_init(&jme->phy_lock);
2986 spin_lock_init(&jme->macaddr_lock);
2987 spin_lock_init(&jme->rxmcs_lock);
2988
2989 atomic_set(&jme->link_changing, 1);
2990 atomic_set(&jme->rx_cleaning, 1);
2991 atomic_set(&jme->tx_cleaning, 1);
2992 atomic_set(&jme->rx_empty, 1);
2993
2994 tasklet_init(&jme->pcc_task,
2995 jme_pcc_tasklet,
2996 (unsigned long) jme);
2997 tasklet_init(&jme->linkch_task,
2998 jme_link_change_tasklet,
2999 (unsigned long) jme);
3000 tasklet_init(&jme->txclean_task,
3001 jme_tx_clean_tasklet,
3002 (unsigned long) jme);
3003 tasklet_init(&jme->rxclean_task,
3004 jme_rx_clean_tasklet,
3005 (unsigned long) jme);
3006 tasklet_init(&jme->rxempty_task,
3007 jme_rx_empty_tasklet,
3008 (unsigned long) jme);
3009 tasklet_disable_nosync(&jme->linkch_task);
3010 tasklet_disable_nosync(&jme->txclean_task);
3011 tasklet_disable_nosync(&jme->rxclean_task);
3012 tasklet_disable_nosync(&jme->rxempty_task);
3013 jme->dpi.cur = PCC_P1;
3014
3015 jme->reg_ghc = 0;
3016 jme->reg_rxcs = RXCS_DEFAULT;
3017 jme->reg_rxmcs = RXMCS_DEFAULT;
3018 jme->reg_txpfc = 0;
3019 jme->reg_pmcs = PMCS_MFEN;
3020 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3021 set_bit(JME_FLAG_TSO, &jme->flags);
3022
3023 /*
3024 * Get Max Read Req Size from PCI Config Space
3025 */
3026 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3027 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3028 switch (jme->mrrs) {
3029 case MRRS_128B:
3030 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3031 break;
3032 case MRRS_256B:
3033 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3034 break;
3035 default:
3036 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3037 break;
3038 }
3039
3040 /*
3041 * Must check before reset_mac_processor
3042 */
3043 jme_check_hw_ver(jme);
3044 jme->mii_if.dev = netdev;
3045 if (jme->fpgaver) {
3046 jme->mii_if.phy_id = 0;
3047 for (i = 1 ; i < 32 ; ++i) {
3048 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3049 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3050 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3051 jme->mii_if.phy_id = i;
3052 break;
3053 }
3054 }
3055
3056 if (!jme->mii_if.phy_id) {
3057 rc = -EIO;
3058 pr_err("Can not find phy_id\n");
3059 goto err_out_unmap;
3060 }
3061
3062 jme->reg_ghc |= GHC_LINK_POLL;
3063 } else {
3064 jme->mii_if.phy_id = 1;
3065 }
3066 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3067 jme->mii_if.supports_gmii = true;
3068 else
3069 jme->mii_if.supports_gmii = false;
3070 jme->mii_if.phy_id_mask = 0x1F;
3071 jme->mii_if.reg_num_mask = 0x1F;
3072 jme->mii_if.mdio_read = jme_mdio_read;
3073 jme->mii_if.mdio_write = jme_mdio_write;
3074
3075 jme_clear_pm(jme);
3076 jme_set_phyfifoa(jme);
3077 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
3078 if (!jme->fpgaver)
3079 jme_phy_init(jme);
3080 jme_phy_off(jme);
3081
3082 /*
3083 * Reset MAC processor and reload EEPROM for MAC Address
3084 */
3085 jme_reset_mac_processor(jme);
3086 rc = jme_reload_eeprom(jme);
3087 if (rc) {
3088 pr_err("Reload eeprom for reading MAC Address error\n");
3089 goto err_out_unmap;
3090 }
3091 jme_load_macaddr(netdev);
3092
3093 /*
3094 * Tell stack that we are not ready to work until open()
3095 */
3096 netif_carrier_off(netdev);
3097
3098 rc = register_netdev(netdev);
3099 if (rc) {
3100 pr_err("Cannot register net device\n");
3101 goto err_out_unmap;
3102 }
3103
3104 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x "
3105 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3106 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3107 "JMC250 Gigabit Ethernet" :
3108 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3109 "JMC260 Fast Ethernet" : "Unknown",
3110 (jme->fpgaver != 0) ? " (FPGA)" : "",
3111 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3112 jme->rev,
3113 netdev->dev_addr[0],
3114 netdev->dev_addr[1],
3115 netdev->dev_addr[2],
3116 netdev->dev_addr[3],
3117 netdev->dev_addr[4],
3118 netdev->dev_addr[5]);
3119
3120 return 0;
3121
3122err_out_unmap:
3123 iounmap(jme->regs);
3124err_out_free_netdev:
3125 pci_set_drvdata(pdev, NULL);
3126 free_netdev(netdev);
3127err_out_release_regions:
3128 pci_release_regions(pdev);
3129err_out_disable_pdev:
3130 pci_disable_device(pdev);
3131err_out:
3132 return rc;
3133}
3134
3135static void __devexit
3136jme_remove_one(struct pci_dev *pdev)
3137{
3138 struct net_device *netdev = pci_get_drvdata(pdev);
3139 struct jme_adapter *jme = netdev_priv(netdev);
3140
3141 unregister_netdev(netdev);
3142 iounmap(jme->regs);
3143 pci_set_drvdata(pdev, NULL);
3144 free_netdev(netdev);
3145 pci_release_regions(pdev);
3146 pci_disable_device(pdev);
3147
3148}
3149
3150static void
3151jme_shutdown(struct pci_dev *pdev)
3152{
3153 struct net_device *netdev = pci_get_drvdata(pdev);
3154 struct jme_adapter *jme = netdev_priv(netdev);
3155
3156 jme_powersave_phy(jme);
3157#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3158 pci_enable_wake(pdev, PCI_D3hot, true);
3159#else
3160 pci_pme_active(pdev, true);
3161#endif
3162}
3163
3164#ifdef CONFIG_PM
3165static int
3166jme_suspend(struct pci_dev *pdev, pm_message_t state)
3167{
3168 struct net_device *netdev = pci_get_drvdata(pdev);
3169 struct jme_adapter *jme = netdev_priv(netdev);
3170
3171 atomic_dec(&jme->link_changing);
3172
3173 netif_device_detach(netdev);
3174 netif_stop_queue(netdev);
3175 jme_stop_irq(jme);
3176
3177 tasklet_disable(&jme->txclean_task);
3178 tasklet_disable(&jme->rxclean_task);
3179 tasklet_disable(&jme->rxempty_task);
3180
3181 if (netif_carrier_ok(netdev)) {
3182 if (test_bit(JME_FLAG_POLL, &jme->flags))
3183 jme_polling_mode(jme);
3184
3185 jme_stop_pcc_timer(jme);
3186 jme_reset_ghc_speed(jme);
3187 jme_disable_rx_engine(jme);
3188 jme_disable_tx_engine(jme);
3189 jme_reset_mac_processor(jme);
3190 jme_free_rx_resources(jme);
3191 jme_free_tx_resources(jme);
3192 netif_carrier_off(netdev);
3193 jme->phylink = 0;
3194 }
3195
3196 tasklet_enable(&jme->txclean_task);
3197 tasklet_hi_enable(&jme->rxclean_task);
3198 tasklet_hi_enable(&jme->rxempty_task);
3199
3200 pci_save_state(pdev);
3201 jme_powersave_phy(jme);
3202 pci_enable_wake(pdev, PCI_D3hot, true);
3203 pci_set_power_state(pdev, PCI_D3hot);
3204
3205 return 0;
3206}
3207
3208static int
3209jme_resume(struct pci_dev *pdev)
3210{
3211 struct net_device *netdev = pci_get_drvdata(pdev);
3212 struct jme_adapter *jme = netdev_priv(netdev);
3213
3214 jme_clear_pm(jme);
3215 pci_restore_state(pdev);
3216
3217 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3218 jme_phy_on(jme);
3219 jme_set_settings(netdev, &jme->old_ecmd);
3220 } else {
3221 jme_reset_phy_processor(jme);
3222 }
3223
3224 jme_start_irq(jme);
3225 netif_device_attach(netdev);
3226
3227 atomic_inc(&jme->link_changing);
3228
3229 jme_reset_link(jme);
3230
3231 return 0;
3232}
3233#endif
3234
3235#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3236static struct pci_device_id jme_pci_tbl[] = {
3237#else
3238static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3239#endif
3240 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3241 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3242 { }
3243};
3244
3245static struct pci_driver jme_driver = {
3246 .name = DRV_NAME,
3247 .id_table = jme_pci_tbl,
3248 .probe = jme_init_one,
3249 .remove = __devexit_p(jme_remove_one),
3250#ifdef CONFIG_PM
3251 .suspend = jme_suspend,
3252 .resume = jme_resume,
3253#endif /* CONFIG_PM */
3254 .shutdown = jme_shutdown,
3255};
3256
3257static int __init
3258jme_init_module(void)
3259{
3260 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3261 return pci_register_driver(&jme_driver);
3262}
3263
3264static void __exit
3265jme_cleanup_module(void)
3266{
3267 pci_unregister_driver(&jme_driver);
3268}
3269
3270module_init(jme_init_module);
3271module_exit(jme_cleanup_module);
3272
3273MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3274MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3275MODULE_LICENSE("GPL");
3276MODULE_VERSION(DRV_VERSION);
3277MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3278
JMicron Ethernet Linux driver