]> bbs.cooldavid.org Git - jme.git/blame_incremental - jme.c
git://bbs.cooldavid.org / jme.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
Add .gitignore
[jme.git] / jme.c
... / ...
CommitLineData
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#include <linux/version.h>
25#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27#endif
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/crc32.h>
37#include <linux/delay.h>
38#include <linux/spinlock.h>
39#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/ipv6.h>
42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/if_vlan.h>
45#include <linux/slab.h>
46#include <net/ip6_checksum.h>
47#include "jme.h"
48
49static int force_pseudohp = -1;
50static int no_pseudohp = -1;
51static int no_extplug = -1;
52module_param(force_pseudohp, int, 0);
53MODULE_PARM_DESC(force_pseudohp,
54 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
55module_param(no_pseudohp, int, 0);
56MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
57module_param(no_extplug, int, 0);
58MODULE_PARM_DESC(no_extplug,
59 "Do not use external plug signal for pseudo hot-plug.");
60
61static int
62jme_mdio_read(struct net_device *netdev, int phy, int reg)
63{
64 struct jme_adapter *jme = netdev_priv(netdev);
65 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
66
67read_again:
68 jwrite32(jme, JME_SMI, SMI_OP_REQ |
69 smi_phy_addr(phy) |
70 smi_reg_addr(reg));
71
72 wmb();
73 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
74 udelay(20);
75 val = jread32(jme, JME_SMI);
76 if ((val & SMI_OP_REQ) == 0)
77 break;
78 }
79
80 if (i == 0) {
81 pr_err("phy(%d) read timeout : %d\n", phy, reg);
82 return 0;
83 }
84
85 if (again--)
86 goto read_again;
87
88 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
89}
90
91static void
92jme_mdio_write(struct net_device *netdev,
93 int phy, int reg, int val)
94{
95 struct jme_adapter *jme = netdev_priv(netdev);
96 int i;
97
98 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
99 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
100 smi_phy_addr(phy) | smi_reg_addr(reg));
101
102 wmb();
103 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
104 udelay(20);
105 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
106 break;
107 }
108
109 if (i == 0)
110 pr_err("phy(%d) write timeout : %d\n", phy, reg);
111}
112
113static inline void
114jme_reset_phy_processor(struct jme_adapter *jme)
115{
116 u32 val;
117
118 jme_mdio_write(jme->dev,
119 jme->mii_if.phy_id,
120 MII_ADVERTISE, ADVERTISE_ALL |
121 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
122
123 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
124 jme_mdio_write(jme->dev,
125 jme->mii_if.phy_id,
126 MII_CTRL1000,
127 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
128
129 val = jme_mdio_read(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR);
132
133 jme_mdio_write(jme->dev,
134 jme->mii_if.phy_id,
135 MII_BMCR, val | BMCR_RESET);
136}
137
138static void
139jme_setup_wakeup_frame(struct jme_adapter *jme,
140 u32 *mask, u32 crc, int fnr)
141{
142 int i;
143
144 /*
145 * Setup CRC pattern
146 */
147 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
148 wmb();
149 jwrite32(jme, JME_WFODP, crc);
150 wmb();
151
152 /*
153 * Setup Mask
154 */
155 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
156 jwrite32(jme, JME_WFOI,
157 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
158 (fnr & WFOI_FRAME_SEL));
159 wmb();
160 jwrite32(jme, JME_WFODP, mask[i]);
161 wmb();
162 }
163}
164
165static inline void
166jme_reset_mac_processor(struct jme_adapter *jme)
167{
168 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
169 u32 crc = 0xCDCDCDCD;
170 u32 gpreg0;
171 int i;
172
173 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
174 udelay(2);
175 jwrite32(jme, JME_GHC, jme->reg_ghc);
176
177 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
178 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
179 jwrite32(jme, JME_RXQDC, 0x00000000);
180 jwrite32(jme, JME_RXNDA, 0x00000000);
181 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
182 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
183 jwrite32(jme, JME_TXQDC, 0x00000000);
184 jwrite32(jme, JME_TXNDA, 0x00000000);
185
186 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
187 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
188 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
189 jme_setup_wakeup_frame(jme, mask, crc, i);
190 if (jme->fpgaver)
191 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
192 else
193 gpreg0 = GPREG0_DEFAULT;
194 jwrite32(jme, JME_GPREG0, gpreg0);
195 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
196}
197
198static inline void
199jme_reset_ghc_speed(struct jme_adapter *jme)
200{
201 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
202 jwrite32(jme, JME_GHC, jme->reg_ghc);
203}
204
205static inline void
206jme_clear_pm(struct jme_adapter *jme)
207{
208 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
209 pci_set_power_state(jme->pdev, PCI_D0);
210 pci_enable_wake(jme->pdev, PCI_D0, false);
211}
212
213static int
214jme_reload_eeprom(struct jme_adapter *jme)
215{
216 u32 val;
217 int i;
218
219 val = jread32(jme, JME_SMBCSR);
220
221 if (val & SMBCSR_EEPROMD) {
222 val |= SMBCSR_CNACK;
223 jwrite32(jme, JME_SMBCSR, val);
224 val |= SMBCSR_RELOAD;
225 jwrite32(jme, JME_SMBCSR, val);
226 mdelay(12);
227
228 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
229 mdelay(1);
230 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
231 break;
232 }
233
234 if (i == 0) {
235 pr_err("eeprom reload timeout\n");
236 return -EIO;
237 }
238 }
239
240 return 0;
241}
242
243static void
244jme_load_macaddr(struct net_device *netdev)
245{
246 struct jme_adapter *jme = netdev_priv(netdev);
247 unsigned char macaddr[6];
248 u32 val;
249
250 spin_lock_bh(&jme->macaddr_lock);
251 val = jread32(jme, JME_RXUMA_LO);
252 macaddr[0] = (val >> 0) & 0xFF;
253 macaddr[1] = (val >> 8) & 0xFF;
254 macaddr[2] = (val >> 16) & 0xFF;
255 macaddr[3] = (val >> 24) & 0xFF;
256 val = jread32(jme, JME_RXUMA_HI);
257 macaddr[4] = (val >> 0) & 0xFF;
258 macaddr[5] = (val >> 8) & 0xFF;
259 memcpy(netdev->dev_addr, macaddr, 6);
260 spin_unlock_bh(&jme->macaddr_lock);
261}
262
263static inline void
264jme_set_rx_pcc(struct jme_adapter *jme, int p)
265{
266 switch (p) {
267 case PCC_OFF:
268 jwrite32(jme, JME_PCCRX0,
269 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
270 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 break;
272 case PCC_P1:
273 jwrite32(jme, JME_PCCRX0,
274 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
275 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 break;
277 case PCC_P2:
278 jwrite32(jme, JME_PCCRX0,
279 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
280 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 break;
282 case PCC_P3:
283 jwrite32(jme, JME_PCCRX0,
284 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
285 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
286 break;
287 default:
288 break;
289 }
290 wmb();
291
292 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
293 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
294}
295
296static void
297jme_start_irq(struct jme_adapter *jme)
298{
299 register struct dynpcc_info *dpi = &(jme->dpi);
300
301 jme_set_rx_pcc(jme, PCC_P1);
302 dpi->cur = PCC_P1;
303 dpi->attempt = PCC_P1;
304 dpi->cnt = 0;
305
306 jwrite32(jme, JME_PCCTX,
307 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
308 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
309 PCCTXQ0_EN
310 );
311
312 /*
313 * Enable Interrupts
314 */
315 jwrite32(jme, JME_IENS, INTR_ENABLE);
316}
317
318static inline void
319jme_stop_irq(struct jme_adapter *jme)
320{
321 /*
322 * Disable Interrupts
323 */
324 jwrite32f(jme, JME_IENC, INTR_ENABLE);
325}
326
327static u32
328jme_linkstat_from_phy(struct jme_adapter *jme)
329{
330 u32 phylink, bmsr;
331
332 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
333 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
334 if (bmsr & BMSR_ANCOMP)
335 phylink |= PHY_LINK_AUTONEG_COMPLETE;
336
337 return phylink;
338}
339
340static inline void
341jme_set_phyfifoa(struct jme_adapter *jme)
342{
343 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
344}
345
346static inline void
347jme_set_phyfifob(struct jme_adapter *jme)
348{
349 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
350}
351
352static int
353jme_check_link(struct net_device *netdev, int testonly)
354{
355 struct jme_adapter *jme = netdev_priv(netdev);
356 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
357 char linkmsg[64];
358 int rc = 0;
359
360 linkmsg[0] = '\0';
361
362 if (jme->fpgaver)
363 phylink = jme_linkstat_from_phy(jme);
364 else
365 phylink = jread32(jme, JME_PHY_LINK);
366
367 if (phylink & PHY_LINK_UP) {
368 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
369 /*
370 * If we did not enable AN
371 * Speed/Duplex Info should be obtained from SMI
372 */
373 phylink = PHY_LINK_UP;
374
375 bmcr = jme_mdio_read(jme->dev,
376 jme->mii_if.phy_id,
377 MII_BMCR);
378
379 phylink |= ((bmcr & BMCR_SPEED1000) &&
380 (bmcr & BMCR_SPEED100) == 0) ?
381 PHY_LINK_SPEED_1000M :
382 (bmcr & BMCR_SPEED100) ?
383 PHY_LINK_SPEED_100M :
384 PHY_LINK_SPEED_10M;
385
386 phylink |= (bmcr & BMCR_FULLDPLX) ?
387 PHY_LINK_DUPLEX : 0;
388
389 strcat(linkmsg, "Forced: ");
390 } else {
391 /*
392 * Keep polling for speed/duplex resolve complete
393 */
394 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
395 --cnt) {
396
397 udelay(1);
398
399 if (jme->fpgaver)
400 phylink = jme_linkstat_from_phy(jme);
401 else
402 phylink = jread32(jme, JME_PHY_LINK);
403 }
404 if (!cnt)
405 pr_err("Waiting speed resolve timeout\n");
406
407 strcat(linkmsg, "ANed: ");
408 }
409
410 if (jme->phylink == phylink) {
411 rc = 1;
412 goto out;
413 }
414 if (testonly)
415 goto out;
416
417 jme->phylink = phylink;
418
419 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
420 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
421 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
422 switch (phylink & PHY_LINK_SPEED_MASK) {
423 case PHY_LINK_SPEED_10M:
424 ghc |= GHC_SPEED_10M |
425 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
426 strcat(linkmsg, "10 Mbps, ");
427 break;
428 case PHY_LINK_SPEED_100M:
429 ghc |= GHC_SPEED_100M |
430 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
431 strcat(linkmsg, "100 Mbps, ");
432 break;
433 case PHY_LINK_SPEED_1000M:
434 ghc |= GHC_SPEED_1000M |
435 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
436 strcat(linkmsg, "1000 Mbps, ");
437 break;
438 default:
439 break;
440 }
441
442 if (phylink & PHY_LINK_DUPLEX) {
443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
444 ghc |= GHC_DPX;
445 } else {
446 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
447 TXMCS_BACKOFF |
448 TXMCS_CARRIERSENSE |
449 TXMCS_COLLISION);
450 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
451 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
452 TXTRHD_TXREN |
453 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
454 }
455
456 gpreg1 = GPREG1_DEFAULT;
457 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
458 if (!(phylink & PHY_LINK_DUPLEX))
459 gpreg1 |= GPREG1_HALFMODEPATCH;
460 switch (phylink & PHY_LINK_SPEED_MASK) {
461 case PHY_LINK_SPEED_10M:
462 jme_set_phyfifoa(jme);
463 gpreg1 |= GPREG1_RSSPATCH;
464 break;
465 case PHY_LINK_SPEED_100M:
466 jme_set_phyfifob(jme);
467 gpreg1 |= GPREG1_RSSPATCH;
468 break;
469 case PHY_LINK_SPEED_1000M:
470 jme_set_phyfifoa(jme);
471 break;
472 default:
473 break;
474 }
475 }
476
477 jwrite32(jme, JME_GPREG1, gpreg1);
478 jwrite32(jme, JME_GHC, ghc);
479 jme->reg_ghc = ghc;
480
481 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
482 "Full-Duplex, " :
483 "Half-Duplex, ");
484 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
485 "MDI-X" :
486 "MDI");
487 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
488 netif_carrier_on(netdev);
489 } else {
490 if (testonly)
491 goto out;
492
493 netif_info(jme, link, jme->dev, "Link is down\n");
494 jme->phylink = 0;
495 netif_carrier_off(netdev);
496 }
497
498out:
499 return rc;
500}
501
502static int
503jme_setup_tx_resources(struct jme_adapter *jme)
504{
505 struct jme_ring *txring = &(jme->txring[0]);
506
507 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
508 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
509 &(txring->dmaalloc),
510 GFP_ATOMIC);
511
512 if (!txring->alloc)
513 goto err_set_null;
514
515 /*
516 * 16 Bytes align
517 */
518 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
519 RING_DESC_ALIGN);
520 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
521 txring->next_to_use = 0;
522 atomic_set(&txring->next_to_clean, 0);
523 atomic_set(&txring->nr_free, jme->tx_ring_size);
524
525 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
526 jme->tx_ring_size, GFP_ATOMIC);
527 if (unlikely(!(txring->bufinf)))
528 goto err_free_txring;
529
530 /*
531 * Initialize Transmit Descriptors
532 */
533 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
534 memset(txring->bufinf, 0,
535 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
536
537 return 0;
538
539err_free_txring:
540 dma_free_coherent(&(jme->pdev->dev),
541 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
542 txring->alloc,
543 txring->dmaalloc);
544
545err_set_null:
546 txring->desc = NULL;
547 txring->dmaalloc = 0;
548 txring->dma = 0;
549 txring->bufinf = NULL;
550
551 return -ENOMEM;
552}
553
554static void
555jme_free_tx_resources(struct jme_adapter *jme)
556{
557 int i;
558 struct jme_ring *txring = &(jme->txring[0]);
559 struct jme_buffer_info *txbi;
560
561 if (txring->alloc) {
562 if (txring->bufinf) {
563 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
564 txbi = txring->bufinf + i;
565 if (txbi->skb) {
566 dev_kfree_skb(txbi->skb);
567 txbi->skb = NULL;
568 }
569 txbi->mapping = 0;
570 txbi->len = 0;
571 txbi->nr_desc = 0;
572 txbi->start_xmit = 0;
573 }
574 kfree(txring->bufinf);
575 }
576
577 dma_free_coherent(&(jme->pdev->dev),
578 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
579 txring->alloc,
580 txring->dmaalloc);
581
582 txring->alloc = NULL;
583 txring->desc = NULL;
584 txring->dmaalloc = 0;
585 txring->dma = 0;
586 txring->bufinf = NULL;
587 }
588 txring->next_to_use = 0;
589 atomic_set(&txring->next_to_clean, 0);
590 atomic_set(&txring->nr_free, 0);
591}
592
593static inline void
594jme_enable_tx_engine(struct jme_adapter *jme)
595{
596 /*
597 * Select Queue 0
598 */
599 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
600 wmb();
601
602 /*
603 * Setup TX Queue 0 DMA Bass Address
604 */
605 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
606 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
607 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
608
609 /*
610 * Setup TX Descptor Count
611 */
612 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
613
614 /*
615 * Enable TX Engine
616 */
617 wmb();
618 jwrite32(jme, JME_TXCS, jme->reg_txcs |
619 TXCS_SELECT_QUEUE0 |
620 TXCS_ENABLE);
621
622}
623
624static inline void
625jme_restart_tx_engine(struct jme_adapter *jme)
626{
627 /*
628 * Restart TX Engine
629 */
630 jwrite32(jme, JME_TXCS, jme->reg_txcs |
631 TXCS_SELECT_QUEUE0 |
632 TXCS_ENABLE);
633}
634
635static inline void
636jme_disable_tx_engine(struct jme_adapter *jme)
637{
638 int i;
639 u32 val;
640
641 /*
642 * Disable TX Engine
643 */
644 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
645 wmb();
646
647 val = jread32(jme, JME_TXCS);
648 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
649 mdelay(1);
650 val = jread32(jme, JME_TXCS);
651 rmb();
652 }
653
654 if (!i)
655 pr_err("Disable TX engine timeout\n");
656}
657
658static void
659jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
660{
661 struct jme_ring *rxring = &(jme->rxring[0]);
662 register struct rxdesc *rxdesc = rxring->desc;
663 struct jme_buffer_info *rxbi = rxring->bufinf;
664 rxdesc += i;
665 rxbi += i;
666
667 rxdesc->dw[0] = 0;
668 rxdesc->dw[1] = 0;
669 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
670 rxdesc->desc1.bufaddrl = cpu_to_le32(
671 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
672 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
673 if (jme->dev->features & NETIF_F_HIGHDMA)
674 rxdesc->desc1.flags = RXFLAG_64BIT;
675 wmb();
676 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
677}
678
679static int
680jme_make_new_rx_buf(struct jme_adapter *jme, int i)
681{
682 struct jme_ring *rxring = &(jme->rxring[0]);
683 struct jme_buffer_info *rxbi = rxring->bufinf + i;
684 struct sk_buff *skb;
685
686 skb = netdev_alloc_skb(jme->dev,
687 jme->dev->mtu + RX_EXTRA_LEN);
688 if (unlikely(!skb))
689 return -ENOMEM;
690#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
691 skb->dev = jme->dev;
692#endif
693
694 rxbi->skb = skb;
695 rxbi->len = skb_tailroom(skb);
696 rxbi->mapping = pci_map_page(jme->pdev,
697 virt_to_page(skb->data),
698 offset_in_page(skb->data),
699 rxbi->len,
700 PCI_DMA_FROMDEVICE);
701
702 return 0;
703}
704
705static void
706jme_free_rx_buf(struct jme_adapter *jme, int i)
707{
708 struct jme_ring *rxring = &(jme->rxring[0]);
709 struct jme_buffer_info *rxbi = rxring->bufinf;
710 rxbi += i;
711
712 if (rxbi->skb) {
713 pci_unmap_page(jme->pdev,
714 rxbi->mapping,
715 rxbi->len,
716 PCI_DMA_FROMDEVICE);
717 dev_kfree_skb(rxbi->skb);
718 rxbi->skb = NULL;
719 rxbi->mapping = 0;
720 rxbi->len = 0;
721 }
722}
723
724static void
725jme_free_rx_resources(struct jme_adapter *jme)
726{
727 int i;
728 struct jme_ring *rxring = &(jme->rxring[0]);
729
730 if (rxring->alloc) {
731 if (rxring->bufinf) {
732 for (i = 0 ; i < jme->rx_ring_size ; ++i)
733 jme_free_rx_buf(jme, i);
734 kfree(rxring->bufinf);
735 }
736
737 dma_free_coherent(&(jme->pdev->dev),
738 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
739 rxring->alloc,
740 rxring->dmaalloc);
741 rxring->alloc = NULL;
742 rxring->desc = NULL;
743 rxring->dmaalloc = 0;
744 rxring->dma = 0;
745 rxring->bufinf = NULL;
746 }
747 rxring->next_to_use = 0;
748 atomic_set(&rxring->next_to_clean, 0);
749}
750
751static int
752jme_setup_rx_resources(struct jme_adapter *jme)
753{
754 int i;
755 struct jme_ring *rxring = &(jme->rxring[0]);
756
757 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
758 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
759 &(rxring->dmaalloc),
760 GFP_ATOMIC);
761 if (!rxring->alloc)
762 goto err_set_null;
763
764 /*
765 * 16 Bytes align
766 */
767 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
768 RING_DESC_ALIGN);
769 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
770 rxring->next_to_use = 0;
771 atomic_set(&rxring->next_to_clean, 0);
772
773 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
774 jme->rx_ring_size, GFP_ATOMIC);
775 if (unlikely(!(rxring->bufinf)))
776 goto err_free_rxring;
777
778 /*
779 * Initiallize Receive Descriptors
780 */
781 memset(rxring->bufinf, 0,
782 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
783 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
784 if (unlikely(jme_make_new_rx_buf(jme, i))) {
785 jme_free_rx_resources(jme);
786 return -ENOMEM;
787 }
788
789 jme_set_clean_rxdesc(jme, i);
790 }
791
792 return 0;
793
794err_free_rxring:
795 dma_free_coherent(&(jme->pdev->dev),
796 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
797 rxring->alloc,
798 rxring->dmaalloc);
799err_set_null:
800 rxring->desc = NULL;
801 rxring->dmaalloc = 0;
802 rxring->dma = 0;
803 rxring->bufinf = NULL;
804
805 return -ENOMEM;
806}
807
808static inline void
809jme_enable_rx_engine(struct jme_adapter *jme)
810{
811 /*
812 * Select Queue 0
813 */
814 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
815 RXCS_QUEUESEL_Q0);
816 wmb();
817
818 /*
819 * Setup RX DMA Bass Address
820 */
821 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
822 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
823 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
824
825 /*
826 * Setup RX Descriptor Count
827 */
828 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
829
830 /*
831 * Setup Unicast Filter
832 */
833 jme_set_multi(jme->dev);
834
835 /*
836 * Enable RX Engine
837 */
838 wmb();
839 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
840 RXCS_QUEUESEL_Q0 |
841 RXCS_ENABLE |
842 RXCS_QST);
843}
844
845static inline void
846jme_restart_rx_engine(struct jme_adapter *jme)
847{
848 /*
849 * Start RX Engine
850 */
851 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
852 RXCS_QUEUESEL_Q0 |
853 RXCS_ENABLE |
854 RXCS_QST);
855}
856
857static inline void
858jme_disable_rx_engine(struct jme_adapter *jme)
859{
860 int i;
861 u32 val;
862
863 /*
864 * Disable RX Engine
865 */
866 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
867 wmb();
868
869 val = jread32(jme, JME_RXCS);
870 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
871 mdelay(1);
872 val = jread32(jme, JME_RXCS);
873 rmb();
874 }
875
876 if (!i)
877 pr_err("Disable RX engine timeout\n");
878
879}
880
881static int
882jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
883{
884 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
885 return false;
886
887 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
888 == RXWBFLAG_TCPON)) {
889 if (flags & RXWBFLAG_IPV4)
890 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
891 return false;
892 }
893
894 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
895 == RXWBFLAG_UDPON)) {
896 if (flags & RXWBFLAG_IPV4)
897 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
898 return false;
899 }
900
901 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
902 == RXWBFLAG_IPV4)) {
903 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
904 return false;
905 }
906
907 return true;
908}
909
910static void
911jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
912{
913 struct jme_ring *rxring = &(jme->rxring[0]);
914 struct rxdesc *rxdesc = rxring->desc;
915 struct jme_buffer_info *rxbi = rxring->bufinf;
916 struct sk_buff *skb;
917 int framesize;
918
919 rxdesc += idx;
920 rxbi += idx;
921
922 skb = rxbi->skb;
923 pci_dma_sync_single_for_cpu(jme->pdev,
924 rxbi->mapping,
925 rxbi->len,
926 PCI_DMA_FROMDEVICE);
927
928 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
929 pci_dma_sync_single_for_device(jme->pdev,
930 rxbi->mapping,
931 rxbi->len,
932 PCI_DMA_FROMDEVICE);
933
934 ++(NET_STAT(jme).rx_dropped);
935 } else {
936 framesize = le16_to_cpu(rxdesc->descwb.framesize)
937 - RX_PREPAD_SIZE;
938
939 skb_reserve(skb, RX_PREPAD_SIZE);
940 skb_put(skb, framesize);
941 skb->protocol = eth_type_trans(skb, jme->dev);
942
943 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
944 skb->ip_summed = CHECKSUM_UNNECESSARY;
945 else
946#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
947 skb->ip_summed = CHECKSUM_NONE;
948#else
949 skb_checksum_none_assert(skb);
950#endif
951
952 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
953 if (jme->vlgrp) {
954 jme->jme_vlan_rx(skb, jme->vlgrp,
955 le16_to_cpu(rxdesc->descwb.vlan));
956 NET_STAT(jme).rx_bytes += 4;
957 } else {
958 dev_kfree_skb(skb);
959 }
960 } else {
961 jme->jme_rx(skb);
962 }
963
964 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
965 cpu_to_le16(RXWBFLAG_DEST_MUL))
966 ++(NET_STAT(jme).multicast);
967
968 NET_STAT(jme).rx_bytes += framesize;
969 ++(NET_STAT(jme).rx_packets);
970 }
971
972 jme_set_clean_rxdesc(jme, idx);
973
974}
975
976static int
977jme_process_receive(struct jme_adapter *jme, int limit)
978{
979 struct jme_ring *rxring = &(jme->rxring[0]);
980 struct rxdesc *rxdesc = rxring->desc;
981 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
982
983 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
984 goto out_inc;
985
986 if (unlikely(atomic_read(&jme->link_changing) != 1))
987 goto out_inc;
988
989 if (unlikely(!netif_carrier_ok(jme->dev)))
990 goto out_inc;
991
992 i = atomic_read(&rxring->next_to_clean);
993 while (limit > 0) {
994 rxdesc = rxring->desc;
995 rxdesc += i;
996
997 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
998 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
999 goto out;
1000 --limit;
1001
1002 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1003
1004 if (unlikely(desccnt > 1 ||
1005 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1006
1007 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1008 ++(NET_STAT(jme).rx_crc_errors);
1009 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1010 ++(NET_STAT(jme).rx_fifo_errors);
1011 else
1012 ++(NET_STAT(jme).rx_errors);
1013
1014 if (desccnt > 1)
1015 limit -= desccnt - 1;
1016
1017 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1018 jme_set_clean_rxdesc(jme, j);
1019 j = (j + 1) & (mask);
1020 }
1021
1022 } else {
1023 jme_alloc_and_feed_skb(jme, i);
1024 }
1025
1026 i = (i + desccnt) & (mask);
1027 }
1028
1029out:
1030 atomic_set(&rxring->next_to_clean, i);
1031
1032out_inc:
1033 atomic_inc(&jme->rx_cleaning);
1034
1035 return limit > 0 ? limit : 0;
1036
1037}
1038
1039static void
1040jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1041{
1042 if (likely(atmp == dpi->cur)) {
1043 dpi->cnt = 0;
1044 return;
1045 }
1046
1047 if (dpi->attempt == atmp) {
1048 ++(dpi->cnt);
1049 } else {
1050 dpi->attempt = atmp;
1051 dpi->cnt = 0;
1052 }
1053
1054}
1055
1056static void
1057jme_dynamic_pcc(struct jme_adapter *jme)
1058{
1059 register struct dynpcc_info *dpi = &(jme->dpi);
1060
1061 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1062 jme_attempt_pcc(dpi, PCC_P3);
1063 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1064 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1065 jme_attempt_pcc(dpi, PCC_P2);
1066 else
1067 jme_attempt_pcc(dpi, PCC_P1);
1068
1069 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1070 if (dpi->attempt < dpi->cur)
1071 tasklet_schedule(&jme->rxclean_task);
1072 jme_set_rx_pcc(jme, dpi->attempt);
1073 dpi->cur = dpi->attempt;
1074 dpi->cnt = 0;
1075 }
1076}
1077
1078static void
1079jme_start_pcc_timer(struct jme_adapter *jme)
1080{
1081 struct dynpcc_info *dpi = &(jme->dpi);
1082 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1083 dpi->last_pkts = NET_STAT(jme).rx_packets;
1084 dpi->intr_cnt = 0;
1085 jwrite32(jme, JME_TMCSR,
1086 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1087}
1088
1089static inline void
1090jme_stop_pcc_timer(struct jme_adapter *jme)
1091{
1092 jwrite32(jme, JME_TMCSR, 0);
1093}
1094
1095static void
1096jme_shutdown_nic(struct jme_adapter *jme)
1097{
1098 u32 phylink;
1099
1100 phylink = jme_linkstat_from_phy(jme);
1101
1102 if (!(phylink & PHY_LINK_UP)) {
1103 /*
1104 * Disable all interrupt before issue timer
1105 */
1106 jme_stop_irq(jme);
1107 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1108 }
1109}
1110
1111static void
1112jme_pcc_tasklet(unsigned long arg)
1113{
1114 struct jme_adapter *jme = (struct jme_adapter *)arg;
1115 struct net_device *netdev = jme->dev;
1116
1117 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1118 jme_shutdown_nic(jme);
1119 return;
1120 }
1121
1122 if (unlikely(!netif_carrier_ok(netdev) ||
1123 (atomic_read(&jme->link_changing) != 1)
1124 )) {
1125 jme_stop_pcc_timer(jme);
1126 return;
1127 }
1128
1129 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1130 jme_dynamic_pcc(jme);
1131
1132 jme_start_pcc_timer(jme);
1133}
1134
1135static inline void
1136jme_polling_mode(struct jme_adapter *jme)
1137{
1138 jme_set_rx_pcc(jme, PCC_OFF);
1139}
1140
1141static inline void
1142jme_interrupt_mode(struct jme_adapter *jme)
1143{
1144 jme_set_rx_pcc(jme, PCC_P1);
1145}
1146
1147static inline int
1148jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1149{
1150 u32 apmc;
1151 apmc = jread32(jme, JME_APMC);
1152 return apmc & JME_APMC_PSEUDO_HP_EN;
1153}
1154
1155static void
1156jme_start_shutdown_timer(struct jme_adapter *jme)
1157{
1158 u32 apmc;
1159
1160 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1161 apmc &= ~JME_APMC_EPIEN_CTRL;
1162 if (!no_extplug) {
1163 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1164 wmb();
1165 }
1166 jwrite32f(jme, JME_APMC, apmc);
1167
1168 jwrite32f(jme, JME_TIMER2, 0);
1169 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1170 jwrite32(jme, JME_TMCSR,
1171 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1172}
1173
1174static void
1175jme_stop_shutdown_timer(struct jme_adapter *jme)
1176{
1177 u32 apmc;
1178
1179 jwrite32f(jme, JME_TMCSR, 0);
1180 jwrite32f(jme, JME_TIMER2, 0);
1181 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1182
1183 apmc = jread32(jme, JME_APMC);
1184 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1185 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1186 wmb();
1187 jwrite32f(jme, JME_APMC, apmc);
1188}
1189
1190static void
1191jme_link_change_tasklet(unsigned long arg)
1192{
1193 struct jme_adapter *jme = (struct jme_adapter *)arg;
1194 struct net_device *netdev = jme->dev;
1195 int rc;
1196
1197 while (!atomic_dec_and_test(&jme->link_changing)) {
1198 atomic_inc(&jme->link_changing);
1199 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1200 while (atomic_read(&jme->link_changing) != 1)
1201 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1202 }
1203
1204 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1205 goto out;
1206
1207 jme->old_mtu = netdev->mtu;
1208 netif_stop_queue(netdev);
1209 if (jme_pseudo_hotplug_enabled(jme))
1210 jme_stop_shutdown_timer(jme);
1211
1212 jme_stop_pcc_timer(jme);
1213 tasklet_disable(&jme->txclean_task);
1214 tasklet_disable(&jme->rxclean_task);
1215 tasklet_disable(&jme->rxempty_task);
1216
1217 if (netif_carrier_ok(netdev)) {
1218 jme_reset_ghc_speed(jme);
1219 jme_disable_rx_engine(jme);
1220 jme_disable_tx_engine(jme);
1221 jme_reset_mac_processor(jme);
1222 jme_free_rx_resources(jme);
1223 jme_free_tx_resources(jme);
1224
1225 if (test_bit(JME_FLAG_POLL, &jme->flags))
1226 jme_polling_mode(jme);
1227
1228 netif_carrier_off(netdev);
1229 }
1230
1231 jme_check_link(netdev, 0);
1232 if (netif_carrier_ok(netdev)) {
1233 rc = jme_setup_rx_resources(jme);
1234 if (rc) {
1235 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1236 goto out_enable_tasklet;
1237 }
1238
1239 rc = jme_setup_tx_resources(jme);
1240 if (rc) {
1241 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1242 goto err_out_free_rx_resources;
1243 }
1244
1245 jme_enable_rx_engine(jme);
1246 jme_enable_tx_engine(jme);
1247
1248 netif_start_queue(netdev);
1249
1250 if (test_bit(JME_FLAG_POLL, &jme->flags))
1251 jme_interrupt_mode(jme);
1252
1253 jme_start_pcc_timer(jme);
1254 } else if (jme_pseudo_hotplug_enabled(jme)) {
1255 jme_start_shutdown_timer(jme);
1256 }
1257
1258 goto out_enable_tasklet;
1259
1260err_out_free_rx_resources:
1261 jme_free_rx_resources(jme);
1262out_enable_tasklet:
1263 tasklet_enable(&jme->txclean_task);
1264 tasklet_hi_enable(&jme->rxclean_task);
1265 tasklet_hi_enable(&jme->rxempty_task);
1266out:
1267 atomic_inc(&jme->link_changing);
1268}
1269
1270static void
1271jme_rx_clean_tasklet(unsigned long arg)
1272{
1273 struct jme_adapter *jme = (struct jme_adapter *)arg;
1274 struct dynpcc_info *dpi = &(jme->dpi);
1275
1276 jme_process_receive(jme, jme->rx_ring_size);
1277 ++(dpi->intr_cnt);
1278
1279}
1280
1281static int
1282jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1283{
1284 struct jme_adapter *jme = jme_napi_priv(holder);
1285 DECLARE_NETDEV
1286 int rest;
1287
1288 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1289
1290 while (atomic_read(&jme->rx_empty) > 0) {
1291 atomic_dec(&jme->rx_empty);
1292 ++(NET_STAT(jme).rx_dropped);
1293 jme_restart_rx_engine(jme);
1294 }
1295 atomic_inc(&jme->rx_empty);
1296
1297 if (rest) {
1298 JME_RX_COMPLETE(netdev, holder);
1299 jme_interrupt_mode(jme);
1300 }
1301
1302 JME_NAPI_WEIGHT_SET(budget, rest);
1303 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1304}
1305
1306static void
1307jme_rx_empty_tasklet(unsigned long arg)
1308{
1309 struct jme_adapter *jme = (struct jme_adapter *)arg;
1310
1311 if (unlikely(atomic_read(&jme->link_changing) != 1))
1312 return;
1313
1314 if (unlikely(!netif_carrier_ok(jme->dev)))
1315 return;
1316
1317 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1318
1319 jme_rx_clean_tasklet(arg);
1320
1321 while (atomic_read(&jme->rx_empty) > 0) {
1322 atomic_dec(&jme->rx_empty);
1323 ++(NET_STAT(jme).rx_dropped);
1324 jme_restart_rx_engine(jme);
1325 }
1326 atomic_inc(&jme->rx_empty);
1327}
1328
1329static void
1330jme_wake_queue_if_stopped(struct jme_adapter *jme)
1331{
1332 struct jme_ring *txring = &(jme->txring[0]);
1333
1334 smp_wmb();
1335 if (unlikely(netif_queue_stopped(jme->dev) &&
1336 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1337 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1338 netif_wake_queue(jme->dev);
1339 }
1340
1341}
1342
1343static void
1344jme_tx_clean_tasklet(unsigned long arg)
1345{
1346 struct jme_adapter *jme = (struct jme_adapter *)arg;
1347 struct jme_ring *txring = &(jme->txring[0]);
1348 struct txdesc *txdesc = txring->desc;
1349 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1350 int i, j, cnt = 0, max, err, mask;
1351
1352 tx_dbg(jme, "Into txclean\n");
1353
1354 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1355 goto out;
1356
1357 if (unlikely(atomic_read(&jme->link_changing) != 1))
1358 goto out;
1359
1360 if (unlikely(!netif_carrier_ok(jme->dev)))
1361 goto out;
1362
1363 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1364 mask = jme->tx_ring_mask;
1365
1366 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1367
1368 ctxbi = txbi + i;
1369
1370 if (likely(ctxbi->skb &&
1371 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1372
1373 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1374 i, ctxbi->nr_desc, jiffies);
1375
1376 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1377
1378 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1379 ttxbi = txbi + ((i + j) & (mask));
1380 txdesc[(i + j) & (mask)].dw[0] = 0;
1381
1382 pci_unmap_page(jme->pdev,
1383 ttxbi->mapping,
1384 ttxbi->len,
1385 PCI_DMA_TODEVICE);
1386
1387 ttxbi->mapping = 0;
1388 ttxbi->len = 0;
1389 }
1390
1391 dev_kfree_skb(ctxbi->skb);
1392
1393 cnt += ctxbi->nr_desc;
1394
1395 if (unlikely(err)) {
1396 ++(NET_STAT(jme).tx_carrier_errors);
1397 } else {
1398 ++(NET_STAT(jme).tx_packets);
1399 NET_STAT(jme).tx_bytes += ctxbi->len;
1400 }
1401
1402 ctxbi->skb = NULL;
1403 ctxbi->len = 0;
1404 ctxbi->start_xmit = 0;
1405
1406 } else {
1407 break;
1408 }
1409
1410 i = (i + ctxbi->nr_desc) & mask;
1411
1412 ctxbi->nr_desc = 0;
1413 }
1414
1415 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1416 atomic_set(&txring->next_to_clean, i);
1417 atomic_add(cnt, &txring->nr_free);
1418
1419 jme_wake_queue_if_stopped(jme);
1420
1421out:
1422 atomic_inc(&jme->tx_cleaning);
1423}
1424
1425static void
1426jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1427{
1428 /*
1429 * Disable interrupt
1430 */
1431 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1432
1433 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1434 /*
1435 * Link change event is critical
1436 * all other events are ignored
1437 */
1438 jwrite32(jme, JME_IEVE, intrstat);
1439 tasklet_schedule(&jme->linkch_task);
1440 goto out_reenable;
1441 }
1442
1443 if (intrstat & INTR_TMINTR) {
1444 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1445 tasklet_schedule(&jme->pcc_task);
1446 }
1447
1448 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1449 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1450 tasklet_schedule(&jme->txclean_task);
1451 }
1452
1453 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1454 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1455 INTR_PCCRX0 |
1456 INTR_RX0EMP)) |
1457 INTR_RX0);
1458 }
1459
1460 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1461 if (intrstat & INTR_RX0EMP)
1462 atomic_inc(&jme->rx_empty);
1463
1464 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1465 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1466 jme_polling_mode(jme);
1467 JME_RX_SCHEDULE(jme);
1468 }
1469 }
1470 } else {
1471 if (intrstat & INTR_RX0EMP) {
1472 atomic_inc(&jme->rx_empty);
1473 tasklet_hi_schedule(&jme->rxempty_task);
1474 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1475 tasklet_hi_schedule(&jme->rxclean_task);
1476 }
1477 }
1478
1479out_reenable:
1480 /*
1481 * Re-enable interrupt
1482 */
1483 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1484}
1485
1486#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1487static irqreturn_t
1488jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1489#else
1490static irqreturn_t
1491jme_intr(int irq, void *dev_id)
1492#endif
1493{
1494 struct net_device *netdev = dev_id;
1495 struct jme_adapter *jme = netdev_priv(netdev);
1496 u32 intrstat;
1497
1498 intrstat = jread32(jme, JME_IEVE);
1499
1500 /*
1501 * Check if it's really an interrupt for us
1502 */
1503 if (unlikely((intrstat & INTR_ENABLE) == 0))
1504 return IRQ_NONE;
1505
1506 /*
1507 * Check if the device still exist
1508 */
1509 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1510 return IRQ_NONE;
1511
1512 jme_intr_msi(jme, intrstat);
1513
1514 return IRQ_HANDLED;
1515}
1516
1517#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1518static irqreturn_t
1519jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1520#else
1521static irqreturn_t
1522jme_msi(int irq, void *dev_id)
1523#endif
1524{
1525 struct net_device *netdev = dev_id;
1526 struct jme_adapter *jme = netdev_priv(netdev);
1527 u32 intrstat;
1528
1529 intrstat = jread32(jme, JME_IEVE);
1530
1531 jme_intr_msi(jme, intrstat);
1532
1533 return IRQ_HANDLED;
1534}
1535
1536static void
1537jme_reset_link(struct jme_adapter *jme)
1538{
1539 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1540}
1541
1542static void
1543jme_restart_an(struct jme_adapter *jme)
1544{
1545 u32 bmcr;
1546
1547 spin_lock_bh(&jme->phy_lock);
1548 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1549 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1550 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1551 spin_unlock_bh(&jme->phy_lock);
1552}
1553
1554static int
1555jme_request_irq(struct jme_adapter *jme)
1556{
1557 int rc;
1558 struct net_device *netdev = jme->dev;
1559#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1560 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1561 int irq_flags = SA_SHIRQ;
1562#else
1563 irq_handler_t handler = jme_intr;
1564 int irq_flags = IRQF_SHARED;
1565#endif
1566
1567 if (!pci_enable_msi(jme->pdev)) {
1568 set_bit(JME_FLAG_MSI, &jme->flags);
1569 handler = jme_msi;
1570 irq_flags = 0;
1571 }
1572
1573 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1574 netdev);
1575 if (rc) {
1576 netdev_err(netdev,
1577 "Unable to request %s interrupt (return: %d)\n",
1578 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1579 rc);
1580
1581 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1582 pci_disable_msi(jme->pdev);
1583 clear_bit(JME_FLAG_MSI, &jme->flags);
1584 }
1585 } else {
1586 netdev->irq = jme->pdev->irq;
1587 }
1588
1589 return rc;
1590}
1591
1592static void
1593jme_free_irq(struct jme_adapter *jme)
1594{
1595 free_irq(jme->pdev->irq, jme->dev);
1596 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1597 pci_disable_msi(jme->pdev);
1598 clear_bit(JME_FLAG_MSI, &jme->flags);
1599 jme->dev->irq = jme->pdev->irq;
1600 }
1601}
1602
1603static int
1604jme_open(struct net_device *netdev)
1605{
1606 struct jme_adapter *jme = netdev_priv(netdev);
1607 int rc;
1608
1609 jme_clear_pm(jme);
1610 JME_NAPI_ENABLE(jme);
1611
1612 tasklet_enable(&jme->linkch_task);
1613 tasklet_enable(&jme->txclean_task);
1614 tasklet_hi_enable(&jme->rxclean_task);
1615 tasklet_hi_enable(&jme->rxempty_task);
1616
1617 rc = jme_request_irq(jme);
1618 if (rc)
1619 goto err_out;
1620
1621 jme_start_irq(jme);
1622
1623 if (test_bit(JME_FLAG_SSET, &jme->flags))
1624 jme_set_settings(netdev, &jme->old_ecmd);
1625 else
1626 jme_reset_phy_processor(jme);
1627
1628 jme_reset_link(jme);
1629
1630 return 0;
1631
1632err_out:
1633 netif_stop_queue(netdev);
1634 netif_carrier_off(netdev);
1635 return rc;
1636}
1637
1638#ifdef CONFIG_PM
1639static void
1640jme_set_100m_half(struct jme_adapter *jme)
1641{
1642 u32 bmcr, tmp;
1643
1644 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1645 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1646 BMCR_SPEED1000 | BMCR_FULLDPLX);
1647 tmp |= BMCR_SPEED100;
1648
1649 if (bmcr != tmp)
1650 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1651
1652 if (jme->fpgaver)
1653 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1654 else
1655 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1656}
1657
1658#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1659static void
1660jme_wait_link(struct jme_adapter *jme)
1661{
1662 u32 phylink, to = JME_WAIT_LINK_TIME;
1663
1664 mdelay(1000);
1665 phylink = jme_linkstat_from_phy(jme);
1666 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1667 mdelay(10);
1668 phylink = jme_linkstat_from_phy(jme);
1669 }
1670}
1671#endif
1672
1673static inline void
1674jme_phy_off(struct jme_adapter *jme)
1675{
1676 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1677}
1678
1679static int
1680jme_close(struct net_device *netdev)
1681{
1682 struct jme_adapter *jme = netdev_priv(netdev);
1683
1684 netif_stop_queue(netdev);
1685 netif_carrier_off(netdev);
1686
1687 jme_stop_irq(jme);
1688 jme_free_irq(jme);
1689
1690 JME_NAPI_DISABLE(jme);
1691
1692 tasklet_disable(&jme->linkch_task);
1693 tasklet_disable(&jme->txclean_task);
1694 tasklet_disable(&jme->rxclean_task);
1695 tasklet_disable(&jme->rxempty_task);
1696
1697 jme_reset_ghc_speed(jme);
1698 jme_disable_rx_engine(jme);
1699 jme_disable_tx_engine(jme);
1700 jme_reset_mac_processor(jme);
1701 jme_free_rx_resources(jme);
1702 jme_free_tx_resources(jme);
1703 jme->phylink = 0;
1704 jme_phy_off(jme);
1705
1706 return 0;
1707}
1708
1709static int
1710jme_alloc_txdesc(struct jme_adapter *jme,
1711 struct sk_buff *skb)
1712{
1713 struct jme_ring *txring = &(jme->txring[0]);
1714 int idx, nr_alloc, mask = jme->tx_ring_mask;
1715
1716 idx = txring->next_to_use;
1717 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1718
1719 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1720 return -1;
1721
1722 atomic_sub(nr_alloc, &txring->nr_free);
1723
1724 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1725
1726 return idx;
1727}
1728
1729static void
1730jme_fill_tx_map(struct pci_dev *pdev,
1731 struct txdesc *txdesc,
1732 struct jme_buffer_info *txbi,
1733 struct page *page,
1734 u32 page_offset,
1735 u32 len,
1736 u8 hidma)
1737{
1738 dma_addr_t dmaaddr;
1739
1740 dmaaddr = pci_map_page(pdev,
1741 page,
1742 page_offset,
1743 len,
1744 PCI_DMA_TODEVICE);
1745
1746 pci_dma_sync_single_for_device(pdev,
1747 dmaaddr,
1748 len,
1749 PCI_DMA_TODEVICE);
1750
1751 txdesc->dw[0] = 0;
1752 txdesc->dw[1] = 0;
1753 txdesc->desc2.flags = TXFLAG_OWN;
1754 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1755 txdesc->desc2.datalen = cpu_to_le16(len);
1756 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1757 txdesc->desc2.bufaddrl = cpu_to_le32(
1758 (__u64)dmaaddr & 0xFFFFFFFFUL);
1759
1760 txbi->mapping = dmaaddr;
1761 txbi->len = len;
1762}
1763
1764static void
1765jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1766{
1767 struct jme_ring *txring = &(jme->txring[0]);
1768 struct txdesc *txdesc = txring->desc, *ctxdesc;
1769 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1770 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1771 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1772 int mask = jme->tx_ring_mask;
1773 struct skb_frag_struct *frag;
1774 u32 len;
1775
1776 for (i = 0 ; i < nr_frags ; ++i) {
1777 frag = &skb_shinfo(skb)->frags[i];
1778 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1779 ctxbi = txbi + ((idx + i + 2) & (mask));
1780
1781 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1782 frag->page_offset, frag->size, hidma);
1783 }
1784
1785 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1786 ctxdesc = txdesc + ((idx + 1) & (mask));
1787 ctxbi = txbi + ((idx + 1) & (mask));
1788 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1789 offset_in_page(skb->data), len, hidma);
1790
1791}
1792
1793static int
1794jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1795{
1796 if (unlikely(
1797#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1798 skb_shinfo(skb)->tso_size
1799#else
1800 skb_shinfo(skb)->gso_size
1801#endif
1802 && skb_header_cloned(skb) &&
1803 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1804 dev_kfree_skb(skb);
1805 return -1;
1806 }
1807
1808 return 0;
1809}
1810
1811static int
1812jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1813{
1814#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1815 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1816#else
1817 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1818#endif
1819 if (*mss) {
1820 *flags |= TXFLAG_LSEN;
1821
1822 if (skb->protocol == htons(ETH_P_IP)) {
1823 struct iphdr *iph = ip_hdr(skb);
1824
1825 iph->check = 0;
1826 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1827 iph->daddr, 0,
1828 IPPROTO_TCP,
1829 0);
1830 } else {
1831 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1832
1833 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1834 &ip6h->daddr, 0,
1835 IPPROTO_TCP,
1836 0);
1837 }
1838
1839 return 0;
1840 }
1841
1842 return 1;
1843}
1844
1845static void
1846jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1847{
1848#ifdef CHECKSUM_PARTIAL
1849 if (skb->ip_summed == CHECKSUM_PARTIAL)
1850#else
1851 if (skb->ip_summed == CHECKSUM_HW)
1852#endif
1853 {
1854 u8 ip_proto;
1855
1856#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1857 if (skb->protocol == htons(ETH_P_IP))
1858 ip_proto = ip_hdr(skb)->protocol;
1859 else if (skb->protocol == htons(ETH_P_IPV6))
1860 ip_proto = ipv6_hdr(skb)->nexthdr;
1861 else
1862 ip_proto = 0;
1863#else
1864 switch (skb->protocol) {
1865 case htons(ETH_P_IP):
1866 ip_proto = ip_hdr(skb)->protocol;
1867 break;
1868 case htons(ETH_P_IPV6):
1869 ip_proto = ipv6_hdr(skb)->nexthdr;
1870 break;
1871 default:
1872 ip_proto = 0;
1873 break;
1874 }
1875#endif
1876
1877 switch (ip_proto) {
1878 case IPPROTO_TCP:
1879 *flags |= TXFLAG_TCPCS;
1880 break;
1881 case IPPROTO_UDP:
1882 *flags |= TXFLAG_UDPCS;
1883 break;
1884 default:
1885 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1886 break;
1887 }
1888 }
1889}
1890
1891static inline void
1892jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1893{
1894 if (vlan_tx_tag_present(skb)) {
1895 *flags |= TXFLAG_TAGON;
1896 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1897 }
1898}
1899
1900static int
1901jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1902{
1903 struct jme_ring *txring = &(jme->txring[0]);
1904 struct txdesc *txdesc;
1905 struct jme_buffer_info *txbi;
1906 u8 flags;
1907
1908 txdesc = (struct txdesc *)txring->desc + idx;
1909 txbi = txring->bufinf + idx;
1910
1911 txdesc->dw[0] = 0;
1912 txdesc->dw[1] = 0;
1913 txdesc->dw[2] = 0;
1914 txdesc->dw[3] = 0;
1915 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1916 /*
1917 * Set OWN bit at final.
1918 * When kernel transmit faster than NIC.
1919 * And NIC trying to send this descriptor before we tell
1920 * it to start sending this TX queue.
1921 * Other fields are already filled correctly.
1922 */
1923 wmb();
1924 flags = TXFLAG_OWN | TXFLAG_INT;
1925 /*
1926 * Set checksum flags while not tso
1927 */
1928 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1929 jme_tx_csum(jme, skb, &flags);
1930 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1931 jme_map_tx_skb(jme, skb, idx);
1932 txdesc->desc1.flags = flags;
1933 /*
1934 * Set tx buffer info after telling NIC to send
1935 * For better tx_clean timing
1936 */
1937 wmb();
1938 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1939 txbi->skb = skb;
1940 txbi->len = skb->len;
1941 txbi->start_xmit = jiffies;
1942 if (!txbi->start_xmit)
1943 txbi->start_xmit = (0UL-1);
1944
1945 return 0;
1946}
1947
1948static void
1949jme_stop_queue_if_full(struct jme_adapter *jme)
1950{
1951 struct jme_ring *txring = &(jme->txring[0]);
1952 struct jme_buffer_info *txbi = txring->bufinf;
1953 int idx = atomic_read(&txring->next_to_clean);
1954
1955 txbi += idx;
1956
1957 smp_wmb();
1958 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1959 netif_stop_queue(jme->dev);
1960 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1961 smp_wmb();
1962 if (atomic_read(&txring->nr_free)
1963 >= (jme->tx_wake_threshold)) {
1964 netif_wake_queue(jme->dev);
1965 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1966 }
1967 }
1968
1969 if (unlikely(txbi->start_xmit &&
1970 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1971 txbi->skb)) {
1972 netif_stop_queue(jme->dev);
1973 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
1974 }
1975}
1976
1977/*
1978 * This function is already protected by netif_tx_lock()
1979 */
1980
1981#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
1982static int
1983#else
1984static netdev_tx_t
1985#endif
1986jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1987{
1988 struct jme_adapter *jme = netdev_priv(netdev);
1989 int idx;
1990
1991 if (unlikely(jme_expand_header(jme, skb))) {
1992 ++(NET_STAT(jme).tx_dropped);
1993 return NETDEV_TX_OK;
1994 }
1995
1996 idx = jme_alloc_txdesc(jme, skb);
1997
1998 if (unlikely(idx < 0)) {
1999 netif_stop_queue(netdev);
2000 netif_err(jme, tx_err, jme->dev,
2001 "BUG! Tx ring full when queue awake!\n");
2002
2003 return NETDEV_TX_BUSY;
2004 }
2005
2006 jme_fill_tx_desc(jme, skb, idx);
2007
2008 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2009 TXCS_SELECT_QUEUE0 |
2010 TXCS_QUEUE0S |
2011 TXCS_ENABLE);
2012#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2013 netdev->trans_start = jiffies;
2014#endif
2015
2016 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2017 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2018 jme_stop_queue_if_full(jme);
2019
2020 return NETDEV_TX_OK;
2021}
2022
2023static int
2024jme_set_macaddr(struct net_device *netdev, void *p)
2025{
2026 struct jme_adapter *jme = netdev_priv(netdev);
2027 struct sockaddr *addr = p;
2028 u32 val;
2029
2030 if (netif_running(netdev))
2031 return -EBUSY;
2032
2033 spin_lock_bh(&jme->macaddr_lock);
2034 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2035
2036 val = (addr->sa_data[3] & 0xff) << 24 |
2037 (addr->sa_data[2] & 0xff) << 16 |
2038 (addr->sa_data[1] & 0xff) << 8 |
2039 (addr->sa_data[0] & 0xff);
2040 jwrite32(jme, JME_RXUMA_LO, val);
2041 val = (addr->sa_data[5] & 0xff) << 8 |
2042 (addr->sa_data[4] & 0xff);
2043 jwrite32(jme, JME_RXUMA_HI, val);
2044 spin_unlock_bh(&jme->macaddr_lock);
2045
2046 return 0;
2047}
2048
2049static void
2050jme_set_multi(struct net_device *netdev)
2051{
2052 struct jme_adapter *jme = netdev_priv(netdev);
2053 u32 mc_hash[2] = {};
2054#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2055 int i;
2056#endif
2057
2058 spin_lock_bh(&jme->rxmcs_lock);
2059
2060 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2061
2062 if (netdev->flags & IFF_PROMISC) {
2063 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2064 } else if (netdev->flags & IFF_ALLMULTI) {
2065 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2066 } else if (netdev->flags & IFF_MULTICAST) {
2067#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2068 struct dev_mc_list *mclist;
2069#else
2070 struct netdev_hw_addr *ha;
2071#endif
2072 int bit_nr;
2073
2074 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2075#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2076 for (i = 0, mclist = netdev->mc_list;
2077 mclist && i < netdev->mc_count;
2078 ++i, mclist = mclist->next) {
2079#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2080 netdev_for_each_mc_addr(mclist, netdev) {
2081#else
2082 netdev_for_each_mc_addr(ha, netdev) {
2083#endif
2084#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2085 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2086#else
2087 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2088#endif
2089 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2090 }
2091
2092 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2093 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2094 }
2095
2096 wmb();
2097 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2098
2099 spin_unlock_bh(&jme->rxmcs_lock);
2100}
2101
2102static int
2103jme_change_mtu(struct net_device *netdev, int new_mtu)
2104{
2105 struct jme_adapter *jme = netdev_priv(netdev);
2106
2107 if (new_mtu == jme->old_mtu)
2108 return 0;
2109
2110 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2111 ((new_mtu) < IPV6_MIN_MTU))
2112 return -EINVAL;
2113
2114 if (new_mtu > 4000) {
2115 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2116 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2117 jme_restart_rx_engine(jme);
2118 } else {
2119 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2120 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2121 jme_restart_rx_engine(jme);
2122 }
2123
2124 if (new_mtu > 1900) {
2125 netdev->features &= ~(NETIF_F_HW_CSUM |
2126 NETIF_F_TSO
2127#ifdef NETIF_F_TSO6
2128 | NETIF_F_TSO6
2129#endif
2130 );
2131 } else {
2132 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2133 netdev->features |= NETIF_F_HW_CSUM;
2134 if (test_bit(JME_FLAG_TSO, &jme->flags))
2135 netdev->features |= NETIF_F_TSO
2136#ifdef NETIF_F_TSO6
2137 | NETIF_F_TSO6
2138#endif
2139 ;
2140 }
2141
2142 netdev->mtu = new_mtu;
2143 jme_reset_link(jme);
2144
2145 return 0;
2146}
2147
2148static void
2149jme_tx_timeout(struct net_device *netdev)
2150{
2151 struct jme_adapter *jme = netdev_priv(netdev);
2152
2153 jme->phylink = 0;
2154 jme_reset_phy_processor(jme);
2155 if (test_bit(JME_FLAG_SSET, &jme->flags))
2156 jme_set_settings(netdev, &jme->old_ecmd);
2157
2158 /*
2159 * Force to Reset the link again
2160 */
2161 jme_reset_link(jme);
2162}
2163
2164static inline void jme_pause_rx(struct jme_adapter *jme)
2165{
2166 atomic_dec(&jme->link_changing);
2167
2168 jme_set_rx_pcc(jme, PCC_OFF);
2169 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2170 JME_NAPI_DISABLE(jme);
2171 } else {
2172 tasklet_disable(&jme->rxclean_task);
2173 tasklet_disable(&jme->rxempty_task);
2174 }
2175}
2176
2177static inline void jme_resume_rx(struct jme_adapter *jme)
2178{
2179 struct dynpcc_info *dpi = &(jme->dpi);
2180
2181 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2182 JME_NAPI_ENABLE(jme);
2183 } else {
2184 tasklet_hi_enable(&jme->rxclean_task);
2185 tasklet_hi_enable(&jme->rxempty_task);
2186 }
2187 dpi->cur = PCC_P1;
2188 dpi->attempt = PCC_P1;
2189 dpi->cnt = 0;
2190 jme_set_rx_pcc(jme, PCC_P1);
2191
2192 atomic_inc(&jme->link_changing);
2193}
2194
2195static void
2196jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2197{
2198 struct jme_adapter *jme = netdev_priv(netdev);
2199
2200 jme_pause_rx(jme);
2201 jme->vlgrp = grp;
2202 jme_resume_rx(jme);
2203}
2204
2205#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2206static void
2207jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2208{
2209 struct jme_adapter *jme = netdev_priv(netdev);
2210
2211 if(jme->vlgrp) {
2212 jme_pause_rx(jme);
2213#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2214 jme->vlgrp->vlan_devices[vid] = NULL;
2215#else
2216 vlan_group_set_device(jme->vlgrp, vid, NULL);
2217#endif
2218 jme_resume_rx(jme);
2219 }
2220}
2221#endif
2222
2223static void
2224jme_get_drvinfo(struct net_device *netdev,
2225 struct ethtool_drvinfo *info)
2226{
2227 struct jme_adapter *jme = netdev_priv(netdev);
2228
2229 strcpy(info->driver, DRV_NAME);
2230 strcpy(info->version, DRV_VERSION);
2231 strcpy(info->bus_info, pci_name(jme->pdev));
2232}
2233
2234static int
2235jme_get_regs_len(struct net_device *netdev)
2236{
2237 return JME_REG_LEN;
2238}
2239
2240static void
2241mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2242{
2243 int i;
2244
2245 for (i = 0 ; i < len ; i += 4)
2246 p[i >> 2] = jread32(jme, reg + i);
2247}
2248
2249static void
2250mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2251{
2252 int i;
2253 u16 *p16 = (u16 *)p;
2254
2255 for (i = 0 ; i < reg_nr ; ++i)
2256 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2257}
2258
2259static void
2260jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2261{
2262 struct jme_adapter *jme = netdev_priv(netdev);
2263 u32 *p32 = (u32 *)p;
2264
2265 memset(p, 0xFF, JME_REG_LEN);
2266
2267 regs->version = 1;
2268 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2269
2270 p32 += 0x100 >> 2;
2271 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2272
2273 p32 += 0x100 >> 2;
2274 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2275
2276 p32 += 0x100 >> 2;
2277 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2278
2279 p32 += 0x100 >> 2;
2280 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2281}
2282
2283static int
2284jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2285{
2286 struct jme_adapter *jme = netdev_priv(netdev);
2287
2288 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2289 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2290
2291 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2292 ecmd->use_adaptive_rx_coalesce = false;
2293 ecmd->rx_coalesce_usecs = 0;
2294 ecmd->rx_max_coalesced_frames = 0;
2295 return 0;
2296 }
2297
2298 ecmd->use_adaptive_rx_coalesce = true;
2299
2300 switch (jme->dpi.cur) {
2301 case PCC_P1:
2302 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2303 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2304 break;
2305 case PCC_P2:
2306 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2307 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2308 break;
2309 case PCC_P3:
2310 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2311 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2312 break;
2313 default:
2314 break;
2315 }
2316
2317 return 0;
2318}
2319
2320static int
2321jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2322{
2323 struct jme_adapter *jme = netdev_priv(netdev);
2324 struct dynpcc_info *dpi = &(jme->dpi);
2325
2326 if (netif_running(netdev))
2327 return -EBUSY;
2328
2329 if (ecmd->use_adaptive_rx_coalesce &&
2330 test_bit(JME_FLAG_POLL, &jme->flags)) {
2331 clear_bit(JME_FLAG_POLL, &jme->flags);
2332 jme->jme_rx = netif_rx;
2333 jme->jme_vlan_rx = vlan_hwaccel_rx;
2334 dpi->cur = PCC_P1;
2335 dpi->attempt = PCC_P1;
2336 dpi->cnt = 0;
2337 jme_set_rx_pcc(jme, PCC_P1);
2338 jme_interrupt_mode(jme);
2339 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2340 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2341 set_bit(JME_FLAG_POLL, &jme->flags);
2342 jme->jme_rx = netif_receive_skb;
2343 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2344 jme_interrupt_mode(jme);
2345 }
2346
2347 return 0;
2348}
2349
2350static void
2351jme_get_pauseparam(struct net_device *netdev,
2352 struct ethtool_pauseparam *ecmd)
2353{
2354 struct jme_adapter *jme = netdev_priv(netdev);
2355 u32 val;
2356
2357 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2358 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2359
2360 spin_lock_bh(&jme->phy_lock);
2361 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2362 spin_unlock_bh(&jme->phy_lock);
2363
2364 ecmd->autoneg =
2365 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2366}
2367
2368static int
2369jme_set_pauseparam(struct net_device *netdev,
2370 struct ethtool_pauseparam *ecmd)
2371{
2372 struct jme_adapter *jme = netdev_priv(netdev);
2373 u32 val;
2374
2375 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2376 (ecmd->tx_pause != 0)) {
2377
2378 if (ecmd->tx_pause)
2379 jme->reg_txpfc |= TXPFC_PF_EN;
2380 else
2381 jme->reg_txpfc &= ~TXPFC_PF_EN;
2382
2383 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2384 }
2385
2386 spin_lock_bh(&jme->rxmcs_lock);
2387 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2388 (ecmd->rx_pause != 0)) {
2389
2390 if (ecmd->rx_pause)
2391 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2392 else
2393 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2394
2395 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2396 }
2397 spin_unlock_bh(&jme->rxmcs_lock);
2398
2399 spin_lock_bh(&jme->phy_lock);
2400 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2401 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2402 (ecmd->autoneg != 0)) {
2403
2404 if (ecmd->autoneg)
2405 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2406 else
2407 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2408
2409 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2410 MII_ADVERTISE, val);
2411 }
2412 spin_unlock_bh(&jme->phy_lock);
2413
2414 return 0;
2415}
2416
2417static void
2418jme_get_wol(struct net_device *netdev,
2419 struct ethtool_wolinfo *wol)
2420{
2421 struct jme_adapter *jme = netdev_priv(netdev);
2422
2423 wol->supported = WAKE_MAGIC | WAKE_PHY;
2424
2425 wol->wolopts = 0;
2426
2427 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2428 wol->wolopts |= WAKE_PHY;
2429
2430 if (jme->reg_pmcs & PMCS_MFEN)
2431 wol->wolopts |= WAKE_MAGIC;
2432
2433}
2434
2435static int
2436jme_set_wol(struct net_device *netdev,
2437 struct ethtool_wolinfo *wol)
2438{
2439 struct jme_adapter *jme = netdev_priv(netdev);
2440
2441 if (wol->wolopts & (WAKE_MAGICSECURE |
2442 WAKE_UCAST |
2443 WAKE_MCAST |
2444 WAKE_BCAST |
2445 WAKE_ARP))
2446 return -EOPNOTSUPP;
2447
2448 jme->reg_pmcs = 0;
2449
2450 if (wol->wolopts & WAKE_PHY)
2451 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2452
2453 if (wol->wolopts & WAKE_MAGIC)
2454 jme->reg_pmcs |= PMCS_MFEN;
2455
2456 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2457
2458 return 0;
2459}
2460
2461static int
2462jme_get_settings(struct net_device *netdev,
2463 struct ethtool_cmd *ecmd)
2464{
2465 struct jme_adapter *jme = netdev_priv(netdev);
2466 int rc;
2467
2468 spin_lock_bh(&jme->phy_lock);
2469 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2470 spin_unlock_bh(&jme->phy_lock);
2471 return rc;
2472}
2473
2474static int
2475jme_set_settings(struct net_device *netdev,
2476 struct ethtool_cmd *ecmd)
2477{
2478 struct jme_adapter *jme = netdev_priv(netdev);
2479 int rc, fdc = 0;
2480
2481 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2482 return -EINVAL;
2483
2484 if (jme->mii_if.force_media &&
2485 ecmd->autoneg != AUTONEG_ENABLE &&
2486 (jme->mii_if.full_duplex != ecmd->duplex))
2487 fdc = 1;
2488
2489 spin_lock_bh(&jme->phy_lock);
2490 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2491 spin_unlock_bh(&jme->phy_lock);
2492
2493 if (!rc && fdc)
2494 jme_reset_link(jme);
2495
2496 if (!rc) {
2497 set_bit(JME_FLAG_SSET, &jme->flags);
2498 jme->old_ecmd = *ecmd;
2499 }
2500
2501 return rc;
2502}
2503
2504static u32
2505jme_get_link(struct net_device *netdev)
2506{
2507 struct jme_adapter *jme = netdev_priv(netdev);
2508 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2509}
2510
2511static u32
2512jme_get_msglevel(struct net_device *netdev)
2513{
2514 struct jme_adapter *jme = netdev_priv(netdev);
2515 return jme->msg_enable;
2516}
2517
2518static void
2519jme_set_msglevel(struct net_device *netdev, u32 value)
2520{
2521 struct jme_adapter *jme = netdev_priv(netdev);
2522 jme->msg_enable = value;
2523}
2524
2525static u32
2526jme_get_rx_csum(struct net_device *netdev)
2527{
2528 struct jme_adapter *jme = netdev_priv(netdev);
2529 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2530}
2531
2532static int
2533jme_set_rx_csum(struct net_device *netdev, u32 on)
2534{
2535 struct jme_adapter *jme = netdev_priv(netdev);
2536
2537 spin_lock_bh(&jme->rxmcs_lock);
2538 if (on)
2539 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2540 else
2541 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2542 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2543 spin_unlock_bh(&jme->rxmcs_lock);
2544
2545 return 0;
2546}
2547
2548static int
2549jme_set_tx_csum(struct net_device *netdev, u32 on)
2550{
2551 struct jme_adapter *jme = netdev_priv(netdev);
2552
2553 if (on) {
2554 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2555 if (netdev->mtu <= 1900)
2556 netdev->features |= NETIF_F_HW_CSUM;
2557 } else {
2558 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2559 netdev->features &= ~NETIF_F_HW_CSUM;
2560 }
2561
2562 return 0;
2563}
2564
2565static int
2566jme_set_tso(struct net_device *netdev, u32 on)
2567{
2568 struct jme_adapter *jme = netdev_priv(netdev);
2569
2570 if (on) {
2571 set_bit(JME_FLAG_TSO, &jme->flags);
2572 if (netdev->mtu <= 1900)
2573 netdev->features |= NETIF_F_TSO
2574#ifdef NETIF_F_TSO6
2575 | NETIF_F_TSO6
2576#endif
2577 ;
2578 } else {
2579 clear_bit(JME_FLAG_TSO, &jme->flags);
2580 netdev->features &= ~(NETIF_F_TSO
2581#ifdef NETIF_F_TSO6
2582 | NETIF_F_TSO6
2583#endif
2584 );
2585 }
2586
2587 return 0;
2588}
2589
2590static int
2591jme_nway_reset(struct net_device *netdev)
2592{
2593 struct jme_adapter *jme = netdev_priv(netdev);
2594 jme_restart_an(jme);
2595 return 0;
2596}
2597
2598static u8
2599jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2600{
2601 u32 val;
2602 int to;
2603
2604 val = jread32(jme, JME_SMBCSR);
2605 to = JME_SMB_BUSY_TIMEOUT;
2606 while ((val & SMBCSR_BUSY) && --to) {
2607 msleep(1);
2608 val = jread32(jme, JME_SMBCSR);
2609 }
2610 if (!to) {
2611 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2612 return 0xFF;
2613 }
2614
2615 jwrite32(jme, JME_SMBINTF,
2616 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2617 SMBINTF_HWRWN_READ |
2618 SMBINTF_HWCMD);
2619
2620 val = jread32(jme, JME_SMBINTF);
2621 to = JME_SMB_BUSY_TIMEOUT;
2622 while ((val & SMBINTF_HWCMD) && --to) {
2623 msleep(1);
2624 val = jread32(jme, JME_SMBINTF);
2625 }
2626 if (!to) {
2627 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2628 return 0xFF;
2629 }
2630
2631 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2632}
2633
2634static void
2635jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2636{
2637 u32 val;
2638 int to;
2639
2640 val = jread32(jme, JME_SMBCSR);
2641 to = JME_SMB_BUSY_TIMEOUT;
2642 while ((val & SMBCSR_BUSY) && --to) {
2643 msleep(1);
2644 val = jread32(jme, JME_SMBCSR);
2645 }
2646 if (!to) {
2647 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2648 return;
2649 }
2650
2651 jwrite32(jme, JME_SMBINTF,
2652 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2653 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2654 SMBINTF_HWRWN_WRITE |
2655 SMBINTF_HWCMD);
2656
2657 val = jread32(jme, JME_SMBINTF);
2658 to = JME_SMB_BUSY_TIMEOUT;
2659 while ((val & SMBINTF_HWCMD) && --to) {
2660 msleep(1);
2661 val = jread32(jme, JME_SMBINTF);
2662 }
2663 if (!to) {
2664 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2665 return;
2666 }
2667
2668 mdelay(2);
2669}
2670
2671static int
2672jme_get_eeprom_len(struct net_device *netdev)
2673{
2674 struct jme_adapter *jme = netdev_priv(netdev);
2675 u32 val;
2676 val = jread32(jme, JME_SMBCSR);
2677 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2678}
2679
2680static int
2681jme_get_eeprom(struct net_device *netdev,
2682 struct ethtool_eeprom *eeprom, u8 *data)
2683{
2684 struct jme_adapter *jme = netdev_priv(netdev);
2685 int i, offset = eeprom->offset, len = eeprom->len;
2686
2687 /*
2688 * ethtool will check the boundary for us
2689 */
2690 eeprom->magic = JME_EEPROM_MAGIC;
2691 for (i = 0 ; i < len ; ++i)
2692 data[i] = jme_smb_read(jme, i + offset);
2693
2694 return 0;
2695}
2696
2697static int
2698jme_set_eeprom(struct net_device *netdev,
2699 struct ethtool_eeprom *eeprom, u8 *data)
2700{
2701 struct jme_adapter *jme = netdev_priv(netdev);
2702 int i, offset = eeprom->offset, len = eeprom->len;
2703
2704 if (eeprom->magic != JME_EEPROM_MAGIC)
2705 return -EINVAL;
2706
2707 /*
2708 * ethtool will check the boundary for us
2709 */
2710 for (i = 0 ; i < len ; ++i)
2711 jme_smb_write(jme, i + offset, data[i]);
2712
2713 return 0;
2714}
2715
2716#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2717static struct ethtool_ops jme_ethtool_ops = {
2718#else
2719static const struct ethtool_ops jme_ethtool_ops = {
2720#endif
2721 .get_drvinfo = jme_get_drvinfo,
2722 .get_regs_len = jme_get_regs_len,
2723 .get_regs = jme_get_regs,
2724 .get_coalesce = jme_get_coalesce,
2725 .set_coalesce = jme_set_coalesce,
2726 .get_pauseparam = jme_get_pauseparam,
2727 .set_pauseparam = jme_set_pauseparam,
2728 .get_wol = jme_get_wol,
2729 .set_wol = jme_set_wol,
2730 .get_settings = jme_get_settings,
2731 .set_settings = jme_set_settings,
2732 .get_link = jme_get_link,
2733 .get_msglevel = jme_get_msglevel,
2734 .set_msglevel = jme_set_msglevel,
2735 .get_rx_csum = jme_get_rx_csum,
2736 .set_rx_csum = jme_set_rx_csum,
2737 .set_tx_csum = jme_set_tx_csum,
2738 .set_tso = jme_set_tso,
2739 .set_sg = ethtool_op_set_sg,
2740 .nway_reset = jme_nway_reset,
2741 .get_eeprom_len = jme_get_eeprom_len,
2742 .get_eeprom = jme_get_eeprom,
2743 .set_eeprom = jme_set_eeprom,
2744};
2745
2746static int
2747jme_pci_dma64(struct pci_dev *pdev)
2748{
2749 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2750#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2751 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2752#else
2753 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2754#endif
2755 )
2756#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2757 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2758#else
2759 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2760#endif
2761 return 1;
2762
2763 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2764#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2765 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2766#else
2767 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2768#endif
2769 )
2770#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2771 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2772#else
2773 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2774#endif
2775 return 1;
2776
2777#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2778 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2779 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2780#else
2781 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2782 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2783#endif
2784 return 0;
2785
2786 return -1;
2787}
2788
2789static inline void
2790jme_phy_init(struct jme_adapter *jme)
2791{
2792 u16 reg26;
2793
2794 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2795 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2796}
2797
2798static inline void
2799jme_check_hw_ver(struct jme_adapter *jme)
2800{
2801 u32 chipmode;
2802
2803 chipmode = jread32(jme, JME_CHIPMODE);
2804
2805 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2806 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2807}
2808
2809#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2810static const struct net_device_ops jme_netdev_ops = {
2811 .ndo_open = jme_open,
2812 .ndo_stop = jme_close,
2813 .ndo_validate_addr = eth_validate_addr,
2814 .ndo_start_xmit = jme_start_xmit,
2815 .ndo_set_mac_address = jme_set_macaddr,
2816 .ndo_set_multicast_list = jme_set_multi,
2817 .ndo_change_mtu = jme_change_mtu,
2818 .ndo_tx_timeout = jme_tx_timeout,
2819 .ndo_vlan_rx_register = jme_vlan_rx_register,
2820};
2821#endif
2822
2823static int __devinit
2824jme_init_one(struct pci_dev *pdev,
2825 const struct pci_device_id *ent)
2826{
2827 int rc = 0, using_dac, i;
2828 struct net_device *netdev;
2829 struct jme_adapter *jme;
2830 u16 bmcr, bmsr;
2831 u32 apmc;
2832
2833 /*
2834 * set up PCI device basics
2835 */
2836 rc = pci_enable_device(pdev);
2837 if (rc) {
2838 pr_err("Cannot enable PCI device\n");
2839 goto err_out;
2840 }
2841
2842 using_dac = jme_pci_dma64(pdev);
2843 if (using_dac < 0) {
2844 pr_err("Cannot set PCI DMA Mask\n");
2845 rc = -EIO;
2846 goto err_out_disable_pdev;
2847 }
2848
2849 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2850 pr_err("No PCI resource region found\n");
2851 rc = -ENOMEM;
2852 goto err_out_disable_pdev;
2853 }
2854
2855 rc = pci_request_regions(pdev, DRV_NAME);
2856 if (rc) {
2857 pr_err("Cannot obtain PCI resource region\n");
2858 goto err_out_disable_pdev;
2859 }
2860
2861 pci_set_master(pdev);
2862
2863 /*
2864 * alloc and init net device
2865 */
2866 netdev = alloc_etherdev(sizeof(*jme));
2867 if (!netdev) {
2868 pr_err("Cannot allocate netdev structure\n");
2869 rc = -ENOMEM;
2870 goto err_out_release_regions;
2871 }
2872#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2873 netdev->netdev_ops = &jme_netdev_ops;
2874#else
2875 netdev->open = jme_open;
2876 netdev->stop = jme_close;
2877 netdev->hard_start_xmit = jme_start_xmit;
2878 netdev->set_mac_address = jme_set_macaddr;
2879 netdev->set_multicast_list = jme_set_multi;
2880 netdev->change_mtu = jme_change_mtu;
2881 netdev->tx_timeout = jme_tx_timeout;
2882 netdev->vlan_rx_register = jme_vlan_rx_register;
2883#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2884 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
2885#endif
2886 NETDEV_GET_STATS(netdev, &jme_get_stats);
2887#endif
2888 netdev->ethtool_ops = &jme_ethtool_ops;
2889 netdev->watchdog_timeo = TX_TIMEOUT;
2890 netdev->features = NETIF_F_HW_CSUM |
2891 NETIF_F_SG |
2892 NETIF_F_TSO |
2893#ifdef NETIF_F_TSO6
2894 NETIF_F_TSO6 |
2895#endif
2896 NETIF_F_HW_VLAN_TX |
2897 NETIF_F_HW_VLAN_RX;
2898 if (using_dac)
2899 netdev->features |= NETIF_F_HIGHDMA;
2900
2901 SET_NETDEV_DEV(netdev, &pdev->dev);
2902 pci_set_drvdata(pdev, netdev);
2903
2904 /*
2905 * init adapter info
2906 */
2907 jme = netdev_priv(netdev);
2908 jme->pdev = pdev;
2909 jme->dev = netdev;
2910 jme->jme_rx = netif_rx;
2911 jme->jme_vlan_rx = vlan_hwaccel_rx;
2912 jme->old_mtu = netdev->mtu = 1500;
2913 jme->phylink = 0;
2914 jme->tx_ring_size = 1 << 10;
2915 jme->tx_ring_mask = jme->tx_ring_size - 1;
2916 jme->tx_wake_threshold = 1 << 9;
2917 jme->rx_ring_size = 1 << 9;
2918 jme->rx_ring_mask = jme->rx_ring_size - 1;
2919 jme->msg_enable = JME_DEF_MSG_ENABLE;
2920 jme->regs = ioremap(pci_resource_start(pdev, 0),
2921 pci_resource_len(pdev, 0));
2922 if (!(jme->regs)) {
2923 pr_err("Mapping PCI resource region error\n");
2924 rc = -ENOMEM;
2925 goto err_out_free_netdev;
2926 }
2927
2928 if (no_pseudohp) {
2929 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2930 jwrite32(jme, JME_APMC, apmc);
2931 } else if (force_pseudohp) {
2932 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2933 jwrite32(jme, JME_APMC, apmc);
2934 }
2935
2936 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2937
2938 spin_lock_init(&jme->phy_lock);
2939 spin_lock_init(&jme->macaddr_lock);
2940 spin_lock_init(&jme->rxmcs_lock);
2941
2942 atomic_set(&jme->link_changing, 1);
2943 atomic_set(&jme->rx_cleaning, 1);
2944 atomic_set(&jme->tx_cleaning, 1);
2945 atomic_set(&jme->rx_empty, 1);
2946
2947 tasklet_init(&jme->pcc_task,
2948 jme_pcc_tasklet,
2949 (unsigned long) jme);
2950 tasklet_init(&jme->linkch_task,
2951 jme_link_change_tasklet,
2952 (unsigned long) jme);
2953 tasklet_init(&jme->txclean_task,
2954 jme_tx_clean_tasklet,
2955 (unsigned long) jme);
2956 tasklet_init(&jme->rxclean_task,
2957 jme_rx_clean_tasklet,
2958 (unsigned long) jme);
2959 tasklet_init(&jme->rxempty_task,
2960 jme_rx_empty_tasklet,
2961 (unsigned long) jme);
2962 tasklet_disable_nosync(&jme->linkch_task);
2963 tasklet_disable_nosync(&jme->txclean_task);
2964 tasklet_disable_nosync(&jme->rxclean_task);
2965 tasklet_disable_nosync(&jme->rxempty_task);
2966 jme->dpi.cur = PCC_P1;
2967
2968 jme->reg_ghc = 0;
2969 jme->reg_rxcs = RXCS_DEFAULT;
2970 jme->reg_rxmcs = RXMCS_DEFAULT;
2971 jme->reg_txpfc = 0;
2972 jme->reg_pmcs = PMCS_MFEN;
2973 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2974 set_bit(JME_FLAG_TSO, &jme->flags);
2975
2976 /*
2977 * Get Max Read Req Size from PCI Config Space
2978 */
2979 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2980 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2981 switch (jme->mrrs) {
2982 case MRRS_128B:
2983 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2984 break;
2985 case MRRS_256B:
2986 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2987 break;
2988 default:
2989 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2990 break;
2991 }
2992
2993 /*
2994 * Must check before reset_mac_processor
2995 */
2996 jme_check_hw_ver(jme);
2997 jme->mii_if.dev = netdev;
2998 if (jme->fpgaver) {
2999 jme->mii_if.phy_id = 0;
3000 for (i = 1 ; i < 32 ; ++i) {
3001 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3002 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3003 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3004 jme->mii_if.phy_id = i;
3005 break;
3006 }
3007 }
3008
3009 if (!jme->mii_if.phy_id) {
3010 rc = -EIO;
3011 pr_err("Can not find phy_id\n");
3012 goto err_out_unmap;
3013 }
3014
3015 jme->reg_ghc |= GHC_LINK_POLL;
3016 } else {
3017 jme->mii_if.phy_id = 1;
3018 }
3019 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3020 jme->mii_if.supports_gmii = true;
3021 else
3022 jme->mii_if.supports_gmii = false;
3023 jme->mii_if.mdio_read = jme_mdio_read;
3024 jme->mii_if.mdio_write = jme_mdio_write;
3025
3026 jme_clear_pm(jme);
3027 jme_set_phyfifoa(jme);
3028 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
3029 if (!jme->fpgaver)
3030 jme_phy_init(jme);
3031 jme_phy_off(jme);
3032
3033 /*
3034 * Reset MAC processor and reload EEPROM for MAC Address
3035 */
3036 jme_reset_mac_processor(jme);
3037 rc = jme_reload_eeprom(jme);
3038 if (rc) {
3039 pr_err("Reload eeprom for reading MAC Address error\n");
3040 goto err_out_unmap;
3041 }
3042 jme_load_macaddr(netdev);
3043
3044 /*
3045 * Tell stack that we are not ready to work until open()
3046 */
3047 netif_carrier_off(netdev);
3048 netif_stop_queue(netdev);
3049
3050 /*
3051 * Register netdev
3052 */
3053 rc = register_netdev(netdev);
3054 if (rc) {
3055 pr_err("Cannot register net device\n");
3056 goto err_out_unmap;
3057 }
3058
3059 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x "
3060 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3061 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3062 "JMC250 Gigabit Ethernet" :
3063 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3064 "JMC260 Fast Ethernet" : "Unknown",
3065 (jme->fpgaver != 0) ? " (FPGA)" : "",
3066 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3067 jme->rev,
3068 netdev->dev_addr[0],
3069 netdev->dev_addr[1],
3070 netdev->dev_addr[2],
3071 netdev->dev_addr[3],
3072 netdev->dev_addr[4],
3073 netdev->dev_addr[5]);
3074
3075 return 0;
3076
3077err_out_unmap:
3078 iounmap(jme->regs);
3079err_out_free_netdev:
3080 pci_set_drvdata(pdev, NULL);
3081 free_netdev(netdev);
3082err_out_release_regions:
3083 pci_release_regions(pdev);
3084err_out_disable_pdev:
3085 pci_disable_device(pdev);
3086err_out:
3087 return rc;
3088}
3089
3090static void __devexit
3091jme_remove_one(struct pci_dev *pdev)
3092{
3093 struct net_device *netdev = pci_get_drvdata(pdev);
3094 struct jme_adapter *jme = netdev_priv(netdev);
3095
3096 unregister_netdev(netdev);
3097 iounmap(jme->regs);
3098 pci_set_drvdata(pdev, NULL);
3099 free_netdev(netdev);
3100 pci_release_regions(pdev);
3101 pci_disable_device(pdev);
3102
3103}
3104
3105#ifdef CONFIG_PM
3106static int
3107jme_suspend(struct pci_dev *pdev, pm_message_t state)
3108{
3109 struct net_device *netdev = pci_get_drvdata(pdev);
3110 struct jme_adapter *jme = netdev_priv(netdev);
3111
3112 atomic_dec(&jme->link_changing);
3113
3114 netif_device_detach(netdev);
3115 netif_stop_queue(netdev);
3116 jme_stop_irq(jme);
3117
3118 tasklet_disable(&jme->txclean_task);
3119 tasklet_disable(&jme->rxclean_task);
3120 tasklet_disable(&jme->rxempty_task);
3121
3122 if (netif_carrier_ok(netdev)) {
3123 if (test_bit(JME_FLAG_POLL, &jme->flags))
3124 jme_polling_mode(jme);
3125
3126 jme_stop_pcc_timer(jme);
3127 jme_reset_ghc_speed(jme);
3128 jme_disable_rx_engine(jme);
3129 jme_disable_tx_engine(jme);
3130 jme_reset_mac_processor(jme);
3131 jme_free_rx_resources(jme);
3132 jme_free_tx_resources(jme);
3133 netif_carrier_off(netdev);
3134 jme->phylink = 0;
3135 }
3136
3137 tasklet_enable(&jme->txclean_task);
3138 tasklet_hi_enable(&jme->rxclean_task);
3139 tasklet_hi_enable(&jme->rxempty_task);
3140
3141 pci_save_state(pdev);
3142 if (jme->reg_pmcs) {
3143 jme_set_100m_half(jme);
3144
3145 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3146 jme_wait_link(jme);
3147
3148 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3149
3150 pci_enable_wake(pdev, PCI_D3cold, true);
3151 } else {
3152 jme_phy_off(jme);
3153 }
3154 pci_set_power_state(pdev, PCI_D3cold);
3155
3156 return 0;
3157}
3158
3159static int
3160jme_resume(struct pci_dev *pdev)
3161{
3162 struct net_device *netdev = pci_get_drvdata(pdev);
3163 struct jme_adapter *jme = netdev_priv(netdev);
3164
3165 jme_clear_pm(jme);
3166 pci_restore_state(pdev);
3167
3168 if (test_bit(JME_FLAG_SSET, &jme->flags))
3169 jme_set_settings(netdev, &jme->old_ecmd);
3170 else
3171 jme_reset_phy_processor(jme);
3172
3173 jme_start_irq(jme);
3174 netif_device_attach(netdev);
3175
3176 atomic_inc(&jme->link_changing);
3177
3178 jme_reset_link(jme);
3179
3180 return 0;
3181}
3182#endif
3183
3184#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3185static struct pci_device_id jme_pci_tbl[] = {
3186#else
3187static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3188#endif
3189 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3190 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3191 { }
3192};
3193
3194static struct pci_driver jme_driver = {
3195 .name = DRV_NAME,
3196 .id_table = jme_pci_tbl,
3197 .probe = jme_init_one,
3198 .remove = __devexit_p(jme_remove_one),
3199#ifdef CONFIG_PM
3200 .suspend = jme_suspend,
3201 .resume = jme_resume,
3202#endif /* CONFIG_PM */
3203};
3204
3205static int __init
3206jme_init_module(void)
3207{
3208 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3209 return pci_register_driver(&jme_driver);
3210}
3211
3212static void __exit
3213jme_cleanup_module(void)
3214{
3215 pci_unregister_driver(&jme_driver);
3216}
3217
3218module_init(jme_init_module);
3219module_exit(jme_cleanup_module);
3220
3221MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3222MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3223MODULE_LICENSE("GPL");
3224MODULE_VERSION(DRV_VERSION);
3225MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3226
JMicron Ethernet Linux driver