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jme: convert offload constraints to ndo_fix_features
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/version.h>
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
38#include <linux/delay.h>
39#include <linux/spinlock.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/if_vlan.h>
46#include <linux/slab.h>
47#include <net/ip6_checksum.h>
48#include "jme.h"
49
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
61
62#ifndef JME_NEW_PM_API
63static void
64jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65{
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71#else
72 pci_pme_active(jme->pdev, enable);
73#endif
74}
75#endif
76
77static int
78jme_mdio_read(struct net_device *netdev, int phy, int reg)
79{
80 struct jme_adapter *jme = netdev_priv(netdev);
81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
82
83read_again:
84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
85 smi_phy_addr(phy) |
86 smi_reg_addr(reg));
87
88 wmb();
89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
90 udelay(20);
91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
93 break;
94 }
95
96 if (i == 0) {
97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
98 return 0;
99 }
100
101 if (again--)
102 goto read_again;
103
104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
105}
106
107static void
108jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
110{
111 struct jme_adapter *jme = netdev_priv(netdev);
112 int i;
113
114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
117
118 wmb();
119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
120 udelay(20);
121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
122 break;
123 }
124
125 if (i == 0)
126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
127}
128
129static inline void
130jme_reset_phy_processor(struct jme_adapter *jme)
131{
132 u32 val;
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
138
139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
142 MII_CTRL1000,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
144
145 val = jme_mdio_read(jme->dev,
146 jme->mii_if.phy_id,
147 MII_BMCR);
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_BMCR, val | BMCR_RESET);
152}
153
154static void
155jme_setup_wakeup_frame(struct jme_adapter *jme,
156 const u32 *mask, u32 crc, int fnr)
157{
158 int i;
159
160 /*
161 * Setup CRC pattern
162 */
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
164 wmb();
165 jwrite32(jme, JME_WFODP, crc);
166 wmb();
167
168 /*
169 * Setup Mask
170 */
171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
175 wmb();
176 jwrite32(jme, JME_WFODP, mask[i]);
177 wmb();
178 }
179}
180
181static inline void
182jme_mac_rxclk_off(struct jme_adapter *jme)
183{
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
186}
187
188static inline void
189jme_mac_rxclk_on(struct jme_adapter *jme)
190{
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
193}
194
195static inline void
196jme_mac_txclk_off(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_mac_txclk_on(struct jme_adapter *jme)
204{
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
208 else
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
211}
212
213static inline void
214jme_reset_ghc_speed(struct jme_adapter *jme)
215{
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_reset_250A2_workaround(struct jme_adapter *jme)
222{
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
224 GPREG1_RSSPATCH);
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
226}
227
228static inline void
229jme_assert_ghc_reset(struct jme_adapter *jme)
230{
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_clear_ghc_reset(struct jme_adapter *jme)
237{
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
240}
241
242static inline void
243jme_reset_mac_processor(struct jme_adapter *jme)
244{
245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
246 u32 crc = 0xCDCDCDCD;
247 u32 gpreg0;
248 int i;
249
250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
252
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
255 udelay(1);
256 jme_assert_ghc_reset(jme);
257 udelay(1);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
260 udelay(1);
261 jme_clear_ghc_reset(jme);
262 udelay(1);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
265 udelay(1);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
268
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
277
278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
281 jme_setup_wakeup_frame(jme, mask, crc, i);
282 if (jme->fpgaver)
283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
284 else
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
287}
288
289static inline void
290jme_clear_pm(struct jme_adapter *jme)
291{
292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
293}
294
295static int
296jme_reload_eeprom(struct jme_adapter *jme)
297{
298 u32 val;
299 int i;
300
301 val = jread32(jme, JME_SMBCSR);
302
303 if (val & SMBCSR_EEPROMD) {
304 val |= SMBCSR_CNACK;
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
308 mdelay(12);
309
310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
311 mdelay(1);
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
313 break;
314 }
315
316 if (i == 0) {
317 pr_err("eeprom reload timeout\n");
318 return -EIO;
319 }
320 }
321
322 return 0;
323}
324
325static void
326jme_load_macaddr(struct net_device *netdev)
327{
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
330 u32 val;
331
332 spin_lock_bh(&jme->macaddr_lock);
333 val = jread32(jme, JME_RXUMA_LO);
334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
338 val = jread32(jme, JME_RXUMA_HI);
339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
343}
344
345static inline void
346jme_set_rx_pcc(struct jme_adapter *jme, int p)
347{
348 switch (p) {
349 case PCC_OFF:
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 break;
354 case PCC_P1:
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 break;
359 case PCC_P2:
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 break;
364 case PCC_P3:
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
368 break;
369 default:
370 break;
371 }
372 wmb();
373
374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
376}
377
378static void
379jme_start_irq(struct jme_adapter *jme)
380{
381 register struct dynpcc_info *dpi = &(jme->dpi);
382
383 jme_set_rx_pcc(jme, PCC_P1);
384 dpi->cur = PCC_P1;
385 dpi->attempt = PCC_P1;
386 dpi->cnt = 0;
387
388 jwrite32(jme, JME_PCCTX,
389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
391 PCCTXQ0_EN
392 );
393
394 /*
395 * Enable Interrupts
396 */
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
398}
399
400static inline void
401jme_stop_irq(struct jme_adapter *jme)
402{
403 /*
404 * Disable Interrupts
405 */
406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
407}
408
409static u32
410jme_linkstat_from_phy(struct jme_adapter *jme)
411{
412 u32 phylink, bmsr;
413
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
416 if (bmsr & BMSR_ANCOMP)
417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
418
419 return phylink;
420}
421
422static inline void
423jme_set_phyfifo_5level(struct jme_adapter *jme)
424{
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
426}
427
428static inline void
429jme_set_phyfifo_8level(struct jme_adapter *jme)
430{
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
432}
433
434static int
435jme_check_link(struct net_device *netdev, int testonly)
436{
437 struct jme_adapter *jme = netdev_priv(netdev);
438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
439 char linkmsg[64];
440 int rc = 0;
441
442 linkmsg[0] = '\0';
443
444 if (jme->fpgaver)
445 phylink = jme_linkstat_from_phy(jme);
446 else
447 phylink = jread32(jme, JME_PHY_LINK);
448
449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
451 /*
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
454 */
455 phylink = PHY_LINK_UP;
456
457 bmcr = jme_mdio_read(jme->dev,
458 jme->mii_if.phy_id,
459 MII_BMCR);
460
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
466 PHY_LINK_SPEED_10M;
467
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 PHY_LINK_DUPLEX : 0;
470
471 strcat(linkmsg, "Forced: ");
472 } else {
473 /*
474 * Keep polling for speed/duplex resolve complete
475 */
476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
477 --cnt) {
478
479 udelay(1);
480
481 if (jme->fpgaver)
482 phylink = jme_linkstat_from_phy(jme);
483 else
484 phylink = jread32(jme, JME_PHY_LINK);
485 }
486 if (!cnt)
487 pr_err("Waiting speed resolve timeout\n");
488
489 strcat(linkmsg, "ANed: ");
490 }
491
492 if (jme->phylink == phylink) {
493 rc = 1;
494 goto out;
495 }
496 if (testonly)
497 goto out;
498
499 jme->phylink = phylink;
500
501 /*
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
504 */
505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
507 jme->reg_ghc |= GHC_SPEED_10M;
508 strcat(linkmsg, "10 Mbps, ");
509 break;
510 case PHY_LINK_SPEED_100M:
511 jme->reg_ghc |= GHC_SPEED_100M;
512 strcat(linkmsg, "100 Mbps, ");
513 break;
514 case PHY_LINK_SPEED_1000M:
515 jme->reg_ghc |= GHC_SPEED_1000M;
516 strcat(linkmsg, "1000 Mbps, ");
517 break;
518 default:
519 break;
520 }
521
522 if (phylink & PHY_LINK_DUPLEX) {
523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
525 jme->reg_ghc |= GHC_DPX;
526 } else {
527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
528 TXMCS_BACKOFF |
529 TXMCS_CARRIERSENSE |
530 TXMCS_COLLISION);
531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
532 }
533
534 jwrite32(jme, JME_GHC, jme->reg_ghc);
535
536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
538 GPREG1_RSSPATCH);
539 if (!(phylink & PHY_LINK_DUPLEX))
540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
543 jme_set_phyfifo_8level(jme);
544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
545 break;
546 case PHY_LINK_SPEED_100M:
547 jme_set_phyfifo_5level(jme);
548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
549 break;
550 case PHY_LINK_SPEED_1000M:
551 jme_set_phyfifo_8level(jme);
552 break;
553 default:
554 break;
555 }
556 }
557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
558
559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 "Full-Duplex, " :
561 "Half-Duplex, ");
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 "MDI-X" :
564 "MDI");
565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
566 netif_carrier_on(netdev);
567 } else {
568 if (testonly)
569 goto out;
570
571 netif_info(jme, link, jme->dev, "Link is down\n");
572 jme->phylink = 0;
573 netif_carrier_off(netdev);
574 }
575
576out:
577 return rc;
578}
579
580static int
581jme_setup_tx_resources(struct jme_adapter *jme)
582{
583 struct jme_ring *txring = &(jme->txring[0]);
584
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
587 &(txring->dmaalloc),
588 GFP_ATOMIC);
589
590 if (!txring->alloc)
591 goto err_set_null;
592
593 /*
594 * 16 Bytes align
595 */
596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
597 RING_DESC_ALIGN);
598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
599 txring->next_to_use = 0;
600 atomic_set(&txring->next_to_clean, 0);
601 atomic_set(&txring->nr_free, jme->tx_ring_size);
602
603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
607
608 /*
609 * Initialize Transmit Descriptors
610 */
611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
612 memset(txring->bufinf, 0,
613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
614
615 return 0;
616
617err_free_txring:
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
620 txring->alloc,
621 txring->dmaalloc);
622
623err_set_null:
624 txring->desc = NULL;
625 txring->dmaalloc = 0;
626 txring->dma = 0;
627 txring->bufinf = NULL;
628
629 return -ENOMEM;
630}
631
632static void
633jme_free_tx_resources(struct jme_adapter *jme)
634{
635 int i;
636 struct jme_ring *txring = &(jme->txring[0]);
637 struct jme_buffer_info *txbi;
638
639 if (txring->alloc) {
640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
643 if (txbi->skb) {
644 dev_kfree_skb(txbi->skb);
645 txbi->skb = NULL;
646 }
647 txbi->mapping = 0;
648 txbi->len = 0;
649 txbi->nr_desc = 0;
650 txbi->start_xmit = 0;
651 }
652 kfree(txring->bufinf);
653 }
654
655 dma_free_coherent(&(jme->pdev->dev),
656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
657 txring->alloc,
658 txring->dmaalloc);
659
660 txring->alloc = NULL;
661 txring->desc = NULL;
662 txring->dmaalloc = 0;
663 txring->dma = 0;
664 txring->bufinf = NULL;
665 }
666 txring->next_to_use = 0;
667 atomic_set(&txring->next_to_clean, 0);
668 atomic_set(&txring->nr_free, 0);
669}
670
671static inline void
672jme_enable_tx_engine(struct jme_adapter *jme)
673{
674 /*
675 * Select Queue 0
676 */
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
678 wmb();
679
680 /*
681 * Setup TX Queue 0 DMA Bass Address
682 */
683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
686
687 /*
688 * Setup TX Descptor Count
689 */
690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
691
692 /*
693 * Enable TX Engine
694 */
695 wmb();
696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
699
700 /*
701 * Start clock for TX MAC Processor
702 */
703 jme_mac_txclk_on(jme);
704}
705
706static inline void
707jme_restart_tx_engine(struct jme_adapter *jme)
708{
709 /*
710 * Restart TX Engine
711 */
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
713 TXCS_SELECT_QUEUE0 |
714 TXCS_ENABLE);
715}
716
717static inline void
718jme_disable_tx_engine(struct jme_adapter *jme)
719{
720 int i;
721 u32 val;
722
723 /*
724 * Disable TX Engine
725 */
726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
727 wmb();
728
729 val = jread32(jme, JME_TXCS);
730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
731 mdelay(1);
732 val = jread32(jme, JME_TXCS);
733 rmb();
734 }
735
736 if (!i)
737 pr_err("Disable TX engine timeout\n");
738
739 /*
740 * Stop clock for TX MAC Processor
741 */
742 jme_mac_txclk_off(jme);
743}
744
745static void
746jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
747{
748 struct jme_ring *rxring = &(jme->rxring[0]);
749 register struct rxdesc *rxdesc = rxring->desc;
750 struct jme_buffer_info *rxbi = rxring->bufinf;
751 rxdesc += i;
752 rxbi += i;
753
754 rxdesc->dw[0] = 0;
755 rxdesc->dw[1] = 0;
756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
760 if (jme->dev->features & NETIF_F_HIGHDMA)
761 rxdesc->desc1.flags = RXFLAG_64BIT;
762 wmb();
763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
764}
765
766static int
767jme_make_new_rx_buf(struct jme_adapter *jme, int i)
768{
769 struct jme_ring *rxring = &(jme->rxring[0]);
770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
771 struct sk_buff *skb;
772 dma_addr_t mapping;
773
774 skb = netdev_alloc_skb(jme->dev,
775 jme->dev->mtu + RX_EXTRA_LEN);
776 if (unlikely(!skb))
777 return -ENOMEM;
778#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
779 skb->dev = jme->dev;
780#endif
781
782 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
783 offset_in_page(skb->data), skb_tailroom(skb),
784 PCI_DMA_FROMDEVICE);
785 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
786 dev_kfree_skb(skb);
787 return -ENOMEM;
788 }
789
790 if (likely(rxbi->mapping))
791 pci_unmap_page(jme->pdev, rxbi->mapping,
792 rxbi->len, PCI_DMA_FROMDEVICE);
793
794 rxbi->skb = skb;
795 rxbi->len = skb_tailroom(skb);
796 rxbi->mapping = mapping;
797 return 0;
798}
799
800static void
801jme_free_rx_buf(struct jme_adapter *jme, int i)
802{
803 struct jme_ring *rxring = &(jme->rxring[0]);
804 struct jme_buffer_info *rxbi = rxring->bufinf;
805 rxbi += i;
806
807 if (rxbi->skb) {
808 pci_unmap_page(jme->pdev,
809 rxbi->mapping,
810 rxbi->len,
811 PCI_DMA_FROMDEVICE);
812 dev_kfree_skb(rxbi->skb);
813 rxbi->skb = NULL;
814 rxbi->mapping = 0;
815 rxbi->len = 0;
816 }
817}
818
819static void
820jme_free_rx_resources(struct jme_adapter *jme)
821{
822 int i;
823 struct jme_ring *rxring = &(jme->rxring[0]);
824
825 if (rxring->alloc) {
826 if (rxring->bufinf) {
827 for (i = 0 ; i < jme->rx_ring_size ; ++i)
828 jme_free_rx_buf(jme, i);
829 kfree(rxring->bufinf);
830 }
831
832 dma_free_coherent(&(jme->pdev->dev),
833 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
834 rxring->alloc,
835 rxring->dmaalloc);
836 rxring->alloc = NULL;
837 rxring->desc = NULL;
838 rxring->dmaalloc = 0;
839 rxring->dma = 0;
840 rxring->bufinf = NULL;
841 }
842 rxring->next_to_use = 0;
843 atomic_set(&rxring->next_to_clean, 0);
844}
845
846static int
847jme_setup_rx_resources(struct jme_adapter *jme)
848{
849 int i;
850 struct jme_ring *rxring = &(jme->rxring[0]);
851
852 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
853 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
854 &(rxring->dmaalloc),
855 GFP_ATOMIC);
856 if (!rxring->alloc)
857 goto err_set_null;
858
859 /*
860 * 16 Bytes align
861 */
862 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
863 RING_DESC_ALIGN);
864 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
865 rxring->next_to_use = 0;
866 atomic_set(&rxring->next_to_clean, 0);
867
868 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
869 jme->rx_ring_size, GFP_ATOMIC);
870 if (unlikely(!(rxring->bufinf)))
871 goto err_free_rxring;
872
873 /*
874 * Initiallize Receive Descriptors
875 */
876 memset(rxring->bufinf, 0,
877 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
878 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
879 if (unlikely(jme_make_new_rx_buf(jme, i))) {
880 jme_free_rx_resources(jme);
881 return -ENOMEM;
882 }
883
884 jme_set_clean_rxdesc(jme, i);
885 }
886
887 return 0;
888
889err_free_rxring:
890 dma_free_coherent(&(jme->pdev->dev),
891 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
892 rxring->alloc,
893 rxring->dmaalloc);
894err_set_null:
895 rxring->desc = NULL;
896 rxring->dmaalloc = 0;
897 rxring->dma = 0;
898 rxring->bufinf = NULL;
899
900 return -ENOMEM;
901}
902
903static inline void
904jme_enable_rx_engine(struct jme_adapter *jme)
905{
906 /*
907 * Select Queue 0
908 */
909 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
910 RXCS_QUEUESEL_Q0);
911 wmb();
912
913 /*
914 * Setup RX DMA Bass Address
915 */
916 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
917 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
918 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
919
920 /*
921 * Setup RX Descriptor Count
922 */
923 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
924
925 /*
926 * Setup Unicast Filter
927 */
928 jme_set_unicastaddr(jme->dev);
929 jme_set_multi(jme->dev);
930
931 /*
932 * Enable RX Engine
933 */
934 wmb();
935 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
936 RXCS_QUEUESEL_Q0 |
937 RXCS_ENABLE |
938 RXCS_QST);
939
940 /*
941 * Start clock for RX MAC Processor
942 */
943 jme_mac_rxclk_on(jme);
944}
945
946static inline void
947jme_restart_rx_engine(struct jme_adapter *jme)
948{
949 /*
950 * Start RX Engine
951 */
952 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
953 RXCS_QUEUESEL_Q0 |
954 RXCS_ENABLE |
955 RXCS_QST);
956}
957
958static inline void
959jme_disable_rx_engine(struct jme_adapter *jme)
960{
961 int i;
962 u32 val;
963
964 /*
965 * Disable RX Engine
966 */
967 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
968 wmb();
969
970 val = jread32(jme, JME_RXCS);
971 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
972 mdelay(1);
973 val = jread32(jme, JME_RXCS);
974 rmb();
975 }
976
977 if (!i)
978 pr_err("Disable RX engine timeout\n");
979
980 /*
981 * Stop clock for RX MAC Processor
982 */
983 jme_mac_rxclk_off(jme);
984}
985
986static u16
987jme_udpsum(struct sk_buff *skb)
988{
989 u16 csum = 0xFFFFu;
990#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
991 struct iphdr *iph;
992 int iphlen;
993 struct udphdr *udph;
994#endif
995
996 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
997 return csum;
998 if (skb->protocol != htons(ETH_P_IP))
999 return csum;
1000#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1001 iph = (struct iphdr *)skb_pull(skb, ETH_HLEN);
1002 iphlen = (iph->ihl << 2);
1003 if ((iph->protocol != IPPROTO_UDP) ||
1004 (skb->len < (iphlen + sizeof(struct udphdr)))) {
1005 skb_push(skb, ETH_HLEN);
1006 return csum;
1007 }
1008 udph = (struct udphdr *)skb_pull(skb, iphlen);
1009 csum = udph->check;
1010 skb_push(skb, iphlen);
1011 skb_push(skb, ETH_HLEN);
1012#else
1013 skb_set_network_header(skb, ETH_HLEN);
1014 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1015 (skb->len < (ETH_HLEN +
1016 (ip_hdr(skb)->ihl << 2) +
1017 sizeof(struct udphdr)))) {
1018 skb_reset_network_header(skb);
1019 return csum;
1020 }
1021 skb_set_transport_header(skb,
1022 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1023 csum = udp_hdr(skb)->check;
1024 skb_reset_transport_header(skb);
1025 skb_reset_network_header(skb);
1026#endif
1027
1028 return csum;
1029}
1030
1031static int
1032jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1033{
1034 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1035 return false;
1036
1037 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1038 == RXWBFLAG_TCPON)) {
1039 if (flags & RXWBFLAG_IPV4)
1040 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1041 return false;
1042 }
1043
1044 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1045 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1046 if (flags & RXWBFLAG_IPV4)
1047 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1048 return false;
1049 }
1050
1051 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1052 == RXWBFLAG_IPV4)) {
1053 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1054 return false;
1055 }
1056
1057 return true;
1058}
1059
1060static void
1061jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1062{
1063 struct jme_ring *rxring = &(jme->rxring[0]);
1064 struct rxdesc *rxdesc = rxring->desc;
1065 struct jme_buffer_info *rxbi = rxring->bufinf;
1066 struct sk_buff *skb;
1067 int framesize;
1068
1069 rxdesc += idx;
1070 rxbi += idx;
1071
1072 skb = rxbi->skb;
1073 pci_dma_sync_single_for_cpu(jme->pdev,
1074 rxbi->mapping,
1075 rxbi->len,
1076 PCI_DMA_FROMDEVICE);
1077
1078 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1079 pci_dma_sync_single_for_device(jme->pdev,
1080 rxbi->mapping,
1081 rxbi->len,
1082 PCI_DMA_FROMDEVICE);
1083
1084 ++(NET_STAT(jme).rx_dropped);
1085 } else {
1086 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1087 - RX_PREPAD_SIZE;
1088
1089 skb_reserve(skb, RX_PREPAD_SIZE);
1090 skb_put(skb, framesize);
1091 skb->protocol = eth_type_trans(skb, jme->dev);
1092
1093 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1094 skb->ip_summed = CHECKSUM_UNNECESSARY;
1095 else
1096#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
1097 skb->ip_summed = CHECKSUM_NONE;
1098#else
1099 skb_checksum_none_assert(skb);
1100#endif
1101
1102 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1103 if (jme->vlgrp) {
1104 jme->jme_vlan_rx(skb, jme->vlgrp,
1105 le16_to_cpu(rxdesc->descwb.vlan));
1106 NET_STAT(jme).rx_bytes += 4;
1107 } else {
1108 dev_kfree_skb(skb);
1109 }
1110 } else {
1111 jme->jme_rx(skb);
1112 }
1113
1114 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1115 cpu_to_le16(RXWBFLAG_DEST_MUL))
1116 ++(NET_STAT(jme).multicast);
1117
1118 NET_STAT(jme).rx_bytes += framesize;
1119 ++(NET_STAT(jme).rx_packets);
1120 }
1121
1122 jme_set_clean_rxdesc(jme, idx);
1123
1124}
1125
1126static int
1127jme_process_receive(struct jme_adapter *jme, int limit)
1128{
1129 struct jme_ring *rxring = &(jme->rxring[0]);
1130 struct rxdesc *rxdesc = rxring->desc;
1131 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1132
1133 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1134 goto out_inc;
1135
1136 if (unlikely(atomic_read(&jme->link_changing) != 1))
1137 goto out_inc;
1138
1139 if (unlikely(!netif_carrier_ok(jme->dev)))
1140 goto out_inc;
1141
1142 i = atomic_read(&rxring->next_to_clean);
1143 while (limit > 0) {
1144 rxdesc = rxring->desc;
1145 rxdesc += i;
1146
1147 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1148 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1149 goto out;
1150 --limit;
1151
1152 rmb();
1153 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1154
1155 if (unlikely(desccnt > 1 ||
1156 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1157
1158 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1159 ++(NET_STAT(jme).rx_crc_errors);
1160 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1161 ++(NET_STAT(jme).rx_fifo_errors);
1162 else
1163 ++(NET_STAT(jme).rx_errors);
1164
1165 if (desccnt > 1)
1166 limit -= desccnt - 1;
1167
1168 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1169 jme_set_clean_rxdesc(jme, j);
1170 j = (j + 1) & (mask);
1171 }
1172
1173 } else {
1174 jme_alloc_and_feed_skb(jme, i);
1175 }
1176
1177 i = (i + desccnt) & (mask);
1178 }
1179
1180out:
1181 atomic_set(&rxring->next_to_clean, i);
1182
1183out_inc:
1184 atomic_inc(&jme->rx_cleaning);
1185
1186 return limit > 0 ? limit : 0;
1187
1188}
1189
1190static void
1191jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1192{
1193 if (likely(atmp == dpi->cur)) {
1194 dpi->cnt = 0;
1195 return;
1196 }
1197
1198 if (dpi->attempt == atmp) {
1199 ++(dpi->cnt);
1200 } else {
1201 dpi->attempt = atmp;
1202 dpi->cnt = 0;
1203 }
1204
1205}
1206
1207static void
1208jme_dynamic_pcc(struct jme_adapter *jme)
1209{
1210 register struct dynpcc_info *dpi = &(jme->dpi);
1211
1212 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1213 jme_attempt_pcc(dpi, PCC_P3);
1214 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1215 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1216 jme_attempt_pcc(dpi, PCC_P2);
1217 else
1218 jme_attempt_pcc(dpi, PCC_P1);
1219
1220 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1221 if (dpi->attempt < dpi->cur)
1222 tasklet_schedule(&jme->rxclean_task);
1223 jme_set_rx_pcc(jme, dpi->attempt);
1224 dpi->cur = dpi->attempt;
1225 dpi->cnt = 0;
1226 }
1227}
1228
1229static void
1230jme_start_pcc_timer(struct jme_adapter *jme)
1231{
1232 struct dynpcc_info *dpi = &(jme->dpi);
1233 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1234 dpi->last_pkts = NET_STAT(jme).rx_packets;
1235 dpi->intr_cnt = 0;
1236 jwrite32(jme, JME_TMCSR,
1237 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1238}
1239
1240static inline void
1241jme_stop_pcc_timer(struct jme_adapter *jme)
1242{
1243 jwrite32(jme, JME_TMCSR, 0);
1244}
1245
1246static void
1247jme_shutdown_nic(struct jme_adapter *jme)
1248{
1249 u32 phylink;
1250
1251 phylink = jme_linkstat_from_phy(jme);
1252
1253 if (!(phylink & PHY_LINK_UP)) {
1254 /*
1255 * Disable all interrupt before issue timer
1256 */
1257 jme_stop_irq(jme);
1258 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1259 }
1260}
1261
1262static void
1263jme_pcc_tasklet(unsigned long arg)
1264{
1265 struct jme_adapter *jme = (struct jme_adapter *)arg;
1266 struct net_device *netdev = jme->dev;
1267
1268 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1269 jme_shutdown_nic(jme);
1270 return;
1271 }
1272
1273 if (unlikely(!netif_carrier_ok(netdev) ||
1274 (atomic_read(&jme->link_changing) != 1)
1275 )) {
1276 jme_stop_pcc_timer(jme);
1277 return;
1278 }
1279
1280 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1281 jme_dynamic_pcc(jme);
1282
1283 jme_start_pcc_timer(jme);
1284}
1285
1286static inline void
1287jme_polling_mode(struct jme_adapter *jme)
1288{
1289 jme_set_rx_pcc(jme, PCC_OFF);
1290}
1291
1292static inline void
1293jme_interrupt_mode(struct jme_adapter *jme)
1294{
1295 jme_set_rx_pcc(jme, PCC_P1);
1296}
1297
1298static inline int
1299jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1300{
1301 u32 apmc;
1302 apmc = jread32(jme, JME_APMC);
1303 return apmc & JME_APMC_PSEUDO_HP_EN;
1304}
1305
1306static void
1307jme_start_shutdown_timer(struct jme_adapter *jme)
1308{
1309 u32 apmc;
1310
1311 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1312 apmc &= ~JME_APMC_EPIEN_CTRL;
1313 if (!no_extplug) {
1314 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1315 wmb();
1316 }
1317 jwrite32f(jme, JME_APMC, apmc);
1318
1319 jwrite32f(jme, JME_TIMER2, 0);
1320 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1321 jwrite32(jme, JME_TMCSR,
1322 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1323}
1324
1325static void
1326jme_stop_shutdown_timer(struct jme_adapter *jme)
1327{
1328 u32 apmc;
1329
1330 jwrite32f(jme, JME_TMCSR, 0);
1331 jwrite32f(jme, JME_TIMER2, 0);
1332 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1333
1334 apmc = jread32(jme, JME_APMC);
1335 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1336 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1337 wmb();
1338 jwrite32f(jme, JME_APMC, apmc);
1339}
1340
1341static void
1342jme_link_change_tasklet(unsigned long arg)
1343{
1344 struct jme_adapter *jme = (struct jme_adapter *)arg;
1345 struct net_device *netdev = jme->dev;
1346 int rc;
1347
1348 while (!atomic_dec_and_test(&jme->link_changing)) {
1349 atomic_inc(&jme->link_changing);
1350 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1351 while (atomic_read(&jme->link_changing) != 1)
1352 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1353 }
1354
1355 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1356 goto out;
1357
1358 jme->old_mtu = netdev->mtu;
1359 netif_stop_queue(netdev);
1360 if (jme_pseudo_hotplug_enabled(jme))
1361 jme_stop_shutdown_timer(jme);
1362
1363 jme_stop_pcc_timer(jme);
1364 tasklet_disable(&jme->txclean_task);
1365 tasklet_disable(&jme->rxclean_task);
1366 tasklet_disable(&jme->rxempty_task);
1367
1368 if (netif_carrier_ok(netdev)) {
1369 jme_disable_rx_engine(jme);
1370 jme_disable_tx_engine(jme);
1371 jme_reset_mac_processor(jme);
1372 jme_free_rx_resources(jme);
1373 jme_free_tx_resources(jme);
1374
1375 if (test_bit(JME_FLAG_POLL, &jme->flags))
1376 jme_polling_mode(jme);
1377
1378 netif_carrier_off(netdev);
1379 }
1380
1381 jme_check_link(netdev, 0);
1382 if (netif_carrier_ok(netdev)) {
1383 rc = jme_setup_rx_resources(jme);
1384 if (rc) {
1385 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1386 goto out_enable_tasklet;
1387 }
1388
1389 rc = jme_setup_tx_resources(jme);
1390 if (rc) {
1391 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1392 goto err_out_free_rx_resources;
1393 }
1394
1395 jme_enable_rx_engine(jme);
1396 jme_enable_tx_engine(jme);
1397
1398 netif_start_queue(netdev);
1399
1400 if (test_bit(JME_FLAG_POLL, &jme->flags))
1401 jme_interrupt_mode(jme);
1402
1403 jme_start_pcc_timer(jme);
1404 } else if (jme_pseudo_hotplug_enabled(jme)) {
1405 jme_start_shutdown_timer(jme);
1406 }
1407
1408 goto out_enable_tasklet;
1409
1410err_out_free_rx_resources:
1411 jme_free_rx_resources(jme);
1412out_enable_tasklet:
1413 tasklet_enable(&jme->txclean_task);
1414 tasklet_hi_enable(&jme->rxclean_task);
1415 tasklet_hi_enable(&jme->rxempty_task);
1416out:
1417 atomic_inc(&jme->link_changing);
1418}
1419
1420static void
1421jme_rx_clean_tasklet(unsigned long arg)
1422{
1423 struct jme_adapter *jme = (struct jme_adapter *)arg;
1424 struct dynpcc_info *dpi = &(jme->dpi);
1425
1426 jme_process_receive(jme, jme->rx_ring_size);
1427 ++(dpi->intr_cnt);
1428
1429}
1430
1431static int
1432jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1433{
1434 struct jme_adapter *jme = jme_napi_priv(holder);
1435 DECLARE_NETDEV
1436 int rest;
1437
1438 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1439
1440 while (atomic_read(&jme->rx_empty) > 0) {
1441 atomic_dec(&jme->rx_empty);
1442 ++(NET_STAT(jme).rx_dropped);
1443 jme_restart_rx_engine(jme);
1444 }
1445 atomic_inc(&jme->rx_empty);
1446
1447 if (rest) {
1448 JME_RX_COMPLETE(netdev, holder);
1449 jme_interrupt_mode(jme);
1450 }
1451
1452 JME_NAPI_WEIGHT_SET(budget, rest);
1453 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1454}
1455
1456static void
1457jme_rx_empty_tasklet(unsigned long arg)
1458{
1459 struct jme_adapter *jme = (struct jme_adapter *)arg;
1460
1461 if (unlikely(atomic_read(&jme->link_changing) != 1))
1462 return;
1463
1464 if (unlikely(!netif_carrier_ok(jme->dev)))
1465 return;
1466
1467 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1468
1469 jme_rx_clean_tasklet(arg);
1470
1471 while (atomic_read(&jme->rx_empty) > 0) {
1472 atomic_dec(&jme->rx_empty);
1473 ++(NET_STAT(jme).rx_dropped);
1474 jme_restart_rx_engine(jme);
1475 }
1476 atomic_inc(&jme->rx_empty);
1477}
1478
1479static void
1480jme_wake_queue_if_stopped(struct jme_adapter *jme)
1481{
1482 struct jme_ring *txring = &(jme->txring[0]);
1483
1484 smp_wmb();
1485 if (unlikely(netif_queue_stopped(jme->dev) &&
1486 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1487 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1488 netif_wake_queue(jme->dev);
1489 }
1490
1491}
1492
1493static void
1494jme_tx_clean_tasklet(unsigned long arg)
1495{
1496 struct jme_adapter *jme = (struct jme_adapter *)arg;
1497 struct jme_ring *txring = &(jme->txring[0]);
1498 struct txdesc *txdesc = txring->desc;
1499 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1500 int i, j, cnt = 0, max, err, mask;
1501
1502 tx_dbg(jme, "Into txclean\n");
1503
1504 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1505 goto out;
1506
1507 if (unlikely(atomic_read(&jme->link_changing) != 1))
1508 goto out;
1509
1510 if (unlikely(!netif_carrier_ok(jme->dev)))
1511 goto out;
1512
1513 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1514 mask = jme->tx_ring_mask;
1515
1516 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1517
1518 ctxbi = txbi + i;
1519
1520 if (likely(ctxbi->skb &&
1521 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1522
1523 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1524 i, ctxbi->nr_desc, jiffies);
1525
1526 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1527
1528 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1529 ttxbi = txbi + ((i + j) & (mask));
1530 txdesc[(i + j) & (mask)].dw[0] = 0;
1531
1532 pci_unmap_page(jme->pdev,
1533 ttxbi->mapping,
1534 ttxbi->len,
1535 PCI_DMA_TODEVICE);
1536
1537 ttxbi->mapping = 0;
1538 ttxbi->len = 0;
1539 }
1540
1541 dev_kfree_skb(ctxbi->skb);
1542
1543 cnt += ctxbi->nr_desc;
1544
1545 if (unlikely(err)) {
1546 ++(NET_STAT(jme).tx_carrier_errors);
1547 } else {
1548 ++(NET_STAT(jme).tx_packets);
1549 NET_STAT(jme).tx_bytes += ctxbi->len;
1550 }
1551
1552 ctxbi->skb = NULL;
1553 ctxbi->len = 0;
1554 ctxbi->start_xmit = 0;
1555
1556 } else {
1557 break;
1558 }
1559
1560 i = (i + ctxbi->nr_desc) & mask;
1561
1562 ctxbi->nr_desc = 0;
1563 }
1564
1565 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1566 atomic_set(&txring->next_to_clean, i);
1567 atomic_add(cnt, &txring->nr_free);
1568
1569 jme_wake_queue_if_stopped(jme);
1570
1571out:
1572 atomic_inc(&jme->tx_cleaning);
1573}
1574
1575static void
1576jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1577{
1578 /*
1579 * Disable interrupt
1580 */
1581 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1582
1583 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1584 /*
1585 * Link change event is critical
1586 * all other events are ignored
1587 */
1588 jwrite32(jme, JME_IEVE, intrstat);
1589 tasklet_schedule(&jme->linkch_task);
1590 goto out_reenable;
1591 }
1592
1593 if (intrstat & INTR_TMINTR) {
1594 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1595 tasklet_schedule(&jme->pcc_task);
1596 }
1597
1598 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1599 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1600 tasklet_schedule(&jme->txclean_task);
1601 }
1602
1603 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1604 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1605 INTR_PCCRX0 |
1606 INTR_RX0EMP)) |
1607 INTR_RX0);
1608 }
1609
1610 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1611 if (intrstat & INTR_RX0EMP)
1612 atomic_inc(&jme->rx_empty);
1613
1614 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1615 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1616 jme_polling_mode(jme);
1617 JME_RX_SCHEDULE(jme);
1618 }
1619 }
1620 } else {
1621 if (intrstat & INTR_RX0EMP) {
1622 atomic_inc(&jme->rx_empty);
1623 tasklet_hi_schedule(&jme->rxempty_task);
1624 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1625 tasklet_hi_schedule(&jme->rxclean_task);
1626 }
1627 }
1628
1629out_reenable:
1630 /*
1631 * Re-enable interrupt
1632 */
1633 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1634}
1635
1636#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1637static irqreturn_t
1638jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1639#else
1640static irqreturn_t
1641jme_intr(int irq, void *dev_id)
1642#endif
1643{
1644 struct net_device *netdev = dev_id;
1645 struct jme_adapter *jme = netdev_priv(netdev);
1646 u32 intrstat;
1647
1648 intrstat = jread32(jme, JME_IEVE);
1649
1650 /*
1651 * Check if it's really an interrupt for us
1652 */
1653 if (unlikely((intrstat & INTR_ENABLE) == 0))
1654 return IRQ_NONE;
1655
1656 /*
1657 * Check if the device still exist
1658 */
1659 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1660 return IRQ_NONE;
1661
1662 jme_intr_msi(jme, intrstat);
1663
1664 return IRQ_HANDLED;
1665}
1666
1667#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1668static irqreturn_t
1669jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1670#else
1671static irqreturn_t
1672jme_msi(int irq, void *dev_id)
1673#endif
1674{
1675 struct net_device *netdev = dev_id;
1676 struct jme_adapter *jme = netdev_priv(netdev);
1677 u32 intrstat;
1678
1679 intrstat = jread32(jme, JME_IEVE);
1680
1681 jme_intr_msi(jme, intrstat);
1682
1683 return IRQ_HANDLED;
1684}
1685
1686static void
1687jme_reset_link(struct jme_adapter *jme)
1688{
1689 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1690}
1691
1692static void
1693jme_restart_an(struct jme_adapter *jme)
1694{
1695 u32 bmcr;
1696
1697 spin_lock_bh(&jme->phy_lock);
1698 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1699 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1700 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1701 spin_unlock_bh(&jme->phy_lock);
1702}
1703
1704static int
1705jme_request_irq(struct jme_adapter *jme)
1706{
1707 int rc;
1708 struct net_device *netdev = jme->dev;
1709#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1710 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1711 int irq_flags = SA_SHIRQ;
1712#else
1713 irq_handler_t handler = jme_intr;
1714 int irq_flags = IRQF_SHARED;
1715#endif
1716
1717 if (!pci_enable_msi(jme->pdev)) {
1718 set_bit(JME_FLAG_MSI, &jme->flags);
1719 handler = jme_msi;
1720 irq_flags = 0;
1721 }
1722
1723 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1724 netdev);
1725 if (rc) {
1726 netdev_err(netdev,
1727 "Unable to request %s interrupt (return: %d)\n",
1728 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1729 rc);
1730
1731 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1732 pci_disable_msi(jme->pdev);
1733 clear_bit(JME_FLAG_MSI, &jme->flags);
1734 }
1735 } else {
1736 netdev->irq = jme->pdev->irq;
1737 }
1738
1739 return rc;
1740}
1741
1742static void
1743jme_free_irq(struct jme_adapter *jme)
1744{
1745 free_irq(jme->pdev->irq, jme->dev);
1746 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1747 pci_disable_msi(jme->pdev);
1748 clear_bit(JME_FLAG_MSI, &jme->flags);
1749 jme->dev->irq = jme->pdev->irq;
1750 }
1751}
1752
1753static inline void
1754jme_new_phy_on(struct jme_adapter *jme)
1755{
1756 u32 reg;
1757
1758 reg = jread32(jme, JME_PHY_PWR);
1759 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1760 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1761 jwrite32(jme, JME_PHY_PWR, reg);
1762
1763 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1764 reg &= ~PE1_GPREG0_PBG;
1765 reg |= PE1_GPREG0_ENBG;
1766 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1767}
1768
1769static inline void
1770jme_new_phy_off(struct jme_adapter *jme)
1771{
1772 u32 reg;
1773
1774 reg = jread32(jme, JME_PHY_PWR);
1775 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1776 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1777 jwrite32(jme, JME_PHY_PWR, reg);
1778
1779 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1780 reg &= ~PE1_GPREG0_PBG;
1781 reg |= PE1_GPREG0_PDD3COLD;
1782 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1783}
1784
1785static inline void
1786jme_phy_on(struct jme_adapter *jme)
1787{
1788 u32 bmcr;
1789
1790 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1791 bmcr &= ~BMCR_PDOWN;
1792 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1793
1794 if (new_phy_power_ctrl(jme->chip_main_rev))
1795 jme_new_phy_on(jme);
1796}
1797
1798static inline void
1799jme_phy_off(struct jme_adapter *jme)
1800{
1801 u32 bmcr;
1802
1803 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1804 bmcr |= BMCR_PDOWN;
1805 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1806
1807 if (new_phy_power_ctrl(jme->chip_main_rev))
1808 jme_new_phy_off(jme);
1809}
1810
1811static int
1812jme_open(struct net_device *netdev)
1813{
1814 struct jme_adapter *jme = netdev_priv(netdev);
1815 int rc;
1816
1817 jme_clear_pm(jme);
1818 JME_NAPI_ENABLE(jme);
1819
1820 tasklet_enable(&jme->linkch_task);
1821 tasklet_enable(&jme->txclean_task);
1822 tasklet_hi_enable(&jme->rxclean_task);
1823 tasklet_hi_enable(&jme->rxempty_task);
1824
1825 rc = jme_request_irq(jme);
1826 if (rc)
1827 goto err_out;
1828
1829 jme_start_irq(jme);
1830
1831 jme_phy_on(jme);
1832 if (test_bit(JME_FLAG_SSET, &jme->flags))
1833 jme_set_settings(netdev, &jme->old_ecmd);
1834 else
1835 jme_reset_phy_processor(jme);
1836
1837 jme_reset_link(jme);
1838
1839 return 0;
1840
1841err_out:
1842 netif_stop_queue(netdev);
1843 netif_carrier_off(netdev);
1844 return rc;
1845}
1846
1847static void
1848jme_set_100m_half(struct jme_adapter *jme)
1849{
1850 u32 bmcr, tmp;
1851
1852 jme_phy_on(jme);
1853 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1854 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1855 BMCR_SPEED1000 | BMCR_FULLDPLX);
1856 tmp |= BMCR_SPEED100;
1857
1858 if (bmcr != tmp)
1859 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1860
1861 if (jme->fpgaver)
1862 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1863 else
1864 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1865}
1866
1867#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1868static void
1869jme_wait_link(struct jme_adapter *jme)
1870{
1871 u32 phylink, to = JME_WAIT_LINK_TIME;
1872
1873 mdelay(1000);
1874 phylink = jme_linkstat_from_phy(jme);
1875 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1876 mdelay(10);
1877 phylink = jme_linkstat_from_phy(jme);
1878 }
1879}
1880
1881static void
1882jme_powersave_phy(struct jme_adapter *jme)
1883{
1884 if (jme->reg_pmcs) {
1885 jme_set_100m_half(jme);
1886 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1887 jme_wait_link(jme);
1888 jme_clear_pm(jme);
1889 } else {
1890 jme_phy_off(jme);
1891 }
1892}
1893
1894static int
1895jme_close(struct net_device *netdev)
1896{
1897 struct jme_adapter *jme = netdev_priv(netdev);
1898
1899 netif_stop_queue(netdev);
1900 netif_carrier_off(netdev);
1901
1902 jme_stop_irq(jme);
1903 jme_free_irq(jme);
1904
1905 JME_NAPI_DISABLE(jme);
1906
1907 tasklet_disable(&jme->linkch_task);
1908 tasklet_disable(&jme->txclean_task);
1909 tasklet_disable(&jme->rxclean_task);
1910 tasklet_disable(&jme->rxempty_task);
1911
1912 jme_disable_rx_engine(jme);
1913 jme_disable_tx_engine(jme);
1914 jme_reset_mac_processor(jme);
1915 jme_free_rx_resources(jme);
1916 jme_free_tx_resources(jme);
1917 jme->phylink = 0;
1918 jme_phy_off(jme);
1919
1920 return 0;
1921}
1922
1923static int
1924jme_alloc_txdesc(struct jme_adapter *jme,
1925 struct sk_buff *skb)
1926{
1927 struct jme_ring *txring = &(jme->txring[0]);
1928 int idx, nr_alloc, mask = jme->tx_ring_mask;
1929
1930 idx = txring->next_to_use;
1931 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1932
1933 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1934 return -1;
1935
1936 atomic_sub(nr_alloc, &txring->nr_free);
1937
1938 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1939
1940 return idx;
1941}
1942
1943static void
1944jme_fill_tx_map(struct pci_dev *pdev,
1945 struct txdesc *txdesc,
1946 struct jme_buffer_info *txbi,
1947 struct page *page,
1948 u32 page_offset,
1949 u32 len,
1950 u8 hidma)
1951{
1952 dma_addr_t dmaaddr;
1953
1954 dmaaddr = pci_map_page(pdev,
1955 page,
1956 page_offset,
1957 len,
1958 PCI_DMA_TODEVICE);
1959
1960 pci_dma_sync_single_for_device(pdev,
1961 dmaaddr,
1962 len,
1963 PCI_DMA_TODEVICE);
1964
1965 txdesc->dw[0] = 0;
1966 txdesc->dw[1] = 0;
1967 txdesc->desc2.flags = TXFLAG_OWN;
1968 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1969 txdesc->desc2.datalen = cpu_to_le16(len);
1970 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1971 txdesc->desc2.bufaddrl = cpu_to_le32(
1972 (__u64)dmaaddr & 0xFFFFFFFFUL);
1973
1974 txbi->mapping = dmaaddr;
1975 txbi->len = len;
1976}
1977
1978static void
1979jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1980{
1981 struct jme_ring *txring = &(jme->txring[0]);
1982 struct txdesc *txdesc = txring->desc, *ctxdesc;
1983 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1984 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1985 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1986 int mask = jme->tx_ring_mask;
1987 struct skb_frag_struct *frag;
1988 u32 len;
1989
1990 for (i = 0 ; i < nr_frags ; ++i) {
1991 frag = &skb_shinfo(skb)->frags[i];
1992 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1993 ctxbi = txbi + ((idx + i + 2) & (mask));
1994
1995 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1996 frag->page_offset, frag->size, hidma);
1997 }
1998
1999 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2000 ctxdesc = txdesc + ((idx + 1) & (mask));
2001 ctxbi = txbi + ((idx + 1) & (mask));
2002 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2003 offset_in_page(skb->data), len, hidma);
2004
2005}
2006
2007static int
2008jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2009{
2010 if (unlikely(
2011#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2012 skb_shinfo(skb)->tso_size
2013#else
2014 skb_shinfo(skb)->gso_size
2015#endif
2016 && skb_header_cloned(skb) &&
2017 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2018 dev_kfree_skb(skb);
2019 return -1;
2020 }
2021
2022 return 0;
2023}
2024
2025static int
2026jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2027{
2028#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2029 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2030#else
2031 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2032#endif
2033 if (*mss) {
2034 *flags |= TXFLAG_LSEN;
2035
2036 if (skb->protocol == htons(ETH_P_IP)) {
2037 struct iphdr *iph = ip_hdr(skb);
2038
2039 iph->check = 0;
2040 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2041 iph->daddr, 0,
2042 IPPROTO_TCP,
2043 0);
2044 } else {
2045 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2046
2047 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2048 &ip6h->daddr, 0,
2049 IPPROTO_TCP,
2050 0);
2051 }
2052
2053 return 0;
2054 }
2055
2056 return 1;
2057}
2058
2059static void
2060jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2061{
2062#ifdef CHECKSUM_PARTIAL
2063 if (skb->ip_summed == CHECKSUM_PARTIAL)
2064#else
2065 if (skb->ip_summed == CHECKSUM_HW)
2066#endif
2067 {
2068 u8 ip_proto;
2069
2070#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2071 if (skb->protocol == htons(ETH_P_IP))
2072 ip_proto = ip_hdr(skb)->protocol;
2073 else if (skb->protocol == htons(ETH_P_IPV6))
2074 ip_proto = ipv6_hdr(skb)->nexthdr;
2075 else
2076 ip_proto = 0;
2077#else
2078 switch (skb->protocol) {
2079 case htons(ETH_P_IP):
2080 ip_proto = ip_hdr(skb)->protocol;
2081 break;
2082 case htons(ETH_P_IPV6):
2083 ip_proto = ipv6_hdr(skb)->nexthdr;
2084 break;
2085 default:
2086 ip_proto = 0;
2087 break;
2088 }
2089#endif
2090
2091 switch (ip_proto) {
2092 case IPPROTO_TCP:
2093 *flags |= TXFLAG_TCPCS;
2094 break;
2095 case IPPROTO_UDP:
2096 *flags |= TXFLAG_UDPCS;
2097 break;
2098 default:
2099 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2100 break;
2101 }
2102 }
2103}
2104
2105static inline void
2106jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2107{
2108 if (vlan_tx_tag_present(skb)) {
2109 *flags |= TXFLAG_TAGON;
2110 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2111 }
2112}
2113
2114static int
2115jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2116{
2117 struct jme_ring *txring = &(jme->txring[0]);
2118 struct txdesc *txdesc;
2119 struct jme_buffer_info *txbi;
2120 u8 flags;
2121
2122 txdesc = (struct txdesc *)txring->desc + idx;
2123 txbi = txring->bufinf + idx;
2124
2125 txdesc->dw[0] = 0;
2126 txdesc->dw[1] = 0;
2127 txdesc->dw[2] = 0;
2128 txdesc->dw[3] = 0;
2129 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2130 /*
2131 * Set OWN bit at final.
2132 * When kernel transmit faster than NIC.
2133 * And NIC trying to send this descriptor before we tell
2134 * it to start sending this TX queue.
2135 * Other fields are already filled correctly.
2136 */
2137 wmb();
2138 flags = TXFLAG_OWN | TXFLAG_INT;
2139 /*
2140 * Set checksum flags while not tso
2141 */
2142 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2143 jme_tx_csum(jme, skb, &flags);
2144 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2145 jme_map_tx_skb(jme, skb, idx);
2146 txdesc->desc1.flags = flags;
2147 /*
2148 * Set tx buffer info after telling NIC to send
2149 * For better tx_clean timing
2150 */
2151 wmb();
2152 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2153 txbi->skb = skb;
2154 txbi->len = skb->len;
2155 txbi->start_xmit = jiffies;
2156 if (!txbi->start_xmit)
2157 txbi->start_xmit = (0UL-1);
2158
2159 return 0;
2160}
2161
2162static void
2163jme_stop_queue_if_full(struct jme_adapter *jme)
2164{
2165 struct jme_ring *txring = &(jme->txring[0]);
2166 struct jme_buffer_info *txbi = txring->bufinf;
2167 int idx = atomic_read(&txring->next_to_clean);
2168
2169 txbi += idx;
2170
2171 smp_wmb();
2172 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2173 netif_stop_queue(jme->dev);
2174 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2175 smp_wmb();
2176 if (atomic_read(&txring->nr_free)
2177 >= (jme->tx_wake_threshold)) {
2178 netif_wake_queue(jme->dev);
2179 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2180 }
2181 }
2182
2183 if (unlikely(txbi->start_xmit &&
2184 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2185 txbi->skb)) {
2186 netif_stop_queue(jme->dev);
2187 netif_info(jme, tx_queued, jme->dev,
2188 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2189 }
2190}
2191
2192/*
2193 * This function is already protected by netif_tx_lock()
2194 */
2195
2196#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2197static int
2198#else
2199static netdev_tx_t
2200#endif
2201jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2202{
2203 struct jme_adapter *jme = netdev_priv(netdev);
2204 int idx;
2205
2206 if (unlikely(jme_expand_header(jme, skb))) {
2207 ++(NET_STAT(jme).tx_dropped);
2208 return NETDEV_TX_OK;
2209 }
2210
2211 idx = jme_alloc_txdesc(jme, skb);
2212
2213 if (unlikely(idx < 0)) {
2214 netif_stop_queue(netdev);
2215 netif_err(jme, tx_err, jme->dev,
2216 "BUG! Tx ring full when queue awake!\n");
2217
2218 return NETDEV_TX_BUSY;
2219 }
2220
2221 jme_fill_tx_desc(jme, skb, idx);
2222
2223 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2224 TXCS_SELECT_QUEUE0 |
2225 TXCS_QUEUE0S |
2226 TXCS_ENABLE);
2227#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2228 netdev->trans_start = jiffies;
2229#endif
2230
2231 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2232 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2233 jme_stop_queue_if_full(jme);
2234
2235 return NETDEV_TX_OK;
2236}
2237
2238static void
2239jme_set_unicastaddr(struct net_device *netdev)
2240{
2241 struct jme_adapter *jme = netdev_priv(netdev);
2242 u32 val;
2243
2244 val = (netdev->dev_addr[3] & 0xff) << 24 |
2245 (netdev->dev_addr[2] & 0xff) << 16 |
2246 (netdev->dev_addr[1] & 0xff) << 8 |
2247 (netdev->dev_addr[0] & 0xff);
2248 jwrite32(jme, JME_RXUMA_LO, val);
2249 val = (netdev->dev_addr[5] & 0xff) << 8 |
2250 (netdev->dev_addr[4] & 0xff);
2251 jwrite32(jme, JME_RXUMA_HI, val);
2252}
2253
2254static int
2255jme_set_macaddr(struct net_device *netdev, void *p)
2256{
2257 struct jme_adapter *jme = netdev_priv(netdev);
2258 struct sockaddr *addr = p;
2259
2260 if (netif_running(netdev))
2261 return -EBUSY;
2262
2263 spin_lock_bh(&jme->macaddr_lock);
2264 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2265 jme_set_unicastaddr(netdev);
2266 spin_unlock_bh(&jme->macaddr_lock);
2267
2268 return 0;
2269}
2270
2271static void
2272jme_set_multi(struct net_device *netdev)
2273{
2274 struct jme_adapter *jme = netdev_priv(netdev);
2275 u32 mc_hash[2] = {};
2276#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2277 int i;
2278#endif
2279
2280 spin_lock_bh(&jme->rxmcs_lock);
2281
2282 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2283
2284 if (netdev->flags & IFF_PROMISC) {
2285 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2286 } else if (netdev->flags & IFF_ALLMULTI) {
2287 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2288 } else if (netdev->flags & IFF_MULTICAST) {
2289#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2290 struct dev_mc_list *mclist;
2291#else
2292 struct netdev_hw_addr *ha;
2293#endif
2294 int bit_nr;
2295
2296 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2297#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2298 for (i = 0, mclist = netdev->mc_list;
2299 mclist && i < netdev->mc_count;
2300 ++i, mclist = mclist->next) {
2301#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2302 netdev_for_each_mc_addr(mclist, netdev) {
2303#else
2304 netdev_for_each_mc_addr(ha, netdev) {
2305#endif
2306#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2307 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2308#else
2309 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2310#endif
2311 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2312 }
2313
2314 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2315 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2316 }
2317
2318 wmb();
2319 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2320
2321 spin_unlock_bh(&jme->rxmcs_lock);
2322}
2323
2324static int
2325jme_change_mtu(struct net_device *netdev, int new_mtu)
2326{
2327 struct jme_adapter *jme = netdev_priv(netdev);
2328
2329 if (new_mtu == jme->old_mtu)
2330 return 0;
2331
2332 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2333 ((new_mtu) < IPV6_MIN_MTU))
2334 return -EINVAL;
2335
2336 if (new_mtu > 4000) {
2337 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2338 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2339 jme_restart_rx_engine(jme);
2340 } else {
2341 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2342 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2343 jme_restart_rx_engine(jme);
2344 }
2345
2346#ifndef __USE_NDO_FIX_FEATURES__
2347 if (new_mtu > 1900) {
2348 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2349 NETIF_F_TSO | NETIF_F_TSO6);
2350 } else {
2351 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2352 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2353 if (test_bit(JME_FLAG_TSO, &jme->flags))
2354 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2355 }
2356#endif
2357
2358 netdev->mtu = new_mtu;
2359#ifdef __USE_NDO_FIX_FEATURES__
2360 netdev_update_features(netdev);
2361#endif
2362 jme_reset_link(jme);
2363
2364 return 0;
2365}
2366
2367static void
2368jme_tx_timeout(struct net_device *netdev)
2369{
2370 struct jme_adapter *jme = netdev_priv(netdev);
2371
2372 jme->phylink = 0;
2373 jme_reset_phy_processor(jme);
2374 if (test_bit(JME_FLAG_SSET, &jme->flags))
2375 jme_set_settings(netdev, &jme->old_ecmd);
2376
2377 /*
2378 * Force to Reset the link again
2379 */
2380 jme_reset_link(jme);
2381}
2382
2383static inline void jme_pause_rx(struct jme_adapter *jme)
2384{
2385 atomic_dec(&jme->link_changing);
2386
2387 jme_set_rx_pcc(jme, PCC_OFF);
2388 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2389 JME_NAPI_DISABLE(jme);
2390 } else {
2391 tasklet_disable(&jme->rxclean_task);
2392 tasklet_disable(&jme->rxempty_task);
2393 }
2394}
2395
2396static inline void jme_resume_rx(struct jme_adapter *jme)
2397{
2398 struct dynpcc_info *dpi = &(jme->dpi);
2399
2400 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2401 JME_NAPI_ENABLE(jme);
2402 } else {
2403 tasklet_hi_enable(&jme->rxclean_task);
2404 tasklet_hi_enable(&jme->rxempty_task);
2405 }
2406 dpi->cur = PCC_P1;
2407 dpi->attempt = PCC_P1;
2408 dpi->cnt = 0;
2409 jme_set_rx_pcc(jme, PCC_P1);
2410
2411 atomic_inc(&jme->link_changing);
2412}
2413
2414static void
2415jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2416{
2417 struct jme_adapter *jme = netdev_priv(netdev);
2418
2419 jme_pause_rx(jme);
2420 jme->vlgrp = grp;
2421 jme_resume_rx(jme);
2422}
2423
2424#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2425static void
2426jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2427{
2428 struct jme_adapter *jme = netdev_priv(netdev);
2429
2430 if(jme->vlgrp) {
2431 jme_pause_rx(jme);
2432#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2433 jme->vlgrp->vlan_devices[vid] = NULL;
2434#else
2435 vlan_group_set_device(jme->vlgrp, vid, NULL);
2436#endif
2437 jme_resume_rx(jme);
2438 }
2439}
2440#endif
2441
2442static void
2443jme_get_drvinfo(struct net_device *netdev,
2444 struct ethtool_drvinfo *info)
2445{
2446 struct jme_adapter *jme = netdev_priv(netdev);
2447
2448 strcpy(info->driver, DRV_NAME);
2449 strcpy(info->version, DRV_VERSION);
2450 strcpy(info->bus_info, pci_name(jme->pdev));
2451}
2452
2453static int
2454jme_get_regs_len(struct net_device *netdev)
2455{
2456 return JME_REG_LEN;
2457}
2458
2459static void
2460mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2461{
2462 int i;
2463
2464 for (i = 0 ; i < len ; i += 4)
2465 p[i >> 2] = jread32(jme, reg + i);
2466}
2467
2468static void
2469mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2470{
2471 int i;
2472 u16 *p16 = (u16 *)p;
2473
2474 for (i = 0 ; i < reg_nr ; ++i)
2475 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2476}
2477
2478static void
2479jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2480{
2481 struct jme_adapter *jme = netdev_priv(netdev);
2482 u32 *p32 = (u32 *)p;
2483
2484 memset(p, 0xFF, JME_REG_LEN);
2485
2486 regs->version = 1;
2487 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2488
2489 p32 += 0x100 >> 2;
2490 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2491
2492 p32 += 0x100 >> 2;
2493 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2494
2495 p32 += 0x100 >> 2;
2496 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2497
2498 p32 += 0x100 >> 2;
2499 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2500}
2501
2502static int
2503jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2504{
2505 struct jme_adapter *jme = netdev_priv(netdev);
2506
2507 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2508 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2509
2510 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2511 ecmd->use_adaptive_rx_coalesce = false;
2512 ecmd->rx_coalesce_usecs = 0;
2513 ecmd->rx_max_coalesced_frames = 0;
2514 return 0;
2515 }
2516
2517 ecmd->use_adaptive_rx_coalesce = true;
2518
2519 switch (jme->dpi.cur) {
2520 case PCC_P1:
2521 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2522 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2523 break;
2524 case PCC_P2:
2525 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2526 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2527 break;
2528 case PCC_P3:
2529 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2530 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2531 break;
2532 default:
2533 break;
2534 }
2535
2536 return 0;
2537}
2538
2539static int
2540jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2541{
2542 struct jme_adapter *jme = netdev_priv(netdev);
2543 struct dynpcc_info *dpi = &(jme->dpi);
2544
2545 if (netif_running(netdev))
2546 return -EBUSY;
2547
2548 if (ecmd->use_adaptive_rx_coalesce &&
2549 test_bit(JME_FLAG_POLL, &jme->flags)) {
2550 clear_bit(JME_FLAG_POLL, &jme->flags);
2551 jme->jme_rx = netif_rx;
2552 jme->jme_vlan_rx = vlan_hwaccel_rx;
2553 dpi->cur = PCC_P1;
2554 dpi->attempt = PCC_P1;
2555 dpi->cnt = 0;
2556 jme_set_rx_pcc(jme, PCC_P1);
2557 jme_interrupt_mode(jme);
2558 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2559 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2560 set_bit(JME_FLAG_POLL, &jme->flags);
2561 jme->jme_rx = netif_receive_skb;
2562 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2563 jme_interrupt_mode(jme);
2564 }
2565
2566 return 0;
2567}
2568
2569static void
2570jme_get_pauseparam(struct net_device *netdev,
2571 struct ethtool_pauseparam *ecmd)
2572{
2573 struct jme_adapter *jme = netdev_priv(netdev);
2574 u32 val;
2575
2576 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2577 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2578
2579 spin_lock_bh(&jme->phy_lock);
2580 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2581 spin_unlock_bh(&jme->phy_lock);
2582
2583 ecmd->autoneg =
2584 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2585}
2586
2587static int
2588jme_set_pauseparam(struct net_device *netdev,
2589 struct ethtool_pauseparam *ecmd)
2590{
2591 struct jme_adapter *jme = netdev_priv(netdev);
2592 u32 val;
2593
2594 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2595 (ecmd->tx_pause != 0)) {
2596
2597 if (ecmd->tx_pause)
2598 jme->reg_txpfc |= TXPFC_PF_EN;
2599 else
2600 jme->reg_txpfc &= ~TXPFC_PF_EN;
2601
2602 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2603 }
2604
2605 spin_lock_bh(&jme->rxmcs_lock);
2606 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2607 (ecmd->rx_pause != 0)) {
2608
2609 if (ecmd->rx_pause)
2610 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2611 else
2612 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2613
2614 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2615 }
2616 spin_unlock_bh(&jme->rxmcs_lock);
2617
2618 spin_lock_bh(&jme->phy_lock);
2619 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2620 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2621 (ecmd->autoneg != 0)) {
2622
2623 if (ecmd->autoneg)
2624 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2625 else
2626 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2627
2628 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2629 MII_ADVERTISE, val);
2630 }
2631 spin_unlock_bh(&jme->phy_lock);
2632
2633 return 0;
2634}
2635
2636static void
2637jme_get_wol(struct net_device *netdev,
2638 struct ethtool_wolinfo *wol)
2639{
2640 struct jme_adapter *jme = netdev_priv(netdev);
2641
2642 wol->supported = WAKE_MAGIC | WAKE_PHY;
2643
2644 wol->wolopts = 0;
2645
2646 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2647 wol->wolopts |= WAKE_PHY;
2648
2649 if (jme->reg_pmcs & PMCS_MFEN)
2650 wol->wolopts |= WAKE_MAGIC;
2651
2652}
2653
2654static int
2655jme_set_wol(struct net_device *netdev,
2656 struct ethtool_wolinfo *wol)
2657{
2658 struct jme_adapter *jme = netdev_priv(netdev);
2659
2660 if (wol->wolopts & (WAKE_MAGICSECURE |
2661 WAKE_UCAST |
2662 WAKE_MCAST |
2663 WAKE_BCAST |
2664 WAKE_ARP))
2665 return -EOPNOTSUPP;
2666
2667 jme->reg_pmcs = 0;
2668
2669 if (wol->wolopts & WAKE_PHY)
2670 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2671
2672 if (wol->wolopts & WAKE_MAGIC)
2673 jme->reg_pmcs |= PMCS_MFEN;
2674
2675 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2676#ifndef JME_NEW_PM_API
2677 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2678#endif
2679#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
2680 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2681#endif
2682
2683 return 0;
2684}
2685
2686static int
2687jme_get_settings(struct net_device *netdev,
2688 struct ethtool_cmd *ecmd)
2689{
2690 struct jme_adapter *jme = netdev_priv(netdev);
2691 int rc;
2692
2693 spin_lock_bh(&jme->phy_lock);
2694 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2695 spin_unlock_bh(&jme->phy_lock);
2696 return rc;
2697}
2698
2699static int
2700jme_set_settings(struct net_device *netdev,
2701 struct ethtool_cmd *ecmd)
2702{
2703 struct jme_adapter *jme = netdev_priv(netdev);
2704 int rc, fdc = 0;
2705
2706 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2707 && ecmd->autoneg != AUTONEG_ENABLE)
2708 return -EINVAL;
2709
2710 /*
2711 * Check If user changed duplex only while force_media.
2712 * Hardware would not generate link change interrupt.
2713 */
2714 if (jme->mii_if.force_media &&
2715 ecmd->autoneg != AUTONEG_ENABLE &&
2716 (jme->mii_if.full_duplex != ecmd->duplex))
2717 fdc = 1;
2718
2719 spin_lock_bh(&jme->phy_lock);
2720 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2721 spin_unlock_bh(&jme->phy_lock);
2722
2723 if (!rc) {
2724 if (fdc)
2725 jme_reset_link(jme);
2726 jme->old_ecmd = *ecmd;
2727 set_bit(JME_FLAG_SSET, &jme->flags);
2728 }
2729
2730 return rc;
2731}
2732
2733static int
2734jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2735{
2736 int rc;
2737 struct jme_adapter *jme = netdev_priv(netdev);
2738 struct mii_ioctl_data *mii_data = if_mii(rq);
2739 unsigned int duplex_chg;
2740
2741 if (cmd == SIOCSMIIREG) {
2742 u16 val = mii_data->val_in;
2743 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2744 (val & BMCR_SPEED1000))
2745 return -EINVAL;
2746 }
2747
2748 spin_lock_bh(&jme->phy_lock);
2749 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2750 spin_unlock_bh(&jme->phy_lock);
2751
2752 if (!rc && (cmd == SIOCSMIIREG)) {
2753 if (duplex_chg)
2754 jme_reset_link(jme);
2755 jme_get_settings(netdev, &jme->old_ecmd);
2756 set_bit(JME_FLAG_SSET, &jme->flags);
2757 }
2758
2759 return rc;
2760}
2761
2762static u32
2763jme_get_link(struct net_device *netdev)
2764{
2765 struct jme_adapter *jme = netdev_priv(netdev);
2766 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2767}
2768
2769static u32
2770jme_get_msglevel(struct net_device *netdev)
2771{
2772 struct jme_adapter *jme = netdev_priv(netdev);
2773 return jme->msg_enable;
2774}
2775
2776static void
2777jme_set_msglevel(struct net_device *netdev, u32 value)
2778{
2779 struct jme_adapter *jme = netdev_priv(netdev);
2780 jme->msg_enable = value;
2781}
2782
2783#ifndef __USE_NDO_FIX_FEATURES__
2784static u32
2785jme_get_rx_csum(struct net_device *netdev)
2786{
2787 struct jme_adapter *jme = netdev_priv(netdev);
2788 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2789}
2790
2791static int
2792jme_set_rx_csum(struct net_device *netdev, u32 on)
2793{
2794 struct jme_adapter *jme = netdev_priv(netdev);
2795
2796 spin_lock_bh(&jme->rxmcs_lock);
2797 if (on)
2798 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2799 else
2800 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2801 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2802 spin_unlock_bh(&jme->rxmcs_lock);
2803
2804 return 0;
2805}
2806
2807static int
2808jme_set_tx_csum(struct net_device *netdev, u32 on)
2809{
2810 struct jme_adapter *jme = netdev_priv(netdev);
2811
2812 if (on) {
2813 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2814 if (netdev->mtu <= 1900)
2815 netdev->features |=
2816 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2817 } else {
2818 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2819 netdev->features &=
2820 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2821 }
2822
2823 return 0;
2824}
2825
2826static int
2827jme_set_tso(struct net_device *netdev, u32 on)
2828{
2829 struct jme_adapter *jme = netdev_priv(netdev);
2830
2831 if (on) {
2832 set_bit(JME_FLAG_TSO, &jme->flags);
2833 if (netdev->mtu <= 1900)
2834 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2835 } else {
2836 clear_bit(JME_FLAG_TSO, &jme->flags);
2837 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2838 }
2839
2840 return 0;
2841}
2842#else
2843static u32
2844jme_fix_features(struct net_device *netdev, u32 features)
2845{
2846 if (netdev->mtu > 1900)
2847 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2848 return features;
2849}
2850
2851static int
2852jme_set_features(struct net_device *netdev, u32 features)
2853{
2854 struct jme_adapter *jme = netdev_priv(netdev);
2855
2856 spin_lock_bh(&jme->rxmcs_lock);
2857 if (features & NETIF_F_RXCSUM)
2858 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2859 else
2860 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2861 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2862 spin_unlock_bh(&jme->rxmcs_lock);
2863
2864 return 0;
2865}
2866#endif
2867
2868static int
2869jme_nway_reset(struct net_device *netdev)
2870{
2871 struct jme_adapter *jme = netdev_priv(netdev);
2872 jme_restart_an(jme);
2873 return 0;
2874}
2875
2876static u8
2877jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2878{
2879 u32 val;
2880 int to;
2881
2882 val = jread32(jme, JME_SMBCSR);
2883 to = JME_SMB_BUSY_TIMEOUT;
2884 while ((val & SMBCSR_BUSY) && --to) {
2885 msleep(1);
2886 val = jread32(jme, JME_SMBCSR);
2887 }
2888 if (!to) {
2889 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2890 return 0xFF;
2891 }
2892
2893 jwrite32(jme, JME_SMBINTF,
2894 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2895 SMBINTF_HWRWN_READ |
2896 SMBINTF_HWCMD);
2897
2898 val = jread32(jme, JME_SMBINTF);
2899 to = JME_SMB_BUSY_TIMEOUT;
2900 while ((val & SMBINTF_HWCMD) && --to) {
2901 msleep(1);
2902 val = jread32(jme, JME_SMBINTF);
2903 }
2904 if (!to) {
2905 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2906 return 0xFF;
2907 }
2908
2909 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2910}
2911
2912static void
2913jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2914{
2915 u32 val;
2916 int to;
2917
2918 val = jread32(jme, JME_SMBCSR);
2919 to = JME_SMB_BUSY_TIMEOUT;
2920 while ((val & SMBCSR_BUSY) && --to) {
2921 msleep(1);
2922 val = jread32(jme, JME_SMBCSR);
2923 }
2924 if (!to) {
2925 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2926 return;
2927 }
2928
2929 jwrite32(jme, JME_SMBINTF,
2930 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2931 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2932 SMBINTF_HWRWN_WRITE |
2933 SMBINTF_HWCMD);
2934
2935 val = jread32(jme, JME_SMBINTF);
2936 to = JME_SMB_BUSY_TIMEOUT;
2937 while ((val & SMBINTF_HWCMD) && --to) {
2938 msleep(1);
2939 val = jread32(jme, JME_SMBINTF);
2940 }
2941 if (!to) {
2942 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2943 return;
2944 }
2945
2946 mdelay(2);
2947}
2948
2949static int
2950jme_get_eeprom_len(struct net_device *netdev)
2951{
2952 struct jme_adapter *jme = netdev_priv(netdev);
2953 u32 val;
2954 val = jread32(jme, JME_SMBCSR);
2955 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2956}
2957
2958static int
2959jme_get_eeprom(struct net_device *netdev,
2960 struct ethtool_eeprom *eeprom, u8 *data)
2961{
2962 struct jme_adapter *jme = netdev_priv(netdev);
2963 int i, offset = eeprom->offset, len = eeprom->len;
2964
2965 /*
2966 * ethtool will check the boundary for us
2967 */
2968 eeprom->magic = JME_EEPROM_MAGIC;
2969 for (i = 0 ; i < len ; ++i)
2970 data[i] = jme_smb_read(jme, i + offset);
2971
2972 return 0;
2973}
2974
2975static int
2976jme_set_eeprom(struct net_device *netdev,
2977 struct ethtool_eeprom *eeprom, u8 *data)
2978{
2979 struct jme_adapter *jme = netdev_priv(netdev);
2980 int i, offset = eeprom->offset, len = eeprom->len;
2981
2982 if (eeprom->magic != JME_EEPROM_MAGIC)
2983 return -EINVAL;
2984
2985 /*
2986 * ethtool will check the boundary for us
2987 */
2988 for (i = 0 ; i < len ; ++i)
2989 jme_smb_write(jme, i + offset, data[i]);
2990
2991 return 0;
2992}
2993
2994#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2995static struct ethtool_ops jme_ethtool_ops = {
2996#else
2997static const struct ethtool_ops jme_ethtool_ops = {
2998#endif
2999 .get_drvinfo = jme_get_drvinfo,
3000 .get_regs_len = jme_get_regs_len,
3001 .get_regs = jme_get_regs,
3002 .get_coalesce = jme_get_coalesce,
3003 .set_coalesce = jme_set_coalesce,
3004 .get_pauseparam = jme_get_pauseparam,
3005 .set_pauseparam = jme_set_pauseparam,
3006 .get_wol = jme_get_wol,
3007 .set_wol = jme_set_wol,
3008 .get_settings = jme_get_settings,
3009 .set_settings = jme_set_settings,
3010 .get_link = jme_get_link,
3011 .get_msglevel = jme_get_msglevel,
3012 .set_msglevel = jme_set_msglevel,
3013#ifndef __USE_NDO_FIX_FEATURES__
3014 .get_rx_csum = jme_get_rx_csum,
3015 .set_rx_csum = jme_set_rx_csum,
3016 .set_tx_csum = jme_set_tx_csum,
3017 .set_tso = jme_set_tso,
3018 .set_sg = ethtool_op_set_sg,
3019#endif
3020 .nway_reset = jme_nway_reset,
3021 .get_eeprom_len = jme_get_eeprom_len,
3022 .get_eeprom = jme_get_eeprom,
3023 .set_eeprom = jme_set_eeprom,
3024};
3025
3026static int
3027jme_pci_dma64(struct pci_dev *pdev)
3028{
3029 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3030#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3031 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
3032#else
3033 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
3034#endif
3035 )
3036#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3037 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3038#else
3039 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
3040#endif
3041 return 1;
3042
3043 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3044#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3045 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3046#else
3047 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3048#endif
3049 )
3050#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3051 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3052#else
3053 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
3054#endif
3055 return 1;
3056
3057#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3058 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3059 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3060#else
3061 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3062 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3063#endif
3064 return 0;
3065
3066 return -1;
3067}
3068
3069static inline void
3070jme_phy_init(struct jme_adapter *jme)
3071{
3072 u16 reg26;
3073
3074 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3075 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3076}
3077
3078static inline void
3079jme_check_hw_ver(struct jme_adapter *jme)
3080{
3081 u32 chipmode;
3082
3083 chipmode = jread32(jme, JME_CHIPMODE);
3084
3085 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3086 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3087 jme->chip_main_rev = jme->chiprev & 0xF;
3088 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3089}
3090
3091#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3092static const struct net_device_ops jme_netdev_ops = {
3093 .ndo_open = jme_open,
3094 .ndo_stop = jme_close,
3095 .ndo_validate_addr = eth_validate_addr,
3096 .ndo_do_ioctl = jme_ioctl,
3097 .ndo_start_xmit = jme_start_xmit,
3098 .ndo_set_mac_address = jme_set_macaddr,
3099 .ndo_set_multicast_list = jme_set_multi,
3100 .ndo_change_mtu = jme_change_mtu,
3101 .ndo_tx_timeout = jme_tx_timeout,
3102 .ndo_vlan_rx_register = jme_vlan_rx_register,
3103#ifdef __USE_NDO_FIX_FEATURES__
3104 .ndo_fix_features = jme_fix_features,
3105 .ndo_set_features = jme_set_features,
3106#endif
3107};
3108#endif
3109
3110static int __devinit
3111jme_init_one(struct pci_dev *pdev,
3112 const struct pci_device_id *ent)
3113{
3114 int rc = 0, using_dac, i;
3115 struct net_device *netdev;
3116 struct jme_adapter *jme;
3117 u16 bmcr, bmsr;
3118 u32 apmc;
3119
3120 /*
3121 * set up PCI device basics
3122 */
3123 rc = pci_enable_device(pdev);
3124 if (rc) {
3125 pr_err("Cannot enable PCI device\n");
3126 goto err_out;
3127 }
3128
3129 using_dac = jme_pci_dma64(pdev);
3130 if (using_dac < 0) {
3131 pr_err("Cannot set PCI DMA Mask\n");
3132 rc = -EIO;
3133 goto err_out_disable_pdev;
3134 }
3135
3136 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3137 pr_err("No PCI resource region found\n");
3138 rc = -ENOMEM;
3139 goto err_out_disable_pdev;
3140 }
3141
3142 rc = pci_request_regions(pdev, DRV_NAME);
3143 if (rc) {
3144 pr_err("Cannot obtain PCI resource region\n");
3145 goto err_out_disable_pdev;
3146 }
3147
3148 pci_set_master(pdev);
3149
3150 /*
3151 * alloc and init net device
3152 */
3153 netdev = alloc_etherdev(sizeof(*jme));
3154 if (!netdev) {
3155 pr_err("Cannot allocate netdev structure\n");
3156 rc = -ENOMEM;
3157 goto err_out_release_regions;
3158 }
3159#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3160 netdev->netdev_ops = &jme_netdev_ops;
3161#else
3162 netdev->open = jme_open;
3163 netdev->stop = jme_close;
3164 netdev->do_ioctl = jme_ioctl;
3165 netdev->hard_start_xmit = jme_start_xmit;
3166 netdev->set_mac_address = jme_set_macaddr;
3167 netdev->set_multicast_list = jme_set_multi;
3168 netdev->change_mtu = jme_change_mtu;
3169 netdev->tx_timeout = jme_tx_timeout;
3170 netdev->vlan_rx_register = jme_vlan_rx_register;
3171#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3172 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3173#endif
3174 NETDEV_GET_STATS(netdev, &jme_get_stats);
3175#endif
3176 netdev->ethtool_ops = &jme_ethtool_ops;
3177 netdev->watchdog_timeo = TX_TIMEOUT;
3178#ifdef __USE_NDO_FIX_FEATURES__
3179 netdev->hw_features = NETIF_F_IP_CSUM |
3180 NETIF_F_IPV6_CSUM |
3181 NETIF_F_SG |
3182 NETIF_F_TSO |
3183 NETIF_F_TSO6 |
3184 NETIF_F_RXCSUM;
3185#endif
3186 netdev->features = NETIF_F_IP_CSUM |
3187 NETIF_F_IPV6_CSUM |
3188 NETIF_F_SG |
3189 NETIF_F_TSO |
3190 NETIF_F_TSO6 |
3191 NETIF_F_HW_VLAN_TX |
3192 NETIF_F_HW_VLAN_RX;
3193 if (using_dac)
3194 netdev->features |= NETIF_F_HIGHDMA;
3195
3196 SET_NETDEV_DEV(netdev, &pdev->dev);
3197 pci_set_drvdata(pdev, netdev);
3198
3199 /*
3200 * init adapter info
3201 */
3202 jme = netdev_priv(netdev);
3203 jme->pdev = pdev;
3204 jme->dev = netdev;
3205 jme->jme_rx = netif_rx;
3206 jme->jme_vlan_rx = vlan_hwaccel_rx;
3207 jme->old_mtu = netdev->mtu = 1500;
3208 jme->phylink = 0;
3209 jme->tx_ring_size = 1 << 10;
3210 jme->tx_ring_mask = jme->tx_ring_size - 1;
3211 jme->tx_wake_threshold = 1 << 9;
3212 jme->rx_ring_size = 1 << 9;
3213 jme->rx_ring_mask = jme->rx_ring_size - 1;
3214 jme->msg_enable = JME_DEF_MSG_ENABLE;
3215 jme->regs = ioremap(pci_resource_start(pdev, 0),
3216 pci_resource_len(pdev, 0));
3217 if (!(jme->regs)) {
3218 pr_err("Mapping PCI resource region error\n");
3219 rc = -ENOMEM;
3220 goto err_out_free_netdev;
3221 }
3222
3223 if (no_pseudohp) {
3224 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3225 jwrite32(jme, JME_APMC, apmc);
3226 } else if (force_pseudohp) {
3227 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3228 jwrite32(jme, JME_APMC, apmc);
3229 }
3230
3231 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3232
3233 spin_lock_init(&jme->phy_lock);
3234 spin_lock_init(&jme->macaddr_lock);
3235 spin_lock_init(&jme->rxmcs_lock);
3236
3237 atomic_set(&jme->link_changing, 1);
3238 atomic_set(&jme->rx_cleaning, 1);
3239 atomic_set(&jme->tx_cleaning, 1);
3240 atomic_set(&jme->rx_empty, 1);
3241
3242 tasklet_init(&jme->pcc_task,
3243 jme_pcc_tasklet,
3244 (unsigned long) jme);
3245 tasklet_init(&jme->linkch_task,
3246 jme_link_change_tasklet,
3247 (unsigned long) jme);
3248 tasklet_init(&jme->txclean_task,
3249 jme_tx_clean_tasklet,
3250 (unsigned long) jme);
3251 tasklet_init(&jme->rxclean_task,
3252 jme_rx_clean_tasklet,
3253 (unsigned long) jme);
3254 tasklet_init(&jme->rxempty_task,
3255 jme_rx_empty_tasklet,
3256 (unsigned long) jme);
3257 tasklet_disable_nosync(&jme->linkch_task);
3258 tasklet_disable_nosync(&jme->txclean_task);
3259 tasklet_disable_nosync(&jme->rxclean_task);
3260 tasklet_disable_nosync(&jme->rxempty_task);
3261 jme->dpi.cur = PCC_P1;
3262
3263 jme->reg_ghc = 0;
3264 jme->reg_rxcs = RXCS_DEFAULT;
3265 jme->reg_rxmcs = RXMCS_DEFAULT;
3266 jme->reg_txpfc = 0;
3267 jme->reg_pmcs = PMCS_MFEN;
3268 jme->reg_gpreg1 = GPREG1_DEFAULT;
3269#ifndef __USE_NDO_FIX_FEATURES__
3270 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3271 set_bit(JME_FLAG_TSO, &jme->flags);
3272#else
3273
3274 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3275 netdev->features |= NETIF_F_RXCSUM;
3276#endif
3277
3278 /*
3279 * Get Max Read Req Size from PCI Config Space
3280 */
3281 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3282 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3283 switch (jme->mrrs) {
3284 case MRRS_128B:
3285 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3286 break;
3287 case MRRS_256B:
3288 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3289 break;
3290 default:
3291 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3292 break;
3293 }
3294
3295 /*
3296 * Must check before reset_mac_processor
3297 */
3298 jme_check_hw_ver(jme);
3299 jme->mii_if.dev = netdev;
3300 if (jme->fpgaver) {
3301 jme->mii_if.phy_id = 0;
3302 for (i = 1 ; i < 32 ; ++i) {
3303 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3304 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3305 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3306 jme->mii_if.phy_id = i;
3307 break;
3308 }
3309 }
3310
3311 if (!jme->mii_if.phy_id) {
3312 rc = -EIO;
3313 pr_err("Can not find phy_id\n");
3314 goto err_out_unmap;
3315 }
3316
3317 jme->reg_ghc |= GHC_LINK_POLL;
3318 } else {
3319 jme->mii_if.phy_id = 1;
3320 }
3321 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3322 jme->mii_if.supports_gmii = true;
3323 else
3324 jme->mii_if.supports_gmii = false;
3325 jme->mii_if.phy_id_mask = 0x1F;
3326 jme->mii_if.reg_num_mask = 0x1F;
3327 jme->mii_if.mdio_read = jme_mdio_read;
3328 jme->mii_if.mdio_write = jme_mdio_write;
3329
3330 jme_clear_pm(jme);
3331 pci_set_power_state(jme->pdev, PCI_D0);
3332#ifndef JME_NEW_PM_API
3333 jme_pci_wakeup_enable(jme, true);
3334#endif
3335#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3336 device_set_wakeup_enable(&pdev->dev, true);
3337#endif
3338
3339 jme_set_phyfifo_5level(jme);
3340#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
3341 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3342#else
3343 jme->pcirev = pdev->revision;
3344#endif
3345 if (!jme->fpgaver)
3346 jme_phy_init(jme);
3347 jme_phy_off(jme);
3348
3349 /*
3350 * Reset MAC processor and reload EEPROM for MAC Address
3351 */
3352 jme_reset_mac_processor(jme);
3353 rc = jme_reload_eeprom(jme);
3354 if (rc) {
3355 pr_err("Reload eeprom for reading MAC Address error\n");
3356 goto err_out_unmap;
3357 }
3358 jme_load_macaddr(netdev);
3359
3360 /*
3361 * Tell stack that we are not ready to work until open()
3362 */
3363 netif_carrier_off(netdev);
3364
3365 rc = register_netdev(netdev);
3366 if (rc) {
3367 pr_err("Cannot register net device\n");
3368 goto err_out_unmap;
3369 }
3370
3371 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3372 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3373 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3374 "JMC250 Gigabit Ethernet" :
3375 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3376 "JMC260 Fast Ethernet" : "Unknown",
3377 (jme->fpgaver != 0) ? " (FPGA)" : "",
3378 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3379 jme->pcirev,
3380 netdev->dev_addr[0],
3381 netdev->dev_addr[1],
3382 netdev->dev_addr[2],
3383 netdev->dev_addr[3],
3384 netdev->dev_addr[4],
3385 netdev->dev_addr[5]);
3386
3387 return 0;
3388
3389err_out_unmap:
3390 iounmap(jme->regs);
3391err_out_free_netdev:
3392 pci_set_drvdata(pdev, NULL);
3393 free_netdev(netdev);
3394err_out_release_regions:
3395 pci_release_regions(pdev);
3396err_out_disable_pdev:
3397 pci_disable_device(pdev);
3398err_out:
3399 return rc;
3400}
3401
3402static void __devexit
3403jme_remove_one(struct pci_dev *pdev)
3404{
3405 struct net_device *netdev = pci_get_drvdata(pdev);
3406 struct jme_adapter *jme = netdev_priv(netdev);
3407
3408 unregister_netdev(netdev);
3409 iounmap(jme->regs);
3410 pci_set_drvdata(pdev, NULL);
3411 free_netdev(netdev);
3412 pci_release_regions(pdev);
3413 pci_disable_device(pdev);
3414
3415}
3416
3417static void
3418jme_shutdown(struct pci_dev *pdev)
3419{
3420 struct net_device *netdev = pci_get_drvdata(pdev);
3421 struct jme_adapter *jme = netdev_priv(netdev);
3422
3423 jme_powersave_phy(jme);
3424#ifndef JME_NEW_PM_API
3425 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3426#endif
3427#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3428 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
3429#endif
3430}
3431
3432#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3433 #ifdef CONFIG_PM
3434 #define JME_HAVE_PM
3435 #endif
3436#else
3437 #ifdef CONFIG_PM_SLEEP
3438 #define JME_HAVE_PM
3439 #endif
3440#endif
3441
3442#ifdef JME_HAVE_PM
3443static int
3444#ifdef JME_NEW_PM_API
3445jme_suspend(struct device *dev)
3446#else
3447jme_suspend(struct pci_dev *pdev, pm_message_t state)
3448#endif
3449{
3450#ifdef JME_NEW_PM_API
3451 struct pci_dev *pdev = to_pci_dev(dev);
3452#endif
3453 struct net_device *netdev = pci_get_drvdata(pdev);
3454 struct jme_adapter *jme = netdev_priv(netdev);
3455
3456 atomic_dec(&jme->link_changing);
3457
3458 netif_device_detach(netdev);
3459 netif_stop_queue(netdev);
3460 jme_stop_irq(jme);
3461
3462 tasklet_disable(&jme->txclean_task);
3463 tasklet_disable(&jme->rxclean_task);
3464 tasklet_disable(&jme->rxempty_task);
3465
3466 if (netif_carrier_ok(netdev)) {
3467 if (test_bit(JME_FLAG_POLL, &jme->flags))
3468 jme_polling_mode(jme);
3469
3470 jme_stop_pcc_timer(jme);
3471 jme_disable_rx_engine(jme);
3472 jme_disable_tx_engine(jme);
3473 jme_reset_mac_processor(jme);
3474 jme_free_rx_resources(jme);
3475 jme_free_tx_resources(jme);
3476 netif_carrier_off(netdev);
3477 jme->phylink = 0;
3478 }
3479
3480 tasklet_enable(&jme->txclean_task);
3481 tasklet_hi_enable(&jme->rxclean_task);
3482 tasklet_hi_enable(&jme->rxempty_task);
3483
3484 jme_powersave_phy(jme);
3485#ifndef JME_NEW_PM_API
3486 pci_save_state(pdev);
3487 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3488 pci_set_power_state(pdev, PCI_D3hot);
3489#endif
3490
3491 return 0;
3492}
3493
3494static int
3495#ifdef JME_NEW_PM_API
3496jme_resume(struct device *dev)
3497#else
3498jme_resume(struct pci_dev *pdev)
3499#endif
3500{
3501#ifdef JME_NEW_PM_API
3502 struct pci_dev *pdev = to_pci_dev(dev);
3503#endif
3504 struct net_device *netdev = pci_get_drvdata(pdev);
3505 struct jme_adapter *jme = netdev_priv(netdev);
3506
3507 jme_clear_pm(jme);
3508#ifndef JME_NEW_PM_API
3509 pci_set_power_state(pdev, PCI_D0);
3510 pci_restore_state(pdev);
3511#endif
3512
3513 jme_phy_on(jme);
3514 if (test_bit(JME_FLAG_SSET, &jme->flags))
3515 jme_set_settings(netdev, &jme->old_ecmd);
3516 else
3517 jme_reset_phy_processor(jme);
3518
3519 jme_start_irq(jme);
3520 netif_device_attach(netdev);
3521
3522 atomic_inc(&jme->link_changing);
3523
3524 jme_reset_link(jme);
3525
3526 return 0;
3527}
3528
3529#ifdef JME_NEW_PM_API
3530static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3531#define JME_PM_OPS (&jme_pm_ops)
3532#endif
3533
3534#else
3535
3536#ifdef JME_NEW_PM_API
3537#define JME_PM_OPS NULL
3538#endif
3539#endif
3540
3541#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3542static struct pci_device_id jme_pci_tbl[] = {
3543#else
3544static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3545#endif
3546 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3547 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3548 { }
3549};
3550
3551static struct pci_driver jme_driver = {
3552 .name = DRV_NAME,
3553 .id_table = jme_pci_tbl,
3554 .probe = jme_init_one,
3555 .remove = __devexit_p(jme_remove_one),
3556 .shutdown = jme_shutdown,
3557#ifndef JME_NEW_PM_API
3558 .suspend = jme_suspend,
3559 .resume = jme_resume
3560#else
3561 .driver.pm = JME_PM_OPS,
3562#endif
3563};
3564
3565static int __init
3566jme_init_module(void)
3567{
3568 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3569 return pci_register_driver(&jme_driver);
3570}
3571
3572static void __exit
3573jme_cleanup_module(void)
3574{
3575 pci_unregister_driver(&jme_driver);
3576}
3577
3578module_init(jme_init_module);
3579module_exit(jme_cleanup_module);
3580
3581MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3582MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3583MODULE_LICENSE("GPL");
3584MODULE_VERSION(DRV_VERSION);
3585MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3586
JMicron Ethernet Linux driver