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Fix pci_dma_mapping_error prototype for older kernel
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/version.h>
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
38#include <linux/delay.h>
39#include <linux/spinlock.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/if_vlan.h>
46#include <linux/slab.h>
47#include <net/ip6_checksum.h>
48#include "jme.h"
49
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
61
62#ifndef JME_NEW_PM_API
63static void
64jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65{
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71#else
72 pci_pme_active(jme->pdev, enable);
73#endif
74}
75#endif
76
77static int
78jme_mdio_read(struct net_device *netdev, int phy, int reg)
79{
80 struct jme_adapter *jme = netdev_priv(netdev);
81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
82
83read_again:
84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
85 smi_phy_addr(phy) |
86 smi_reg_addr(reg));
87
88 wmb();
89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
90 udelay(20);
91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
93 break;
94 }
95
96 if (i == 0) {
97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
98 return 0;
99 }
100
101 if (again--)
102 goto read_again;
103
104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
105}
106
107static void
108jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
110{
111 struct jme_adapter *jme = netdev_priv(netdev);
112 int i;
113
114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
117
118 wmb();
119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
120 udelay(20);
121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
122 break;
123 }
124
125 if (i == 0)
126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
127}
128
129static inline void
130jme_reset_phy_processor(struct jme_adapter *jme)
131{
132 u32 val;
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
138
139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
142 MII_CTRL1000,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
144
145 val = jme_mdio_read(jme->dev,
146 jme->mii_if.phy_id,
147 MII_BMCR);
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_BMCR, val | BMCR_RESET);
152}
153
154static void
155jme_setup_wakeup_frame(struct jme_adapter *jme,
156 const u32 *mask, u32 crc, int fnr)
157{
158 int i;
159
160 /*
161 * Setup CRC pattern
162 */
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
164 wmb();
165 jwrite32(jme, JME_WFODP, crc);
166 wmb();
167
168 /*
169 * Setup Mask
170 */
171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
175 wmb();
176 jwrite32(jme, JME_WFODP, mask[i]);
177 wmb();
178 }
179}
180
181static inline void
182jme_mac_rxclk_off(struct jme_adapter *jme)
183{
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
186}
187
188static inline void
189jme_mac_rxclk_on(struct jme_adapter *jme)
190{
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
193}
194
195static inline void
196jme_mac_txclk_off(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_mac_txclk_on(struct jme_adapter *jme)
204{
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
208 else
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
211}
212
213static inline void
214jme_reset_ghc_speed(struct jme_adapter *jme)
215{
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_reset_250A2_workaround(struct jme_adapter *jme)
222{
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
224 GPREG1_RSSPATCH);
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
226}
227
228static inline void
229jme_assert_ghc_reset(struct jme_adapter *jme)
230{
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_clear_ghc_reset(struct jme_adapter *jme)
237{
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
240}
241
242static inline void
243jme_reset_mac_processor(struct jme_adapter *jme)
244{
245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
246 u32 crc = 0xCDCDCDCD;
247 u32 gpreg0;
248 int i;
249
250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
252
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
255 udelay(1);
256 jme_assert_ghc_reset(jme);
257 udelay(1);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
260 udelay(1);
261 jme_clear_ghc_reset(jme);
262 udelay(1);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
265 udelay(1);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
268
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
277
278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
281 jme_setup_wakeup_frame(jme, mask, crc, i);
282 if (jme->fpgaver)
283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
284 else
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
287}
288
289static inline void
290jme_clear_pm(struct jme_adapter *jme)
291{
292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
293}
294
295static int
296jme_reload_eeprom(struct jme_adapter *jme)
297{
298 u32 val;
299 int i;
300
301 val = jread32(jme, JME_SMBCSR);
302
303 if (val & SMBCSR_EEPROMD) {
304 val |= SMBCSR_CNACK;
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
308 mdelay(12);
309
310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
311 mdelay(1);
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
313 break;
314 }
315
316 if (i == 0) {
317 pr_err("eeprom reload timeout\n");
318 return -EIO;
319 }
320 }
321
322 return 0;
323}
324
325static void
326jme_load_macaddr(struct net_device *netdev)
327{
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
330 u32 val;
331
332 spin_lock_bh(&jme->macaddr_lock);
333 val = jread32(jme, JME_RXUMA_LO);
334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
338 val = jread32(jme, JME_RXUMA_HI);
339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
343}
344
345static inline void
346jme_set_rx_pcc(struct jme_adapter *jme, int p)
347{
348 switch (p) {
349 case PCC_OFF:
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 break;
354 case PCC_P1:
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 break;
359 case PCC_P2:
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 break;
364 case PCC_P3:
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
368 break;
369 default:
370 break;
371 }
372 wmb();
373
374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
376}
377
378static void
379jme_start_irq(struct jme_adapter *jme)
380{
381 register struct dynpcc_info *dpi = &(jme->dpi);
382
383 jme_set_rx_pcc(jme, PCC_P1);
384 dpi->cur = PCC_P1;
385 dpi->attempt = PCC_P1;
386 dpi->cnt = 0;
387
388 jwrite32(jme, JME_PCCTX,
389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
391 PCCTXQ0_EN
392 );
393
394 /*
395 * Enable Interrupts
396 */
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
398}
399
400static inline void
401jme_stop_irq(struct jme_adapter *jme)
402{
403 /*
404 * Disable Interrupts
405 */
406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
407}
408
409static u32
410jme_linkstat_from_phy(struct jme_adapter *jme)
411{
412 u32 phylink, bmsr;
413
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
416 if (bmsr & BMSR_ANCOMP)
417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
418
419 return phylink;
420}
421
422static inline void
423jme_set_phyfifo_5level(struct jme_adapter *jme)
424{
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
426}
427
428static inline void
429jme_set_phyfifo_8level(struct jme_adapter *jme)
430{
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
432}
433
434static int
435jme_check_link(struct net_device *netdev, int testonly)
436{
437 struct jme_adapter *jme = netdev_priv(netdev);
438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
439 char linkmsg[64];
440 int rc = 0;
441
442 linkmsg[0] = '\0';
443
444 if (jme->fpgaver)
445 phylink = jme_linkstat_from_phy(jme);
446 else
447 phylink = jread32(jme, JME_PHY_LINK);
448
449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
451 /*
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
454 */
455 phylink = PHY_LINK_UP;
456
457 bmcr = jme_mdio_read(jme->dev,
458 jme->mii_if.phy_id,
459 MII_BMCR);
460
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
466 PHY_LINK_SPEED_10M;
467
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 PHY_LINK_DUPLEX : 0;
470
471 strcat(linkmsg, "Forced: ");
472 } else {
473 /*
474 * Keep polling for speed/duplex resolve complete
475 */
476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
477 --cnt) {
478
479 udelay(1);
480
481 if (jme->fpgaver)
482 phylink = jme_linkstat_from_phy(jme);
483 else
484 phylink = jread32(jme, JME_PHY_LINK);
485 }
486 if (!cnt)
487 pr_err("Waiting speed resolve timeout\n");
488
489 strcat(linkmsg, "ANed: ");
490 }
491
492 if (jme->phylink == phylink) {
493 rc = 1;
494 goto out;
495 }
496 if (testonly)
497 goto out;
498
499 jme->phylink = phylink;
500
501 /*
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
504 */
505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
507 jme->reg_ghc |= GHC_SPEED_10M;
508 strcat(linkmsg, "10 Mbps, ");
509 break;
510 case PHY_LINK_SPEED_100M:
511 jme->reg_ghc |= GHC_SPEED_100M;
512 strcat(linkmsg, "100 Mbps, ");
513 break;
514 case PHY_LINK_SPEED_1000M:
515 jme->reg_ghc |= GHC_SPEED_1000M;
516 strcat(linkmsg, "1000 Mbps, ");
517 break;
518 default:
519 break;
520 }
521
522 if (phylink & PHY_LINK_DUPLEX) {
523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
525 jme->reg_ghc |= GHC_DPX;
526 } else {
527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
528 TXMCS_BACKOFF |
529 TXMCS_CARRIERSENSE |
530 TXMCS_COLLISION);
531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
532 }
533
534 jwrite32(jme, JME_GHC, jme->reg_ghc);
535
536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
538 GPREG1_RSSPATCH);
539 if (!(phylink & PHY_LINK_DUPLEX))
540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
543 jme_set_phyfifo_8level(jme);
544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
545 break;
546 case PHY_LINK_SPEED_100M:
547 jme_set_phyfifo_5level(jme);
548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
549 break;
550 case PHY_LINK_SPEED_1000M:
551 jme_set_phyfifo_8level(jme);
552 break;
553 default:
554 break;
555 }
556 }
557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
558
559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 "Full-Duplex, " :
561 "Half-Duplex, ");
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 "MDI-X" :
564 "MDI");
565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
566 netif_carrier_on(netdev);
567 } else {
568 if (testonly)
569 goto out;
570
571 netif_info(jme, link, jme->dev, "Link is down\n");
572 jme->phylink = 0;
573 netif_carrier_off(netdev);
574 }
575
576out:
577 return rc;
578}
579
580static int
581jme_setup_tx_resources(struct jme_adapter *jme)
582{
583 struct jme_ring *txring = &(jme->txring[0]);
584
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
587 &(txring->dmaalloc),
588 GFP_ATOMIC);
589
590 if (!txring->alloc)
591 goto err_set_null;
592
593 /*
594 * 16 Bytes align
595 */
596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
597 RING_DESC_ALIGN);
598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
599 txring->next_to_use = 0;
600 atomic_set(&txring->next_to_clean, 0);
601 atomic_set(&txring->nr_free, jme->tx_ring_size);
602
603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
607
608 /*
609 * Initialize Transmit Descriptors
610 */
611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
612 memset(txring->bufinf, 0,
613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
614
615 return 0;
616
617err_free_txring:
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
620 txring->alloc,
621 txring->dmaalloc);
622
623err_set_null:
624 txring->desc = NULL;
625 txring->dmaalloc = 0;
626 txring->dma = 0;
627 txring->bufinf = NULL;
628
629 return -ENOMEM;
630}
631
632static void
633jme_free_tx_resources(struct jme_adapter *jme)
634{
635 int i;
636 struct jme_ring *txring = &(jme->txring[0]);
637 struct jme_buffer_info *txbi;
638
639 if (txring->alloc) {
640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
643 if (txbi->skb) {
644 dev_kfree_skb(txbi->skb);
645 txbi->skb = NULL;
646 }
647 txbi->mapping = 0;
648 txbi->len = 0;
649 txbi->nr_desc = 0;
650 txbi->start_xmit = 0;
651 }
652 kfree(txring->bufinf);
653 }
654
655 dma_free_coherent(&(jme->pdev->dev),
656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
657 txring->alloc,
658 txring->dmaalloc);
659
660 txring->alloc = NULL;
661 txring->desc = NULL;
662 txring->dmaalloc = 0;
663 txring->dma = 0;
664 txring->bufinf = NULL;
665 }
666 txring->next_to_use = 0;
667 atomic_set(&txring->next_to_clean, 0);
668 atomic_set(&txring->nr_free, 0);
669}
670
671static inline void
672jme_enable_tx_engine(struct jme_adapter *jme)
673{
674 /*
675 * Select Queue 0
676 */
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
678 wmb();
679
680 /*
681 * Setup TX Queue 0 DMA Bass Address
682 */
683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
686
687 /*
688 * Setup TX Descptor Count
689 */
690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
691
692 /*
693 * Enable TX Engine
694 */
695 wmb();
696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
699
700 /*
701 * Start clock for TX MAC Processor
702 */
703 jme_mac_txclk_on(jme);
704}
705
706static inline void
707jme_restart_tx_engine(struct jme_adapter *jme)
708{
709 /*
710 * Restart TX Engine
711 */
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
713 TXCS_SELECT_QUEUE0 |
714 TXCS_ENABLE);
715}
716
717static inline void
718jme_disable_tx_engine(struct jme_adapter *jme)
719{
720 int i;
721 u32 val;
722
723 /*
724 * Disable TX Engine
725 */
726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
727 wmb();
728
729 val = jread32(jme, JME_TXCS);
730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
731 mdelay(1);
732 val = jread32(jme, JME_TXCS);
733 rmb();
734 }
735
736 if (!i)
737 pr_err("Disable TX engine timeout\n");
738
739 /*
740 * Stop clock for TX MAC Processor
741 */
742 jme_mac_txclk_off(jme);
743}
744
745static void
746jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
747{
748 struct jme_ring *rxring = &(jme->rxring[0]);
749 register struct rxdesc *rxdesc = rxring->desc;
750 struct jme_buffer_info *rxbi = rxring->bufinf;
751 rxdesc += i;
752 rxbi += i;
753
754 rxdesc->dw[0] = 0;
755 rxdesc->dw[1] = 0;
756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
760 if (jme->dev->features & NETIF_F_HIGHDMA)
761 rxdesc->desc1.flags = RXFLAG_64BIT;
762 wmb();
763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
764}
765
766static int
767jme_make_new_rx_buf(struct jme_adapter *jme, int i)
768{
769 struct jme_ring *rxring = &(jme->rxring[0]);
770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
771 struct sk_buff *skb;
772 dma_addr_t mapping;
773
774 skb = netdev_alloc_skb(jme->dev,
775 jme->dev->mtu + RX_EXTRA_LEN);
776 if (unlikely(!skb))
777 return -ENOMEM;
778#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
779 skb->dev = jme->dev;
780#endif
781
782 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
783 offset_in_page(skb->data), skb_tailroom(skb),
784 PCI_DMA_FROMDEVICE);
785#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
786 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping)))
787#else
788 if (unlikely(pci_dma_mapping_error(mapping)))
789#endif
790 {
791 dev_kfree_skb(skb);
792 return -ENOMEM;
793 }
794
795 if (likely(rxbi->mapping))
796 pci_unmap_page(jme->pdev, rxbi->mapping,
797 rxbi->len, PCI_DMA_FROMDEVICE);
798
799 rxbi->skb = skb;
800 rxbi->len = skb_tailroom(skb);
801 rxbi->mapping = mapping;
802 return 0;
803}
804
805static void
806jme_free_rx_buf(struct jme_adapter *jme, int i)
807{
808 struct jme_ring *rxring = &(jme->rxring[0]);
809 struct jme_buffer_info *rxbi = rxring->bufinf;
810 rxbi += i;
811
812 if (rxbi->skb) {
813 pci_unmap_page(jme->pdev,
814 rxbi->mapping,
815 rxbi->len,
816 PCI_DMA_FROMDEVICE);
817 dev_kfree_skb(rxbi->skb);
818 rxbi->skb = NULL;
819 rxbi->mapping = 0;
820 rxbi->len = 0;
821 }
822}
823
824static void
825jme_free_rx_resources(struct jme_adapter *jme)
826{
827 int i;
828 struct jme_ring *rxring = &(jme->rxring[0]);
829
830 if (rxring->alloc) {
831 if (rxring->bufinf) {
832 for (i = 0 ; i < jme->rx_ring_size ; ++i)
833 jme_free_rx_buf(jme, i);
834 kfree(rxring->bufinf);
835 }
836
837 dma_free_coherent(&(jme->pdev->dev),
838 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
839 rxring->alloc,
840 rxring->dmaalloc);
841 rxring->alloc = NULL;
842 rxring->desc = NULL;
843 rxring->dmaalloc = 0;
844 rxring->dma = 0;
845 rxring->bufinf = NULL;
846 }
847 rxring->next_to_use = 0;
848 atomic_set(&rxring->next_to_clean, 0);
849}
850
851static int
852jme_setup_rx_resources(struct jme_adapter *jme)
853{
854 int i;
855 struct jme_ring *rxring = &(jme->rxring[0]);
856
857 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
858 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
859 &(rxring->dmaalloc),
860 GFP_ATOMIC);
861 if (!rxring->alloc)
862 goto err_set_null;
863
864 /*
865 * 16 Bytes align
866 */
867 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
868 RING_DESC_ALIGN);
869 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
870 rxring->next_to_use = 0;
871 atomic_set(&rxring->next_to_clean, 0);
872
873 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
874 jme->rx_ring_size, GFP_ATOMIC);
875 if (unlikely(!(rxring->bufinf)))
876 goto err_free_rxring;
877
878 /*
879 * Initiallize Receive Descriptors
880 */
881 memset(rxring->bufinf, 0,
882 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
883 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
884 if (unlikely(jme_make_new_rx_buf(jme, i))) {
885 jme_free_rx_resources(jme);
886 return -ENOMEM;
887 }
888
889 jme_set_clean_rxdesc(jme, i);
890 }
891
892 return 0;
893
894err_free_rxring:
895 dma_free_coherent(&(jme->pdev->dev),
896 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
897 rxring->alloc,
898 rxring->dmaalloc);
899err_set_null:
900 rxring->desc = NULL;
901 rxring->dmaalloc = 0;
902 rxring->dma = 0;
903 rxring->bufinf = NULL;
904
905 return -ENOMEM;
906}
907
908static inline void
909jme_enable_rx_engine(struct jme_adapter *jme)
910{
911 /*
912 * Select Queue 0
913 */
914 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
915 RXCS_QUEUESEL_Q0);
916 wmb();
917
918 /*
919 * Setup RX DMA Bass Address
920 */
921 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
922 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
923 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
924
925 /*
926 * Setup RX Descriptor Count
927 */
928 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
929
930 /*
931 * Setup Unicast Filter
932 */
933 jme_set_unicastaddr(jme->dev);
934 jme_set_multi(jme->dev);
935
936 /*
937 * Enable RX Engine
938 */
939 wmb();
940 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
941 RXCS_QUEUESEL_Q0 |
942 RXCS_ENABLE |
943 RXCS_QST);
944
945 /*
946 * Start clock for RX MAC Processor
947 */
948 jme_mac_rxclk_on(jme);
949}
950
951static inline void
952jme_restart_rx_engine(struct jme_adapter *jme)
953{
954 /*
955 * Start RX Engine
956 */
957 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
958 RXCS_QUEUESEL_Q0 |
959 RXCS_ENABLE |
960 RXCS_QST);
961}
962
963static inline void
964jme_disable_rx_engine(struct jme_adapter *jme)
965{
966 int i;
967 u32 val;
968
969 /*
970 * Disable RX Engine
971 */
972 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
973 wmb();
974
975 val = jread32(jme, JME_RXCS);
976 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
977 mdelay(1);
978 val = jread32(jme, JME_RXCS);
979 rmb();
980 }
981
982 if (!i)
983 pr_err("Disable RX engine timeout\n");
984
985 /*
986 * Stop clock for RX MAC Processor
987 */
988 jme_mac_rxclk_off(jme);
989}
990
991static u16
992jme_udpsum(struct sk_buff *skb)
993{
994 u16 csum = 0xFFFFu;
995#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
996 struct iphdr *iph;
997 int iphlen;
998 struct udphdr *udph;
999#endif
1000
1001 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
1002 return csum;
1003 if (skb->protocol != htons(ETH_P_IP))
1004 return csum;
1005#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1006 iph = (struct iphdr *)skb_pull(skb, ETH_HLEN);
1007 iphlen = (iph->ihl << 2);
1008 if ((iph->protocol != IPPROTO_UDP) ||
1009 (skb->len < (iphlen + sizeof(struct udphdr)))) {
1010 skb_push(skb, ETH_HLEN);
1011 return csum;
1012 }
1013 udph = (struct udphdr *)skb_pull(skb, iphlen);
1014 csum = udph->check;
1015 skb_push(skb, iphlen);
1016 skb_push(skb, ETH_HLEN);
1017#else
1018 skb_set_network_header(skb, ETH_HLEN);
1019 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1020 (skb->len < (ETH_HLEN +
1021 (ip_hdr(skb)->ihl << 2) +
1022 sizeof(struct udphdr)))) {
1023 skb_reset_network_header(skb);
1024 return csum;
1025 }
1026 skb_set_transport_header(skb,
1027 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1028 csum = udp_hdr(skb)->check;
1029 skb_reset_transport_header(skb);
1030 skb_reset_network_header(skb);
1031#endif
1032
1033 return csum;
1034}
1035
1036static int
1037jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1038{
1039 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1040 return false;
1041
1042 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1043 == RXWBFLAG_TCPON)) {
1044 if (flags & RXWBFLAG_IPV4)
1045 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1046 return false;
1047 }
1048
1049 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1050 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1051 if (flags & RXWBFLAG_IPV4)
1052 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1053 return false;
1054 }
1055
1056 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1057 == RXWBFLAG_IPV4)) {
1058 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1059 return false;
1060 }
1061
1062 return true;
1063}
1064
1065static void
1066jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1067{
1068 struct jme_ring *rxring = &(jme->rxring[0]);
1069 struct rxdesc *rxdesc = rxring->desc;
1070 struct jme_buffer_info *rxbi = rxring->bufinf;
1071 struct sk_buff *skb;
1072 int framesize;
1073
1074 rxdesc += idx;
1075 rxbi += idx;
1076
1077 skb = rxbi->skb;
1078 pci_dma_sync_single_for_cpu(jme->pdev,
1079 rxbi->mapping,
1080 rxbi->len,
1081 PCI_DMA_FROMDEVICE);
1082
1083 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1084 pci_dma_sync_single_for_device(jme->pdev,
1085 rxbi->mapping,
1086 rxbi->len,
1087 PCI_DMA_FROMDEVICE);
1088
1089 ++(NET_STAT(jme).rx_dropped);
1090 } else {
1091 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1092 - RX_PREPAD_SIZE;
1093
1094 skb_reserve(skb, RX_PREPAD_SIZE);
1095 skb_put(skb, framesize);
1096 skb->protocol = eth_type_trans(skb, jme->dev);
1097
1098 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1099 skb->ip_summed = CHECKSUM_UNNECESSARY;
1100 else
1101#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
1102 skb->ip_summed = CHECKSUM_NONE;
1103#else
1104 skb_checksum_none_assert(skb);
1105#endif
1106
1107#ifndef __UNIFY_VLAN_RX_PATH__
1108 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1109 if (jme->vlgrp) {
1110 jme->jme_vlan_rx(skb, jme->vlgrp,
1111 le16_to_cpu(rxdesc->descwb.vlan));
1112 NET_STAT(jme).rx_bytes += 4;
1113 } else {
1114 dev_kfree_skb(skb);
1115 }
1116 } else {
1117 jme->jme_rx(skb);
1118 }
1119#else
1120 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1121 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1122
1123 __vlan_hwaccel_put_tag(skb, vid);
1124 NET_STAT(jme).rx_bytes += 4;
1125 }
1126 jme->jme_rx(skb);
1127#endif
1128
1129 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1130 cpu_to_le16(RXWBFLAG_DEST_MUL))
1131 ++(NET_STAT(jme).multicast);
1132
1133 NET_STAT(jme).rx_bytes += framesize;
1134 ++(NET_STAT(jme).rx_packets);
1135 }
1136
1137 jme_set_clean_rxdesc(jme, idx);
1138
1139}
1140
1141static int
1142jme_process_receive(struct jme_adapter *jme, int limit)
1143{
1144 struct jme_ring *rxring = &(jme->rxring[0]);
1145 struct rxdesc *rxdesc = rxring->desc;
1146 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1147
1148 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1149 goto out_inc;
1150
1151 if (unlikely(atomic_read(&jme->link_changing) != 1))
1152 goto out_inc;
1153
1154 if (unlikely(!netif_carrier_ok(jme->dev)))
1155 goto out_inc;
1156
1157 i = atomic_read(&rxring->next_to_clean);
1158 while (limit > 0) {
1159 rxdesc = rxring->desc;
1160 rxdesc += i;
1161
1162 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1163 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1164 goto out;
1165 --limit;
1166
1167 rmb();
1168 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1169
1170 if (unlikely(desccnt > 1 ||
1171 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1172
1173 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1174 ++(NET_STAT(jme).rx_crc_errors);
1175 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1176 ++(NET_STAT(jme).rx_fifo_errors);
1177 else
1178 ++(NET_STAT(jme).rx_errors);
1179
1180 if (desccnt > 1)
1181 limit -= desccnt - 1;
1182
1183 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1184 jme_set_clean_rxdesc(jme, j);
1185 j = (j + 1) & (mask);
1186 }
1187
1188 } else {
1189 jme_alloc_and_feed_skb(jme, i);
1190 }
1191
1192 i = (i + desccnt) & (mask);
1193 }
1194
1195out:
1196 atomic_set(&rxring->next_to_clean, i);
1197
1198out_inc:
1199 atomic_inc(&jme->rx_cleaning);
1200
1201 return limit > 0 ? limit : 0;
1202
1203}
1204
1205static void
1206jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1207{
1208 if (likely(atmp == dpi->cur)) {
1209 dpi->cnt = 0;
1210 return;
1211 }
1212
1213 if (dpi->attempt == atmp) {
1214 ++(dpi->cnt);
1215 } else {
1216 dpi->attempt = atmp;
1217 dpi->cnt = 0;
1218 }
1219
1220}
1221
1222static void
1223jme_dynamic_pcc(struct jme_adapter *jme)
1224{
1225 register struct dynpcc_info *dpi = &(jme->dpi);
1226
1227 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1228 jme_attempt_pcc(dpi, PCC_P3);
1229 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1230 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1231 jme_attempt_pcc(dpi, PCC_P2);
1232 else
1233 jme_attempt_pcc(dpi, PCC_P1);
1234
1235 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1236 if (dpi->attempt < dpi->cur)
1237 tasklet_schedule(&jme->rxclean_task);
1238 jme_set_rx_pcc(jme, dpi->attempt);
1239 dpi->cur = dpi->attempt;
1240 dpi->cnt = 0;
1241 }
1242}
1243
1244static void
1245jme_start_pcc_timer(struct jme_adapter *jme)
1246{
1247 struct dynpcc_info *dpi = &(jme->dpi);
1248 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1249 dpi->last_pkts = NET_STAT(jme).rx_packets;
1250 dpi->intr_cnt = 0;
1251 jwrite32(jme, JME_TMCSR,
1252 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1253}
1254
1255static inline void
1256jme_stop_pcc_timer(struct jme_adapter *jme)
1257{
1258 jwrite32(jme, JME_TMCSR, 0);
1259}
1260
1261static void
1262jme_shutdown_nic(struct jme_adapter *jme)
1263{
1264 u32 phylink;
1265
1266 phylink = jme_linkstat_from_phy(jme);
1267
1268 if (!(phylink & PHY_LINK_UP)) {
1269 /*
1270 * Disable all interrupt before issue timer
1271 */
1272 jme_stop_irq(jme);
1273 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1274 }
1275}
1276
1277static void
1278jme_pcc_tasklet(unsigned long arg)
1279{
1280 struct jme_adapter *jme = (struct jme_adapter *)arg;
1281 struct net_device *netdev = jme->dev;
1282
1283 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1284 jme_shutdown_nic(jme);
1285 return;
1286 }
1287
1288 if (unlikely(!netif_carrier_ok(netdev) ||
1289 (atomic_read(&jme->link_changing) != 1)
1290 )) {
1291 jme_stop_pcc_timer(jme);
1292 return;
1293 }
1294
1295 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1296 jme_dynamic_pcc(jme);
1297
1298 jme_start_pcc_timer(jme);
1299}
1300
1301static inline void
1302jme_polling_mode(struct jme_adapter *jme)
1303{
1304 jme_set_rx_pcc(jme, PCC_OFF);
1305}
1306
1307static inline void
1308jme_interrupt_mode(struct jme_adapter *jme)
1309{
1310 jme_set_rx_pcc(jme, PCC_P1);
1311}
1312
1313static inline int
1314jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1315{
1316 u32 apmc;
1317 apmc = jread32(jme, JME_APMC);
1318 return apmc & JME_APMC_PSEUDO_HP_EN;
1319}
1320
1321static void
1322jme_start_shutdown_timer(struct jme_adapter *jme)
1323{
1324 u32 apmc;
1325
1326 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1327 apmc &= ~JME_APMC_EPIEN_CTRL;
1328 if (!no_extplug) {
1329 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1330 wmb();
1331 }
1332 jwrite32f(jme, JME_APMC, apmc);
1333
1334 jwrite32f(jme, JME_TIMER2, 0);
1335 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1336 jwrite32(jme, JME_TMCSR,
1337 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1338}
1339
1340static void
1341jme_stop_shutdown_timer(struct jme_adapter *jme)
1342{
1343 u32 apmc;
1344
1345 jwrite32f(jme, JME_TMCSR, 0);
1346 jwrite32f(jme, JME_TIMER2, 0);
1347 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1348
1349 apmc = jread32(jme, JME_APMC);
1350 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1351 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1352 wmb();
1353 jwrite32f(jme, JME_APMC, apmc);
1354}
1355
1356static void
1357jme_link_change_tasklet(unsigned long arg)
1358{
1359 struct jme_adapter *jme = (struct jme_adapter *)arg;
1360 struct net_device *netdev = jme->dev;
1361 int rc;
1362
1363 while (!atomic_dec_and_test(&jme->link_changing)) {
1364 atomic_inc(&jme->link_changing);
1365 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1366 while (atomic_read(&jme->link_changing) != 1)
1367 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1368 }
1369
1370 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1371 goto out;
1372
1373 jme->old_mtu = netdev->mtu;
1374 netif_stop_queue(netdev);
1375 if (jme_pseudo_hotplug_enabled(jme))
1376 jme_stop_shutdown_timer(jme);
1377
1378 jme_stop_pcc_timer(jme);
1379 tasklet_disable(&jme->txclean_task);
1380 tasklet_disable(&jme->rxclean_task);
1381 tasklet_disable(&jme->rxempty_task);
1382
1383 if (netif_carrier_ok(netdev)) {
1384 jme_disable_rx_engine(jme);
1385 jme_disable_tx_engine(jme);
1386 jme_reset_mac_processor(jme);
1387 jme_free_rx_resources(jme);
1388 jme_free_tx_resources(jme);
1389
1390 if (test_bit(JME_FLAG_POLL, &jme->flags))
1391 jme_polling_mode(jme);
1392
1393 netif_carrier_off(netdev);
1394 }
1395
1396 jme_check_link(netdev, 0);
1397 if (netif_carrier_ok(netdev)) {
1398 rc = jme_setup_rx_resources(jme);
1399 if (rc) {
1400 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1401 goto out_enable_tasklet;
1402 }
1403
1404 rc = jme_setup_tx_resources(jme);
1405 if (rc) {
1406 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1407 goto err_out_free_rx_resources;
1408 }
1409
1410 jme_enable_rx_engine(jme);
1411 jme_enable_tx_engine(jme);
1412
1413 netif_start_queue(netdev);
1414
1415 if (test_bit(JME_FLAG_POLL, &jme->flags))
1416 jme_interrupt_mode(jme);
1417
1418 jme_start_pcc_timer(jme);
1419 } else if (jme_pseudo_hotplug_enabled(jme)) {
1420 jme_start_shutdown_timer(jme);
1421 }
1422
1423 goto out_enable_tasklet;
1424
1425err_out_free_rx_resources:
1426 jme_free_rx_resources(jme);
1427out_enable_tasklet:
1428 tasklet_enable(&jme->txclean_task);
1429 tasklet_hi_enable(&jme->rxclean_task);
1430 tasklet_hi_enable(&jme->rxempty_task);
1431out:
1432 atomic_inc(&jme->link_changing);
1433}
1434
1435static void
1436jme_rx_clean_tasklet(unsigned long arg)
1437{
1438 struct jme_adapter *jme = (struct jme_adapter *)arg;
1439 struct dynpcc_info *dpi = &(jme->dpi);
1440
1441 jme_process_receive(jme, jme->rx_ring_size);
1442 ++(dpi->intr_cnt);
1443
1444}
1445
1446static int
1447jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1448{
1449 struct jme_adapter *jme = jme_napi_priv(holder);
1450 DECLARE_NETDEV
1451 int rest;
1452
1453 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1454
1455 while (atomic_read(&jme->rx_empty) > 0) {
1456 atomic_dec(&jme->rx_empty);
1457 ++(NET_STAT(jme).rx_dropped);
1458 jme_restart_rx_engine(jme);
1459 }
1460 atomic_inc(&jme->rx_empty);
1461
1462 if (rest) {
1463 JME_RX_COMPLETE(netdev, holder);
1464 jme_interrupt_mode(jme);
1465 }
1466
1467 JME_NAPI_WEIGHT_SET(budget, rest);
1468 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1469}
1470
1471static void
1472jme_rx_empty_tasklet(unsigned long arg)
1473{
1474 struct jme_adapter *jme = (struct jme_adapter *)arg;
1475
1476 if (unlikely(atomic_read(&jme->link_changing) != 1))
1477 return;
1478
1479 if (unlikely(!netif_carrier_ok(jme->dev)))
1480 return;
1481
1482 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1483
1484 jme_rx_clean_tasklet(arg);
1485
1486 while (atomic_read(&jme->rx_empty) > 0) {
1487 atomic_dec(&jme->rx_empty);
1488 ++(NET_STAT(jme).rx_dropped);
1489 jme_restart_rx_engine(jme);
1490 }
1491 atomic_inc(&jme->rx_empty);
1492}
1493
1494static void
1495jme_wake_queue_if_stopped(struct jme_adapter *jme)
1496{
1497 struct jme_ring *txring = &(jme->txring[0]);
1498
1499 smp_wmb();
1500 if (unlikely(netif_queue_stopped(jme->dev) &&
1501 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1502 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1503 netif_wake_queue(jme->dev);
1504 }
1505
1506}
1507
1508static void
1509jme_tx_clean_tasklet(unsigned long arg)
1510{
1511 struct jme_adapter *jme = (struct jme_adapter *)arg;
1512 struct jme_ring *txring = &(jme->txring[0]);
1513 struct txdesc *txdesc = txring->desc;
1514 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1515 int i, j, cnt = 0, max, err, mask;
1516
1517 tx_dbg(jme, "Into txclean\n");
1518
1519 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1520 goto out;
1521
1522 if (unlikely(atomic_read(&jme->link_changing) != 1))
1523 goto out;
1524
1525 if (unlikely(!netif_carrier_ok(jme->dev)))
1526 goto out;
1527
1528 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1529 mask = jme->tx_ring_mask;
1530
1531 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1532
1533 ctxbi = txbi + i;
1534
1535 if (likely(ctxbi->skb &&
1536 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1537
1538 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1539 i, ctxbi->nr_desc, jiffies);
1540
1541 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1542
1543 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1544 ttxbi = txbi + ((i + j) & (mask));
1545 txdesc[(i + j) & (mask)].dw[0] = 0;
1546
1547 pci_unmap_page(jme->pdev,
1548 ttxbi->mapping,
1549 ttxbi->len,
1550 PCI_DMA_TODEVICE);
1551
1552 ttxbi->mapping = 0;
1553 ttxbi->len = 0;
1554 }
1555
1556 dev_kfree_skb(ctxbi->skb);
1557
1558 cnt += ctxbi->nr_desc;
1559
1560 if (unlikely(err)) {
1561 ++(NET_STAT(jme).tx_carrier_errors);
1562 } else {
1563 ++(NET_STAT(jme).tx_packets);
1564 NET_STAT(jme).tx_bytes += ctxbi->len;
1565 }
1566
1567 ctxbi->skb = NULL;
1568 ctxbi->len = 0;
1569 ctxbi->start_xmit = 0;
1570
1571 } else {
1572 break;
1573 }
1574
1575 i = (i + ctxbi->nr_desc) & mask;
1576
1577 ctxbi->nr_desc = 0;
1578 }
1579
1580 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1581 atomic_set(&txring->next_to_clean, i);
1582 atomic_add(cnt, &txring->nr_free);
1583
1584 jme_wake_queue_if_stopped(jme);
1585
1586out:
1587 atomic_inc(&jme->tx_cleaning);
1588}
1589
1590static void
1591jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1592{
1593 /*
1594 * Disable interrupt
1595 */
1596 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1597
1598 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1599 /*
1600 * Link change event is critical
1601 * all other events are ignored
1602 */
1603 jwrite32(jme, JME_IEVE, intrstat);
1604 tasklet_schedule(&jme->linkch_task);
1605 goto out_reenable;
1606 }
1607
1608 if (intrstat & INTR_TMINTR) {
1609 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1610 tasklet_schedule(&jme->pcc_task);
1611 }
1612
1613 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1614 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1615 tasklet_schedule(&jme->txclean_task);
1616 }
1617
1618 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1619 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1620 INTR_PCCRX0 |
1621 INTR_RX0EMP)) |
1622 INTR_RX0);
1623 }
1624
1625 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1626 if (intrstat & INTR_RX0EMP)
1627 atomic_inc(&jme->rx_empty);
1628
1629 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1630 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1631 jme_polling_mode(jme);
1632 JME_RX_SCHEDULE(jme);
1633 }
1634 }
1635 } else {
1636 if (intrstat & INTR_RX0EMP) {
1637 atomic_inc(&jme->rx_empty);
1638 tasklet_hi_schedule(&jme->rxempty_task);
1639 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1640 tasklet_hi_schedule(&jme->rxclean_task);
1641 }
1642 }
1643
1644out_reenable:
1645 /*
1646 * Re-enable interrupt
1647 */
1648 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1649}
1650
1651#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1652static irqreturn_t
1653jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1654#else
1655static irqreturn_t
1656jme_intr(int irq, void *dev_id)
1657#endif
1658{
1659 struct net_device *netdev = dev_id;
1660 struct jme_adapter *jme = netdev_priv(netdev);
1661 u32 intrstat;
1662
1663 intrstat = jread32(jme, JME_IEVE);
1664
1665 /*
1666 * Check if it's really an interrupt for us
1667 */
1668 if (unlikely((intrstat & INTR_ENABLE) == 0))
1669 return IRQ_NONE;
1670
1671 /*
1672 * Check if the device still exist
1673 */
1674 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1675 return IRQ_NONE;
1676
1677 jme_intr_msi(jme, intrstat);
1678
1679 return IRQ_HANDLED;
1680}
1681
1682#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1683static irqreturn_t
1684jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1685#else
1686static irqreturn_t
1687jme_msi(int irq, void *dev_id)
1688#endif
1689{
1690 struct net_device *netdev = dev_id;
1691 struct jme_adapter *jme = netdev_priv(netdev);
1692 u32 intrstat;
1693
1694 intrstat = jread32(jme, JME_IEVE);
1695
1696 jme_intr_msi(jme, intrstat);
1697
1698 return IRQ_HANDLED;
1699}
1700
1701static void
1702jme_reset_link(struct jme_adapter *jme)
1703{
1704 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1705}
1706
1707static void
1708jme_restart_an(struct jme_adapter *jme)
1709{
1710 u32 bmcr;
1711
1712 spin_lock_bh(&jme->phy_lock);
1713 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1714 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1715 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1716 spin_unlock_bh(&jme->phy_lock);
1717}
1718
1719static int
1720jme_request_irq(struct jme_adapter *jme)
1721{
1722 int rc;
1723 struct net_device *netdev = jme->dev;
1724#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1725 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1726 int irq_flags = SA_SHIRQ;
1727#else
1728 irq_handler_t handler = jme_intr;
1729 int irq_flags = IRQF_SHARED;
1730#endif
1731
1732 if (!pci_enable_msi(jme->pdev)) {
1733 set_bit(JME_FLAG_MSI, &jme->flags);
1734 handler = jme_msi;
1735 irq_flags = 0;
1736 }
1737
1738 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1739 netdev);
1740 if (rc) {
1741 netdev_err(netdev,
1742 "Unable to request %s interrupt (return: %d)\n",
1743 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1744 rc);
1745
1746 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1747 pci_disable_msi(jme->pdev);
1748 clear_bit(JME_FLAG_MSI, &jme->flags);
1749 }
1750 } else {
1751 netdev->irq = jme->pdev->irq;
1752 }
1753
1754 return rc;
1755}
1756
1757static void
1758jme_free_irq(struct jme_adapter *jme)
1759{
1760 free_irq(jme->pdev->irq, jme->dev);
1761 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1762 pci_disable_msi(jme->pdev);
1763 clear_bit(JME_FLAG_MSI, &jme->flags);
1764 jme->dev->irq = jme->pdev->irq;
1765 }
1766}
1767
1768static inline void
1769jme_new_phy_on(struct jme_adapter *jme)
1770{
1771 u32 reg;
1772
1773 reg = jread32(jme, JME_PHY_PWR);
1774 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1775 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1776 jwrite32(jme, JME_PHY_PWR, reg);
1777
1778 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1779 reg &= ~PE1_GPREG0_PBG;
1780 reg |= PE1_GPREG0_ENBG;
1781 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1782}
1783
1784static inline void
1785jme_new_phy_off(struct jme_adapter *jme)
1786{
1787 u32 reg;
1788
1789 reg = jread32(jme, JME_PHY_PWR);
1790 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1791 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1792 jwrite32(jme, JME_PHY_PWR, reg);
1793
1794 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1795 reg &= ~PE1_GPREG0_PBG;
1796 reg |= PE1_GPREG0_PDD3COLD;
1797 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1798}
1799
1800static inline void
1801jme_phy_on(struct jme_adapter *jme)
1802{
1803 u32 bmcr;
1804
1805 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1806 bmcr &= ~BMCR_PDOWN;
1807 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1808
1809 if (new_phy_power_ctrl(jme->chip_main_rev))
1810 jme_new_phy_on(jme);
1811}
1812
1813static inline void
1814jme_phy_off(struct jme_adapter *jme)
1815{
1816 u32 bmcr;
1817
1818 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1819 bmcr |= BMCR_PDOWN;
1820 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1821
1822 if (new_phy_power_ctrl(jme->chip_main_rev))
1823 jme_new_phy_off(jme);
1824}
1825
1826static int
1827jme_open(struct net_device *netdev)
1828{
1829 struct jme_adapter *jme = netdev_priv(netdev);
1830 int rc;
1831
1832 jme_clear_pm(jme);
1833 JME_NAPI_ENABLE(jme);
1834
1835 tasklet_enable(&jme->linkch_task);
1836 tasklet_enable(&jme->txclean_task);
1837 tasklet_hi_enable(&jme->rxclean_task);
1838 tasklet_hi_enable(&jme->rxempty_task);
1839
1840 rc = jme_request_irq(jme);
1841 if (rc)
1842 goto err_out;
1843
1844 jme_start_irq(jme);
1845
1846 jme_phy_on(jme);
1847 if (test_bit(JME_FLAG_SSET, &jme->flags))
1848 jme_set_settings(netdev, &jme->old_ecmd);
1849 else
1850 jme_reset_phy_processor(jme);
1851
1852 jme_reset_link(jme);
1853
1854 return 0;
1855
1856err_out:
1857 netif_stop_queue(netdev);
1858 netif_carrier_off(netdev);
1859 return rc;
1860}
1861
1862static void
1863jme_set_100m_half(struct jme_adapter *jme)
1864{
1865 u32 bmcr, tmp;
1866
1867 jme_phy_on(jme);
1868 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1869 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1870 BMCR_SPEED1000 | BMCR_FULLDPLX);
1871 tmp |= BMCR_SPEED100;
1872
1873 if (bmcr != tmp)
1874 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1875
1876 if (jme->fpgaver)
1877 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1878 else
1879 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1880}
1881
1882#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1883static void
1884jme_wait_link(struct jme_adapter *jme)
1885{
1886 u32 phylink, to = JME_WAIT_LINK_TIME;
1887
1888 mdelay(1000);
1889 phylink = jme_linkstat_from_phy(jme);
1890 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1891 mdelay(10);
1892 phylink = jme_linkstat_from_phy(jme);
1893 }
1894}
1895
1896static void
1897jme_powersave_phy(struct jme_adapter *jme)
1898{
1899 if (jme->reg_pmcs) {
1900 jme_set_100m_half(jme);
1901 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1902 jme_wait_link(jme);
1903 jme_clear_pm(jme);
1904 } else {
1905 jme_phy_off(jme);
1906 }
1907}
1908
1909static int
1910jme_close(struct net_device *netdev)
1911{
1912 struct jme_adapter *jme = netdev_priv(netdev);
1913
1914 netif_stop_queue(netdev);
1915 netif_carrier_off(netdev);
1916
1917 jme_stop_irq(jme);
1918 jme_free_irq(jme);
1919
1920 JME_NAPI_DISABLE(jme);
1921
1922 tasklet_disable(&jme->linkch_task);
1923 tasklet_disable(&jme->txclean_task);
1924 tasklet_disable(&jme->rxclean_task);
1925 tasklet_disable(&jme->rxempty_task);
1926
1927 jme_disable_rx_engine(jme);
1928 jme_disable_tx_engine(jme);
1929 jme_reset_mac_processor(jme);
1930 jme_free_rx_resources(jme);
1931 jme_free_tx_resources(jme);
1932 jme->phylink = 0;
1933 jme_phy_off(jme);
1934
1935 return 0;
1936}
1937
1938static int
1939jme_alloc_txdesc(struct jme_adapter *jme,
1940 struct sk_buff *skb)
1941{
1942 struct jme_ring *txring = &(jme->txring[0]);
1943 int idx, nr_alloc, mask = jme->tx_ring_mask;
1944
1945 idx = txring->next_to_use;
1946 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1947
1948 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1949 return -1;
1950
1951 atomic_sub(nr_alloc, &txring->nr_free);
1952
1953 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1954
1955 return idx;
1956}
1957
1958static void
1959jme_fill_tx_map(struct pci_dev *pdev,
1960 struct txdesc *txdesc,
1961 struct jme_buffer_info *txbi,
1962 struct page *page,
1963 u32 page_offset,
1964 u32 len,
1965 u8 hidma)
1966{
1967 dma_addr_t dmaaddr;
1968
1969 dmaaddr = pci_map_page(pdev,
1970 page,
1971 page_offset,
1972 len,
1973 PCI_DMA_TODEVICE);
1974
1975 pci_dma_sync_single_for_device(pdev,
1976 dmaaddr,
1977 len,
1978 PCI_DMA_TODEVICE);
1979
1980 txdesc->dw[0] = 0;
1981 txdesc->dw[1] = 0;
1982 txdesc->desc2.flags = TXFLAG_OWN;
1983 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1984 txdesc->desc2.datalen = cpu_to_le16(len);
1985 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1986 txdesc->desc2.bufaddrl = cpu_to_le32(
1987 (__u64)dmaaddr & 0xFFFFFFFFUL);
1988
1989 txbi->mapping = dmaaddr;
1990 txbi->len = len;
1991}
1992
1993static void
1994jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1995{
1996 struct jme_ring *txring = &(jme->txring[0]);
1997 struct txdesc *txdesc = txring->desc, *ctxdesc;
1998 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1999 u8 hidma = !!(jme->dev->features & NETIF_F_HIGHDMA);
2000 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2001 int mask = jme->tx_ring_mask;
2002 const struct skb_frag_struct *frag;
2003 u32 len;
2004
2005 for (i = 0 ; i < nr_frags ; ++i) {
2006 frag = &skb_shinfo(skb)->frags[i];
2007 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2008 ctxbi = txbi + ((idx + i + 2) & (mask));
2009
2010#ifndef __USE_SKB_FRAG_API__
2011 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
2012 frag->page_offset, frag->size, hidma);
2013#else
2014 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2015 skb_frag_page(frag),
2016 frag->page_offset, skb_frag_size(frag), hidma);
2017#endif
2018 }
2019
2020 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2021 ctxdesc = txdesc + ((idx + 1) & (mask));
2022 ctxbi = txbi + ((idx + 1) & (mask));
2023 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2024 offset_in_page(skb->data), len, hidma);
2025
2026}
2027
2028static int
2029jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2030{
2031 if (unlikely(
2032#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2033 skb_shinfo(skb)->tso_size
2034#else
2035 skb_shinfo(skb)->gso_size
2036#endif
2037 && skb_header_cloned(skb) &&
2038 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2039 dev_kfree_skb(skb);
2040 return -1;
2041 }
2042
2043 return 0;
2044}
2045
2046static int
2047jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2048{
2049#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2050 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2051#else
2052 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2053#endif
2054 if (*mss) {
2055 *flags |= TXFLAG_LSEN;
2056
2057 if (skb->protocol == htons(ETH_P_IP)) {
2058 struct iphdr *iph = ip_hdr(skb);
2059
2060 iph->check = 0;
2061 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2062 iph->daddr, 0,
2063 IPPROTO_TCP,
2064 0);
2065 } else {
2066 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2067
2068 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2069 &ip6h->daddr, 0,
2070 IPPROTO_TCP,
2071 0);
2072 }
2073
2074 return 0;
2075 }
2076
2077 return 1;
2078}
2079
2080static void
2081jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2082{
2083#ifdef CHECKSUM_PARTIAL
2084 if (skb->ip_summed == CHECKSUM_PARTIAL)
2085#else
2086 if (skb->ip_summed == CHECKSUM_HW)
2087#endif
2088 {
2089 u8 ip_proto;
2090
2091#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2092 if (skb->protocol == htons(ETH_P_IP))
2093 ip_proto = ip_hdr(skb)->protocol;
2094 else if (skb->protocol == htons(ETH_P_IPV6))
2095 ip_proto = ipv6_hdr(skb)->nexthdr;
2096 else
2097 ip_proto = 0;
2098#else
2099 switch (skb->protocol) {
2100 case htons(ETH_P_IP):
2101 ip_proto = ip_hdr(skb)->protocol;
2102 break;
2103 case htons(ETH_P_IPV6):
2104 ip_proto = ipv6_hdr(skb)->nexthdr;
2105 break;
2106 default:
2107 ip_proto = 0;
2108 break;
2109 }
2110#endif
2111
2112 switch (ip_proto) {
2113 case IPPROTO_TCP:
2114 *flags |= TXFLAG_TCPCS;
2115 break;
2116 case IPPROTO_UDP:
2117 *flags |= TXFLAG_UDPCS;
2118 break;
2119 default:
2120 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2121 break;
2122 }
2123 }
2124}
2125
2126static inline void
2127jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2128{
2129 if (vlan_tx_tag_present(skb)) {
2130 *flags |= TXFLAG_TAGON;
2131 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2132 }
2133}
2134
2135static int
2136jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2137{
2138 struct jme_ring *txring = &(jme->txring[0]);
2139 struct txdesc *txdesc;
2140 struct jme_buffer_info *txbi;
2141 u8 flags;
2142
2143 txdesc = (struct txdesc *)txring->desc + idx;
2144 txbi = txring->bufinf + idx;
2145
2146 txdesc->dw[0] = 0;
2147 txdesc->dw[1] = 0;
2148 txdesc->dw[2] = 0;
2149 txdesc->dw[3] = 0;
2150 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2151 /*
2152 * Set OWN bit at final.
2153 * When kernel transmit faster than NIC.
2154 * And NIC trying to send this descriptor before we tell
2155 * it to start sending this TX queue.
2156 * Other fields are already filled correctly.
2157 */
2158 wmb();
2159 flags = TXFLAG_OWN | TXFLAG_INT;
2160 /*
2161 * Set checksum flags while not tso
2162 */
2163 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2164 jme_tx_csum(jme, skb, &flags);
2165 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2166 jme_map_tx_skb(jme, skb, idx);
2167 txdesc->desc1.flags = flags;
2168 /*
2169 * Set tx buffer info after telling NIC to send
2170 * For better tx_clean timing
2171 */
2172 wmb();
2173 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2174 txbi->skb = skb;
2175 txbi->len = skb->len;
2176 txbi->start_xmit = jiffies;
2177 if (!txbi->start_xmit)
2178 txbi->start_xmit = (0UL-1);
2179
2180 return 0;
2181}
2182
2183static void
2184jme_stop_queue_if_full(struct jme_adapter *jme)
2185{
2186 struct jme_ring *txring = &(jme->txring[0]);
2187 struct jme_buffer_info *txbi = txring->bufinf;
2188 int idx = atomic_read(&txring->next_to_clean);
2189
2190 txbi += idx;
2191
2192 smp_wmb();
2193 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2194 netif_stop_queue(jme->dev);
2195 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2196 smp_wmb();
2197 if (atomic_read(&txring->nr_free)
2198 >= (jme->tx_wake_threshold)) {
2199 netif_wake_queue(jme->dev);
2200 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2201 }
2202 }
2203
2204 if (unlikely(txbi->start_xmit &&
2205 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2206 txbi->skb)) {
2207 netif_stop_queue(jme->dev);
2208 netif_info(jme, tx_queued, jme->dev,
2209 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2210 }
2211}
2212
2213/*
2214 * This function is already protected by netif_tx_lock()
2215 */
2216
2217#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2218static int
2219#else
2220static netdev_tx_t
2221#endif
2222jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2223{
2224 struct jme_adapter *jme = netdev_priv(netdev);
2225 int idx;
2226
2227 if (unlikely(jme_expand_header(jme, skb))) {
2228 ++(NET_STAT(jme).tx_dropped);
2229 return NETDEV_TX_OK;
2230 }
2231
2232 idx = jme_alloc_txdesc(jme, skb);
2233
2234 if (unlikely(idx < 0)) {
2235 netif_stop_queue(netdev);
2236 netif_err(jme, tx_err, jme->dev,
2237 "BUG! Tx ring full when queue awake!\n");
2238
2239 return NETDEV_TX_BUSY;
2240 }
2241
2242 jme_fill_tx_desc(jme, skb, idx);
2243
2244 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2245 TXCS_SELECT_QUEUE0 |
2246 TXCS_QUEUE0S |
2247 TXCS_ENABLE);
2248#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2249 netdev->trans_start = jiffies;
2250#endif
2251
2252 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2253 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2254 jme_stop_queue_if_full(jme);
2255
2256 return NETDEV_TX_OK;
2257}
2258
2259static void
2260jme_set_unicastaddr(struct net_device *netdev)
2261{
2262 struct jme_adapter *jme = netdev_priv(netdev);
2263 u32 val;
2264
2265 val = (netdev->dev_addr[3] & 0xff) << 24 |
2266 (netdev->dev_addr[2] & 0xff) << 16 |
2267 (netdev->dev_addr[1] & 0xff) << 8 |
2268 (netdev->dev_addr[0] & 0xff);
2269 jwrite32(jme, JME_RXUMA_LO, val);
2270 val = (netdev->dev_addr[5] & 0xff) << 8 |
2271 (netdev->dev_addr[4] & 0xff);
2272 jwrite32(jme, JME_RXUMA_HI, val);
2273}
2274
2275static int
2276jme_set_macaddr(struct net_device *netdev, void *p)
2277{
2278 struct jme_adapter *jme = netdev_priv(netdev);
2279 struct sockaddr *addr = p;
2280
2281 if (netif_running(netdev))
2282 return -EBUSY;
2283
2284 spin_lock_bh(&jme->macaddr_lock);
2285 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2286 jme_set_unicastaddr(netdev);
2287 spin_unlock_bh(&jme->macaddr_lock);
2288
2289 return 0;
2290}
2291
2292static void
2293jme_set_multi(struct net_device *netdev)
2294{
2295 struct jme_adapter *jme = netdev_priv(netdev);
2296 u32 mc_hash[2] = {};
2297#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2298 int i;
2299#endif
2300
2301 spin_lock_bh(&jme->rxmcs_lock);
2302
2303 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2304
2305 if (netdev->flags & IFF_PROMISC) {
2306 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2307 } else if (netdev->flags & IFF_ALLMULTI) {
2308 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2309 } else if (netdev->flags & IFF_MULTICAST) {
2310#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2311 struct dev_mc_list *mclist;
2312#else
2313 struct netdev_hw_addr *ha;
2314#endif
2315 int bit_nr;
2316
2317 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2318#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2319 for (i = 0, mclist = netdev->mc_list;
2320 mclist && i < netdev->mc_count;
2321 ++i, mclist = mclist->next) {
2322#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2323 netdev_for_each_mc_addr(mclist, netdev) {
2324#else
2325 netdev_for_each_mc_addr(ha, netdev) {
2326#endif
2327#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2328 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2329#else
2330 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2331#endif
2332 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2333 }
2334
2335 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2336 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2337 }
2338
2339 wmb();
2340 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2341
2342 spin_unlock_bh(&jme->rxmcs_lock);
2343}
2344
2345static int
2346jme_change_mtu(struct net_device *netdev, int new_mtu)
2347{
2348 struct jme_adapter *jme = netdev_priv(netdev);
2349
2350 if (new_mtu == jme->old_mtu)
2351 return 0;
2352
2353 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2354 ((new_mtu) < IPV6_MIN_MTU))
2355 return -EINVAL;
2356
2357 if (new_mtu > 4000) {
2358 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2359 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2360 jme_restart_rx_engine(jme);
2361 } else {
2362 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2363 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2364 jme_restart_rx_engine(jme);
2365 }
2366
2367#ifndef __USE_NDO_FIX_FEATURES__
2368 if (new_mtu > 1900) {
2369 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2370 NETIF_F_TSO | NETIF_F_TSO6);
2371 } else {
2372 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2373 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2374 if (test_bit(JME_FLAG_TSO, &jme->flags))
2375 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2376 }
2377#endif
2378
2379 netdev->mtu = new_mtu;
2380#ifdef __USE_NDO_FIX_FEATURES__
2381 netdev_update_features(netdev);
2382#endif
2383 jme_reset_link(jme);
2384
2385 return 0;
2386}
2387
2388static void
2389jme_tx_timeout(struct net_device *netdev)
2390{
2391 struct jme_adapter *jme = netdev_priv(netdev);
2392
2393 jme->phylink = 0;
2394 jme_reset_phy_processor(jme);
2395 if (test_bit(JME_FLAG_SSET, &jme->flags))
2396 jme_set_settings(netdev, &jme->old_ecmd);
2397
2398 /*
2399 * Force to Reset the link again
2400 */
2401 jme_reset_link(jme);
2402}
2403
2404static inline void jme_pause_rx(struct jme_adapter *jme)
2405{
2406 atomic_dec(&jme->link_changing);
2407
2408 jme_set_rx_pcc(jme, PCC_OFF);
2409 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2410 JME_NAPI_DISABLE(jme);
2411 } else {
2412 tasklet_disable(&jme->rxclean_task);
2413 tasklet_disable(&jme->rxempty_task);
2414 }
2415}
2416
2417static inline void jme_resume_rx(struct jme_adapter *jme)
2418{
2419 struct dynpcc_info *dpi = &(jme->dpi);
2420
2421 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2422 JME_NAPI_ENABLE(jme);
2423 } else {
2424 tasklet_hi_enable(&jme->rxclean_task);
2425 tasklet_hi_enable(&jme->rxempty_task);
2426 }
2427 dpi->cur = PCC_P1;
2428 dpi->attempt = PCC_P1;
2429 dpi->cnt = 0;
2430 jme_set_rx_pcc(jme, PCC_P1);
2431
2432 atomic_inc(&jme->link_changing);
2433}
2434
2435#ifndef __UNIFY_VLAN_RX_PATH__
2436static void
2437jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2438{
2439 struct jme_adapter *jme = netdev_priv(netdev);
2440
2441 jme_pause_rx(jme);
2442 jme->vlgrp = grp;
2443 jme_resume_rx(jme);
2444}
2445#endif
2446
2447#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2448static void
2449jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2450{
2451 struct jme_adapter *jme = netdev_priv(netdev);
2452
2453 if(jme->vlgrp) {
2454 jme_pause_rx(jme);
2455#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2456 jme->vlgrp->vlan_devices[vid] = NULL;
2457#else
2458 vlan_group_set_device(jme->vlgrp, vid, NULL);
2459#endif
2460 jme_resume_rx(jme);
2461 }
2462}
2463#endif
2464
2465static void
2466jme_get_drvinfo(struct net_device *netdev,
2467 struct ethtool_drvinfo *info)
2468{
2469 struct jme_adapter *jme = netdev_priv(netdev);
2470
2471 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2472 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2473 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2474}
2475
2476static int
2477jme_get_regs_len(struct net_device *netdev)
2478{
2479 return JME_REG_LEN;
2480}
2481
2482static void
2483mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2484{
2485 int i;
2486
2487 for (i = 0 ; i < len ; i += 4)
2488 p[i >> 2] = jread32(jme, reg + i);
2489}
2490
2491static void
2492mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2493{
2494 int i;
2495 u16 *p16 = (u16 *)p;
2496
2497 for (i = 0 ; i < reg_nr ; ++i)
2498 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2499}
2500
2501static void
2502jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2503{
2504 struct jme_adapter *jme = netdev_priv(netdev);
2505 u32 *p32 = (u32 *)p;
2506
2507 memset(p, 0xFF, JME_REG_LEN);
2508
2509 regs->version = 1;
2510 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2511
2512 p32 += 0x100 >> 2;
2513 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2514
2515 p32 += 0x100 >> 2;
2516 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2517
2518 p32 += 0x100 >> 2;
2519 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2520
2521 p32 += 0x100 >> 2;
2522 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2523}
2524
2525static int
2526jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2527{
2528 struct jme_adapter *jme = netdev_priv(netdev);
2529
2530 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2531 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2532
2533 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2534 ecmd->use_adaptive_rx_coalesce = false;
2535 ecmd->rx_coalesce_usecs = 0;
2536 ecmd->rx_max_coalesced_frames = 0;
2537 return 0;
2538 }
2539
2540 ecmd->use_adaptive_rx_coalesce = true;
2541
2542 switch (jme->dpi.cur) {
2543 case PCC_P1:
2544 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2545 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2546 break;
2547 case PCC_P2:
2548 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2549 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2550 break;
2551 case PCC_P3:
2552 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2553 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2554 break;
2555 default:
2556 break;
2557 }
2558
2559 return 0;
2560}
2561
2562static int
2563jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2564{
2565 struct jme_adapter *jme = netdev_priv(netdev);
2566 struct dynpcc_info *dpi = &(jme->dpi);
2567
2568 if (netif_running(netdev))
2569 return -EBUSY;
2570
2571 if (ecmd->use_adaptive_rx_coalesce &&
2572 test_bit(JME_FLAG_POLL, &jme->flags)) {
2573 clear_bit(JME_FLAG_POLL, &jme->flags);
2574 jme->jme_rx = netif_rx;
2575#ifndef __UNIFY_VLAN_RX_PATH__
2576 jme->jme_vlan_rx = vlan_hwaccel_rx;
2577#endif
2578 dpi->cur = PCC_P1;
2579 dpi->attempt = PCC_P1;
2580 dpi->cnt = 0;
2581 jme_set_rx_pcc(jme, PCC_P1);
2582 jme_interrupt_mode(jme);
2583 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2584 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2585 set_bit(JME_FLAG_POLL, &jme->flags);
2586 jme->jme_rx = netif_receive_skb;
2587#ifndef __UNIFY_VLAN_RX_PATH__
2588 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2589#endif
2590 jme_interrupt_mode(jme);
2591 }
2592
2593 return 0;
2594}
2595
2596static void
2597jme_get_pauseparam(struct net_device *netdev,
2598 struct ethtool_pauseparam *ecmd)
2599{
2600 struct jme_adapter *jme = netdev_priv(netdev);
2601 u32 val;
2602
2603 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2604 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2605
2606 spin_lock_bh(&jme->phy_lock);
2607 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2608 spin_unlock_bh(&jme->phy_lock);
2609
2610 ecmd->autoneg =
2611 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2612}
2613
2614static int
2615jme_set_pauseparam(struct net_device *netdev,
2616 struct ethtool_pauseparam *ecmd)
2617{
2618 struct jme_adapter *jme = netdev_priv(netdev);
2619 u32 val;
2620
2621 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2622 (ecmd->tx_pause != 0)) {
2623
2624 if (ecmd->tx_pause)
2625 jme->reg_txpfc |= TXPFC_PF_EN;
2626 else
2627 jme->reg_txpfc &= ~TXPFC_PF_EN;
2628
2629 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2630 }
2631
2632 spin_lock_bh(&jme->rxmcs_lock);
2633 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2634 (ecmd->rx_pause != 0)) {
2635
2636 if (ecmd->rx_pause)
2637 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2638 else
2639 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2640
2641 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2642 }
2643 spin_unlock_bh(&jme->rxmcs_lock);
2644
2645 spin_lock_bh(&jme->phy_lock);
2646 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2647 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2648 (ecmd->autoneg != 0)) {
2649
2650 if (ecmd->autoneg)
2651 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2652 else
2653 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2654
2655 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2656 MII_ADVERTISE, val);
2657 }
2658 spin_unlock_bh(&jme->phy_lock);
2659
2660 return 0;
2661}
2662
2663static void
2664jme_get_wol(struct net_device *netdev,
2665 struct ethtool_wolinfo *wol)
2666{
2667 struct jme_adapter *jme = netdev_priv(netdev);
2668
2669 wol->supported = WAKE_MAGIC | WAKE_PHY;
2670
2671 wol->wolopts = 0;
2672
2673 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2674 wol->wolopts |= WAKE_PHY;
2675
2676 if (jme->reg_pmcs & PMCS_MFEN)
2677 wol->wolopts |= WAKE_MAGIC;
2678
2679}
2680
2681static int
2682jme_set_wol(struct net_device *netdev,
2683 struct ethtool_wolinfo *wol)
2684{
2685 struct jme_adapter *jme = netdev_priv(netdev);
2686
2687 if (wol->wolopts & (WAKE_MAGICSECURE |
2688 WAKE_UCAST |
2689 WAKE_MCAST |
2690 WAKE_BCAST |
2691 WAKE_ARP))
2692 return -EOPNOTSUPP;
2693
2694 jme->reg_pmcs = 0;
2695
2696 if (wol->wolopts & WAKE_PHY)
2697 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2698
2699 if (wol->wolopts & WAKE_MAGIC)
2700 jme->reg_pmcs |= PMCS_MFEN;
2701
2702 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2703#ifndef JME_NEW_PM_API
2704 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2705#endif
2706#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
2707 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2708#endif
2709
2710 return 0;
2711}
2712
2713static int
2714jme_get_settings(struct net_device *netdev,
2715 struct ethtool_cmd *ecmd)
2716{
2717 struct jme_adapter *jme = netdev_priv(netdev);
2718 int rc;
2719
2720 spin_lock_bh(&jme->phy_lock);
2721 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2722 spin_unlock_bh(&jme->phy_lock);
2723 return rc;
2724}
2725
2726static int
2727jme_set_settings(struct net_device *netdev,
2728 struct ethtool_cmd *ecmd)
2729{
2730 struct jme_adapter *jme = netdev_priv(netdev);
2731 int rc, fdc = 0;
2732
2733 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2734 && ecmd->autoneg != AUTONEG_ENABLE)
2735 return -EINVAL;
2736
2737 /*
2738 * Check If user changed duplex only while force_media.
2739 * Hardware would not generate link change interrupt.
2740 */
2741 if (jme->mii_if.force_media &&
2742 ecmd->autoneg != AUTONEG_ENABLE &&
2743 (jme->mii_if.full_duplex != ecmd->duplex))
2744 fdc = 1;
2745
2746 spin_lock_bh(&jme->phy_lock);
2747 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2748 spin_unlock_bh(&jme->phy_lock);
2749
2750 if (!rc) {
2751 if (fdc)
2752 jme_reset_link(jme);
2753 jme->old_ecmd = *ecmd;
2754 set_bit(JME_FLAG_SSET, &jme->flags);
2755 }
2756
2757 return rc;
2758}
2759
2760static int
2761jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2762{
2763 int rc;
2764 struct jme_adapter *jme = netdev_priv(netdev);
2765 struct mii_ioctl_data *mii_data = if_mii(rq);
2766 unsigned int duplex_chg;
2767
2768 if (cmd == SIOCSMIIREG) {
2769 u16 val = mii_data->val_in;
2770 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2771 (val & BMCR_SPEED1000))
2772 return -EINVAL;
2773 }
2774
2775 spin_lock_bh(&jme->phy_lock);
2776 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2777 spin_unlock_bh(&jme->phy_lock);
2778
2779 if (!rc && (cmd == SIOCSMIIREG)) {
2780 if (duplex_chg)
2781 jme_reset_link(jme);
2782 jme_get_settings(netdev, &jme->old_ecmd);
2783 set_bit(JME_FLAG_SSET, &jme->flags);
2784 }
2785
2786 return rc;
2787}
2788
2789static u32
2790jme_get_link(struct net_device *netdev)
2791{
2792 struct jme_adapter *jme = netdev_priv(netdev);
2793 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2794}
2795
2796static u32
2797jme_get_msglevel(struct net_device *netdev)
2798{
2799 struct jme_adapter *jme = netdev_priv(netdev);
2800 return jme->msg_enable;
2801}
2802
2803static void
2804jme_set_msglevel(struct net_device *netdev, u32 value)
2805{
2806 struct jme_adapter *jme = netdev_priv(netdev);
2807 jme->msg_enable = value;
2808}
2809
2810#ifndef __USE_NDO_FIX_FEATURES__
2811static u32
2812jme_get_rx_csum(struct net_device *netdev)
2813{
2814 struct jme_adapter *jme = netdev_priv(netdev);
2815 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2816}
2817
2818static int
2819jme_set_rx_csum(struct net_device *netdev, u32 on)
2820{
2821 struct jme_adapter *jme = netdev_priv(netdev);
2822
2823 spin_lock_bh(&jme->rxmcs_lock);
2824 if (on)
2825 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2826 else
2827 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2828 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2829 spin_unlock_bh(&jme->rxmcs_lock);
2830
2831 return 0;
2832}
2833
2834static int
2835jme_set_tx_csum(struct net_device *netdev, u32 on)
2836{
2837 struct jme_adapter *jme = netdev_priv(netdev);
2838
2839 if (on) {
2840 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2841 if (netdev->mtu <= 1900)
2842 netdev->features |=
2843 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2844 } else {
2845 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2846 netdev->features &=
2847 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2848 }
2849
2850 return 0;
2851}
2852
2853static int
2854jme_set_tso(struct net_device *netdev, u32 on)
2855{
2856 struct jme_adapter *jme = netdev_priv(netdev);
2857
2858 if (on) {
2859 set_bit(JME_FLAG_TSO, &jme->flags);
2860 if (netdev->mtu <= 1900)
2861 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2862 } else {
2863 clear_bit(JME_FLAG_TSO, &jme->flags);
2864 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2865 }
2866
2867 return 0;
2868}
2869#else
2870#ifndef __NEW_FIX_FEATURES_TYPE__
2871static u32
2872jme_fix_features(struct net_device *netdev, u32 features)
2873#else
2874static netdev_features_t
2875jme_fix_features(struct net_device *netdev, netdev_features_t features)
2876#endif
2877{
2878 if (netdev->mtu > 1900)
2879 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2880 return features;
2881}
2882
2883static int
2884#ifndef __NEW_FIX_FEATURES_TYPE__
2885jme_set_features(struct net_device *netdev, u32 features)
2886#else
2887jme_set_features(struct net_device *netdev, netdev_features_t features)
2888#endif
2889{
2890 struct jme_adapter *jme = netdev_priv(netdev);
2891
2892 spin_lock_bh(&jme->rxmcs_lock);
2893 if (features & NETIF_F_RXCSUM)
2894 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2895 else
2896 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2897 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2898 spin_unlock_bh(&jme->rxmcs_lock);
2899
2900 return 0;
2901}
2902#endif
2903
2904static int
2905jme_nway_reset(struct net_device *netdev)
2906{
2907 struct jme_adapter *jme = netdev_priv(netdev);
2908 jme_restart_an(jme);
2909 return 0;
2910}
2911
2912static u8
2913jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2914{
2915 u32 val;
2916 int to;
2917
2918 val = jread32(jme, JME_SMBCSR);
2919 to = JME_SMB_BUSY_TIMEOUT;
2920 while ((val & SMBCSR_BUSY) && --to) {
2921 msleep(1);
2922 val = jread32(jme, JME_SMBCSR);
2923 }
2924 if (!to) {
2925 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2926 return 0xFF;
2927 }
2928
2929 jwrite32(jme, JME_SMBINTF,
2930 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2931 SMBINTF_HWRWN_READ |
2932 SMBINTF_HWCMD);
2933
2934 val = jread32(jme, JME_SMBINTF);
2935 to = JME_SMB_BUSY_TIMEOUT;
2936 while ((val & SMBINTF_HWCMD) && --to) {
2937 msleep(1);
2938 val = jread32(jme, JME_SMBINTF);
2939 }
2940 if (!to) {
2941 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2942 return 0xFF;
2943 }
2944
2945 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2946}
2947
2948static void
2949jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2950{
2951 u32 val;
2952 int to;
2953
2954 val = jread32(jme, JME_SMBCSR);
2955 to = JME_SMB_BUSY_TIMEOUT;
2956 while ((val & SMBCSR_BUSY) && --to) {
2957 msleep(1);
2958 val = jread32(jme, JME_SMBCSR);
2959 }
2960 if (!to) {
2961 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2962 return;
2963 }
2964
2965 jwrite32(jme, JME_SMBINTF,
2966 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2967 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2968 SMBINTF_HWRWN_WRITE |
2969 SMBINTF_HWCMD);
2970
2971 val = jread32(jme, JME_SMBINTF);
2972 to = JME_SMB_BUSY_TIMEOUT;
2973 while ((val & SMBINTF_HWCMD) && --to) {
2974 msleep(1);
2975 val = jread32(jme, JME_SMBINTF);
2976 }
2977 if (!to) {
2978 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2979 return;
2980 }
2981
2982 mdelay(2);
2983}
2984
2985static int
2986jme_get_eeprom_len(struct net_device *netdev)
2987{
2988 struct jme_adapter *jme = netdev_priv(netdev);
2989 u32 val;
2990 val = jread32(jme, JME_SMBCSR);
2991 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2992}
2993
2994static int
2995jme_get_eeprom(struct net_device *netdev,
2996 struct ethtool_eeprom *eeprom, u8 *data)
2997{
2998 struct jme_adapter *jme = netdev_priv(netdev);
2999 int i, offset = eeprom->offset, len = eeprom->len;
3000
3001 /*
3002 * ethtool will check the boundary for us
3003 */
3004 eeprom->magic = JME_EEPROM_MAGIC;
3005 for (i = 0 ; i < len ; ++i)
3006 data[i] = jme_smb_read(jme, i + offset);
3007
3008 return 0;
3009}
3010
3011static int
3012jme_set_eeprom(struct net_device *netdev,
3013 struct ethtool_eeprom *eeprom, u8 *data)
3014{
3015 struct jme_adapter *jme = netdev_priv(netdev);
3016 int i, offset = eeprom->offset, len = eeprom->len;
3017
3018 if (eeprom->magic != JME_EEPROM_MAGIC)
3019 return -EINVAL;
3020
3021 /*
3022 * ethtool will check the boundary for us
3023 */
3024 for (i = 0 ; i < len ; ++i)
3025 jme_smb_write(jme, i + offset, data[i]);
3026
3027 return 0;
3028}
3029
3030#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
3031static struct ethtool_ops jme_ethtool_ops = {
3032#else
3033static const struct ethtool_ops jme_ethtool_ops = {
3034#endif
3035 .get_drvinfo = jme_get_drvinfo,
3036 .get_regs_len = jme_get_regs_len,
3037 .get_regs = jme_get_regs,
3038 .get_coalesce = jme_get_coalesce,
3039 .set_coalesce = jme_set_coalesce,
3040 .get_pauseparam = jme_get_pauseparam,
3041 .set_pauseparam = jme_set_pauseparam,
3042 .get_wol = jme_get_wol,
3043 .set_wol = jme_set_wol,
3044 .get_settings = jme_get_settings,
3045 .set_settings = jme_set_settings,
3046 .get_link = jme_get_link,
3047 .get_msglevel = jme_get_msglevel,
3048 .set_msglevel = jme_set_msglevel,
3049#ifndef __USE_NDO_FIX_FEATURES__
3050 .get_rx_csum = jme_get_rx_csum,
3051 .set_rx_csum = jme_set_rx_csum,
3052 .set_tx_csum = jme_set_tx_csum,
3053 .set_tso = jme_set_tso,
3054 .set_sg = ethtool_op_set_sg,
3055#endif
3056 .nway_reset = jme_nway_reset,
3057 .get_eeprom_len = jme_get_eeprom_len,
3058 .get_eeprom = jme_get_eeprom,
3059 .set_eeprom = jme_set_eeprom,
3060};
3061
3062static int
3063jme_pci_dma64(struct pci_dev *pdev)
3064{
3065 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3066#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3067 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
3068#else
3069 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
3070#endif
3071 )
3072#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3073 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3074#else
3075 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
3076#endif
3077 return 1;
3078
3079 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3080#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3081 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3082#else
3083 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3084#endif
3085 )
3086#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3087 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3088#else
3089 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
3090#endif
3091 return 1;
3092
3093#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3094 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3095 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3096#else
3097 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3098 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3099#endif
3100 return 0;
3101
3102 return -1;
3103}
3104
3105static inline void
3106jme_phy_init(struct jme_adapter *jme)
3107{
3108 u16 reg26;
3109
3110 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3111 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3112}
3113
3114static inline void
3115jme_check_hw_ver(struct jme_adapter *jme)
3116{
3117 u32 chipmode;
3118
3119 chipmode = jread32(jme, JME_CHIPMODE);
3120
3121 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3122 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3123 jme->chip_main_rev = jme->chiprev & 0xF;
3124 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3125}
3126
3127#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3128static const struct net_device_ops jme_netdev_ops = {
3129 .ndo_open = jme_open,
3130 .ndo_stop = jme_close,
3131 .ndo_validate_addr = eth_validate_addr,
3132 .ndo_do_ioctl = jme_ioctl,
3133 .ndo_start_xmit = jme_start_xmit,
3134 .ndo_set_mac_address = jme_set_macaddr,
3135#ifndef __USE_NDO_SET_RX_MODE__
3136 .ndo_set_multicast_list = jme_set_multi,
3137#else
3138 .ndo_set_rx_mode = jme_set_multi,
3139#endif
3140 .ndo_change_mtu = jme_change_mtu,
3141 .ndo_tx_timeout = jme_tx_timeout,
3142#ifndef __UNIFY_VLAN_RX_PATH__
3143 .ndo_vlan_rx_register = jme_vlan_rx_register,
3144#endif
3145#ifdef __USE_NDO_FIX_FEATURES__
3146 .ndo_fix_features = jme_fix_features,
3147 .ndo_set_features = jme_set_features,
3148#endif
3149};
3150#endif
3151
3152static int __devinit
3153jme_init_one(struct pci_dev *pdev,
3154 const struct pci_device_id *ent)
3155{
3156 int rc = 0, using_dac, i;
3157 struct net_device *netdev;
3158 struct jme_adapter *jme;
3159 u16 bmcr, bmsr;
3160 u32 apmc;
3161
3162 /*
3163 * set up PCI device basics
3164 */
3165 rc = pci_enable_device(pdev);
3166 if (rc) {
3167 pr_err("Cannot enable PCI device\n");
3168 goto err_out;
3169 }
3170
3171 using_dac = jme_pci_dma64(pdev);
3172 if (using_dac < 0) {
3173 pr_err("Cannot set PCI DMA Mask\n");
3174 rc = -EIO;
3175 goto err_out_disable_pdev;
3176 }
3177
3178 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3179 pr_err("No PCI resource region found\n");
3180 rc = -ENOMEM;
3181 goto err_out_disable_pdev;
3182 }
3183
3184 rc = pci_request_regions(pdev, DRV_NAME);
3185 if (rc) {
3186 pr_err("Cannot obtain PCI resource region\n");
3187 goto err_out_disable_pdev;
3188 }
3189
3190 pci_set_master(pdev);
3191
3192 /*
3193 * alloc and init net device
3194 */
3195 netdev = alloc_etherdev(sizeof(*jme));
3196 if (!netdev) {
3197 pr_err("Cannot allocate netdev structure\n");
3198 rc = -ENOMEM;
3199 goto err_out_release_regions;
3200 }
3201#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3202 netdev->netdev_ops = &jme_netdev_ops;
3203#else
3204 netdev->open = jme_open;
3205 netdev->stop = jme_close;
3206 netdev->do_ioctl = jme_ioctl;
3207 netdev->hard_start_xmit = jme_start_xmit;
3208 netdev->set_mac_address = jme_set_macaddr;
3209 netdev->set_multicast_list = jme_set_multi;
3210 netdev->change_mtu = jme_change_mtu;
3211 netdev->tx_timeout = jme_tx_timeout;
3212 netdev->vlan_rx_register = jme_vlan_rx_register;
3213#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3214 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3215#endif
3216 NETDEV_GET_STATS(netdev, &jme_get_stats);
3217#endif
3218 netdev->ethtool_ops = &jme_ethtool_ops;
3219 netdev->watchdog_timeo = TX_TIMEOUT;
3220#ifdef __USE_NDO_FIX_FEATURES__
3221 netdev->hw_features = NETIF_F_IP_CSUM |
3222 NETIF_F_IPV6_CSUM |
3223 NETIF_F_SG |
3224 NETIF_F_TSO |
3225 NETIF_F_TSO6 |
3226 NETIF_F_RXCSUM;
3227#endif
3228 netdev->features = NETIF_F_IP_CSUM |
3229 NETIF_F_IPV6_CSUM |
3230 NETIF_F_SG |
3231 NETIF_F_TSO |
3232 NETIF_F_TSO6 |
3233 NETIF_F_HW_VLAN_TX |
3234 NETIF_F_HW_VLAN_RX;
3235 if (using_dac)
3236 netdev->features |= NETIF_F_HIGHDMA;
3237
3238 SET_NETDEV_DEV(netdev, &pdev->dev);
3239 pci_set_drvdata(pdev, netdev);
3240
3241 /*
3242 * init adapter info
3243 */
3244 jme = netdev_priv(netdev);
3245 jme->pdev = pdev;
3246 jme->dev = netdev;
3247 jme->jme_rx = netif_rx;
3248#ifndef __UNIFY_VLAN_RX_PATH__
3249 jme->jme_vlan_rx = vlan_hwaccel_rx;
3250#endif
3251 jme->old_mtu = netdev->mtu = 1500;
3252 jme->phylink = 0;
3253 jme->tx_ring_size = 1 << 10;
3254 jme->tx_ring_mask = jme->tx_ring_size - 1;
3255 jme->tx_wake_threshold = 1 << 9;
3256 jme->rx_ring_size = 1 << 9;
3257 jme->rx_ring_mask = jme->rx_ring_size - 1;
3258 jme->msg_enable = JME_DEF_MSG_ENABLE;
3259 jme->regs = ioremap(pci_resource_start(pdev, 0),
3260 pci_resource_len(pdev, 0));
3261 if (!(jme->regs)) {
3262 pr_err("Mapping PCI resource region error\n");
3263 rc = -ENOMEM;
3264 goto err_out_free_netdev;
3265 }
3266
3267 if (no_pseudohp) {
3268 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3269 jwrite32(jme, JME_APMC, apmc);
3270 } else if (force_pseudohp) {
3271 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3272 jwrite32(jme, JME_APMC, apmc);
3273 }
3274
3275 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3276
3277 spin_lock_init(&jme->phy_lock);
3278 spin_lock_init(&jme->macaddr_lock);
3279 spin_lock_init(&jme->rxmcs_lock);
3280
3281 atomic_set(&jme->link_changing, 1);
3282 atomic_set(&jme->rx_cleaning, 1);
3283 atomic_set(&jme->tx_cleaning, 1);
3284 atomic_set(&jme->rx_empty, 1);
3285
3286 tasklet_init(&jme->pcc_task,
3287 jme_pcc_tasklet,
3288 (unsigned long) jme);
3289 tasklet_init(&jme->linkch_task,
3290 jme_link_change_tasklet,
3291 (unsigned long) jme);
3292 tasklet_init(&jme->txclean_task,
3293 jme_tx_clean_tasklet,
3294 (unsigned long) jme);
3295 tasklet_init(&jme->rxclean_task,
3296 jme_rx_clean_tasklet,
3297 (unsigned long) jme);
3298 tasklet_init(&jme->rxempty_task,
3299 jme_rx_empty_tasklet,
3300 (unsigned long) jme);
3301 tasklet_disable_nosync(&jme->linkch_task);
3302 tasklet_disable_nosync(&jme->txclean_task);
3303 tasklet_disable_nosync(&jme->rxclean_task);
3304 tasklet_disable_nosync(&jme->rxempty_task);
3305 jme->dpi.cur = PCC_P1;
3306
3307 jme->reg_ghc = 0;
3308 jme->reg_rxcs = RXCS_DEFAULT;
3309 jme->reg_rxmcs = RXMCS_DEFAULT;
3310 jme->reg_txpfc = 0;
3311 jme->reg_pmcs = PMCS_MFEN;
3312 jme->reg_gpreg1 = GPREG1_DEFAULT;
3313#ifndef __USE_NDO_FIX_FEATURES__
3314 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3315 set_bit(JME_FLAG_TSO, &jme->flags);
3316#else
3317
3318 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3319 netdev->features |= NETIF_F_RXCSUM;
3320#endif
3321
3322 /*
3323 * Get Max Read Req Size from PCI Config Space
3324 */
3325 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3326 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3327 switch (jme->mrrs) {
3328 case MRRS_128B:
3329 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3330 break;
3331 case MRRS_256B:
3332 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3333 break;
3334 default:
3335 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3336 break;
3337 }
3338
3339 /*
3340 * Must check before reset_mac_processor
3341 */
3342 jme_check_hw_ver(jme);
3343 jme->mii_if.dev = netdev;
3344 if (jme->fpgaver) {
3345 jme->mii_if.phy_id = 0;
3346 for (i = 1 ; i < 32 ; ++i) {
3347 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3348 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3349 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3350 jme->mii_if.phy_id = i;
3351 break;
3352 }
3353 }
3354
3355 if (!jme->mii_if.phy_id) {
3356 rc = -EIO;
3357 pr_err("Can not find phy_id\n");
3358 goto err_out_unmap;
3359 }
3360
3361 jme->reg_ghc |= GHC_LINK_POLL;
3362 } else {
3363 jme->mii_if.phy_id = 1;
3364 }
3365 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3366 jme->mii_if.supports_gmii = true;
3367 else
3368 jme->mii_if.supports_gmii = false;
3369 jme->mii_if.phy_id_mask = 0x1F;
3370 jme->mii_if.reg_num_mask = 0x1F;
3371 jme->mii_if.mdio_read = jme_mdio_read;
3372 jme->mii_if.mdio_write = jme_mdio_write;
3373
3374 jme_clear_pm(jme);
3375 pci_set_power_state(jme->pdev, PCI_D0);
3376#ifndef JME_NEW_PM_API
3377 jme_pci_wakeup_enable(jme, true);
3378#endif
3379#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3380 device_set_wakeup_enable(&pdev->dev, true);
3381#endif
3382
3383 jme_set_phyfifo_5level(jme);
3384#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
3385 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3386#else
3387 jme->pcirev = pdev->revision;
3388#endif
3389 if (!jme->fpgaver)
3390 jme_phy_init(jme);
3391 jme_phy_off(jme);
3392
3393 /*
3394 * Reset MAC processor and reload EEPROM for MAC Address
3395 */
3396 jme_reset_mac_processor(jme);
3397 rc = jme_reload_eeprom(jme);
3398 if (rc) {
3399 pr_err("Reload eeprom for reading MAC Address error\n");
3400 goto err_out_unmap;
3401 }
3402 jme_load_macaddr(netdev);
3403
3404 /*
3405 * Tell stack that we are not ready to work until open()
3406 */
3407 netif_carrier_off(netdev);
3408
3409 rc = register_netdev(netdev);
3410 if (rc) {
3411 pr_err("Cannot register net device\n");
3412 goto err_out_unmap;
3413 }
3414
3415 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3416 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3417 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3418 "JMC250 Gigabit Ethernet" :
3419 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3420 "JMC260 Fast Ethernet" : "Unknown",
3421 (jme->fpgaver != 0) ? " (FPGA)" : "",
3422 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3423 jme->pcirev,
3424 netdev->dev_addr[0],
3425 netdev->dev_addr[1],
3426 netdev->dev_addr[2],
3427 netdev->dev_addr[3],
3428 netdev->dev_addr[4],
3429 netdev->dev_addr[5]);
3430
3431 return 0;
3432
3433err_out_unmap:
3434 iounmap(jme->regs);
3435err_out_free_netdev:
3436 pci_set_drvdata(pdev, NULL);
3437 free_netdev(netdev);
3438err_out_release_regions:
3439 pci_release_regions(pdev);
3440err_out_disable_pdev:
3441 pci_disable_device(pdev);
3442err_out:
3443 return rc;
3444}
3445
3446static void __devexit
3447jme_remove_one(struct pci_dev *pdev)
3448{
3449 struct net_device *netdev = pci_get_drvdata(pdev);
3450 struct jme_adapter *jme = netdev_priv(netdev);
3451
3452 unregister_netdev(netdev);
3453 iounmap(jme->regs);
3454 pci_set_drvdata(pdev, NULL);
3455 free_netdev(netdev);
3456 pci_release_regions(pdev);
3457 pci_disable_device(pdev);
3458
3459}
3460
3461static void
3462jme_shutdown(struct pci_dev *pdev)
3463{
3464 struct net_device *netdev = pci_get_drvdata(pdev);
3465 struct jme_adapter *jme = netdev_priv(netdev);
3466
3467 jme_powersave_phy(jme);
3468#ifndef JME_NEW_PM_API
3469 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3470#endif
3471#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3472 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
3473#endif
3474}
3475
3476#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3477 #ifdef CONFIG_PM
3478 #define JME_HAVE_PM
3479 #endif
3480#else
3481 #ifdef CONFIG_PM_SLEEP
3482 #define JME_HAVE_PM
3483 #endif
3484#endif
3485
3486#ifdef JME_HAVE_PM
3487static int
3488#ifdef JME_NEW_PM_API
3489jme_suspend(struct device *dev)
3490#else
3491jme_suspend(struct pci_dev *pdev, pm_message_t state)
3492#endif
3493{
3494#ifdef JME_NEW_PM_API
3495 struct pci_dev *pdev = to_pci_dev(dev);
3496#endif
3497 struct net_device *netdev = pci_get_drvdata(pdev);
3498 struct jme_adapter *jme = netdev_priv(netdev);
3499
3500 atomic_dec(&jme->link_changing);
3501
3502 netif_device_detach(netdev);
3503 netif_stop_queue(netdev);
3504 jme_stop_irq(jme);
3505
3506 tasklet_disable(&jme->txclean_task);
3507 tasklet_disable(&jme->rxclean_task);
3508 tasklet_disable(&jme->rxempty_task);
3509
3510 if (netif_carrier_ok(netdev)) {
3511 if (test_bit(JME_FLAG_POLL, &jme->flags))
3512 jme_polling_mode(jme);
3513
3514 jme_stop_pcc_timer(jme);
3515 jme_disable_rx_engine(jme);
3516 jme_disable_tx_engine(jme);
3517 jme_reset_mac_processor(jme);
3518 jme_free_rx_resources(jme);
3519 jme_free_tx_resources(jme);
3520 netif_carrier_off(netdev);
3521 jme->phylink = 0;
3522 }
3523
3524 tasklet_enable(&jme->txclean_task);
3525 tasklet_hi_enable(&jme->rxclean_task);
3526 tasklet_hi_enable(&jme->rxempty_task);
3527
3528 jme_powersave_phy(jme);
3529#ifndef JME_NEW_PM_API
3530 pci_save_state(pdev);
3531 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3532 pci_set_power_state(pdev, PCI_D3hot);
3533#endif
3534
3535 return 0;
3536}
3537
3538static int
3539#ifdef JME_NEW_PM_API
3540jme_resume(struct device *dev)
3541#else
3542jme_resume(struct pci_dev *pdev)
3543#endif
3544{
3545#ifdef JME_NEW_PM_API
3546 struct pci_dev *pdev = to_pci_dev(dev);
3547#endif
3548 struct net_device *netdev = pci_get_drvdata(pdev);
3549 struct jme_adapter *jme = netdev_priv(netdev);
3550
3551 jme_clear_pm(jme);
3552#ifndef JME_NEW_PM_API
3553 pci_set_power_state(pdev, PCI_D0);
3554 pci_restore_state(pdev);
3555#endif
3556
3557 jme_phy_on(jme);
3558 if (test_bit(JME_FLAG_SSET, &jme->flags))
3559 jme_set_settings(netdev, &jme->old_ecmd);
3560 else
3561 jme_reset_phy_processor(jme);
3562
3563 jme_start_irq(jme);
3564 netif_device_attach(netdev);
3565
3566 atomic_inc(&jme->link_changing);
3567
3568 jme_reset_link(jme);
3569
3570 return 0;
3571}
3572
3573#ifdef JME_NEW_PM_API
3574static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3575#define JME_PM_OPS (&jme_pm_ops)
3576#endif
3577
3578#else
3579
3580#ifdef JME_NEW_PM_API
3581#define JME_PM_OPS NULL
3582#endif
3583#endif
3584
3585#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3586static struct pci_device_id jme_pci_tbl[] = {
3587#else
3588static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3589#endif
3590 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3591 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3592 { }
3593};
3594
3595static struct pci_driver jme_driver = {
3596 .name = DRV_NAME,
3597 .id_table = jme_pci_tbl,
3598 .probe = jme_init_one,
3599 .remove = __devexit_p(jme_remove_one),
3600 .shutdown = jme_shutdown,
3601#ifndef JME_NEW_PM_API
3602 .suspend = jme_suspend,
3603 .resume = jme_resume
3604#else
3605 .driver.pm = JME_PM_OPS,
3606#endif
3607};
3608
3609static int __init
3610jme_init_module(void)
3611{
3612 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3613 return pci_register_driver(&jme_driver);
3614}
3615
3616static void __exit
3617jme_cleanup_module(void)
3618{
3619 pci_unregister_driver(&jme_driver);
3620}
3621
3622module_init(jme_init_module);
3623module_exit(jme_cleanup_module);
3624
3625MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3626MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3627MODULE_LICENSE("GPL");
3628MODULE_VERSION(DRV_VERSION);
3629MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3630
JMicron Ethernet Linux driver