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jme: do vlan cleanup
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/version.h>
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
38#include <linux/delay.h>
39#include <linux/spinlock.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/if_vlan.h>
46#include <linux/slab.h>
47#include <net/ip6_checksum.h>
48#include "jme.h"
49
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
61
62#ifndef JME_NEW_PM_API
63static void
64jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65{
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71#else
72 pci_pme_active(jme->pdev, enable);
73#endif
74}
75#endif
76
77static int
78jme_mdio_read(struct net_device *netdev, int phy, int reg)
79{
80 struct jme_adapter *jme = netdev_priv(netdev);
81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
82
83read_again:
84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
85 smi_phy_addr(phy) |
86 smi_reg_addr(reg));
87
88 wmb();
89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
90 udelay(20);
91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
93 break;
94 }
95
96 if (i == 0) {
97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
98 return 0;
99 }
100
101 if (again--)
102 goto read_again;
103
104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
105}
106
107static void
108jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
110{
111 struct jme_adapter *jme = netdev_priv(netdev);
112 int i;
113
114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
117
118 wmb();
119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
120 udelay(20);
121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
122 break;
123 }
124
125 if (i == 0)
126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
127}
128
129static inline void
130jme_reset_phy_processor(struct jme_adapter *jme)
131{
132 u32 val;
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
138
139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
142 MII_CTRL1000,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
144
145 val = jme_mdio_read(jme->dev,
146 jme->mii_if.phy_id,
147 MII_BMCR);
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_BMCR, val | BMCR_RESET);
152}
153
154static void
155jme_setup_wakeup_frame(struct jme_adapter *jme,
156 const u32 *mask, u32 crc, int fnr)
157{
158 int i;
159
160 /*
161 * Setup CRC pattern
162 */
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
164 wmb();
165 jwrite32(jme, JME_WFODP, crc);
166 wmb();
167
168 /*
169 * Setup Mask
170 */
171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
175 wmb();
176 jwrite32(jme, JME_WFODP, mask[i]);
177 wmb();
178 }
179}
180
181static inline void
182jme_mac_rxclk_off(struct jme_adapter *jme)
183{
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
186}
187
188static inline void
189jme_mac_rxclk_on(struct jme_adapter *jme)
190{
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
193}
194
195static inline void
196jme_mac_txclk_off(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_mac_txclk_on(struct jme_adapter *jme)
204{
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
208 else
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
211}
212
213static inline void
214jme_reset_ghc_speed(struct jme_adapter *jme)
215{
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_reset_250A2_workaround(struct jme_adapter *jme)
222{
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
224 GPREG1_RSSPATCH);
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
226}
227
228static inline void
229jme_assert_ghc_reset(struct jme_adapter *jme)
230{
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_clear_ghc_reset(struct jme_adapter *jme)
237{
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
240}
241
242static inline void
243jme_reset_mac_processor(struct jme_adapter *jme)
244{
245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
246 u32 crc = 0xCDCDCDCD;
247 u32 gpreg0;
248 int i;
249
250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
252
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
255 udelay(1);
256 jme_assert_ghc_reset(jme);
257 udelay(1);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
260 udelay(1);
261 jme_clear_ghc_reset(jme);
262 udelay(1);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
265 udelay(1);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
268
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
277
278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
281 jme_setup_wakeup_frame(jme, mask, crc, i);
282 if (jme->fpgaver)
283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
284 else
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
287}
288
289static inline void
290jme_clear_pm(struct jme_adapter *jme)
291{
292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
293}
294
295static int
296jme_reload_eeprom(struct jme_adapter *jme)
297{
298 u32 val;
299 int i;
300
301 val = jread32(jme, JME_SMBCSR);
302
303 if (val & SMBCSR_EEPROMD) {
304 val |= SMBCSR_CNACK;
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
308 mdelay(12);
309
310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
311 mdelay(1);
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
313 break;
314 }
315
316 if (i == 0) {
317 pr_err("eeprom reload timeout\n");
318 return -EIO;
319 }
320 }
321
322 return 0;
323}
324
325static void
326jme_load_macaddr(struct net_device *netdev)
327{
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
330 u32 val;
331
332 spin_lock_bh(&jme->macaddr_lock);
333 val = jread32(jme, JME_RXUMA_LO);
334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
338 val = jread32(jme, JME_RXUMA_HI);
339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
343}
344
345static inline void
346jme_set_rx_pcc(struct jme_adapter *jme, int p)
347{
348 switch (p) {
349 case PCC_OFF:
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 break;
354 case PCC_P1:
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 break;
359 case PCC_P2:
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 break;
364 case PCC_P3:
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
368 break;
369 default:
370 break;
371 }
372 wmb();
373
374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
376}
377
378static void
379jme_start_irq(struct jme_adapter *jme)
380{
381 register struct dynpcc_info *dpi = &(jme->dpi);
382
383 jme_set_rx_pcc(jme, PCC_P1);
384 dpi->cur = PCC_P1;
385 dpi->attempt = PCC_P1;
386 dpi->cnt = 0;
387
388 jwrite32(jme, JME_PCCTX,
389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
391 PCCTXQ0_EN
392 );
393
394 /*
395 * Enable Interrupts
396 */
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
398}
399
400static inline void
401jme_stop_irq(struct jme_adapter *jme)
402{
403 /*
404 * Disable Interrupts
405 */
406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
407}
408
409static u32
410jme_linkstat_from_phy(struct jme_adapter *jme)
411{
412 u32 phylink, bmsr;
413
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
416 if (bmsr & BMSR_ANCOMP)
417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
418
419 return phylink;
420}
421
422static inline void
423jme_set_phyfifo_5level(struct jme_adapter *jme)
424{
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
426}
427
428static inline void
429jme_set_phyfifo_8level(struct jme_adapter *jme)
430{
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
432}
433
434static int
435jme_check_link(struct net_device *netdev, int testonly)
436{
437 struct jme_adapter *jme = netdev_priv(netdev);
438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
439 char linkmsg[64];
440 int rc = 0;
441
442 linkmsg[0] = '\0';
443
444 if (jme->fpgaver)
445 phylink = jme_linkstat_from_phy(jme);
446 else
447 phylink = jread32(jme, JME_PHY_LINK);
448
449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
451 /*
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
454 */
455 phylink = PHY_LINK_UP;
456
457 bmcr = jme_mdio_read(jme->dev,
458 jme->mii_if.phy_id,
459 MII_BMCR);
460
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
466 PHY_LINK_SPEED_10M;
467
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 PHY_LINK_DUPLEX : 0;
470
471 strcat(linkmsg, "Forced: ");
472 } else {
473 /*
474 * Keep polling for speed/duplex resolve complete
475 */
476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
477 --cnt) {
478
479 udelay(1);
480
481 if (jme->fpgaver)
482 phylink = jme_linkstat_from_phy(jme);
483 else
484 phylink = jread32(jme, JME_PHY_LINK);
485 }
486 if (!cnt)
487 pr_err("Waiting speed resolve timeout\n");
488
489 strcat(linkmsg, "ANed: ");
490 }
491
492 if (jme->phylink == phylink) {
493 rc = 1;
494 goto out;
495 }
496 if (testonly)
497 goto out;
498
499 jme->phylink = phylink;
500
501 /*
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
504 */
505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
507 jme->reg_ghc |= GHC_SPEED_10M;
508 strcat(linkmsg, "10 Mbps, ");
509 break;
510 case PHY_LINK_SPEED_100M:
511 jme->reg_ghc |= GHC_SPEED_100M;
512 strcat(linkmsg, "100 Mbps, ");
513 break;
514 case PHY_LINK_SPEED_1000M:
515 jme->reg_ghc |= GHC_SPEED_1000M;
516 strcat(linkmsg, "1000 Mbps, ");
517 break;
518 default:
519 break;
520 }
521
522 if (phylink & PHY_LINK_DUPLEX) {
523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
525 jme->reg_ghc |= GHC_DPX;
526 } else {
527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
528 TXMCS_BACKOFF |
529 TXMCS_CARRIERSENSE |
530 TXMCS_COLLISION);
531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
532 }
533
534 jwrite32(jme, JME_GHC, jme->reg_ghc);
535
536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
538 GPREG1_RSSPATCH);
539 if (!(phylink & PHY_LINK_DUPLEX))
540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
543 jme_set_phyfifo_8level(jme);
544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
545 break;
546 case PHY_LINK_SPEED_100M:
547 jme_set_phyfifo_5level(jme);
548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
549 break;
550 case PHY_LINK_SPEED_1000M:
551 jme_set_phyfifo_8level(jme);
552 break;
553 default:
554 break;
555 }
556 }
557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
558
559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 "Full-Duplex, " :
561 "Half-Duplex, ");
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 "MDI-X" :
564 "MDI");
565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
566 netif_carrier_on(netdev);
567 } else {
568 if (testonly)
569 goto out;
570
571 netif_info(jme, link, jme->dev, "Link is down\n");
572 jme->phylink = 0;
573 netif_carrier_off(netdev);
574 }
575
576out:
577 return rc;
578}
579
580static int
581jme_setup_tx_resources(struct jme_adapter *jme)
582{
583 struct jme_ring *txring = &(jme->txring[0]);
584
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
587 &(txring->dmaalloc),
588 GFP_ATOMIC);
589
590 if (!txring->alloc)
591 goto err_set_null;
592
593 /*
594 * 16 Bytes align
595 */
596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
597 RING_DESC_ALIGN);
598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
599 txring->next_to_use = 0;
600 atomic_set(&txring->next_to_clean, 0);
601 atomic_set(&txring->nr_free, jme->tx_ring_size);
602
603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
607
608 /*
609 * Initialize Transmit Descriptors
610 */
611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
612 memset(txring->bufinf, 0,
613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
614
615 return 0;
616
617err_free_txring:
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
620 txring->alloc,
621 txring->dmaalloc);
622
623err_set_null:
624 txring->desc = NULL;
625 txring->dmaalloc = 0;
626 txring->dma = 0;
627 txring->bufinf = NULL;
628
629 return -ENOMEM;
630}
631
632static void
633jme_free_tx_resources(struct jme_adapter *jme)
634{
635 int i;
636 struct jme_ring *txring = &(jme->txring[0]);
637 struct jme_buffer_info *txbi;
638
639 if (txring->alloc) {
640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
643 if (txbi->skb) {
644 dev_kfree_skb(txbi->skb);
645 txbi->skb = NULL;
646 }
647 txbi->mapping = 0;
648 txbi->len = 0;
649 txbi->nr_desc = 0;
650 txbi->start_xmit = 0;
651 }
652 kfree(txring->bufinf);
653 }
654
655 dma_free_coherent(&(jme->pdev->dev),
656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
657 txring->alloc,
658 txring->dmaalloc);
659
660 txring->alloc = NULL;
661 txring->desc = NULL;
662 txring->dmaalloc = 0;
663 txring->dma = 0;
664 txring->bufinf = NULL;
665 }
666 txring->next_to_use = 0;
667 atomic_set(&txring->next_to_clean, 0);
668 atomic_set(&txring->nr_free, 0);
669}
670
671static inline void
672jme_enable_tx_engine(struct jme_adapter *jme)
673{
674 /*
675 * Select Queue 0
676 */
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
678 wmb();
679
680 /*
681 * Setup TX Queue 0 DMA Bass Address
682 */
683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
686
687 /*
688 * Setup TX Descptor Count
689 */
690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
691
692 /*
693 * Enable TX Engine
694 */
695 wmb();
696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
699
700 /*
701 * Start clock for TX MAC Processor
702 */
703 jme_mac_txclk_on(jme);
704}
705
706static inline void
707jme_restart_tx_engine(struct jme_adapter *jme)
708{
709 /*
710 * Restart TX Engine
711 */
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
713 TXCS_SELECT_QUEUE0 |
714 TXCS_ENABLE);
715}
716
717static inline void
718jme_disable_tx_engine(struct jme_adapter *jme)
719{
720 int i;
721 u32 val;
722
723 /*
724 * Disable TX Engine
725 */
726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
727 wmb();
728
729 val = jread32(jme, JME_TXCS);
730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
731 mdelay(1);
732 val = jread32(jme, JME_TXCS);
733 rmb();
734 }
735
736 if (!i)
737 pr_err("Disable TX engine timeout\n");
738
739 /*
740 * Stop clock for TX MAC Processor
741 */
742 jme_mac_txclk_off(jme);
743}
744
745static void
746jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
747{
748 struct jme_ring *rxring = &(jme->rxring[0]);
749 register struct rxdesc *rxdesc = rxring->desc;
750 struct jme_buffer_info *rxbi = rxring->bufinf;
751 rxdesc += i;
752 rxbi += i;
753
754 rxdesc->dw[0] = 0;
755 rxdesc->dw[1] = 0;
756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
760 if (jme->dev->features & NETIF_F_HIGHDMA)
761 rxdesc->desc1.flags = RXFLAG_64BIT;
762 wmb();
763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
764}
765
766static int
767jme_make_new_rx_buf(struct jme_adapter *jme, int i)
768{
769 struct jme_ring *rxring = &(jme->rxring[0]);
770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
771 struct sk_buff *skb;
772 dma_addr_t mapping;
773
774 skb = netdev_alloc_skb(jme->dev,
775 jme->dev->mtu + RX_EXTRA_LEN);
776 if (unlikely(!skb))
777 return -ENOMEM;
778#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
779 skb->dev = jme->dev;
780#endif
781
782 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
783 offset_in_page(skb->data), skb_tailroom(skb),
784 PCI_DMA_FROMDEVICE);
785 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
786 dev_kfree_skb(skb);
787 return -ENOMEM;
788 }
789
790 if (likely(rxbi->mapping))
791 pci_unmap_page(jme->pdev, rxbi->mapping,
792 rxbi->len, PCI_DMA_FROMDEVICE);
793
794 rxbi->skb = skb;
795 rxbi->len = skb_tailroom(skb);
796 rxbi->mapping = mapping;
797 return 0;
798}
799
800static void
801jme_free_rx_buf(struct jme_adapter *jme, int i)
802{
803 struct jme_ring *rxring = &(jme->rxring[0]);
804 struct jme_buffer_info *rxbi = rxring->bufinf;
805 rxbi += i;
806
807 if (rxbi->skb) {
808 pci_unmap_page(jme->pdev,
809 rxbi->mapping,
810 rxbi->len,
811 PCI_DMA_FROMDEVICE);
812 dev_kfree_skb(rxbi->skb);
813 rxbi->skb = NULL;
814 rxbi->mapping = 0;
815 rxbi->len = 0;
816 }
817}
818
819static void
820jme_free_rx_resources(struct jme_adapter *jme)
821{
822 int i;
823 struct jme_ring *rxring = &(jme->rxring[0]);
824
825 if (rxring->alloc) {
826 if (rxring->bufinf) {
827 for (i = 0 ; i < jme->rx_ring_size ; ++i)
828 jme_free_rx_buf(jme, i);
829 kfree(rxring->bufinf);
830 }
831
832 dma_free_coherent(&(jme->pdev->dev),
833 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
834 rxring->alloc,
835 rxring->dmaalloc);
836 rxring->alloc = NULL;
837 rxring->desc = NULL;
838 rxring->dmaalloc = 0;
839 rxring->dma = 0;
840 rxring->bufinf = NULL;
841 }
842 rxring->next_to_use = 0;
843 atomic_set(&rxring->next_to_clean, 0);
844}
845
846static int
847jme_setup_rx_resources(struct jme_adapter *jme)
848{
849 int i;
850 struct jme_ring *rxring = &(jme->rxring[0]);
851
852 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
853 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
854 &(rxring->dmaalloc),
855 GFP_ATOMIC);
856 if (!rxring->alloc)
857 goto err_set_null;
858
859 /*
860 * 16 Bytes align
861 */
862 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
863 RING_DESC_ALIGN);
864 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
865 rxring->next_to_use = 0;
866 atomic_set(&rxring->next_to_clean, 0);
867
868 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
869 jme->rx_ring_size, GFP_ATOMIC);
870 if (unlikely(!(rxring->bufinf)))
871 goto err_free_rxring;
872
873 /*
874 * Initiallize Receive Descriptors
875 */
876 memset(rxring->bufinf, 0,
877 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
878 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
879 if (unlikely(jme_make_new_rx_buf(jme, i))) {
880 jme_free_rx_resources(jme);
881 return -ENOMEM;
882 }
883
884 jme_set_clean_rxdesc(jme, i);
885 }
886
887 return 0;
888
889err_free_rxring:
890 dma_free_coherent(&(jme->pdev->dev),
891 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
892 rxring->alloc,
893 rxring->dmaalloc);
894err_set_null:
895 rxring->desc = NULL;
896 rxring->dmaalloc = 0;
897 rxring->dma = 0;
898 rxring->bufinf = NULL;
899
900 return -ENOMEM;
901}
902
903static inline void
904jme_enable_rx_engine(struct jme_adapter *jme)
905{
906 /*
907 * Select Queue 0
908 */
909 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
910 RXCS_QUEUESEL_Q0);
911 wmb();
912
913 /*
914 * Setup RX DMA Bass Address
915 */
916 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
917 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
918 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
919
920 /*
921 * Setup RX Descriptor Count
922 */
923 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
924
925 /*
926 * Setup Unicast Filter
927 */
928 jme_set_unicastaddr(jme->dev);
929 jme_set_multi(jme->dev);
930
931 /*
932 * Enable RX Engine
933 */
934 wmb();
935 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
936 RXCS_QUEUESEL_Q0 |
937 RXCS_ENABLE |
938 RXCS_QST);
939
940 /*
941 * Start clock for RX MAC Processor
942 */
943 jme_mac_rxclk_on(jme);
944}
945
946static inline void
947jme_restart_rx_engine(struct jme_adapter *jme)
948{
949 /*
950 * Start RX Engine
951 */
952 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
953 RXCS_QUEUESEL_Q0 |
954 RXCS_ENABLE |
955 RXCS_QST);
956}
957
958static inline void
959jme_disable_rx_engine(struct jme_adapter *jme)
960{
961 int i;
962 u32 val;
963
964 /*
965 * Disable RX Engine
966 */
967 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
968 wmb();
969
970 val = jread32(jme, JME_RXCS);
971 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
972 mdelay(1);
973 val = jread32(jme, JME_RXCS);
974 rmb();
975 }
976
977 if (!i)
978 pr_err("Disable RX engine timeout\n");
979
980 /*
981 * Stop clock for RX MAC Processor
982 */
983 jme_mac_rxclk_off(jme);
984}
985
986static u16
987jme_udpsum(struct sk_buff *skb)
988{
989 u16 csum = 0xFFFFu;
990#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
991 struct iphdr *iph;
992 int iphlen;
993 struct udphdr *udph;
994#endif
995
996 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
997 return csum;
998 if (skb->protocol != htons(ETH_P_IP))
999 return csum;
1000#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1001 iph = (struct iphdr *)skb_pull(skb, ETH_HLEN);
1002 iphlen = (iph->ihl << 2);
1003 if ((iph->protocol != IPPROTO_UDP) ||
1004 (skb->len < (iphlen + sizeof(struct udphdr)))) {
1005 skb_push(skb, ETH_HLEN);
1006 return csum;
1007 }
1008 udph = (struct udphdr *)skb_pull(skb, iphlen);
1009 csum = udph->check;
1010 skb_push(skb, iphlen);
1011 skb_push(skb, ETH_HLEN);
1012#else
1013 skb_set_network_header(skb, ETH_HLEN);
1014 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1015 (skb->len < (ETH_HLEN +
1016 (ip_hdr(skb)->ihl << 2) +
1017 sizeof(struct udphdr)))) {
1018 skb_reset_network_header(skb);
1019 return csum;
1020 }
1021 skb_set_transport_header(skb,
1022 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1023 csum = udp_hdr(skb)->check;
1024 skb_reset_transport_header(skb);
1025 skb_reset_network_header(skb);
1026#endif
1027
1028 return csum;
1029}
1030
1031static int
1032jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1033{
1034 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1035 return false;
1036
1037 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1038 == RXWBFLAG_TCPON)) {
1039 if (flags & RXWBFLAG_IPV4)
1040 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1041 return false;
1042 }
1043
1044 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1045 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1046 if (flags & RXWBFLAG_IPV4)
1047 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1048 return false;
1049 }
1050
1051 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1052 == RXWBFLAG_IPV4)) {
1053 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1054 return false;
1055 }
1056
1057 return true;
1058}
1059
1060static void
1061jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1062{
1063 struct jme_ring *rxring = &(jme->rxring[0]);
1064 struct rxdesc *rxdesc = rxring->desc;
1065 struct jme_buffer_info *rxbi = rxring->bufinf;
1066 struct sk_buff *skb;
1067 int framesize;
1068
1069 rxdesc += idx;
1070 rxbi += idx;
1071
1072 skb = rxbi->skb;
1073 pci_dma_sync_single_for_cpu(jme->pdev,
1074 rxbi->mapping,
1075 rxbi->len,
1076 PCI_DMA_FROMDEVICE);
1077
1078 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1079 pci_dma_sync_single_for_device(jme->pdev,
1080 rxbi->mapping,
1081 rxbi->len,
1082 PCI_DMA_FROMDEVICE);
1083
1084 ++(NET_STAT(jme).rx_dropped);
1085 } else {
1086 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1087 - RX_PREPAD_SIZE;
1088
1089 skb_reserve(skb, RX_PREPAD_SIZE);
1090 skb_put(skb, framesize);
1091 skb->protocol = eth_type_trans(skb, jme->dev);
1092
1093 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1094 skb->ip_summed = CHECKSUM_UNNECESSARY;
1095 else
1096#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
1097 skb->ip_summed = CHECKSUM_NONE;
1098#else
1099 skb_checksum_none_assert(skb);
1100#endif
1101
1102#ifndef __UNIFY_VLAN_RX_PATH__
1103 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1104 if (jme->vlgrp) {
1105 jme->jme_vlan_rx(skb, jme->vlgrp,
1106 le16_to_cpu(rxdesc->descwb.vlan));
1107 NET_STAT(jme).rx_bytes += 4;
1108 } else {
1109 dev_kfree_skb(skb);
1110 }
1111 } else {
1112 jme->jme_rx(skb);
1113 }
1114#else
1115 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1116 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1117
1118 __vlan_hwaccel_put_tag(skb, vid);
1119 NET_STAT(jme).rx_bytes += 4;
1120 }
1121 jme->jme_rx(skb);
1122#endif
1123
1124 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1125 cpu_to_le16(RXWBFLAG_DEST_MUL))
1126 ++(NET_STAT(jme).multicast);
1127
1128 NET_STAT(jme).rx_bytes += framesize;
1129 ++(NET_STAT(jme).rx_packets);
1130 }
1131
1132 jme_set_clean_rxdesc(jme, idx);
1133
1134}
1135
1136static int
1137jme_process_receive(struct jme_adapter *jme, int limit)
1138{
1139 struct jme_ring *rxring = &(jme->rxring[0]);
1140 struct rxdesc *rxdesc = rxring->desc;
1141 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1142
1143 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1144 goto out_inc;
1145
1146 if (unlikely(atomic_read(&jme->link_changing) != 1))
1147 goto out_inc;
1148
1149 if (unlikely(!netif_carrier_ok(jme->dev)))
1150 goto out_inc;
1151
1152 i = atomic_read(&rxring->next_to_clean);
1153 while (limit > 0) {
1154 rxdesc = rxring->desc;
1155 rxdesc += i;
1156
1157 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1158 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1159 goto out;
1160 --limit;
1161
1162 rmb();
1163 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1164
1165 if (unlikely(desccnt > 1 ||
1166 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1167
1168 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1169 ++(NET_STAT(jme).rx_crc_errors);
1170 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1171 ++(NET_STAT(jme).rx_fifo_errors);
1172 else
1173 ++(NET_STAT(jme).rx_errors);
1174
1175 if (desccnt > 1)
1176 limit -= desccnt - 1;
1177
1178 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1179 jme_set_clean_rxdesc(jme, j);
1180 j = (j + 1) & (mask);
1181 }
1182
1183 } else {
1184 jme_alloc_and_feed_skb(jme, i);
1185 }
1186
1187 i = (i + desccnt) & (mask);
1188 }
1189
1190out:
1191 atomic_set(&rxring->next_to_clean, i);
1192
1193out_inc:
1194 atomic_inc(&jme->rx_cleaning);
1195
1196 return limit > 0 ? limit : 0;
1197
1198}
1199
1200static void
1201jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1202{
1203 if (likely(atmp == dpi->cur)) {
1204 dpi->cnt = 0;
1205 return;
1206 }
1207
1208 if (dpi->attempt == atmp) {
1209 ++(dpi->cnt);
1210 } else {
1211 dpi->attempt = atmp;
1212 dpi->cnt = 0;
1213 }
1214
1215}
1216
1217static void
1218jme_dynamic_pcc(struct jme_adapter *jme)
1219{
1220 register struct dynpcc_info *dpi = &(jme->dpi);
1221
1222 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1223 jme_attempt_pcc(dpi, PCC_P3);
1224 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1225 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1226 jme_attempt_pcc(dpi, PCC_P2);
1227 else
1228 jme_attempt_pcc(dpi, PCC_P1);
1229
1230 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1231 if (dpi->attempt < dpi->cur)
1232 tasklet_schedule(&jme->rxclean_task);
1233 jme_set_rx_pcc(jme, dpi->attempt);
1234 dpi->cur = dpi->attempt;
1235 dpi->cnt = 0;
1236 }
1237}
1238
1239static void
1240jme_start_pcc_timer(struct jme_adapter *jme)
1241{
1242 struct dynpcc_info *dpi = &(jme->dpi);
1243 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1244 dpi->last_pkts = NET_STAT(jme).rx_packets;
1245 dpi->intr_cnt = 0;
1246 jwrite32(jme, JME_TMCSR,
1247 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1248}
1249
1250static inline void
1251jme_stop_pcc_timer(struct jme_adapter *jme)
1252{
1253 jwrite32(jme, JME_TMCSR, 0);
1254}
1255
1256static void
1257jme_shutdown_nic(struct jme_adapter *jme)
1258{
1259 u32 phylink;
1260
1261 phylink = jme_linkstat_from_phy(jme);
1262
1263 if (!(phylink & PHY_LINK_UP)) {
1264 /*
1265 * Disable all interrupt before issue timer
1266 */
1267 jme_stop_irq(jme);
1268 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1269 }
1270}
1271
1272static void
1273jme_pcc_tasklet(unsigned long arg)
1274{
1275 struct jme_adapter *jme = (struct jme_adapter *)arg;
1276 struct net_device *netdev = jme->dev;
1277
1278 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1279 jme_shutdown_nic(jme);
1280 return;
1281 }
1282
1283 if (unlikely(!netif_carrier_ok(netdev) ||
1284 (atomic_read(&jme->link_changing) != 1)
1285 )) {
1286 jme_stop_pcc_timer(jme);
1287 return;
1288 }
1289
1290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1291 jme_dynamic_pcc(jme);
1292
1293 jme_start_pcc_timer(jme);
1294}
1295
1296static inline void
1297jme_polling_mode(struct jme_adapter *jme)
1298{
1299 jme_set_rx_pcc(jme, PCC_OFF);
1300}
1301
1302static inline void
1303jme_interrupt_mode(struct jme_adapter *jme)
1304{
1305 jme_set_rx_pcc(jme, PCC_P1);
1306}
1307
1308static inline int
1309jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1310{
1311 u32 apmc;
1312 apmc = jread32(jme, JME_APMC);
1313 return apmc & JME_APMC_PSEUDO_HP_EN;
1314}
1315
1316static void
1317jme_start_shutdown_timer(struct jme_adapter *jme)
1318{
1319 u32 apmc;
1320
1321 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1322 apmc &= ~JME_APMC_EPIEN_CTRL;
1323 if (!no_extplug) {
1324 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1325 wmb();
1326 }
1327 jwrite32f(jme, JME_APMC, apmc);
1328
1329 jwrite32f(jme, JME_TIMER2, 0);
1330 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1331 jwrite32(jme, JME_TMCSR,
1332 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1333}
1334
1335static void
1336jme_stop_shutdown_timer(struct jme_adapter *jme)
1337{
1338 u32 apmc;
1339
1340 jwrite32f(jme, JME_TMCSR, 0);
1341 jwrite32f(jme, JME_TIMER2, 0);
1342 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1343
1344 apmc = jread32(jme, JME_APMC);
1345 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1346 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1347 wmb();
1348 jwrite32f(jme, JME_APMC, apmc);
1349}
1350
1351static void
1352jme_link_change_tasklet(unsigned long arg)
1353{
1354 struct jme_adapter *jme = (struct jme_adapter *)arg;
1355 struct net_device *netdev = jme->dev;
1356 int rc;
1357
1358 while (!atomic_dec_and_test(&jme->link_changing)) {
1359 atomic_inc(&jme->link_changing);
1360 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1361 while (atomic_read(&jme->link_changing) != 1)
1362 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1363 }
1364
1365 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1366 goto out;
1367
1368 jme->old_mtu = netdev->mtu;
1369 netif_stop_queue(netdev);
1370 if (jme_pseudo_hotplug_enabled(jme))
1371 jme_stop_shutdown_timer(jme);
1372
1373 jme_stop_pcc_timer(jme);
1374 tasklet_disable(&jme->txclean_task);
1375 tasklet_disable(&jme->rxclean_task);
1376 tasklet_disable(&jme->rxempty_task);
1377
1378 if (netif_carrier_ok(netdev)) {
1379 jme_disable_rx_engine(jme);
1380 jme_disable_tx_engine(jme);
1381 jme_reset_mac_processor(jme);
1382 jme_free_rx_resources(jme);
1383 jme_free_tx_resources(jme);
1384
1385 if (test_bit(JME_FLAG_POLL, &jme->flags))
1386 jme_polling_mode(jme);
1387
1388 netif_carrier_off(netdev);
1389 }
1390
1391 jme_check_link(netdev, 0);
1392 if (netif_carrier_ok(netdev)) {
1393 rc = jme_setup_rx_resources(jme);
1394 if (rc) {
1395 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1396 goto out_enable_tasklet;
1397 }
1398
1399 rc = jme_setup_tx_resources(jme);
1400 if (rc) {
1401 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1402 goto err_out_free_rx_resources;
1403 }
1404
1405 jme_enable_rx_engine(jme);
1406 jme_enable_tx_engine(jme);
1407
1408 netif_start_queue(netdev);
1409
1410 if (test_bit(JME_FLAG_POLL, &jme->flags))
1411 jme_interrupt_mode(jme);
1412
1413 jme_start_pcc_timer(jme);
1414 } else if (jme_pseudo_hotplug_enabled(jme)) {
1415 jme_start_shutdown_timer(jme);
1416 }
1417
1418 goto out_enable_tasklet;
1419
1420err_out_free_rx_resources:
1421 jme_free_rx_resources(jme);
1422out_enable_tasklet:
1423 tasklet_enable(&jme->txclean_task);
1424 tasklet_hi_enable(&jme->rxclean_task);
1425 tasklet_hi_enable(&jme->rxempty_task);
1426out:
1427 atomic_inc(&jme->link_changing);
1428}
1429
1430static void
1431jme_rx_clean_tasklet(unsigned long arg)
1432{
1433 struct jme_adapter *jme = (struct jme_adapter *)arg;
1434 struct dynpcc_info *dpi = &(jme->dpi);
1435
1436 jme_process_receive(jme, jme->rx_ring_size);
1437 ++(dpi->intr_cnt);
1438
1439}
1440
1441static int
1442jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1443{
1444 struct jme_adapter *jme = jme_napi_priv(holder);
1445 DECLARE_NETDEV
1446 int rest;
1447
1448 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1449
1450 while (atomic_read(&jme->rx_empty) > 0) {
1451 atomic_dec(&jme->rx_empty);
1452 ++(NET_STAT(jme).rx_dropped);
1453 jme_restart_rx_engine(jme);
1454 }
1455 atomic_inc(&jme->rx_empty);
1456
1457 if (rest) {
1458 JME_RX_COMPLETE(netdev, holder);
1459 jme_interrupt_mode(jme);
1460 }
1461
1462 JME_NAPI_WEIGHT_SET(budget, rest);
1463 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1464}
1465
1466static void
1467jme_rx_empty_tasklet(unsigned long arg)
1468{
1469 struct jme_adapter *jme = (struct jme_adapter *)arg;
1470
1471 if (unlikely(atomic_read(&jme->link_changing) != 1))
1472 return;
1473
1474 if (unlikely(!netif_carrier_ok(jme->dev)))
1475 return;
1476
1477 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1478
1479 jme_rx_clean_tasklet(arg);
1480
1481 while (atomic_read(&jme->rx_empty) > 0) {
1482 atomic_dec(&jme->rx_empty);
1483 ++(NET_STAT(jme).rx_dropped);
1484 jme_restart_rx_engine(jme);
1485 }
1486 atomic_inc(&jme->rx_empty);
1487}
1488
1489static void
1490jme_wake_queue_if_stopped(struct jme_adapter *jme)
1491{
1492 struct jme_ring *txring = &(jme->txring[0]);
1493
1494 smp_wmb();
1495 if (unlikely(netif_queue_stopped(jme->dev) &&
1496 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1497 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1498 netif_wake_queue(jme->dev);
1499 }
1500
1501}
1502
1503static void
1504jme_tx_clean_tasklet(unsigned long arg)
1505{
1506 struct jme_adapter *jme = (struct jme_adapter *)arg;
1507 struct jme_ring *txring = &(jme->txring[0]);
1508 struct txdesc *txdesc = txring->desc;
1509 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1510 int i, j, cnt = 0, max, err, mask;
1511
1512 tx_dbg(jme, "Into txclean\n");
1513
1514 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1515 goto out;
1516
1517 if (unlikely(atomic_read(&jme->link_changing) != 1))
1518 goto out;
1519
1520 if (unlikely(!netif_carrier_ok(jme->dev)))
1521 goto out;
1522
1523 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1524 mask = jme->tx_ring_mask;
1525
1526 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1527
1528 ctxbi = txbi + i;
1529
1530 if (likely(ctxbi->skb &&
1531 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1532
1533 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1534 i, ctxbi->nr_desc, jiffies);
1535
1536 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1537
1538 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1539 ttxbi = txbi + ((i + j) & (mask));
1540 txdesc[(i + j) & (mask)].dw[0] = 0;
1541
1542 pci_unmap_page(jme->pdev,
1543 ttxbi->mapping,
1544 ttxbi->len,
1545 PCI_DMA_TODEVICE);
1546
1547 ttxbi->mapping = 0;
1548 ttxbi->len = 0;
1549 }
1550
1551 dev_kfree_skb(ctxbi->skb);
1552
1553 cnt += ctxbi->nr_desc;
1554
1555 if (unlikely(err)) {
1556 ++(NET_STAT(jme).tx_carrier_errors);
1557 } else {
1558 ++(NET_STAT(jme).tx_packets);
1559 NET_STAT(jme).tx_bytes += ctxbi->len;
1560 }
1561
1562 ctxbi->skb = NULL;
1563 ctxbi->len = 0;
1564 ctxbi->start_xmit = 0;
1565
1566 } else {
1567 break;
1568 }
1569
1570 i = (i + ctxbi->nr_desc) & mask;
1571
1572 ctxbi->nr_desc = 0;
1573 }
1574
1575 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1576 atomic_set(&txring->next_to_clean, i);
1577 atomic_add(cnt, &txring->nr_free);
1578
1579 jme_wake_queue_if_stopped(jme);
1580
1581out:
1582 atomic_inc(&jme->tx_cleaning);
1583}
1584
1585static void
1586jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1587{
1588 /*
1589 * Disable interrupt
1590 */
1591 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1592
1593 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1594 /*
1595 * Link change event is critical
1596 * all other events are ignored
1597 */
1598 jwrite32(jme, JME_IEVE, intrstat);
1599 tasklet_schedule(&jme->linkch_task);
1600 goto out_reenable;
1601 }
1602
1603 if (intrstat & INTR_TMINTR) {
1604 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1605 tasklet_schedule(&jme->pcc_task);
1606 }
1607
1608 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1609 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1610 tasklet_schedule(&jme->txclean_task);
1611 }
1612
1613 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1614 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1615 INTR_PCCRX0 |
1616 INTR_RX0EMP)) |
1617 INTR_RX0);
1618 }
1619
1620 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1621 if (intrstat & INTR_RX0EMP)
1622 atomic_inc(&jme->rx_empty);
1623
1624 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1625 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1626 jme_polling_mode(jme);
1627 JME_RX_SCHEDULE(jme);
1628 }
1629 }
1630 } else {
1631 if (intrstat & INTR_RX0EMP) {
1632 atomic_inc(&jme->rx_empty);
1633 tasklet_hi_schedule(&jme->rxempty_task);
1634 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1635 tasklet_hi_schedule(&jme->rxclean_task);
1636 }
1637 }
1638
1639out_reenable:
1640 /*
1641 * Re-enable interrupt
1642 */
1643 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1644}
1645
1646#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1647static irqreturn_t
1648jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1649#else
1650static irqreturn_t
1651jme_intr(int irq, void *dev_id)
1652#endif
1653{
1654 struct net_device *netdev = dev_id;
1655 struct jme_adapter *jme = netdev_priv(netdev);
1656 u32 intrstat;
1657
1658 intrstat = jread32(jme, JME_IEVE);
1659
1660 /*
1661 * Check if it's really an interrupt for us
1662 */
1663 if (unlikely((intrstat & INTR_ENABLE) == 0))
1664 return IRQ_NONE;
1665
1666 /*
1667 * Check if the device still exist
1668 */
1669 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1670 return IRQ_NONE;
1671
1672 jme_intr_msi(jme, intrstat);
1673
1674 return IRQ_HANDLED;
1675}
1676
1677#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1678static irqreturn_t
1679jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1680#else
1681static irqreturn_t
1682jme_msi(int irq, void *dev_id)
1683#endif
1684{
1685 struct net_device *netdev = dev_id;
1686 struct jme_adapter *jme = netdev_priv(netdev);
1687 u32 intrstat;
1688
1689 intrstat = jread32(jme, JME_IEVE);
1690
1691 jme_intr_msi(jme, intrstat);
1692
1693 return IRQ_HANDLED;
1694}
1695
1696static void
1697jme_reset_link(struct jme_adapter *jme)
1698{
1699 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1700}
1701
1702static void
1703jme_restart_an(struct jme_adapter *jme)
1704{
1705 u32 bmcr;
1706
1707 spin_lock_bh(&jme->phy_lock);
1708 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1709 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1710 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1711 spin_unlock_bh(&jme->phy_lock);
1712}
1713
1714static int
1715jme_request_irq(struct jme_adapter *jme)
1716{
1717 int rc;
1718 struct net_device *netdev = jme->dev;
1719#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1720 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1721 int irq_flags = SA_SHIRQ;
1722#else
1723 irq_handler_t handler = jme_intr;
1724 int irq_flags = IRQF_SHARED;
1725#endif
1726
1727 if (!pci_enable_msi(jme->pdev)) {
1728 set_bit(JME_FLAG_MSI, &jme->flags);
1729 handler = jme_msi;
1730 irq_flags = 0;
1731 }
1732
1733 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1734 netdev);
1735 if (rc) {
1736 netdev_err(netdev,
1737 "Unable to request %s interrupt (return: %d)\n",
1738 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1739 rc);
1740
1741 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1742 pci_disable_msi(jme->pdev);
1743 clear_bit(JME_FLAG_MSI, &jme->flags);
1744 }
1745 } else {
1746 netdev->irq = jme->pdev->irq;
1747 }
1748
1749 return rc;
1750}
1751
1752static void
1753jme_free_irq(struct jme_adapter *jme)
1754{
1755 free_irq(jme->pdev->irq, jme->dev);
1756 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1757 pci_disable_msi(jme->pdev);
1758 clear_bit(JME_FLAG_MSI, &jme->flags);
1759 jme->dev->irq = jme->pdev->irq;
1760 }
1761}
1762
1763static inline void
1764jme_new_phy_on(struct jme_adapter *jme)
1765{
1766 u32 reg;
1767
1768 reg = jread32(jme, JME_PHY_PWR);
1769 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1770 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1771 jwrite32(jme, JME_PHY_PWR, reg);
1772
1773 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1774 reg &= ~PE1_GPREG0_PBG;
1775 reg |= PE1_GPREG0_ENBG;
1776 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1777}
1778
1779static inline void
1780jme_new_phy_off(struct jme_adapter *jme)
1781{
1782 u32 reg;
1783
1784 reg = jread32(jme, JME_PHY_PWR);
1785 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1786 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1787 jwrite32(jme, JME_PHY_PWR, reg);
1788
1789 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1790 reg &= ~PE1_GPREG0_PBG;
1791 reg |= PE1_GPREG0_PDD3COLD;
1792 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1793}
1794
1795static inline void
1796jme_phy_on(struct jme_adapter *jme)
1797{
1798 u32 bmcr;
1799
1800 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1801 bmcr &= ~BMCR_PDOWN;
1802 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1803
1804 if (new_phy_power_ctrl(jme->chip_main_rev))
1805 jme_new_phy_on(jme);
1806}
1807
1808static inline void
1809jme_phy_off(struct jme_adapter *jme)
1810{
1811 u32 bmcr;
1812
1813 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1814 bmcr |= BMCR_PDOWN;
1815 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1816
1817 if (new_phy_power_ctrl(jme->chip_main_rev))
1818 jme_new_phy_off(jme);
1819}
1820
1821static int
1822jme_open(struct net_device *netdev)
1823{
1824 struct jme_adapter *jme = netdev_priv(netdev);
1825 int rc;
1826
1827 jme_clear_pm(jme);
1828 JME_NAPI_ENABLE(jme);
1829
1830 tasklet_enable(&jme->linkch_task);
1831 tasklet_enable(&jme->txclean_task);
1832 tasklet_hi_enable(&jme->rxclean_task);
1833 tasklet_hi_enable(&jme->rxempty_task);
1834
1835 rc = jme_request_irq(jme);
1836 if (rc)
1837 goto err_out;
1838
1839 jme_start_irq(jme);
1840
1841 jme_phy_on(jme);
1842 if (test_bit(JME_FLAG_SSET, &jme->flags))
1843 jme_set_settings(netdev, &jme->old_ecmd);
1844 else
1845 jme_reset_phy_processor(jme);
1846
1847 jme_reset_link(jme);
1848
1849 return 0;
1850
1851err_out:
1852 netif_stop_queue(netdev);
1853 netif_carrier_off(netdev);
1854 return rc;
1855}
1856
1857static void
1858jme_set_100m_half(struct jme_adapter *jme)
1859{
1860 u32 bmcr, tmp;
1861
1862 jme_phy_on(jme);
1863 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1864 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1865 BMCR_SPEED1000 | BMCR_FULLDPLX);
1866 tmp |= BMCR_SPEED100;
1867
1868 if (bmcr != tmp)
1869 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1870
1871 if (jme->fpgaver)
1872 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1873 else
1874 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1875}
1876
1877#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1878static void
1879jme_wait_link(struct jme_adapter *jme)
1880{
1881 u32 phylink, to = JME_WAIT_LINK_TIME;
1882
1883 mdelay(1000);
1884 phylink = jme_linkstat_from_phy(jme);
1885 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1886 mdelay(10);
1887 phylink = jme_linkstat_from_phy(jme);
1888 }
1889}
1890
1891static void
1892jme_powersave_phy(struct jme_adapter *jme)
1893{
1894 if (jme->reg_pmcs) {
1895 jme_set_100m_half(jme);
1896 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1897 jme_wait_link(jme);
1898 jme_clear_pm(jme);
1899 } else {
1900 jme_phy_off(jme);
1901 }
1902}
1903
1904static int
1905jme_close(struct net_device *netdev)
1906{
1907 struct jme_adapter *jme = netdev_priv(netdev);
1908
1909 netif_stop_queue(netdev);
1910 netif_carrier_off(netdev);
1911
1912 jme_stop_irq(jme);
1913 jme_free_irq(jme);
1914
1915 JME_NAPI_DISABLE(jme);
1916
1917 tasklet_disable(&jme->linkch_task);
1918 tasklet_disable(&jme->txclean_task);
1919 tasklet_disable(&jme->rxclean_task);
1920 tasklet_disable(&jme->rxempty_task);
1921
1922 jme_disable_rx_engine(jme);
1923 jme_disable_tx_engine(jme);
1924 jme_reset_mac_processor(jme);
1925 jme_free_rx_resources(jme);
1926 jme_free_tx_resources(jme);
1927 jme->phylink = 0;
1928 jme_phy_off(jme);
1929
1930 return 0;
1931}
1932
1933static int
1934jme_alloc_txdesc(struct jme_adapter *jme,
1935 struct sk_buff *skb)
1936{
1937 struct jme_ring *txring = &(jme->txring[0]);
1938 int idx, nr_alloc, mask = jme->tx_ring_mask;
1939
1940 idx = txring->next_to_use;
1941 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1942
1943 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1944 return -1;
1945
1946 atomic_sub(nr_alloc, &txring->nr_free);
1947
1948 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1949
1950 return idx;
1951}
1952
1953static void
1954jme_fill_tx_map(struct pci_dev *pdev,
1955 struct txdesc *txdesc,
1956 struct jme_buffer_info *txbi,
1957 struct page *page,
1958 u32 page_offset,
1959 u32 len,
1960 u8 hidma)
1961{
1962 dma_addr_t dmaaddr;
1963
1964 dmaaddr = pci_map_page(pdev,
1965 page,
1966 page_offset,
1967 len,
1968 PCI_DMA_TODEVICE);
1969
1970 pci_dma_sync_single_for_device(pdev,
1971 dmaaddr,
1972 len,
1973 PCI_DMA_TODEVICE);
1974
1975 txdesc->dw[0] = 0;
1976 txdesc->dw[1] = 0;
1977 txdesc->desc2.flags = TXFLAG_OWN;
1978 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1979 txdesc->desc2.datalen = cpu_to_le16(len);
1980 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1981 txdesc->desc2.bufaddrl = cpu_to_le32(
1982 (__u64)dmaaddr & 0xFFFFFFFFUL);
1983
1984 txbi->mapping = dmaaddr;
1985 txbi->len = len;
1986}
1987
1988static void
1989jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1990{
1991 struct jme_ring *txring = &(jme->txring[0]);
1992 struct txdesc *txdesc = txring->desc, *ctxdesc;
1993 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1994 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1995 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1996 int mask = jme->tx_ring_mask;
1997 struct skb_frag_struct *frag;
1998 u32 len;
1999
2000 for (i = 0 ; i < nr_frags ; ++i) {
2001 frag = &skb_shinfo(skb)->frags[i];
2002 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2003 ctxbi = txbi + ((idx + i + 2) & (mask));
2004
2005 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
2006 frag->page_offset, frag->size, hidma);
2007 }
2008
2009 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2010 ctxdesc = txdesc + ((idx + 1) & (mask));
2011 ctxbi = txbi + ((idx + 1) & (mask));
2012 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2013 offset_in_page(skb->data), len, hidma);
2014
2015}
2016
2017static int
2018jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2019{
2020 if (unlikely(
2021#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2022 skb_shinfo(skb)->tso_size
2023#else
2024 skb_shinfo(skb)->gso_size
2025#endif
2026 && skb_header_cloned(skb) &&
2027 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2028 dev_kfree_skb(skb);
2029 return -1;
2030 }
2031
2032 return 0;
2033}
2034
2035static int
2036jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2037{
2038#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2039 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2040#else
2041 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2042#endif
2043 if (*mss) {
2044 *flags |= TXFLAG_LSEN;
2045
2046 if (skb->protocol == htons(ETH_P_IP)) {
2047 struct iphdr *iph = ip_hdr(skb);
2048
2049 iph->check = 0;
2050 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2051 iph->daddr, 0,
2052 IPPROTO_TCP,
2053 0);
2054 } else {
2055 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2056
2057 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2058 &ip6h->daddr, 0,
2059 IPPROTO_TCP,
2060 0);
2061 }
2062
2063 return 0;
2064 }
2065
2066 return 1;
2067}
2068
2069static void
2070jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2071{
2072#ifdef CHECKSUM_PARTIAL
2073 if (skb->ip_summed == CHECKSUM_PARTIAL)
2074#else
2075 if (skb->ip_summed == CHECKSUM_HW)
2076#endif
2077 {
2078 u8 ip_proto;
2079
2080#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2081 if (skb->protocol == htons(ETH_P_IP))
2082 ip_proto = ip_hdr(skb)->protocol;
2083 else if (skb->protocol == htons(ETH_P_IPV6))
2084 ip_proto = ipv6_hdr(skb)->nexthdr;
2085 else
2086 ip_proto = 0;
2087#else
2088 switch (skb->protocol) {
2089 case htons(ETH_P_IP):
2090 ip_proto = ip_hdr(skb)->protocol;
2091 break;
2092 case htons(ETH_P_IPV6):
2093 ip_proto = ipv6_hdr(skb)->nexthdr;
2094 break;
2095 default:
2096 ip_proto = 0;
2097 break;
2098 }
2099#endif
2100
2101 switch (ip_proto) {
2102 case IPPROTO_TCP:
2103 *flags |= TXFLAG_TCPCS;
2104 break;
2105 case IPPROTO_UDP:
2106 *flags |= TXFLAG_UDPCS;
2107 break;
2108 default:
2109 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2110 break;
2111 }
2112 }
2113}
2114
2115static inline void
2116jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2117{
2118 if (vlan_tx_tag_present(skb)) {
2119 *flags |= TXFLAG_TAGON;
2120 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2121 }
2122}
2123
2124static int
2125jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2126{
2127 struct jme_ring *txring = &(jme->txring[0]);
2128 struct txdesc *txdesc;
2129 struct jme_buffer_info *txbi;
2130 u8 flags;
2131
2132 txdesc = (struct txdesc *)txring->desc + idx;
2133 txbi = txring->bufinf + idx;
2134
2135 txdesc->dw[0] = 0;
2136 txdesc->dw[1] = 0;
2137 txdesc->dw[2] = 0;
2138 txdesc->dw[3] = 0;
2139 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2140 /*
2141 * Set OWN bit at final.
2142 * When kernel transmit faster than NIC.
2143 * And NIC trying to send this descriptor before we tell
2144 * it to start sending this TX queue.
2145 * Other fields are already filled correctly.
2146 */
2147 wmb();
2148 flags = TXFLAG_OWN | TXFLAG_INT;
2149 /*
2150 * Set checksum flags while not tso
2151 */
2152 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2153 jme_tx_csum(jme, skb, &flags);
2154 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2155 jme_map_tx_skb(jme, skb, idx);
2156 txdesc->desc1.flags = flags;
2157 /*
2158 * Set tx buffer info after telling NIC to send
2159 * For better tx_clean timing
2160 */
2161 wmb();
2162 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2163 txbi->skb = skb;
2164 txbi->len = skb->len;
2165 txbi->start_xmit = jiffies;
2166 if (!txbi->start_xmit)
2167 txbi->start_xmit = (0UL-1);
2168
2169 return 0;
2170}
2171
2172static void
2173jme_stop_queue_if_full(struct jme_adapter *jme)
2174{
2175 struct jme_ring *txring = &(jme->txring[0]);
2176 struct jme_buffer_info *txbi = txring->bufinf;
2177 int idx = atomic_read(&txring->next_to_clean);
2178
2179 txbi += idx;
2180
2181 smp_wmb();
2182 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2183 netif_stop_queue(jme->dev);
2184 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2185 smp_wmb();
2186 if (atomic_read(&txring->nr_free)
2187 >= (jme->tx_wake_threshold)) {
2188 netif_wake_queue(jme->dev);
2189 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2190 }
2191 }
2192
2193 if (unlikely(txbi->start_xmit &&
2194 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2195 txbi->skb)) {
2196 netif_stop_queue(jme->dev);
2197 netif_info(jme, tx_queued, jme->dev,
2198 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2199 }
2200}
2201
2202/*
2203 * This function is already protected by netif_tx_lock()
2204 */
2205
2206#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2207static int
2208#else
2209static netdev_tx_t
2210#endif
2211jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2212{
2213 struct jme_adapter *jme = netdev_priv(netdev);
2214 int idx;
2215
2216 if (unlikely(jme_expand_header(jme, skb))) {
2217 ++(NET_STAT(jme).tx_dropped);
2218 return NETDEV_TX_OK;
2219 }
2220
2221 idx = jme_alloc_txdesc(jme, skb);
2222
2223 if (unlikely(idx < 0)) {
2224 netif_stop_queue(netdev);
2225 netif_err(jme, tx_err, jme->dev,
2226 "BUG! Tx ring full when queue awake!\n");
2227
2228 return NETDEV_TX_BUSY;
2229 }
2230
2231 jme_fill_tx_desc(jme, skb, idx);
2232
2233 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2234 TXCS_SELECT_QUEUE0 |
2235 TXCS_QUEUE0S |
2236 TXCS_ENABLE);
2237#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2238 netdev->trans_start = jiffies;
2239#endif
2240
2241 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2242 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2243 jme_stop_queue_if_full(jme);
2244
2245 return NETDEV_TX_OK;
2246}
2247
2248static void
2249jme_set_unicastaddr(struct net_device *netdev)
2250{
2251 struct jme_adapter *jme = netdev_priv(netdev);
2252 u32 val;
2253
2254 val = (netdev->dev_addr[3] & 0xff) << 24 |
2255 (netdev->dev_addr[2] & 0xff) << 16 |
2256 (netdev->dev_addr[1] & 0xff) << 8 |
2257 (netdev->dev_addr[0] & 0xff);
2258 jwrite32(jme, JME_RXUMA_LO, val);
2259 val = (netdev->dev_addr[5] & 0xff) << 8 |
2260 (netdev->dev_addr[4] & 0xff);
2261 jwrite32(jme, JME_RXUMA_HI, val);
2262}
2263
2264static int
2265jme_set_macaddr(struct net_device *netdev, void *p)
2266{
2267 struct jme_adapter *jme = netdev_priv(netdev);
2268 struct sockaddr *addr = p;
2269
2270 if (netif_running(netdev))
2271 return -EBUSY;
2272
2273 spin_lock_bh(&jme->macaddr_lock);
2274 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2275 jme_set_unicastaddr(netdev);
2276 spin_unlock_bh(&jme->macaddr_lock);
2277
2278 return 0;
2279}
2280
2281static void
2282jme_set_multi(struct net_device *netdev)
2283{
2284 struct jme_adapter *jme = netdev_priv(netdev);
2285 u32 mc_hash[2] = {};
2286#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2287 int i;
2288#endif
2289
2290 spin_lock_bh(&jme->rxmcs_lock);
2291
2292 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2293
2294 if (netdev->flags & IFF_PROMISC) {
2295 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2296 } else if (netdev->flags & IFF_ALLMULTI) {
2297 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2298 } else if (netdev->flags & IFF_MULTICAST) {
2299#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2300 struct dev_mc_list *mclist;
2301#else
2302 struct netdev_hw_addr *ha;
2303#endif
2304 int bit_nr;
2305
2306 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2307#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2308 for (i = 0, mclist = netdev->mc_list;
2309 mclist && i < netdev->mc_count;
2310 ++i, mclist = mclist->next) {
2311#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2312 netdev_for_each_mc_addr(mclist, netdev) {
2313#else
2314 netdev_for_each_mc_addr(ha, netdev) {
2315#endif
2316#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2317 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2318#else
2319 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2320#endif
2321 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2322 }
2323
2324 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2325 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2326 }
2327
2328 wmb();
2329 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2330
2331 spin_unlock_bh(&jme->rxmcs_lock);
2332}
2333
2334static int
2335jme_change_mtu(struct net_device *netdev, int new_mtu)
2336{
2337 struct jme_adapter *jme = netdev_priv(netdev);
2338
2339 if (new_mtu == jme->old_mtu)
2340 return 0;
2341
2342 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2343 ((new_mtu) < IPV6_MIN_MTU))
2344 return -EINVAL;
2345
2346 if (new_mtu > 4000) {
2347 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2348 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2349 jme_restart_rx_engine(jme);
2350 } else {
2351 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2352 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2353 jme_restart_rx_engine(jme);
2354 }
2355
2356#ifndef __USE_NDO_FIX_FEATURES__
2357 if (new_mtu > 1900) {
2358 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2359 NETIF_F_TSO | NETIF_F_TSO6);
2360 } else {
2361 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2362 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2363 if (test_bit(JME_FLAG_TSO, &jme->flags))
2364 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2365 }
2366#endif
2367
2368 netdev->mtu = new_mtu;
2369#ifdef __USE_NDO_FIX_FEATURES__
2370 netdev_update_features(netdev);
2371#endif
2372 jme_reset_link(jme);
2373
2374 return 0;
2375}
2376
2377static void
2378jme_tx_timeout(struct net_device *netdev)
2379{
2380 struct jme_adapter *jme = netdev_priv(netdev);
2381
2382 jme->phylink = 0;
2383 jme_reset_phy_processor(jme);
2384 if (test_bit(JME_FLAG_SSET, &jme->flags))
2385 jme_set_settings(netdev, &jme->old_ecmd);
2386
2387 /*
2388 * Force to Reset the link again
2389 */
2390 jme_reset_link(jme);
2391}
2392
2393static inline void jme_pause_rx(struct jme_adapter *jme)
2394{
2395 atomic_dec(&jme->link_changing);
2396
2397 jme_set_rx_pcc(jme, PCC_OFF);
2398 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2399 JME_NAPI_DISABLE(jme);
2400 } else {
2401 tasklet_disable(&jme->rxclean_task);
2402 tasklet_disable(&jme->rxempty_task);
2403 }
2404}
2405
2406static inline void jme_resume_rx(struct jme_adapter *jme)
2407{
2408 struct dynpcc_info *dpi = &(jme->dpi);
2409
2410 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2411 JME_NAPI_ENABLE(jme);
2412 } else {
2413 tasklet_hi_enable(&jme->rxclean_task);
2414 tasklet_hi_enable(&jme->rxempty_task);
2415 }
2416 dpi->cur = PCC_P1;
2417 dpi->attempt = PCC_P1;
2418 dpi->cnt = 0;
2419 jme_set_rx_pcc(jme, PCC_P1);
2420
2421 atomic_inc(&jme->link_changing);
2422}
2423
2424#ifndef __UNIFY_VLAN_RX_PATH__
2425static void
2426jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2427{
2428 struct jme_adapter *jme = netdev_priv(netdev);
2429
2430 jme_pause_rx(jme);
2431 jme->vlgrp = grp;
2432 jme_resume_rx(jme);
2433}
2434#endif
2435
2436#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2437static void
2438jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2439{
2440 struct jme_adapter *jme = netdev_priv(netdev);
2441
2442 if(jme->vlgrp) {
2443 jme_pause_rx(jme);
2444#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2445 jme->vlgrp->vlan_devices[vid] = NULL;
2446#else
2447 vlan_group_set_device(jme->vlgrp, vid, NULL);
2448#endif
2449 jme_resume_rx(jme);
2450 }
2451}
2452#endif
2453
2454static void
2455jme_get_drvinfo(struct net_device *netdev,
2456 struct ethtool_drvinfo *info)
2457{
2458 struct jme_adapter *jme = netdev_priv(netdev);
2459
2460 strcpy(info->driver, DRV_NAME);
2461 strcpy(info->version, DRV_VERSION);
2462 strcpy(info->bus_info, pci_name(jme->pdev));
2463}
2464
2465static int
2466jme_get_regs_len(struct net_device *netdev)
2467{
2468 return JME_REG_LEN;
2469}
2470
2471static void
2472mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2473{
2474 int i;
2475
2476 for (i = 0 ; i < len ; i += 4)
2477 p[i >> 2] = jread32(jme, reg + i);
2478}
2479
2480static void
2481mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2482{
2483 int i;
2484 u16 *p16 = (u16 *)p;
2485
2486 for (i = 0 ; i < reg_nr ; ++i)
2487 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2488}
2489
2490static void
2491jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2492{
2493 struct jme_adapter *jme = netdev_priv(netdev);
2494 u32 *p32 = (u32 *)p;
2495
2496 memset(p, 0xFF, JME_REG_LEN);
2497
2498 regs->version = 1;
2499 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2500
2501 p32 += 0x100 >> 2;
2502 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2503
2504 p32 += 0x100 >> 2;
2505 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2506
2507 p32 += 0x100 >> 2;
2508 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2509
2510 p32 += 0x100 >> 2;
2511 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2512}
2513
2514static int
2515jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2516{
2517 struct jme_adapter *jme = netdev_priv(netdev);
2518
2519 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2520 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2521
2522 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2523 ecmd->use_adaptive_rx_coalesce = false;
2524 ecmd->rx_coalesce_usecs = 0;
2525 ecmd->rx_max_coalesced_frames = 0;
2526 return 0;
2527 }
2528
2529 ecmd->use_adaptive_rx_coalesce = true;
2530
2531 switch (jme->dpi.cur) {
2532 case PCC_P1:
2533 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2534 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2535 break;
2536 case PCC_P2:
2537 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2538 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2539 break;
2540 case PCC_P3:
2541 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2542 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2543 break;
2544 default:
2545 break;
2546 }
2547
2548 return 0;
2549}
2550
2551static int
2552jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2553{
2554 struct jme_adapter *jme = netdev_priv(netdev);
2555 struct dynpcc_info *dpi = &(jme->dpi);
2556
2557 if (netif_running(netdev))
2558 return -EBUSY;
2559
2560 if (ecmd->use_adaptive_rx_coalesce &&
2561 test_bit(JME_FLAG_POLL, &jme->flags)) {
2562 clear_bit(JME_FLAG_POLL, &jme->flags);
2563 jme->jme_rx = netif_rx;
2564#ifndef __UNIFY_VLAN_RX_PATH__
2565 jme->jme_vlan_rx = vlan_hwaccel_rx;
2566#endif
2567 dpi->cur = PCC_P1;
2568 dpi->attempt = PCC_P1;
2569 dpi->cnt = 0;
2570 jme_set_rx_pcc(jme, PCC_P1);
2571 jme_interrupt_mode(jme);
2572 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2573 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2574 set_bit(JME_FLAG_POLL, &jme->flags);
2575 jme->jme_rx = netif_receive_skb;
2576#ifndef __UNIFY_VLAN_RX_PATH__
2577 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2578#endif
2579 jme_interrupt_mode(jme);
2580 }
2581
2582 return 0;
2583}
2584
2585static void
2586jme_get_pauseparam(struct net_device *netdev,
2587 struct ethtool_pauseparam *ecmd)
2588{
2589 struct jme_adapter *jme = netdev_priv(netdev);
2590 u32 val;
2591
2592 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2593 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2594
2595 spin_lock_bh(&jme->phy_lock);
2596 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2597 spin_unlock_bh(&jme->phy_lock);
2598
2599 ecmd->autoneg =
2600 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2601}
2602
2603static int
2604jme_set_pauseparam(struct net_device *netdev,
2605 struct ethtool_pauseparam *ecmd)
2606{
2607 struct jme_adapter *jme = netdev_priv(netdev);
2608 u32 val;
2609
2610 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2611 (ecmd->tx_pause != 0)) {
2612
2613 if (ecmd->tx_pause)
2614 jme->reg_txpfc |= TXPFC_PF_EN;
2615 else
2616 jme->reg_txpfc &= ~TXPFC_PF_EN;
2617
2618 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2619 }
2620
2621 spin_lock_bh(&jme->rxmcs_lock);
2622 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2623 (ecmd->rx_pause != 0)) {
2624
2625 if (ecmd->rx_pause)
2626 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2627 else
2628 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2629
2630 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2631 }
2632 spin_unlock_bh(&jme->rxmcs_lock);
2633
2634 spin_lock_bh(&jme->phy_lock);
2635 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2636 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2637 (ecmd->autoneg != 0)) {
2638
2639 if (ecmd->autoneg)
2640 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2641 else
2642 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2643
2644 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2645 MII_ADVERTISE, val);
2646 }
2647 spin_unlock_bh(&jme->phy_lock);
2648
2649 return 0;
2650}
2651
2652static void
2653jme_get_wol(struct net_device *netdev,
2654 struct ethtool_wolinfo *wol)
2655{
2656 struct jme_adapter *jme = netdev_priv(netdev);
2657
2658 wol->supported = WAKE_MAGIC | WAKE_PHY;
2659
2660 wol->wolopts = 0;
2661
2662 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2663 wol->wolopts |= WAKE_PHY;
2664
2665 if (jme->reg_pmcs & PMCS_MFEN)
2666 wol->wolopts |= WAKE_MAGIC;
2667
2668}
2669
2670static int
2671jme_set_wol(struct net_device *netdev,
2672 struct ethtool_wolinfo *wol)
2673{
2674 struct jme_adapter *jme = netdev_priv(netdev);
2675
2676 if (wol->wolopts & (WAKE_MAGICSECURE |
2677 WAKE_UCAST |
2678 WAKE_MCAST |
2679 WAKE_BCAST |
2680 WAKE_ARP))
2681 return -EOPNOTSUPP;
2682
2683 jme->reg_pmcs = 0;
2684
2685 if (wol->wolopts & WAKE_PHY)
2686 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2687
2688 if (wol->wolopts & WAKE_MAGIC)
2689 jme->reg_pmcs |= PMCS_MFEN;
2690
2691 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2692#ifndef JME_NEW_PM_API
2693 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2694#endif
2695#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
2696 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2697#endif
2698
2699 return 0;
2700}
2701
2702static int
2703jme_get_settings(struct net_device *netdev,
2704 struct ethtool_cmd *ecmd)
2705{
2706 struct jme_adapter *jme = netdev_priv(netdev);
2707 int rc;
2708
2709 spin_lock_bh(&jme->phy_lock);
2710 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2711 spin_unlock_bh(&jme->phy_lock);
2712 return rc;
2713}
2714
2715static int
2716jme_set_settings(struct net_device *netdev,
2717 struct ethtool_cmd *ecmd)
2718{
2719 struct jme_adapter *jme = netdev_priv(netdev);
2720 int rc, fdc = 0;
2721
2722 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2723 && ecmd->autoneg != AUTONEG_ENABLE)
2724 return -EINVAL;
2725
2726 /*
2727 * Check If user changed duplex only while force_media.
2728 * Hardware would not generate link change interrupt.
2729 */
2730 if (jme->mii_if.force_media &&
2731 ecmd->autoneg != AUTONEG_ENABLE &&
2732 (jme->mii_if.full_duplex != ecmd->duplex))
2733 fdc = 1;
2734
2735 spin_lock_bh(&jme->phy_lock);
2736 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2737 spin_unlock_bh(&jme->phy_lock);
2738
2739 if (!rc) {
2740 if (fdc)
2741 jme_reset_link(jme);
2742 jme->old_ecmd = *ecmd;
2743 set_bit(JME_FLAG_SSET, &jme->flags);
2744 }
2745
2746 return rc;
2747}
2748
2749static int
2750jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2751{
2752 int rc;
2753 struct jme_adapter *jme = netdev_priv(netdev);
2754 struct mii_ioctl_data *mii_data = if_mii(rq);
2755 unsigned int duplex_chg;
2756
2757 if (cmd == SIOCSMIIREG) {
2758 u16 val = mii_data->val_in;
2759 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2760 (val & BMCR_SPEED1000))
2761 return -EINVAL;
2762 }
2763
2764 spin_lock_bh(&jme->phy_lock);
2765 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2766 spin_unlock_bh(&jme->phy_lock);
2767
2768 if (!rc && (cmd == SIOCSMIIREG)) {
2769 if (duplex_chg)
2770 jme_reset_link(jme);
2771 jme_get_settings(netdev, &jme->old_ecmd);
2772 set_bit(JME_FLAG_SSET, &jme->flags);
2773 }
2774
2775 return rc;
2776}
2777
2778static u32
2779jme_get_link(struct net_device *netdev)
2780{
2781 struct jme_adapter *jme = netdev_priv(netdev);
2782 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2783}
2784
2785static u32
2786jme_get_msglevel(struct net_device *netdev)
2787{
2788 struct jme_adapter *jme = netdev_priv(netdev);
2789 return jme->msg_enable;
2790}
2791
2792static void
2793jme_set_msglevel(struct net_device *netdev, u32 value)
2794{
2795 struct jme_adapter *jme = netdev_priv(netdev);
2796 jme->msg_enable = value;
2797}
2798
2799#ifndef __USE_NDO_FIX_FEATURES__
2800static u32
2801jme_get_rx_csum(struct net_device *netdev)
2802{
2803 struct jme_adapter *jme = netdev_priv(netdev);
2804 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2805}
2806
2807static int
2808jme_set_rx_csum(struct net_device *netdev, u32 on)
2809{
2810 struct jme_adapter *jme = netdev_priv(netdev);
2811
2812 spin_lock_bh(&jme->rxmcs_lock);
2813 if (on)
2814 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2815 else
2816 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2817 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2818 spin_unlock_bh(&jme->rxmcs_lock);
2819
2820 return 0;
2821}
2822
2823static int
2824jme_set_tx_csum(struct net_device *netdev, u32 on)
2825{
2826 struct jme_adapter *jme = netdev_priv(netdev);
2827
2828 if (on) {
2829 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2830 if (netdev->mtu <= 1900)
2831 netdev->features |=
2832 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2833 } else {
2834 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2835 netdev->features &=
2836 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2837 }
2838
2839 return 0;
2840}
2841
2842static int
2843jme_set_tso(struct net_device *netdev, u32 on)
2844{
2845 struct jme_adapter *jme = netdev_priv(netdev);
2846
2847 if (on) {
2848 set_bit(JME_FLAG_TSO, &jme->flags);
2849 if (netdev->mtu <= 1900)
2850 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2851 } else {
2852 clear_bit(JME_FLAG_TSO, &jme->flags);
2853 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2854 }
2855
2856 return 0;
2857}
2858#else
2859static u32
2860jme_fix_features(struct net_device *netdev, u32 features)
2861{
2862 if (netdev->mtu > 1900)
2863 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2864 return features;
2865}
2866
2867static int
2868jme_set_features(struct net_device *netdev, u32 features)
2869{
2870 struct jme_adapter *jme = netdev_priv(netdev);
2871
2872 spin_lock_bh(&jme->rxmcs_lock);
2873 if (features & NETIF_F_RXCSUM)
2874 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2875 else
2876 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2877 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2878 spin_unlock_bh(&jme->rxmcs_lock);
2879
2880 return 0;
2881}
2882#endif
2883
2884static int
2885jme_nway_reset(struct net_device *netdev)
2886{
2887 struct jme_adapter *jme = netdev_priv(netdev);
2888 jme_restart_an(jme);
2889 return 0;
2890}
2891
2892static u8
2893jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2894{
2895 u32 val;
2896 int to;
2897
2898 val = jread32(jme, JME_SMBCSR);
2899 to = JME_SMB_BUSY_TIMEOUT;
2900 while ((val & SMBCSR_BUSY) && --to) {
2901 msleep(1);
2902 val = jread32(jme, JME_SMBCSR);
2903 }
2904 if (!to) {
2905 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2906 return 0xFF;
2907 }
2908
2909 jwrite32(jme, JME_SMBINTF,
2910 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2911 SMBINTF_HWRWN_READ |
2912 SMBINTF_HWCMD);
2913
2914 val = jread32(jme, JME_SMBINTF);
2915 to = JME_SMB_BUSY_TIMEOUT;
2916 while ((val & SMBINTF_HWCMD) && --to) {
2917 msleep(1);
2918 val = jread32(jme, JME_SMBINTF);
2919 }
2920 if (!to) {
2921 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2922 return 0xFF;
2923 }
2924
2925 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2926}
2927
2928static void
2929jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2930{
2931 u32 val;
2932 int to;
2933
2934 val = jread32(jme, JME_SMBCSR);
2935 to = JME_SMB_BUSY_TIMEOUT;
2936 while ((val & SMBCSR_BUSY) && --to) {
2937 msleep(1);
2938 val = jread32(jme, JME_SMBCSR);
2939 }
2940 if (!to) {
2941 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2942 return;
2943 }
2944
2945 jwrite32(jme, JME_SMBINTF,
2946 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2947 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2948 SMBINTF_HWRWN_WRITE |
2949 SMBINTF_HWCMD);
2950
2951 val = jread32(jme, JME_SMBINTF);
2952 to = JME_SMB_BUSY_TIMEOUT;
2953 while ((val & SMBINTF_HWCMD) && --to) {
2954 msleep(1);
2955 val = jread32(jme, JME_SMBINTF);
2956 }
2957 if (!to) {
2958 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2959 return;
2960 }
2961
2962 mdelay(2);
2963}
2964
2965static int
2966jme_get_eeprom_len(struct net_device *netdev)
2967{
2968 struct jme_adapter *jme = netdev_priv(netdev);
2969 u32 val;
2970 val = jread32(jme, JME_SMBCSR);
2971 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2972}
2973
2974static int
2975jme_get_eeprom(struct net_device *netdev,
2976 struct ethtool_eeprom *eeprom, u8 *data)
2977{
2978 struct jme_adapter *jme = netdev_priv(netdev);
2979 int i, offset = eeprom->offset, len = eeprom->len;
2980
2981 /*
2982 * ethtool will check the boundary for us
2983 */
2984 eeprom->magic = JME_EEPROM_MAGIC;
2985 for (i = 0 ; i < len ; ++i)
2986 data[i] = jme_smb_read(jme, i + offset);
2987
2988 return 0;
2989}
2990
2991static int
2992jme_set_eeprom(struct net_device *netdev,
2993 struct ethtool_eeprom *eeprom, u8 *data)
2994{
2995 struct jme_adapter *jme = netdev_priv(netdev);
2996 int i, offset = eeprom->offset, len = eeprom->len;
2997
2998 if (eeprom->magic != JME_EEPROM_MAGIC)
2999 return -EINVAL;
3000
3001 /*
3002 * ethtool will check the boundary for us
3003 */
3004 for (i = 0 ; i < len ; ++i)
3005 jme_smb_write(jme, i + offset, data[i]);
3006
3007 return 0;
3008}
3009
3010#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
3011static struct ethtool_ops jme_ethtool_ops = {
3012#else
3013static const struct ethtool_ops jme_ethtool_ops = {
3014#endif
3015 .get_drvinfo = jme_get_drvinfo,
3016 .get_regs_len = jme_get_regs_len,
3017 .get_regs = jme_get_regs,
3018 .get_coalesce = jme_get_coalesce,
3019 .set_coalesce = jme_set_coalesce,
3020 .get_pauseparam = jme_get_pauseparam,
3021 .set_pauseparam = jme_set_pauseparam,
3022 .get_wol = jme_get_wol,
3023 .set_wol = jme_set_wol,
3024 .get_settings = jme_get_settings,
3025 .set_settings = jme_set_settings,
3026 .get_link = jme_get_link,
3027 .get_msglevel = jme_get_msglevel,
3028 .set_msglevel = jme_set_msglevel,
3029#ifndef __USE_NDO_FIX_FEATURES__
3030 .get_rx_csum = jme_get_rx_csum,
3031 .set_rx_csum = jme_set_rx_csum,
3032 .set_tx_csum = jme_set_tx_csum,
3033 .set_tso = jme_set_tso,
3034 .set_sg = ethtool_op_set_sg,
3035#endif
3036 .nway_reset = jme_nway_reset,
3037 .get_eeprom_len = jme_get_eeprom_len,
3038 .get_eeprom = jme_get_eeprom,
3039 .set_eeprom = jme_set_eeprom,
3040};
3041
3042static int
3043jme_pci_dma64(struct pci_dev *pdev)
3044{
3045 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3046#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3047 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
3048#else
3049 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
3050#endif
3051 )
3052#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3053 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3054#else
3055 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
3056#endif
3057 return 1;
3058
3059 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3060#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3061 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3062#else
3063 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3064#endif
3065 )
3066#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3067 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3068#else
3069 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
3070#endif
3071 return 1;
3072
3073#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3074 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3075 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3076#else
3077 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3078 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3079#endif
3080 return 0;
3081
3082 return -1;
3083}
3084
3085static inline void
3086jme_phy_init(struct jme_adapter *jme)
3087{
3088 u16 reg26;
3089
3090 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3091 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3092}
3093
3094static inline void
3095jme_check_hw_ver(struct jme_adapter *jme)
3096{
3097 u32 chipmode;
3098
3099 chipmode = jread32(jme, JME_CHIPMODE);
3100
3101 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3102 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3103 jme->chip_main_rev = jme->chiprev & 0xF;
3104 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3105}
3106
3107#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3108static const struct net_device_ops jme_netdev_ops = {
3109 .ndo_open = jme_open,
3110 .ndo_stop = jme_close,
3111 .ndo_validate_addr = eth_validate_addr,
3112 .ndo_do_ioctl = jme_ioctl,
3113 .ndo_start_xmit = jme_start_xmit,
3114 .ndo_set_mac_address = jme_set_macaddr,
3115 .ndo_set_multicast_list = jme_set_multi,
3116 .ndo_change_mtu = jme_change_mtu,
3117 .ndo_tx_timeout = jme_tx_timeout,
3118#ifndef __UNIFY_VLAN_RX_PATH__
3119 .ndo_vlan_rx_register = jme_vlan_rx_register,
3120#endif
3121#ifdef __USE_NDO_FIX_FEATURES__
3122 .ndo_fix_features = jme_fix_features,
3123 .ndo_set_features = jme_set_features,
3124#endif
3125};
3126#endif
3127
3128static int __devinit
3129jme_init_one(struct pci_dev *pdev,
3130 const struct pci_device_id *ent)
3131{
3132 int rc = 0, using_dac, i;
3133 struct net_device *netdev;
3134 struct jme_adapter *jme;
3135 u16 bmcr, bmsr;
3136 u32 apmc;
3137
3138 /*
3139 * set up PCI device basics
3140 */
3141 rc = pci_enable_device(pdev);
3142 if (rc) {
3143 pr_err("Cannot enable PCI device\n");
3144 goto err_out;
3145 }
3146
3147 using_dac = jme_pci_dma64(pdev);
3148 if (using_dac < 0) {
3149 pr_err("Cannot set PCI DMA Mask\n");
3150 rc = -EIO;
3151 goto err_out_disable_pdev;
3152 }
3153
3154 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3155 pr_err("No PCI resource region found\n");
3156 rc = -ENOMEM;
3157 goto err_out_disable_pdev;
3158 }
3159
3160 rc = pci_request_regions(pdev, DRV_NAME);
3161 if (rc) {
3162 pr_err("Cannot obtain PCI resource region\n");
3163 goto err_out_disable_pdev;
3164 }
3165
3166 pci_set_master(pdev);
3167
3168 /*
3169 * alloc and init net device
3170 */
3171 netdev = alloc_etherdev(sizeof(*jme));
3172 if (!netdev) {
3173 pr_err("Cannot allocate netdev structure\n");
3174 rc = -ENOMEM;
3175 goto err_out_release_regions;
3176 }
3177#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3178 netdev->netdev_ops = &jme_netdev_ops;
3179#else
3180 netdev->open = jme_open;
3181 netdev->stop = jme_close;
3182 netdev->do_ioctl = jme_ioctl;
3183 netdev->hard_start_xmit = jme_start_xmit;
3184 netdev->set_mac_address = jme_set_macaddr;
3185 netdev->set_multicast_list = jme_set_multi;
3186 netdev->change_mtu = jme_change_mtu;
3187 netdev->tx_timeout = jme_tx_timeout;
3188 netdev->vlan_rx_register = jme_vlan_rx_register;
3189#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3190 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3191#endif
3192 NETDEV_GET_STATS(netdev, &jme_get_stats);
3193#endif
3194 netdev->ethtool_ops = &jme_ethtool_ops;
3195 netdev->watchdog_timeo = TX_TIMEOUT;
3196#ifdef __USE_NDO_FIX_FEATURES__
3197 netdev->hw_features = NETIF_F_IP_CSUM |
3198 NETIF_F_IPV6_CSUM |
3199 NETIF_F_SG |
3200 NETIF_F_TSO |
3201 NETIF_F_TSO6 |
3202 NETIF_F_RXCSUM;
3203#endif
3204 netdev->features = NETIF_F_IP_CSUM |
3205 NETIF_F_IPV6_CSUM |
3206 NETIF_F_SG |
3207 NETIF_F_TSO |
3208 NETIF_F_TSO6 |
3209 NETIF_F_HW_VLAN_TX |
3210 NETIF_F_HW_VLAN_RX;
3211 if (using_dac)
3212 netdev->features |= NETIF_F_HIGHDMA;
3213
3214 SET_NETDEV_DEV(netdev, &pdev->dev);
3215 pci_set_drvdata(pdev, netdev);
3216
3217 /*
3218 * init adapter info
3219 */
3220 jme = netdev_priv(netdev);
3221 jme->pdev = pdev;
3222 jme->dev = netdev;
3223 jme->jme_rx = netif_rx;
3224#ifndef __UNIFY_VLAN_RX_PATH__
3225 jme->jme_vlan_rx = vlan_hwaccel_rx;
3226#endif
3227 jme->old_mtu = netdev->mtu = 1500;
3228 jme->phylink = 0;
3229 jme->tx_ring_size = 1 << 10;
3230 jme->tx_ring_mask = jme->tx_ring_size - 1;
3231 jme->tx_wake_threshold = 1 << 9;
3232 jme->rx_ring_size = 1 << 9;
3233 jme->rx_ring_mask = jme->rx_ring_size - 1;
3234 jme->msg_enable = JME_DEF_MSG_ENABLE;
3235 jme->regs = ioremap(pci_resource_start(pdev, 0),
3236 pci_resource_len(pdev, 0));
3237 if (!(jme->regs)) {
3238 pr_err("Mapping PCI resource region error\n");
3239 rc = -ENOMEM;
3240 goto err_out_free_netdev;
3241 }
3242
3243 if (no_pseudohp) {
3244 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3245 jwrite32(jme, JME_APMC, apmc);
3246 } else if (force_pseudohp) {
3247 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3248 jwrite32(jme, JME_APMC, apmc);
3249 }
3250
3251 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3252
3253 spin_lock_init(&jme->phy_lock);
3254 spin_lock_init(&jme->macaddr_lock);
3255 spin_lock_init(&jme->rxmcs_lock);
3256
3257 atomic_set(&jme->link_changing, 1);
3258 atomic_set(&jme->rx_cleaning, 1);
3259 atomic_set(&jme->tx_cleaning, 1);
3260 atomic_set(&jme->rx_empty, 1);
3261
3262 tasklet_init(&jme->pcc_task,
3263 jme_pcc_tasklet,
3264 (unsigned long) jme);
3265 tasklet_init(&jme->linkch_task,
3266 jme_link_change_tasklet,
3267 (unsigned long) jme);
3268 tasklet_init(&jme->txclean_task,
3269 jme_tx_clean_tasklet,
3270 (unsigned long) jme);
3271 tasklet_init(&jme->rxclean_task,
3272 jme_rx_clean_tasklet,
3273 (unsigned long) jme);
3274 tasklet_init(&jme->rxempty_task,
3275 jme_rx_empty_tasklet,
3276 (unsigned long) jme);
3277 tasklet_disable_nosync(&jme->linkch_task);
3278 tasklet_disable_nosync(&jme->txclean_task);
3279 tasklet_disable_nosync(&jme->rxclean_task);
3280 tasklet_disable_nosync(&jme->rxempty_task);
3281 jme->dpi.cur = PCC_P1;
3282
3283 jme->reg_ghc = 0;
3284 jme->reg_rxcs = RXCS_DEFAULT;
3285 jme->reg_rxmcs = RXMCS_DEFAULT;
3286 jme->reg_txpfc = 0;
3287 jme->reg_pmcs = PMCS_MFEN;
3288 jme->reg_gpreg1 = GPREG1_DEFAULT;
3289#ifndef __USE_NDO_FIX_FEATURES__
3290 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3291 set_bit(JME_FLAG_TSO, &jme->flags);
3292#else
3293
3294 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3295 netdev->features |= NETIF_F_RXCSUM;
3296#endif
3297
3298 /*
3299 * Get Max Read Req Size from PCI Config Space
3300 */
3301 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3302 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3303 switch (jme->mrrs) {
3304 case MRRS_128B:
3305 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3306 break;
3307 case MRRS_256B:
3308 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3309 break;
3310 default:
3311 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3312 break;
3313 }
3314
3315 /*
3316 * Must check before reset_mac_processor
3317 */
3318 jme_check_hw_ver(jme);
3319 jme->mii_if.dev = netdev;
3320 if (jme->fpgaver) {
3321 jme->mii_if.phy_id = 0;
3322 for (i = 1 ; i < 32 ; ++i) {
3323 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3324 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3325 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3326 jme->mii_if.phy_id = i;
3327 break;
3328 }
3329 }
3330
3331 if (!jme->mii_if.phy_id) {
3332 rc = -EIO;
3333 pr_err("Can not find phy_id\n");
3334 goto err_out_unmap;
3335 }
3336
3337 jme->reg_ghc |= GHC_LINK_POLL;
3338 } else {
3339 jme->mii_if.phy_id = 1;
3340 }
3341 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3342 jme->mii_if.supports_gmii = true;
3343 else
3344 jme->mii_if.supports_gmii = false;
3345 jme->mii_if.phy_id_mask = 0x1F;
3346 jme->mii_if.reg_num_mask = 0x1F;
3347 jme->mii_if.mdio_read = jme_mdio_read;
3348 jme->mii_if.mdio_write = jme_mdio_write;
3349
3350 jme_clear_pm(jme);
3351 pci_set_power_state(jme->pdev, PCI_D0);
3352#ifndef JME_NEW_PM_API
3353 jme_pci_wakeup_enable(jme, true);
3354#endif
3355#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3356 device_set_wakeup_enable(&pdev->dev, true);
3357#endif
3358
3359 jme_set_phyfifo_5level(jme);
3360#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
3361 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3362#else
3363 jme->pcirev = pdev->revision;
3364#endif
3365 if (!jme->fpgaver)
3366 jme_phy_init(jme);
3367 jme_phy_off(jme);
3368
3369 /*
3370 * Reset MAC processor and reload EEPROM for MAC Address
3371 */
3372 jme_reset_mac_processor(jme);
3373 rc = jme_reload_eeprom(jme);
3374 if (rc) {
3375 pr_err("Reload eeprom for reading MAC Address error\n");
3376 goto err_out_unmap;
3377 }
3378 jme_load_macaddr(netdev);
3379
3380 /*
3381 * Tell stack that we are not ready to work until open()
3382 */
3383 netif_carrier_off(netdev);
3384
3385 rc = register_netdev(netdev);
3386 if (rc) {
3387 pr_err("Cannot register net device\n");
3388 goto err_out_unmap;
3389 }
3390
3391 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3392 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3393 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3394 "JMC250 Gigabit Ethernet" :
3395 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3396 "JMC260 Fast Ethernet" : "Unknown",
3397 (jme->fpgaver != 0) ? " (FPGA)" : "",
3398 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3399 jme->pcirev,
3400 netdev->dev_addr[0],
3401 netdev->dev_addr[1],
3402 netdev->dev_addr[2],
3403 netdev->dev_addr[3],
3404 netdev->dev_addr[4],
3405 netdev->dev_addr[5]);
3406
3407 return 0;
3408
3409err_out_unmap:
3410 iounmap(jme->regs);
3411err_out_free_netdev:
3412 pci_set_drvdata(pdev, NULL);
3413 free_netdev(netdev);
3414err_out_release_regions:
3415 pci_release_regions(pdev);
3416err_out_disable_pdev:
3417 pci_disable_device(pdev);
3418err_out:
3419 return rc;
3420}
3421
3422static void __devexit
3423jme_remove_one(struct pci_dev *pdev)
3424{
3425 struct net_device *netdev = pci_get_drvdata(pdev);
3426 struct jme_adapter *jme = netdev_priv(netdev);
3427
3428 unregister_netdev(netdev);
3429 iounmap(jme->regs);
3430 pci_set_drvdata(pdev, NULL);
3431 free_netdev(netdev);
3432 pci_release_regions(pdev);
3433 pci_disable_device(pdev);
3434
3435}
3436
3437static void
3438jme_shutdown(struct pci_dev *pdev)
3439{
3440 struct net_device *netdev = pci_get_drvdata(pdev);
3441 struct jme_adapter *jme = netdev_priv(netdev);
3442
3443 jme_powersave_phy(jme);
3444#ifndef JME_NEW_PM_API
3445 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3446#endif
3447#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3448 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
3449#endif
3450}
3451
3452#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3453 #ifdef CONFIG_PM
3454 #define JME_HAVE_PM
3455 #endif
3456#else
3457 #ifdef CONFIG_PM_SLEEP
3458 #define JME_HAVE_PM
3459 #endif
3460#endif
3461
3462#ifdef JME_HAVE_PM
3463static int
3464#ifdef JME_NEW_PM_API
3465jme_suspend(struct device *dev)
3466#else
3467jme_suspend(struct pci_dev *pdev, pm_message_t state)
3468#endif
3469{
3470#ifdef JME_NEW_PM_API
3471 struct pci_dev *pdev = to_pci_dev(dev);
3472#endif
3473 struct net_device *netdev = pci_get_drvdata(pdev);
3474 struct jme_adapter *jme = netdev_priv(netdev);
3475
3476 atomic_dec(&jme->link_changing);
3477
3478 netif_device_detach(netdev);
3479 netif_stop_queue(netdev);
3480 jme_stop_irq(jme);
3481
3482 tasklet_disable(&jme->txclean_task);
3483 tasklet_disable(&jme->rxclean_task);
3484 tasklet_disable(&jme->rxempty_task);
3485
3486 if (netif_carrier_ok(netdev)) {
3487 if (test_bit(JME_FLAG_POLL, &jme->flags))
3488 jme_polling_mode(jme);
3489
3490 jme_stop_pcc_timer(jme);
3491 jme_disable_rx_engine(jme);
3492 jme_disable_tx_engine(jme);
3493 jme_reset_mac_processor(jme);
3494 jme_free_rx_resources(jme);
3495 jme_free_tx_resources(jme);
3496 netif_carrier_off(netdev);
3497 jme->phylink = 0;
3498 }
3499
3500 tasklet_enable(&jme->txclean_task);
3501 tasklet_hi_enable(&jme->rxclean_task);
3502 tasklet_hi_enable(&jme->rxempty_task);
3503
3504 jme_powersave_phy(jme);
3505#ifndef JME_NEW_PM_API
3506 pci_save_state(pdev);
3507 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3508 pci_set_power_state(pdev, PCI_D3hot);
3509#endif
3510
3511 return 0;
3512}
3513
3514static int
3515#ifdef JME_NEW_PM_API
3516jme_resume(struct device *dev)
3517#else
3518jme_resume(struct pci_dev *pdev)
3519#endif
3520{
3521#ifdef JME_NEW_PM_API
3522 struct pci_dev *pdev = to_pci_dev(dev);
3523#endif
3524 struct net_device *netdev = pci_get_drvdata(pdev);
3525 struct jme_adapter *jme = netdev_priv(netdev);
3526
3527 jme_clear_pm(jme);
3528#ifndef JME_NEW_PM_API
3529 pci_set_power_state(pdev, PCI_D0);
3530 pci_restore_state(pdev);
3531#endif
3532
3533 jme_phy_on(jme);
3534 if (test_bit(JME_FLAG_SSET, &jme->flags))
3535 jme_set_settings(netdev, &jme->old_ecmd);
3536 else
3537 jme_reset_phy_processor(jme);
3538
3539 jme_start_irq(jme);
3540 netif_device_attach(netdev);
3541
3542 atomic_inc(&jme->link_changing);
3543
3544 jme_reset_link(jme);
3545
3546 return 0;
3547}
3548
3549#ifdef JME_NEW_PM_API
3550static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3551#define JME_PM_OPS (&jme_pm_ops)
3552#endif
3553
3554#else
3555
3556#ifdef JME_NEW_PM_API
3557#define JME_PM_OPS NULL
3558#endif
3559#endif
3560
3561#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3562static struct pci_device_id jme_pci_tbl[] = {
3563#else
3564static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3565#endif
3566 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3567 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3568 { }
3569};
3570
3571static struct pci_driver jme_driver = {
3572 .name = DRV_NAME,
3573 .id_table = jme_pci_tbl,
3574 .probe = jme_init_one,
3575 .remove = __devexit_p(jme_remove_one),
3576 .shutdown = jme_shutdown,
3577#ifndef JME_NEW_PM_API
3578 .suspend = jme_suspend,
3579 .resume = jme_resume
3580#else
3581 .driver.pm = JME_PM_OPS,
3582#endif
3583};
3584
3585static int __init
3586jme_init_module(void)
3587{
3588 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3589 return pci_register_driver(&jme_driver);
3590}
3591
3592static void __exit
3593jme_cleanup_module(void)
3594{
3595 pci_unregister_driver(&jme_driver);
3596}
3597
3598module_init(jme_init_module);
3599module_exit(jme_cleanup_module);
3600
3601MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3602MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3603MODULE_LICENSE("GPL");
3604MODULE_VERSION(DRV_VERSION);
3605MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3606
JMicron Ethernet Linux driver