]> bbs.cooldavid.org Git - jme.git/blame_incremental - jme.c
git://bbs.cooldavid.org / jme.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
jme: Rename phyfifo function for easier understand
[jme.git] / jme.c
... / ...
CommitLineData
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/crc32.h>
35#include <linux/delay.h>
36#include <linux/spinlock.h>
37#include <linux/in.h>
38#include <linux/ip.h>
39#include <linux/ipv6.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/if_vlan.h>
43#include <linux/slab.h>
44#include <net/ip6_checksum.h>
45#include "jme.h"
46
47static int force_pseudohp = -1;
48static int no_pseudohp = -1;
49static int no_extplug = -1;
50module_param(force_pseudohp, int, 0);
51MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53module_param(no_pseudohp, int, 0);
54MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55module_param(no_extplug, int, 0);
56MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
58
59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
61{
62 struct jme_adapter *jme = netdev_priv(netdev);
63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
64
65read_again:
66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
69
70 wmb();
71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72 udelay(20);
73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
75 break;
76 }
77
78 if (i == 0) {
79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
80 return 0;
81 }
82
83 if (again--)
84 goto read_again;
85
86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
87}
88
89static void
90jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
92{
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
99
100 wmb();
101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 break;
105 }
106
107 if (i == 0)
108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
109}
110
111static inline void
112jme_reset_phy_processor(struct jme_adapter *jme)
113{
114 u32 val;
115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120
121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126
127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
134}
135
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
138 const u32 *mask, u32 crc, int fnr)
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
162
163static inline void
164jme_reset_mac_processor(struct jme_adapter *jme)
165{
166 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194}
195
196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
204jme_clear_pm(struct jme_adapter *jme)
205{
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209}
210
211static int
212jme_reload_eeprom(struct jme_adapter *jme)
213{
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 pr_err("eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239}
240
241static void
242jme_load_macaddr(struct net_device *netdev)
243{
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259}
260
261static inline void
262jme_set_rx_pcc(struct jme_adapter *jme, int p)
263{
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
292}
293
294static void
295jme_start_irq(struct jme_adapter *jme)
296{
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314}
315
316static inline void
317jme_stop_irq(struct jme_adapter *jme)
318{
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323}
324
325static u32
326jme_linkstat_from_phy(struct jme_adapter *jme)
327{
328 u32 phylink, bmsr;
329
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if (bmsr & BMSR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335 return phylink;
336}
337
338static inline void
339jme_set_phyfifo_5level(struct jme_adapter *jme)
340{
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342}
343
344static inline void
345jme_set_phyfifo_8level(struct jme_adapter *jme)
346{
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348}
349
350static int
351jme_check_link(struct net_device *netdev, int testonly)
352{
353 struct jme_adapter *jme = netdev_priv(netdev);
354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
355 char linkmsg[64];
356 int rc = 0;
357
358 linkmsg[0] = '\0';
359
360 if (jme->fpgaver)
361 phylink = jme_linkstat_from_phy(jme);
362 else
363 phylink = jread32(jme, JME_PHY_LINK);
364
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
367 /*
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
370 */
371 phylink = PHY_LINK_UP;
372
373 bmcr = jme_mdio_read(jme->dev,
374 jme->mii_if.phy_id,
375 MII_BMCR);
376
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
382 PHY_LINK_SPEED_10M;
383
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
385 PHY_LINK_DUPLEX : 0;
386
387 strcat(linkmsg, "Forced: ");
388 } else {
389 /*
390 * Keep polling for speed/duplex resolve complete
391 */
392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
393 --cnt) {
394
395 udelay(1);
396
397 if (jme->fpgaver)
398 phylink = jme_linkstat_from_phy(jme);
399 else
400 phylink = jread32(jme, JME_PHY_LINK);
401 }
402 if (!cnt)
403 pr_err("Waiting speed resolve timeout\n");
404
405 strcat(linkmsg, "ANed: ");
406 }
407
408 if (jme->phylink == phylink) {
409 rc = 1;
410 goto out;
411 }
412 if (testonly)
413 goto out;
414
415 jme->phylink = phylink;
416
417 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
418 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
419 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
420 switch (phylink & PHY_LINK_SPEED_MASK) {
421 case PHY_LINK_SPEED_10M:
422 ghc |= GHC_SPEED_10M |
423 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
424 strcat(linkmsg, "10 Mbps, ");
425 break;
426 case PHY_LINK_SPEED_100M:
427 ghc |= GHC_SPEED_100M |
428 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
429 strcat(linkmsg, "100 Mbps, ");
430 break;
431 case PHY_LINK_SPEED_1000M:
432 ghc |= GHC_SPEED_1000M |
433 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
434 strcat(linkmsg, "1000 Mbps, ");
435 break;
436 default:
437 break;
438 }
439
440 if (phylink & PHY_LINK_DUPLEX) {
441 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
442 ghc |= GHC_DPX;
443 } else {
444 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
445 TXMCS_BACKOFF |
446 TXMCS_CARRIERSENSE |
447 TXMCS_COLLISION);
448 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
449 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
450 TXTRHD_TXREN |
451 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
452 }
453
454 gpreg1 = GPREG1_DEFAULT;
455 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
456 if (!(phylink & PHY_LINK_DUPLEX))
457 gpreg1 |= GPREG1_HALFMODEPATCH;
458 switch (phylink & PHY_LINK_SPEED_MASK) {
459 case PHY_LINK_SPEED_10M:
460 jme_set_phyfifo_8level(jme);
461 gpreg1 |= GPREG1_RSSPATCH;
462 break;
463 case PHY_LINK_SPEED_100M:
464 jme_set_phyfifo_5level(jme);
465 gpreg1 |= GPREG1_RSSPATCH;
466 break;
467 case PHY_LINK_SPEED_1000M:
468 jme_set_phyfifo_8level(jme);
469 break;
470 default:
471 break;
472 }
473 }
474
475 jwrite32(jme, JME_GPREG1, gpreg1);
476 jwrite32(jme, JME_GHC, ghc);
477 jme->reg_ghc = ghc;
478
479 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
480 "Full-Duplex, " :
481 "Half-Duplex, ");
482 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
483 "MDI-X" :
484 "MDI");
485 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
486 netif_carrier_on(netdev);
487 } else {
488 if (testonly)
489 goto out;
490
491 netif_info(jme, link, jme->dev, "Link is down\n");
492 jme->phylink = 0;
493 netif_carrier_off(netdev);
494 }
495
496out:
497 return rc;
498}
499
500static int
501jme_setup_tx_resources(struct jme_adapter *jme)
502{
503 struct jme_ring *txring = &(jme->txring[0]);
504
505 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
506 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
507 &(txring->dmaalloc),
508 GFP_ATOMIC);
509
510 if (!txring->alloc)
511 goto err_set_null;
512
513 /*
514 * 16 Bytes align
515 */
516 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
517 RING_DESC_ALIGN);
518 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
519 txring->next_to_use = 0;
520 atomic_set(&txring->next_to_clean, 0);
521 atomic_set(&txring->nr_free, jme->tx_ring_size);
522
523 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
524 jme->tx_ring_size, GFP_ATOMIC);
525 if (unlikely(!(txring->bufinf)))
526 goto err_free_txring;
527
528 /*
529 * Initialize Transmit Descriptors
530 */
531 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
532 memset(txring->bufinf, 0,
533 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
534
535 return 0;
536
537err_free_txring:
538 dma_free_coherent(&(jme->pdev->dev),
539 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
540 txring->alloc,
541 txring->dmaalloc);
542
543err_set_null:
544 txring->desc = NULL;
545 txring->dmaalloc = 0;
546 txring->dma = 0;
547 txring->bufinf = NULL;
548
549 return -ENOMEM;
550}
551
552static void
553jme_free_tx_resources(struct jme_adapter *jme)
554{
555 int i;
556 struct jme_ring *txring = &(jme->txring[0]);
557 struct jme_buffer_info *txbi;
558
559 if (txring->alloc) {
560 if (txring->bufinf) {
561 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
562 txbi = txring->bufinf + i;
563 if (txbi->skb) {
564 dev_kfree_skb(txbi->skb);
565 txbi->skb = NULL;
566 }
567 txbi->mapping = 0;
568 txbi->len = 0;
569 txbi->nr_desc = 0;
570 txbi->start_xmit = 0;
571 }
572 kfree(txring->bufinf);
573 }
574
575 dma_free_coherent(&(jme->pdev->dev),
576 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
577 txring->alloc,
578 txring->dmaalloc);
579
580 txring->alloc = NULL;
581 txring->desc = NULL;
582 txring->dmaalloc = 0;
583 txring->dma = 0;
584 txring->bufinf = NULL;
585 }
586 txring->next_to_use = 0;
587 atomic_set(&txring->next_to_clean, 0);
588 atomic_set(&txring->nr_free, 0);
589}
590
591static inline void
592jme_enable_tx_engine(struct jme_adapter *jme)
593{
594 /*
595 * Select Queue 0
596 */
597 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
598 wmb();
599
600 /*
601 * Setup TX Queue 0 DMA Bass Address
602 */
603 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
604 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
605 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
606
607 /*
608 * Setup TX Descptor Count
609 */
610 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
611
612 /*
613 * Enable TX Engine
614 */
615 wmb();
616 jwrite32(jme, JME_TXCS, jme->reg_txcs |
617 TXCS_SELECT_QUEUE0 |
618 TXCS_ENABLE);
619
620}
621
622static inline void
623jme_restart_tx_engine(struct jme_adapter *jme)
624{
625 /*
626 * Restart TX Engine
627 */
628 jwrite32(jme, JME_TXCS, jme->reg_txcs |
629 TXCS_SELECT_QUEUE0 |
630 TXCS_ENABLE);
631}
632
633static inline void
634jme_disable_tx_engine(struct jme_adapter *jme)
635{
636 int i;
637 u32 val;
638
639 /*
640 * Disable TX Engine
641 */
642 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
643 wmb();
644
645 val = jread32(jme, JME_TXCS);
646 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
647 mdelay(1);
648 val = jread32(jme, JME_TXCS);
649 rmb();
650 }
651
652 if (!i)
653 pr_err("Disable TX engine timeout\n");
654}
655
656static void
657jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
658{
659 struct jme_ring *rxring = &(jme->rxring[0]);
660 register struct rxdesc *rxdesc = rxring->desc;
661 struct jme_buffer_info *rxbi = rxring->bufinf;
662 rxdesc += i;
663 rxbi += i;
664
665 rxdesc->dw[0] = 0;
666 rxdesc->dw[1] = 0;
667 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
668 rxdesc->desc1.bufaddrl = cpu_to_le32(
669 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
670 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
671 if (jme->dev->features & NETIF_F_HIGHDMA)
672 rxdesc->desc1.flags = RXFLAG_64BIT;
673 wmb();
674 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
675}
676
677static int
678jme_make_new_rx_buf(struct jme_adapter *jme, int i)
679{
680 struct jme_ring *rxring = &(jme->rxring[0]);
681 struct jme_buffer_info *rxbi = rxring->bufinf + i;
682 struct sk_buff *skb;
683
684 skb = netdev_alloc_skb(jme->dev,
685 jme->dev->mtu + RX_EXTRA_LEN);
686 if (unlikely(!skb))
687 return -ENOMEM;
688
689 rxbi->skb = skb;
690 rxbi->len = skb_tailroom(skb);
691 rxbi->mapping = pci_map_page(jme->pdev,
692 virt_to_page(skb->data),
693 offset_in_page(skb->data),
694 rxbi->len,
695 PCI_DMA_FROMDEVICE);
696
697 return 0;
698}
699
700static void
701jme_free_rx_buf(struct jme_adapter *jme, int i)
702{
703 struct jme_ring *rxring = &(jme->rxring[0]);
704 struct jme_buffer_info *rxbi = rxring->bufinf;
705 rxbi += i;
706
707 if (rxbi->skb) {
708 pci_unmap_page(jme->pdev,
709 rxbi->mapping,
710 rxbi->len,
711 PCI_DMA_FROMDEVICE);
712 dev_kfree_skb(rxbi->skb);
713 rxbi->skb = NULL;
714 rxbi->mapping = 0;
715 rxbi->len = 0;
716 }
717}
718
719static void
720jme_free_rx_resources(struct jme_adapter *jme)
721{
722 int i;
723 struct jme_ring *rxring = &(jme->rxring[0]);
724
725 if (rxring->alloc) {
726 if (rxring->bufinf) {
727 for (i = 0 ; i < jme->rx_ring_size ; ++i)
728 jme_free_rx_buf(jme, i);
729 kfree(rxring->bufinf);
730 }
731
732 dma_free_coherent(&(jme->pdev->dev),
733 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
734 rxring->alloc,
735 rxring->dmaalloc);
736 rxring->alloc = NULL;
737 rxring->desc = NULL;
738 rxring->dmaalloc = 0;
739 rxring->dma = 0;
740 rxring->bufinf = NULL;
741 }
742 rxring->next_to_use = 0;
743 atomic_set(&rxring->next_to_clean, 0);
744}
745
746static int
747jme_setup_rx_resources(struct jme_adapter *jme)
748{
749 int i;
750 struct jme_ring *rxring = &(jme->rxring[0]);
751
752 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
753 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
754 &(rxring->dmaalloc),
755 GFP_ATOMIC);
756 if (!rxring->alloc)
757 goto err_set_null;
758
759 /*
760 * 16 Bytes align
761 */
762 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
763 RING_DESC_ALIGN);
764 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
765 rxring->next_to_use = 0;
766 atomic_set(&rxring->next_to_clean, 0);
767
768 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
769 jme->rx_ring_size, GFP_ATOMIC);
770 if (unlikely(!(rxring->bufinf)))
771 goto err_free_rxring;
772
773 /*
774 * Initiallize Receive Descriptors
775 */
776 memset(rxring->bufinf, 0,
777 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
778 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
779 if (unlikely(jme_make_new_rx_buf(jme, i))) {
780 jme_free_rx_resources(jme);
781 return -ENOMEM;
782 }
783
784 jme_set_clean_rxdesc(jme, i);
785 }
786
787 return 0;
788
789err_free_rxring:
790 dma_free_coherent(&(jme->pdev->dev),
791 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
792 rxring->alloc,
793 rxring->dmaalloc);
794err_set_null:
795 rxring->desc = NULL;
796 rxring->dmaalloc = 0;
797 rxring->dma = 0;
798 rxring->bufinf = NULL;
799
800 return -ENOMEM;
801}
802
803static inline void
804jme_enable_rx_engine(struct jme_adapter *jme)
805{
806 /*
807 * Select Queue 0
808 */
809 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
810 RXCS_QUEUESEL_Q0);
811 wmb();
812
813 /*
814 * Setup RX DMA Bass Address
815 */
816 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
817 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
818 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
819
820 /*
821 * Setup RX Descriptor Count
822 */
823 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
824
825 /*
826 * Setup Unicast Filter
827 */
828 jme_set_multi(jme->dev);
829
830 /*
831 * Enable RX Engine
832 */
833 wmb();
834 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
835 RXCS_QUEUESEL_Q0 |
836 RXCS_ENABLE |
837 RXCS_QST);
838}
839
840static inline void
841jme_restart_rx_engine(struct jme_adapter *jme)
842{
843 /*
844 * Start RX Engine
845 */
846 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
847 RXCS_QUEUESEL_Q0 |
848 RXCS_ENABLE |
849 RXCS_QST);
850}
851
852static inline void
853jme_disable_rx_engine(struct jme_adapter *jme)
854{
855 int i;
856 u32 val;
857
858 /*
859 * Disable RX Engine
860 */
861 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
862 wmb();
863
864 val = jread32(jme, JME_RXCS);
865 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
866 mdelay(1);
867 val = jread32(jme, JME_RXCS);
868 rmb();
869 }
870
871 if (!i)
872 pr_err("Disable RX engine timeout\n");
873
874}
875
876static int
877jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
878{
879 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
880 return false;
881
882 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
883 == RXWBFLAG_TCPON)) {
884 if (flags & RXWBFLAG_IPV4)
885 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
886 return false;
887 }
888
889 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
890 == RXWBFLAG_UDPON)) {
891 if (flags & RXWBFLAG_IPV4)
892 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
893 return false;
894 }
895
896 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
897 == RXWBFLAG_IPV4)) {
898 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
899 return false;
900 }
901
902 return true;
903}
904
905static void
906jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
907{
908 struct jme_ring *rxring = &(jme->rxring[0]);
909 struct rxdesc *rxdesc = rxring->desc;
910 struct jme_buffer_info *rxbi = rxring->bufinf;
911 struct sk_buff *skb;
912 int framesize;
913
914 rxdesc += idx;
915 rxbi += idx;
916
917 skb = rxbi->skb;
918 pci_dma_sync_single_for_cpu(jme->pdev,
919 rxbi->mapping,
920 rxbi->len,
921 PCI_DMA_FROMDEVICE);
922
923 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
924 pci_dma_sync_single_for_device(jme->pdev,
925 rxbi->mapping,
926 rxbi->len,
927 PCI_DMA_FROMDEVICE);
928
929 ++(NET_STAT(jme).rx_dropped);
930 } else {
931 framesize = le16_to_cpu(rxdesc->descwb.framesize)
932 - RX_PREPAD_SIZE;
933
934 skb_reserve(skb, RX_PREPAD_SIZE);
935 skb_put(skb, framesize);
936 skb->protocol = eth_type_trans(skb, jme->dev);
937
938 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
939 skb->ip_summed = CHECKSUM_UNNECESSARY;
940 else
941 skb_checksum_none_assert(skb);
942
943 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
944 if (jme->vlgrp) {
945 jme->jme_vlan_rx(skb, jme->vlgrp,
946 le16_to_cpu(rxdesc->descwb.vlan));
947 NET_STAT(jme).rx_bytes += 4;
948 } else {
949 dev_kfree_skb(skb);
950 }
951 } else {
952 jme->jme_rx(skb);
953 }
954
955 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
956 cpu_to_le16(RXWBFLAG_DEST_MUL))
957 ++(NET_STAT(jme).multicast);
958
959 NET_STAT(jme).rx_bytes += framesize;
960 ++(NET_STAT(jme).rx_packets);
961 }
962
963 jme_set_clean_rxdesc(jme, idx);
964
965}
966
967static int
968jme_process_receive(struct jme_adapter *jme, int limit)
969{
970 struct jme_ring *rxring = &(jme->rxring[0]);
971 struct rxdesc *rxdesc = rxring->desc;
972 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
973
974 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
975 goto out_inc;
976
977 if (unlikely(atomic_read(&jme->link_changing) != 1))
978 goto out_inc;
979
980 if (unlikely(!netif_carrier_ok(jme->dev)))
981 goto out_inc;
982
983 i = atomic_read(&rxring->next_to_clean);
984 while (limit > 0) {
985 rxdesc = rxring->desc;
986 rxdesc += i;
987
988 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
989 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
990 goto out;
991 --limit;
992
993 rmb();
994 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
995
996 if (unlikely(desccnt > 1 ||
997 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
998
999 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1000 ++(NET_STAT(jme).rx_crc_errors);
1001 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1002 ++(NET_STAT(jme).rx_fifo_errors);
1003 else
1004 ++(NET_STAT(jme).rx_errors);
1005
1006 if (desccnt > 1)
1007 limit -= desccnt - 1;
1008
1009 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1010 jme_set_clean_rxdesc(jme, j);
1011 j = (j + 1) & (mask);
1012 }
1013
1014 } else {
1015 jme_alloc_and_feed_skb(jme, i);
1016 }
1017
1018 i = (i + desccnt) & (mask);
1019 }
1020
1021out:
1022 atomic_set(&rxring->next_to_clean, i);
1023
1024out_inc:
1025 atomic_inc(&jme->rx_cleaning);
1026
1027 return limit > 0 ? limit : 0;
1028
1029}
1030
1031static void
1032jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1033{
1034 if (likely(atmp == dpi->cur)) {
1035 dpi->cnt = 0;
1036 return;
1037 }
1038
1039 if (dpi->attempt == atmp) {
1040 ++(dpi->cnt);
1041 } else {
1042 dpi->attempt = atmp;
1043 dpi->cnt = 0;
1044 }
1045
1046}
1047
1048static void
1049jme_dynamic_pcc(struct jme_adapter *jme)
1050{
1051 register struct dynpcc_info *dpi = &(jme->dpi);
1052
1053 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1054 jme_attempt_pcc(dpi, PCC_P3);
1055 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1056 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1057 jme_attempt_pcc(dpi, PCC_P2);
1058 else
1059 jme_attempt_pcc(dpi, PCC_P1);
1060
1061 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1062 if (dpi->attempt < dpi->cur)
1063 tasklet_schedule(&jme->rxclean_task);
1064 jme_set_rx_pcc(jme, dpi->attempt);
1065 dpi->cur = dpi->attempt;
1066 dpi->cnt = 0;
1067 }
1068}
1069
1070static void
1071jme_start_pcc_timer(struct jme_adapter *jme)
1072{
1073 struct dynpcc_info *dpi = &(jme->dpi);
1074 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1075 dpi->last_pkts = NET_STAT(jme).rx_packets;
1076 dpi->intr_cnt = 0;
1077 jwrite32(jme, JME_TMCSR,
1078 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1079}
1080
1081static inline void
1082jme_stop_pcc_timer(struct jme_adapter *jme)
1083{
1084 jwrite32(jme, JME_TMCSR, 0);
1085}
1086
1087static void
1088jme_shutdown_nic(struct jme_adapter *jme)
1089{
1090 u32 phylink;
1091
1092 phylink = jme_linkstat_from_phy(jme);
1093
1094 if (!(phylink & PHY_LINK_UP)) {
1095 /*
1096 * Disable all interrupt before issue timer
1097 */
1098 jme_stop_irq(jme);
1099 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1100 }
1101}
1102
1103static void
1104jme_pcc_tasklet(unsigned long arg)
1105{
1106 struct jme_adapter *jme = (struct jme_adapter *)arg;
1107 struct net_device *netdev = jme->dev;
1108
1109 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1110 jme_shutdown_nic(jme);
1111 return;
1112 }
1113
1114 if (unlikely(!netif_carrier_ok(netdev) ||
1115 (atomic_read(&jme->link_changing) != 1)
1116 )) {
1117 jme_stop_pcc_timer(jme);
1118 return;
1119 }
1120
1121 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1122 jme_dynamic_pcc(jme);
1123
1124 jme_start_pcc_timer(jme);
1125}
1126
1127static inline void
1128jme_polling_mode(struct jme_adapter *jme)
1129{
1130 jme_set_rx_pcc(jme, PCC_OFF);
1131}
1132
1133static inline void
1134jme_interrupt_mode(struct jme_adapter *jme)
1135{
1136 jme_set_rx_pcc(jme, PCC_P1);
1137}
1138
1139static inline int
1140jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1141{
1142 u32 apmc;
1143 apmc = jread32(jme, JME_APMC);
1144 return apmc & JME_APMC_PSEUDO_HP_EN;
1145}
1146
1147static void
1148jme_start_shutdown_timer(struct jme_adapter *jme)
1149{
1150 u32 apmc;
1151
1152 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1153 apmc &= ~JME_APMC_EPIEN_CTRL;
1154 if (!no_extplug) {
1155 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1156 wmb();
1157 }
1158 jwrite32f(jme, JME_APMC, apmc);
1159
1160 jwrite32f(jme, JME_TIMER2, 0);
1161 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1162 jwrite32(jme, JME_TMCSR,
1163 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1164}
1165
1166static void
1167jme_stop_shutdown_timer(struct jme_adapter *jme)
1168{
1169 u32 apmc;
1170
1171 jwrite32f(jme, JME_TMCSR, 0);
1172 jwrite32f(jme, JME_TIMER2, 0);
1173 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1174
1175 apmc = jread32(jme, JME_APMC);
1176 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1177 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1178 wmb();
1179 jwrite32f(jme, JME_APMC, apmc);
1180}
1181
1182static void
1183jme_link_change_tasklet(unsigned long arg)
1184{
1185 struct jme_adapter *jme = (struct jme_adapter *)arg;
1186 struct net_device *netdev = jme->dev;
1187 int rc;
1188
1189 while (!atomic_dec_and_test(&jme->link_changing)) {
1190 atomic_inc(&jme->link_changing);
1191 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1192 while (atomic_read(&jme->link_changing) != 1)
1193 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1194 }
1195
1196 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1197 goto out;
1198
1199 jme->old_mtu = netdev->mtu;
1200 netif_stop_queue(netdev);
1201 if (jme_pseudo_hotplug_enabled(jme))
1202 jme_stop_shutdown_timer(jme);
1203
1204 jme_stop_pcc_timer(jme);
1205 tasklet_disable(&jme->txclean_task);
1206 tasklet_disable(&jme->rxclean_task);
1207 tasklet_disable(&jme->rxempty_task);
1208
1209 if (netif_carrier_ok(netdev)) {
1210 jme_reset_ghc_speed(jme);
1211 jme_disable_rx_engine(jme);
1212 jme_disable_tx_engine(jme);
1213 jme_reset_mac_processor(jme);
1214 jme_free_rx_resources(jme);
1215 jme_free_tx_resources(jme);
1216
1217 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218 jme_polling_mode(jme);
1219
1220 netif_carrier_off(netdev);
1221 }
1222
1223 jme_check_link(netdev, 0);
1224 if (netif_carrier_ok(netdev)) {
1225 rc = jme_setup_rx_resources(jme);
1226 if (rc) {
1227 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1228 goto out_enable_tasklet;
1229 }
1230
1231 rc = jme_setup_tx_resources(jme);
1232 if (rc) {
1233 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1234 goto err_out_free_rx_resources;
1235 }
1236
1237 jme_enable_rx_engine(jme);
1238 jme_enable_tx_engine(jme);
1239
1240 netif_start_queue(netdev);
1241
1242 if (test_bit(JME_FLAG_POLL, &jme->flags))
1243 jme_interrupt_mode(jme);
1244
1245 jme_start_pcc_timer(jme);
1246 } else if (jme_pseudo_hotplug_enabled(jme)) {
1247 jme_start_shutdown_timer(jme);
1248 }
1249
1250 goto out_enable_tasklet;
1251
1252err_out_free_rx_resources:
1253 jme_free_rx_resources(jme);
1254out_enable_tasklet:
1255 tasklet_enable(&jme->txclean_task);
1256 tasklet_hi_enable(&jme->rxclean_task);
1257 tasklet_hi_enable(&jme->rxempty_task);
1258out:
1259 atomic_inc(&jme->link_changing);
1260}
1261
1262static void
1263jme_rx_clean_tasklet(unsigned long arg)
1264{
1265 struct jme_adapter *jme = (struct jme_adapter *)arg;
1266 struct dynpcc_info *dpi = &(jme->dpi);
1267
1268 jme_process_receive(jme, jme->rx_ring_size);
1269 ++(dpi->intr_cnt);
1270
1271}
1272
1273static int
1274jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1275{
1276 struct jme_adapter *jme = jme_napi_priv(holder);
1277 int rest;
1278
1279 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1280
1281 while (atomic_read(&jme->rx_empty) > 0) {
1282 atomic_dec(&jme->rx_empty);
1283 ++(NET_STAT(jme).rx_dropped);
1284 jme_restart_rx_engine(jme);
1285 }
1286 atomic_inc(&jme->rx_empty);
1287
1288 if (rest) {
1289 JME_RX_COMPLETE(netdev, holder);
1290 jme_interrupt_mode(jme);
1291 }
1292
1293 JME_NAPI_WEIGHT_SET(budget, rest);
1294 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1295}
1296
1297static void
1298jme_rx_empty_tasklet(unsigned long arg)
1299{
1300 struct jme_adapter *jme = (struct jme_adapter *)arg;
1301
1302 if (unlikely(atomic_read(&jme->link_changing) != 1))
1303 return;
1304
1305 if (unlikely(!netif_carrier_ok(jme->dev)))
1306 return;
1307
1308 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1309
1310 jme_rx_clean_tasklet(arg);
1311
1312 while (atomic_read(&jme->rx_empty) > 0) {
1313 atomic_dec(&jme->rx_empty);
1314 ++(NET_STAT(jme).rx_dropped);
1315 jme_restart_rx_engine(jme);
1316 }
1317 atomic_inc(&jme->rx_empty);
1318}
1319
1320static void
1321jme_wake_queue_if_stopped(struct jme_adapter *jme)
1322{
1323 struct jme_ring *txring = &(jme->txring[0]);
1324
1325 smp_wmb();
1326 if (unlikely(netif_queue_stopped(jme->dev) &&
1327 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1328 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1329 netif_wake_queue(jme->dev);
1330 }
1331
1332}
1333
1334static void
1335jme_tx_clean_tasklet(unsigned long arg)
1336{
1337 struct jme_adapter *jme = (struct jme_adapter *)arg;
1338 struct jme_ring *txring = &(jme->txring[0]);
1339 struct txdesc *txdesc = txring->desc;
1340 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1341 int i, j, cnt = 0, max, err, mask;
1342
1343 tx_dbg(jme, "Into txclean\n");
1344
1345 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1346 goto out;
1347
1348 if (unlikely(atomic_read(&jme->link_changing) != 1))
1349 goto out;
1350
1351 if (unlikely(!netif_carrier_ok(jme->dev)))
1352 goto out;
1353
1354 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1355 mask = jme->tx_ring_mask;
1356
1357 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1358
1359 ctxbi = txbi + i;
1360
1361 if (likely(ctxbi->skb &&
1362 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1363
1364 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1365 i, ctxbi->nr_desc, jiffies);
1366
1367 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1368
1369 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1370 ttxbi = txbi + ((i + j) & (mask));
1371 txdesc[(i + j) & (mask)].dw[0] = 0;
1372
1373 pci_unmap_page(jme->pdev,
1374 ttxbi->mapping,
1375 ttxbi->len,
1376 PCI_DMA_TODEVICE);
1377
1378 ttxbi->mapping = 0;
1379 ttxbi->len = 0;
1380 }
1381
1382 dev_kfree_skb(ctxbi->skb);
1383
1384 cnt += ctxbi->nr_desc;
1385
1386 if (unlikely(err)) {
1387 ++(NET_STAT(jme).tx_carrier_errors);
1388 } else {
1389 ++(NET_STAT(jme).tx_packets);
1390 NET_STAT(jme).tx_bytes += ctxbi->len;
1391 }
1392
1393 ctxbi->skb = NULL;
1394 ctxbi->len = 0;
1395 ctxbi->start_xmit = 0;
1396
1397 } else {
1398 break;
1399 }
1400
1401 i = (i + ctxbi->nr_desc) & mask;
1402
1403 ctxbi->nr_desc = 0;
1404 }
1405
1406 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1407 atomic_set(&txring->next_to_clean, i);
1408 atomic_add(cnt, &txring->nr_free);
1409
1410 jme_wake_queue_if_stopped(jme);
1411
1412out:
1413 atomic_inc(&jme->tx_cleaning);
1414}
1415
1416static void
1417jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1418{
1419 /*
1420 * Disable interrupt
1421 */
1422 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1423
1424 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1425 /*
1426 * Link change event is critical
1427 * all other events are ignored
1428 */
1429 jwrite32(jme, JME_IEVE, intrstat);
1430 tasklet_schedule(&jme->linkch_task);
1431 goto out_reenable;
1432 }
1433
1434 if (intrstat & INTR_TMINTR) {
1435 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1436 tasklet_schedule(&jme->pcc_task);
1437 }
1438
1439 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1440 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1441 tasklet_schedule(&jme->txclean_task);
1442 }
1443
1444 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1445 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1446 INTR_PCCRX0 |
1447 INTR_RX0EMP)) |
1448 INTR_RX0);
1449 }
1450
1451 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1452 if (intrstat & INTR_RX0EMP)
1453 atomic_inc(&jme->rx_empty);
1454
1455 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1456 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1457 jme_polling_mode(jme);
1458 JME_RX_SCHEDULE(jme);
1459 }
1460 }
1461 } else {
1462 if (intrstat & INTR_RX0EMP) {
1463 atomic_inc(&jme->rx_empty);
1464 tasklet_hi_schedule(&jme->rxempty_task);
1465 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1466 tasklet_hi_schedule(&jme->rxclean_task);
1467 }
1468 }
1469
1470out_reenable:
1471 /*
1472 * Re-enable interrupt
1473 */
1474 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1475}
1476
1477static irqreturn_t
1478jme_intr(int irq, void *dev_id)
1479{
1480 struct net_device *netdev = dev_id;
1481 struct jme_adapter *jme = netdev_priv(netdev);
1482 u32 intrstat;
1483
1484 intrstat = jread32(jme, JME_IEVE);
1485
1486 /*
1487 * Check if it's really an interrupt for us
1488 */
1489 if (unlikely((intrstat & INTR_ENABLE) == 0))
1490 return IRQ_NONE;
1491
1492 /*
1493 * Check if the device still exist
1494 */
1495 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1496 return IRQ_NONE;
1497
1498 jme_intr_msi(jme, intrstat);
1499
1500 return IRQ_HANDLED;
1501}
1502
1503static irqreturn_t
1504jme_msi(int irq, void *dev_id)
1505{
1506 struct net_device *netdev = dev_id;
1507 struct jme_adapter *jme = netdev_priv(netdev);
1508 u32 intrstat;
1509
1510 intrstat = jread32(jme, JME_IEVE);
1511
1512 jme_intr_msi(jme, intrstat);
1513
1514 return IRQ_HANDLED;
1515}
1516
1517static void
1518jme_reset_link(struct jme_adapter *jme)
1519{
1520 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1521}
1522
1523static void
1524jme_restart_an(struct jme_adapter *jme)
1525{
1526 u32 bmcr;
1527
1528 spin_lock_bh(&jme->phy_lock);
1529 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1530 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1531 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1532 spin_unlock_bh(&jme->phy_lock);
1533}
1534
1535static int
1536jme_request_irq(struct jme_adapter *jme)
1537{
1538 int rc;
1539 struct net_device *netdev = jme->dev;
1540 irq_handler_t handler = jme_intr;
1541 int irq_flags = IRQF_SHARED;
1542
1543 if (!pci_enable_msi(jme->pdev)) {
1544 set_bit(JME_FLAG_MSI, &jme->flags);
1545 handler = jme_msi;
1546 irq_flags = 0;
1547 }
1548
1549 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1550 netdev);
1551 if (rc) {
1552 netdev_err(netdev,
1553 "Unable to request %s interrupt (return: %d)\n",
1554 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1555 rc);
1556
1557 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1558 pci_disable_msi(jme->pdev);
1559 clear_bit(JME_FLAG_MSI, &jme->flags);
1560 }
1561 } else {
1562 netdev->irq = jme->pdev->irq;
1563 }
1564
1565 return rc;
1566}
1567
1568static void
1569jme_free_irq(struct jme_adapter *jme)
1570{
1571 free_irq(jme->pdev->irq, jme->dev);
1572 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1573 pci_disable_msi(jme->pdev);
1574 clear_bit(JME_FLAG_MSI, &jme->flags);
1575 jme->dev->irq = jme->pdev->irq;
1576 }
1577}
1578
1579static inline void
1580jme_new_phy_on(struct jme_adapter *jme)
1581{
1582 u32 reg;
1583
1584 reg = jread32(jme, JME_PHY_PWR);
1585 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1586 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1587 jwrite32(jme, JME_PHY_PWR, reg);
1588
1589 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1590 reg &= ~PE1_GPREG0_PBG;
1591 reg |= PE1_GPREG0_ENBG;
1592 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1593}
1594
1595static inline void
1596jme_new_phy_off(struct jme_adapter *jme)
1597{
1598 u32 reg;
1599
1600 reg = jread32(jme, JME_PHY_PWR);
1601 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1602 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1603 jwrite32(jme, JME_PHY_PWR, reg);
1604
1605 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1606 reg &= ~PE1_GPREG0_PBG;
1607 reg |= PE1_GPREG0_PDD3COLD;
1608 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1609}
1610
1611static inline void
1612jme_phy_on(struct jme_adapter *jme)
1613{
1614 u32 bmcr;
1615
1616 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1617 bmcr &= ~BMCR_PDOWN;
1618 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1619
1620 if (new_phy_power_ctrl(jme->chip_main_rev))
1621 jme_new_phy_on(jme);
1622}
1623
1624static inline void
1625jme_phy_off(struct jme_adapter *jme)
1626{
1627 u32 bmcr;
1628
1629 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1630 bmcr |= BMCR_PDOWN;
1631 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1632
1633 if (new_phy_power_ctrl(jme->chip_main_rev))
1634 jme_new_phy_off(jme);
1635}
1636
1637static int
1638jme_open(struct net_device *netdev)
1639{
1640 struct jme_adapter *jme = netdev_priv(netdev);
1641 int rc;
1642
1643 jme_clear_pm(jme);
1644 JME_NAPI_ENABLE(jme);
1645
1646 tasklet_enable(&jme->linkch_task);
1647 tasklet_enable(&jme->txclean_task);
1648 tasklet_hi_enable(&jme->rxclean_task);
1649 tasklet_hi_enable(&jme->rxempty_task);
1650
1651 rc = jme_request_irq(jme);
1652 if (rc)
1653 goto err_out;
1654
1655 jme_start_irq(jme);
1656
1657 jme_phy_on(jme);
1658 if (test_bit(JME_FLAG_SSET, &jme->flags))
1659 jme_set_settings(netdev, &jme->old_ecmd);
1660 else
1661 jme_reset_phy_processor(jme);
1662
1663 jme_reset_link(jme);
1664
1665 return 0;
1666
1667err_out:
1668 netif_stop_queue(netdev);
1669 netif_carrier_off(netdev);
1670 return rc;
1671}
1672
1673static void
1674jme_set_100m_half(struct jme_adapter *jme)
1675{
1676 u32 bmcr, tmp;
1677
1678 jme_phy_on(jme);
1679 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1680 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1681 BMCR_SPEED1000 | BMCR_FULLDPLX);
1682 tmp |= BMCR_SPEED100;
1683
1684 if (bmcr != tmp)
1685 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1686
1687 if (jme->fpgaver)
1688 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1689 else
1690 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1691}
1692
1693#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1694static void
1695jme_wait_link(struct jme_adapter *jme)
1696{
1697 u32 phylink, to = JME_WAIT_LINK_TIME;
1698
1699 mdelay(1000);
1700 phylink = jme_linkstat_from_phy(jme);
1701 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1702 mdelay(10);
1703 phylink = jme_linkstat_from_phy(jme);
1704 }
1705}
1706
1707static void
1708jme_powersave_phy(struct jme_adapter *jme)
1709{
1710 if (jme->reg_pmcs) {
1711 jme_set_100m_half(jme);
1712
1713 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1714 jme_wait_link(jme);
1715
1716 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1717 } else {
1718 jme_phy_off(jme);
1719 }
1720}
1721
1722static int
1723jme_close(struct net_device *netdev)
1724{
1725 struct jme_adapter *jme = netdev_priv(netdev);
1726
1727 netif_stop_queue(netdev);
1728 netif_carrier_off(netdev);
1729
1730 jme_stop_irq(jme);
1731 jme_free_irq(jme);
1732
1733 JME_NAPI_DISABLE(jme);
1734
1735 tasklet_disable(&jme->linkch_task);
1736 tasklet_disable(&jme->txclean_task);
1737 tasklet_disable(&jme->rxclean_task);
1738 tasklet_disable(&jme->rxempty_task);
1739
1740 jme_reset_ghc_speed(jme);
1741 jme_disable_rx_engine(jme);
1742 jme_disable_tx_engine(jme);
1743 jme_reset_mac_processor(jme);
1744 jme_free_rx_resources(jme);
1745 jme_free_tx_resources(jme);
1746 jme->phylink = 0;
1747 jme_phy_off(jme);
1748
1749 return 0;
1750}
1751
1752static int
1753jme_alloc_txdesc(struct jme_adapter *jme,
1754 struct sk_buff *skb)
1755{
1756 struct jme_ring *txring = &(jme->txring[0]);
1757 int idx, nr_alloc, mask = jme->tx_ring_mask;
1758
1759 idx = txring->next_to_use;
1760 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1761
1762 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1763 return -1;
1764
1765 atomic_sub(nr_alloc, &txring->nr_free);
1766
1767 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1768
1769 return idx;
1770}
1771
1772static void
1773jme_fill_tx_map(struct pci_dev *pdev,
1774 struct txdesc *txdesc,
1775 struct jme_buffer_info *txbi,
1776 struct page *page,
1777 u32 page_offset,
1778 u32 len,
1779 u8 hidma)
1780{
1781 dma_addr_t dmaaddr;
1782
1783 dmaaddr = pci_map_page(pdev,
1784 page,
1785 page_offset,
1786 len,
1787 PCI_DMA_TODEVICE);
1788
1789 pci_dma_sync_single_for_device(pdev,
1790 dmaaddr,
1791 len,
1792 PCI_DMA_TODEVICE);
1793
1794 txdesc->dw[0] = 0;
1795 txdesc->dw[1] = 0;
1796 txdesc->desc2.flags = TXFLAG_OWN;
1797 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1798 txdesc->desc2.datalen = cpu_to_le16(len);
1799 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1800 txdesc->desc2.bufaddrl = cpu_to_le32(
1801 (__u64)dmaaddr & 0xFFFFFFFFUL);
1802
1803 txbi->mapping = dmaaddr;
1804 txbi->len = len;
1805}
1806
1807static void
1808jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1809{
1810 struct jme_ring *txring = &(jme->txring[0]);
1811 struct txdesc *txdesc = txring->desc, *ctxdesc;
1812 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1813 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1814 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1815 int mask = jme->tx_ring_mask;
1816 struct skb_frag_struct *frag;
1817 u32 len;
1818
1819 for (i = 0 ; i < nr_frags ; ++i) {
1820 frag = &skb_shinfo(skb)->frags[i];
1821 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1822 ctxbi = txbi + ((idx + i + 2) & (mask));
1823
1824 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1825 frag->page_offset, frag->size, hidma);
1826 }
1827
1828 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1829 ctxdesc = txdesc + ((idx + 1) & (mask));
1830 ctxbi = txbi + ((idx + 1) & (mask));
1831 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1832 offset_in_page(skb->data), len, hidma);
1833
1834}
1835
1836static int
1837jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1838{
1839 if (unlikely(skb_shinfo(skb)->gso_size &&
1840 skb_header_cloned(skb) &&
1841 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1842 dev_kfree_skb(skb);
1843 return -1;
1844 }
1845
1846 return 0;
1847}
1848
1849static int
1850jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1851{
1852 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1853 if (*mss) {
1854 *flags |= TXFLAG_LSEN;
1855
1856 if (skb->protocol == htons(ETH_P_IP)) {
1857 struct iphdr *iph = ip_hdr(skb);
1858
1859 iph->check = 0;
1860 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1861 iph->daddr, 0,
1862 IPPROTO_TCP,
1863 0);
1864 } else {
1865 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1866
1867 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1868 &ip6h->daddr, 0,
1869 IPPROTO_TCP,
1870 0);
1871 }
1872
1873 return 0;
1874 }
1875
1876 return 1;
1877}
1878
1879static void
1880jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1881{
1882 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1883 u8 ip_proto;
1884
1885 switch (skb->protocol) {
1886 case htons(ETH_P_IP):
1887 ip_proto = ip_hdr(skb)->protocol;
1888 break;
1889 case htons(ETH_P_IPV6):
1890 ip_proto = ipv6_hdr(skb)->nexthdr;
1891 break;
1892 default:
1893 ip_proto = 0;
1894 break;
1895 }
1896
1897 switch (ip_proto) {
1898 case IPPROTO_TCP:
1899 *flags |= TXFLAG_TCPCS;
1900 break;
1901 case IPPROTO_UDP:
1902 *flags |= TXFLAG_UDPCS;
1903 break;
1904 default:
1905 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1906 break;
1907 }
1908 }
1909}
1910
1911static inline void
1912jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1913{
1914 if (vlan_tx_tag_present(skb)) {
1915 *flags |= TXFLAG_TAGON;
1916 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1917 }
1918}
1919
1920static int
1921jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1922{
1923 struct jme_ring *txring = &(jme->txring[0]);
1924 struct txdesc *txdesc;
1925 struct jme_buffer_info *txbi;
1926 u8 flags;
1927
1928 txdesc = (struct txdesc *)txring->desc + idx;
1929 txbi = txring->bufinf + idx;
1930
1931 txdesc->dw[0] = 0;
1932 txdesc->dw[1] = 0;
1933 txdesc->dw[2] = 0;
1934 txdesc->dw[3] = 0;
1935 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1936 /*
1937 * Set OWN bit at final.
1938 * When kernel transmit faster than NIC.
1939 * And NIC trying to send this descriptor before we tell
1940 * it to start sending this TX queue.
1941 * Other fields are already filled correctly.
1942 */
1943 wmb();
1944 flags = TXFLAG_OWN | TXFLAG_INT;
1945 /*
1946 * Set checksum flags while not tso
1947 */
1948 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1949 jme_tx_csum(jme, skb, &flags);
1950 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1951 jme_map_tx_skb(jme, skb, idx);
1952 txdesc->desc1.flags = flags;
1953 /*
1954 * Set tx buffer info after telling NIC to send
1955 * For better tx_clean timing
1956 */
1957 wmb();
1958 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1959 txbi->skb = skb;
1960 txbi->len = skb->len;
1961 txbi->start_xmit = jiffies;
1962 if (!txbi->start_xmit)
1963 txbi->start_xmit = (0UL-1);
1964
1965 return 0;
1966}
1967
1968static void
1969jme_stop_queue_if_full(struct jme_adapter *jme)
1970{
1971 struct jme_ring *txring = &(jme->txring[0]);
1972 struct jme_buffer_info *txbi = txring->bufinf;
1973 int idx = atomic_read(&txring->next_to_clean);
1974
1975 txbi += idx;
1976
1977 smp_wmb();
1978 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1979 netif_stop_queue(jme->dev);
1980 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1981 smp_wmb();
1982 if (atomic_read(&txring->nr_free)
1983 >= (jme->tx_wake_threshold)) {
1984 netif_wake_queue(jme->dev);
1985 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1986 }
1987 }
1988
1989 if (unlikely(txbi->start_xmit &&
1990 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1991 txbi->skb)) {
1992 netif_stop_queue(jme->dev);
1993 netif_info(jme, tx_queued, jme->dev,
1994 "TX Queue Stopped %d@%lu\n", idx, jiffies);
1995 }
1996}
1997
1998/*
1999 * This function is already protected by netif_tx_lock()
2000 */
2001
2002static netdev_tx_t
2003jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2004{
2005 struct jme_adapter *jme = netdev_priv(netdev);
2006 int idx;
2007
2008 if (unlikely(jme_expand_header(jme, skb))) {
2009 ++(NET_STAT(jme).tx_dropped);
2010 return NETDEV_TX_OK;
2011 }
2012
2013 idx = jme_alloc_txdesc(jme, skb);
2014
2015 if (unlikely(idx < 0)) {
2016 netif_stop_queue(netdev);
2017 netif_err(jme, tx_err, jme->dev,
2018 "BUG! Tx ring full when queue awake!\n");
2019
2020 return NETDEV_TX_BUSY;
2021 }
2022
2023 jme_fill_tx_desc(jme, skb, idx);
2024
2025 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2026 TXCS_SELECT_QUEUE0 |
2027 TXCS_QUEUE0S |
2028 TXCS_ENABLE);
2029
2030 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2031 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2032 jme_stop_queue_if_full(jme);
2033
2034 return NETDEV_TX_OK;
2035}
2036
2037static int
2038jme_set_macaddr(struct net_device *netdev, void *p)
2039{
2040 struct jme_adapter *jme = netdev_priv(netdev);
2041 struct sockaddr *addr = p;
2042 u32 val;
2043
2044 if (netif_running(netdev))
2045 return -EBUSY;
2046
2047 spin_lock_bh(&jme->macaddr_lock);
2048 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2049
2050 val = (addr->sa_data[3] & 0xff) << 24 |
2051 (addr->sa_data[2] & 0xff) << 16 |
2052 (addr->sa_data[1] & 0xff) << 8 |
2053 (addr->sa_data[0] & 0xff);
2054 jwrite32(jme, JME_RXUMA_LO, val);
2055 val = (addr->sa_data[5] & 0xff) << 8 |
2056 (addr->sa_data[4] & 0xff);
2057 jwrite32(jme, JME_RXUMA_HI, val);
2058 spin_unlock_bh(&jme->macaddr_lock);
2059
2060 return 0;
2061}
2062
2063static void
2064jme_set_multi(struct net_device *netdev)
2065{
2066 struct jme_adapter *jme = netdev_priv(netdev);
2067 u32 mc_hash[2] = {};
2068
2069 spin_lock_bh(&jme->rxmcs_lock);
2070
2071 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2072
2073 if (netdev->flags & IFF_PROMISC) {
2074 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2075 } else if (netdev->flags & IFF_ALLMULTI) {
2076 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2077 } else if (netdev->flags & IFF_MULTICAST) {
2078 struct netdev_hw_addr *ha;
2079 int bit_nr;
2080
2081 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2082 netdev_for_each_mc_addr(ha, netdev) {
2083 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2084 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2085 }
2086
2087 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2088 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2089 }
2090
2091 wmb();
2092 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2093
2094 spin_unlock_bh(&jme->rxmcs_lock);
2095}
2096
2097static int
2098jme_change_mtu(struct net_device *netdev, int new_mtu)
2099{
2100 struct jme_adapter *jme = netdev_priv(netdev);
2101
2102 if (new_mtu == jme->old_mtu)
2103 return 0;
2104
2105 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2106 ((new_mtu) < IPV6_MIN_MTU))
2107 return -EINVAL;
2108
2109 if (new_mtu > 4000) {
2110 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2111 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2112 jme_restart_rx_engine(jme);
2113 } else {
2114 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2115 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2116 jme_restart_rx_engine(jme);
2117 }
2118
2119 if (new_mtu > 1900) {
2120 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2121 NETIF_F_TSO | NETIF_F_TSO6);
2122 } else {
2123 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2124 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2125 if (test_bit(JME_FLAG_TSO, &jme->flags))
2126 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2127 }
2128
2129 netdev->mtu = new_mtu;
2130 jme_reset_link(jme);
2131
2132 return 0;
2133}
2134
2135static void
2136jme_tx_timeout(struct net_device *netdev)
2137{
2138 struct jme_adapter *jme = netdev_priv(netdev);
2139
2140 jme->phylink = 0;
2141 jme_reset_phy_processor(jme);
2142 if (test_bit(JME_FLAG_SSET, &jme->flags))
2143 jme_set_settings(netdev, &jme->old_ecmd);
2144
2145 /*
2146 * Force to Reset the link again
2147 */
2148 jme_reset_link(jme);
2149}
2150
2151static inline void jme_pause_rx(struct jme_adapter *jme)
2152{
2153 atomic_dec(&jme->link_changing);
2154
2155 jme_set_rx_pcc(jme, PCC_OFF);
2156 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2157 JME_NAPI_DISABLE(jme);
2158 } else {
2159 tasklet_disable(&jme->rxclean_task);
2160 tasklet_disable(&jme->rxempty_task);
2161 }
2162}
2163
2164static inline void jme_resume_rx(struct jme_adapter *jme)
2165{
2166 struct dynpcc_info *dpi = &(jme->dpi);
2167
2168 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2169 JME_NAPI_ENABLE(jme);
2170 } else {
2171 tasklet_hi_enable(&jme->rxclean_task);
2172 tasklet_hi_enable(&jme->rxempty_task);
2173 }
2174 dpi->cur = PCC_P1;
2175 dpi->attempt = PCC_P1;
2176 dpi->cnt = 0;
2177 jme_set_rx_pcc(jme, PCC_P1);
2178
2179 atomic_inc(&jme->link_changing);
2180}
2181
2182static void
2183jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2184{
2185 struct jme_adapter *jme = netdev_priv(netdev);
2186
2187 jme_pause_rx(jme);
2188 jme->vlgrp = grp;
2189 jme_resume_rx(jme);
2190}
2191
2192static void
2193jme_get_drvinfo(struct net_device *netdev,
2194 struct ethtool_drvinfo *info)
2195{
2196 struct jme_adapter *jme = netdev_priv(netdev);
2197
2198 strcpy(info->driver, DRV_NAME);
2199 strcpy(info->version, DRV_VERSION);
2200 strcpy(info->bus_info, pci_name(jme->pdev));
2201}
2202
2203static int
2204jme_get_regs_len(struct net_device *netdev)
2205{
2206 return JME_REG_LEN;
2207}
2208
2209static void
2210mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2211{
2212 int i;
2213
2214 for (i = 0 ; i < len ; i += 4)
2215 p[i >> 2] = jread32(jme, reg + i);
2216}
2217
2218static void
2219mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2220{
2221 int i;
2222 u16 *p16 = (u16 *)p;
2223
2224 for (i = 0 ; i < reg_nr ; ++i)
2225 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2226}
2227
2228static void
2229jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2230{
2231 struct jme_adapter *jme = netdev_priv(netdev);
2232 u32 *p32 = (u32 *)p;
2233
2234 memset(p, 0xFF, JME_REG_LEN);
2235
2236 regs->version = 1;
2237 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2238
2239 p32 += 0x100 >> 2;
2240 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2241
2242 p32 += 0x100 >> 2;
2243 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2244
2245 p32 += 0x100 >> 2;
2246 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2247
2248 p32 += 0x100 >> 2;
2249 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2250}
2251
2252static int
2253jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2254{
2255 struct jme_adapter *jme = netdev_priv(netdev);
2256
2257 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2258 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2259
2260 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2261 ecmd->use_adaptive_rx_coalesce = false;
2262 ecmd->rx_coalesce_usecs = 0;
2263 ecmd->rx_max_coalesced_frames = 0;
2264 return 0;
2265 }
2266
2267 ecmd->use_adaptive_rx_coalesce = true;
2268
2269 switch (jme->dpi.cur) {
2270 case PCC_P1:
2271 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2272 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2273 break;
2274 case PCC_P2:
2275 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2276 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2277 break;
2278 case PCC_P3:
2279 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2280 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2281 break;
2282 default:
2283 break;
2284 }
2285
2286 return 0;
2287}
2288
2289static int
2290jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2291{
2292 struct jme_adapter *jme = netdev_priv(netdev);
2293 struct dynpcc_info *dpi = &(jme->dpi);
2294
2295 if (netif_running(netdev))
2296 return -EBUSY;
2297
2298 if (ecmd->use_adaptive_rx_coalesce &&
2299 test_bit(JME_FLAG_POLL, &jme->flags)) {
2300 clear_bit(JME_FLAG_POLL, &jme->flags);
2301 jme->jme_rx = netif_rx;
2302 jme->jme_vlan_rx = vlan_hwaccel_rx;
2303 dpi->cur = PCC_P1;
2304 dpi->attempt = PCC_P1;
2305 dpi->cnt = 0;
2306 jme_set_rx_pcc(jme, PCC_P1);
2307 jme_interrupt_mode(jme);
2308 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2309 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2310 set_bit(JME_FLAG_POLL, &jme->flags);
2311 jme->jme_rx = netif_receive_skb;
2312 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2313 jme_interrupt_mode(jme);
2314 }
2315
2316 return 0;
2317}
2318
2319static void
2320jme_get_pauseparam(struct net_device *netdev,
2321 struct ethtool_pauseparam *ecmd)
2322{
2323 struct jme_adapter *jme = netdev_priv(netdev);
2324 u32 val;
2325
2326 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2327 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2328
2329 spin_lock_bh(&jme->phy_lock);
2330 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2331 spin_unlock_bh(&jme->phy_lock);
2332
2333 ecmd->autoneg =
2334 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2335}
2336
2337static int
2338jme_set_pauseparam(struct net_device *netdev,
2339 struct ethtool_pauseparam *ecmd)
2340{
2341 struct jme_adapter *jme = netdev_priv(netdev);
2342 u32 val;
2343
2344 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2345 (ecmd->tx_pause != 0)) {
2346
2347 if (ecmd->tx_pause)
2348 jme->reg_txpfc |= TXPFC_PF_EN;
2349 else
2350 jme->reg_txpfc &= ~TXPFC_PF_EN;
2351
2352 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2353 }
2354
2355 spin_lock_bh(&jme->rxmcs_lock);
2356 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2357 (ecmd->rx_pause != 0)) {
2358
2359 if (ecmd->rx_pause)
2360 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2361 else
2362 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2363
2364 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2365 }
2366 spin_unlock_bh(&jme->rxmcs_lock);
2367
2368 spin_lock_bh(&jme->phy_lock);
2369 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2370 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2371 (ecmd->autoneg != 0)) {
2372
2373 if (ecmd->autoneg)
2374 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2375 else
2376 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2377
2378 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2379 MII_ADVERTISE, val);
2380 }
2381 spin_unlock_bh(&jme->phy_lock);
2382
2383 return 0;
2384}
2385
2386static void
2387jme_get_wol(struct net_device *netdev,
2388 struct ethtool_wolinfo *wol)
2389{
2390 struct jme_adapter *jme = netdev_priv(netdev);
2391
2392 wol->supported = WAKE_MAGIC | WAKE_PHY;
2393
2394 wol->wolopts = 0;
2395
2396 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2397 wol->wolopts |= WAKE_PHY;
2398
2399 if (jme->reg_pmcs & PMCS_MFEN)
2400 wol->wolopts |= WAKE_MAGIC;
2401
2402}
2403
2404static int
2405jme_set_wol(struct net_device *netdev,
2406 struct ethtool_wolinfo *wol)
2407{
2408 struct jme_adapter *jme = netdev_priv(netdev);
2409
2410 if (wol->wolopts & (WAKE_MAGICSECURE |
2411 WAKE_UCAST |
2412 WAKE_MCAST |
2413 WAKE_BCAST |
2414 WAKE_ARP))
2415 return -EOPNOTSUPP;
2416
2417 jme->reg_pmcs = 0;
2418
2419 if (wol->wolopts & WAKE_PHY)
2420 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2421
2422 if (wol->wolopts & WAKE_MAGIC)
2423 jme->reg_pmcs |= PMCS_MFEN;
2424
2425 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2426
2427 return 0;
2428}
2429
2430static int
2431jme_get_settings(struct net_device *netdev,
2432 struct ethtool_cmd *ecmd)
2433{
2434 struct jme_adapter *jme = netdev_priv(netdev);
2435 int rc;
2436
2437 spin_lock_bh(&jme->phy_lock);
2438 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2439 spin_unlock_bh(&jme->phy_lock);
2440 return rc;
2441}
2442
2443static int
2444jme_set_settings(struct net_device *netdev,
2445 struct ethtool_cmd *ecmd)
2446{
2447 struct jme_adapter *jme = netdev_priv(netdev);
2448 int rc, fdc = 0;
2449
2450 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2451 return -EINVAL;
2452
2453 /*
2454 * Check If user changed duplex only while force_media.
2455 * Hardware would not generate link change interrupt.
2456 */
2457 if (jme->mii_if.force_media &&
2458 ecmd->autoneg != AUTONEG_ENABLE &&
2459 (jme->mii_if.full_duplex != ecmd->duplex))
2460 fdc = 1;
2461
2462 spin_lock_bh(&jme->phy_lock);
2463 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2464 spin_unlock_bh(&jme->phy_lock);
2465
2466 if (!rc) {
2467 if (fdc)
2468 jme_reset_link(jme);
2469 jme->old_ecmd = *ecmd;
2470 set_bit(JME_FLAG_SSET, &jme->flags);
2471 }
2472
2473 return rc;
2474}
2475
2476static int
2477jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2478{
2479 int rc;
2480 struct jme_adapter *jme = netdev_priv(netdev);
2481 struct mii_ioctl_data *mii_data = if_mii(rq);
2482 unsigned int duplex_chg;
2483
2484 if (cmd == SIOCSMIIREG) {
2485 u16 val = mii_data->val_in;
2486 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2487 (val & BMCR_SPEED1000))
2488 return -EINVAL;
2489 }
2490
2491 spin_lock_bh(&jme->phy_lock);
2492 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2493 spin_unlock_bh(&jme->phy_lock);
2494
2495 if (!rc && (cmd == SIOCSMIIREG)) {
2496 if (duplex_chg)
2497 jme_reset_link(jme);
2498 jme_get_settings(netdev, &jme->old_ecmd);
2499 set_bit(JME_FLAG_SSET, &jme->flags);
2500 }
2501
2502 return rc;
2503}
2504
2505static u32
2506jme_get_link(struct net_device *netdev)
2507{
2508 struct jme_adapter *jme = netdev_priv(netdev);
2509 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2510}
2511
2512static u32
2513jme_get_msglevel(struct net_device *netdev)
2514{
2515 struct jme_adapter *jme = netdev_priv(netdev);
2516 return jme->msg_enable;
2517}
2518
2519static void
2520jme_set_msglevel(struct net_device *netdev, u32 value)
2521{
2522 struct jme_adapter *jme = netdev_priv(netdev);
2523 jme->msg_enable = value;
2524}
2525
2526static u32
2527jme_get_rx_csum(struct net_device *netdev)
2528{
2529 struct jme_adapter *jme = netdev_priv(netdev);
2530 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2531}
2532
2533static int
2534jme_set_rx_csum(struct net_device *netdev, u32 on)
2535{
2536 struct jme_adapter *jme = netdev_priv(netdev);
2537
2538 spin_lock_bh(&jme->rxmcs_lock);
2539 if (on)
2540 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2541 else
2542 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2543 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2544 spin_unlock_bh(&jme->rxmcs_lock);
2545
2546 return 0;
2547}
2548
2549static int
2550jme_set_tx_csum(struct net_device *netdev, u32 on)
2551{
2552 struct jme_adapter *jme = netdev_priv(netdev);
2553
2554 if (on) {
2555 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2556 if (netdev->mtu <= 1900)
2557 netdev->features |=
2558 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2559 } else {
2560 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2561 netdev->features &=
2562 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2563 }
2564
2565 return 0;
2566}
2567
2568static int
2569jme_set_tso(struct net_device *netdev, u32 on)
2570{
2571 struct jme_adapter *jme = netdev_priv(netdev);
2572
2573 if (on) {
2574 set_bit(JME_FLAG_TSO, &jme->flags);
2575 if (netdev->mtu <= 1900)
2576 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2577 } else {
2578 clear_bit(JME_FLAG_TSO, &jme->flags);
2579 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2580 }
2581
2582 return 0;
2583}
2584
2585static int
2586jme_nway_reset(struct net_device *netdev)
2587{
2588 struct jme_adapter *jme = netdev_priv(netdev);
2589 jme_restart_an(jme);
2590 return 0;
2591}
2592
2593static u8
2594jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2595{
2596 u32 val;
2597 int to;
2598
2599 val = jread32(jme, JME_SMBCSR);
2600 to = JME_SMB_BUSY_TIMEOUT;
2601 while ((val & SMBCSR_BUSY) && --to) {
2602 msleep(1);
2603 val = jread32(jme, JME_SMBCSR);
2604 }
2605 if (!to) {
2606 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2607 return 0xFF;
2608 }
2609
2610 jwrite32(jme, JME_SMBINTF,
2611 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2612 SMBINTF_HWRWN_READ |
2613 SMBINTF_HWCMD);
2614
2615 val = jread32(jme, JME_SMBINTF);
2616 to = JME_SMB_BUSY_TIMEOUT;
2617 while ((val & SMBINTF_HWCMD) && --to) {
2618 msleep(1);
2619 val = jread32(jme, JME_SMBINTF);
2620 }
2621 if (!to) {
2622 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2623 return 0xFF;
2624 }
2625
2626 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2627}
2628
2629static void
2630jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2631{
2632 u32 val;
2633 int to;
2634
2635 val = jread32(jme, JME_SMBCSR);
2636 to = JME_SMB_BUSY_TIMEOUT;
2637 while ((val & SMBCSR_BUSY) && --to) {
2638 msleep(1);
2639 val = jread32(jme, JME_SMBCSR);
2640 }
2641 if (!to) {
2642 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2643 return;
2644 }
2645
2646 jwrite32(jme, JME_SMBINTF,
2647 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2648 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2649 SMBINTF_HWRWN_WRITE |
2650 SMBINTF_HWCMD);
2651
2652 val = jread32(jme, JME_SMBINTF);
2653 to = JME_SMB_BUSY_TIMEOUT;
2654 while ((val & SMBINTF_HWCMD) && --to) {
2655 msleep(1);
2656 val = jread32(jme, JME_SMBINTF);
2657 }
2658 if (!to) {
2659 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2660 return;
2661 }
2662
2663 mdelay(2);
2664}
2665
2666static int
2667jme_get_eeprom_len(struct net_device *netdev)
2668{
2669 struct jme_adapter *jme = netdev_priv(netdev);
2670 u32 val;
2671 val = jread32(jme, JME_SMBCSR);
2672 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2673}
2674
2675static int
2676jme_get_eeprom(struct net_device *netdev,
2677 struct ethtool_eeprom *eeprom, u8 *data)
2678{
2679 struct jme_adapter *jme = netdev_priv(netdev);
2680 int i, offset = eeprom->offset, len = eeprom->len;
2681
2682 /*
2683 * ethtool will check the boundary for us
2684 */
2685 eeprom->magic = JME_EEPROM_MAGIC;
2686 for (i = 0 ; i < len ; ++i)
2687 data[i] = jme_smb_read(jme, i + offset);
2688
2689 return 0;
2690}
2691
2692static int
2693jme_set_eeprom(struct net_device *netdev,
2694 struct ethtool_eeprom *eeprom, u8 *data)
2695{
2696 struct jme_adapter *jme = netdev_priv(netdev);
2697 int i, offset = eeprom->offset, len = eeprom->len;
2698
2699 if (eeprom->magic != JME_EEPROM_MAGIC)
2700 return -EINVAL;
2701
2702 /*
2703 * ethtool will check the boundary for us
2704 */
2705 for (i = 0 ; i < len ; ++i)
2706 jme_smb_write(jme, i + offset, data[i]);
2707
2708 return 0;
2709}
2710
2711static const struct ethtool_ops jme_ethtool_ops = {
2712 .get_drvinfo = jme_get_drvinfo,
2713 .get_regs_len = jme_get_regs_len,
2714 .get_regs = jme_get_regs,
2715 .get_coalesce = jme_get_coalesce,
2716 .set_coalesce = jme_set_coalesce,
2717 .get_pauseparam = jme_get_pauseparam,
2718 .set_pauseparam = jme_set_pauseparam,
2719 .get_wol = jme_get_wol,
2720 .set_wol = jme_set_wol,
2721 .get_settings = jme_get_settings,
2722 .set_settings = jme_set_settings,
2723 .get_link = jme_get_link,
2724 .get_msglevel = jme_get_msglevel,
2725 .set_msglevel = jme_set_msglevel,
2726 .get_rx_csum = jme_get_rx_csum,
2727 .set_rx_csum = jme_set_rx_csum,
2728 .set_tx_csum = jme_set_tx_csum,
2729 .set_tso = jme_set_tso,
2730 .set_sg = ethtool_op_set_sg,
2731 .nway_reset = jme_nway_reset,
2732 .get_eeprom_len = jme_get_eeprom_len,
2733 .get_eeprom = jme_get_eeprom,
2734 .set_eeprom = jme_set_eeprom,
2735};
2736
2737static int
2738jme_pci_dma64(struct pci_dev *pdev)
2739{
2740 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2741 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2742 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2743 return 1;
2744
2745 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2746 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2747 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2748 return 1;
2749
2750 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2751 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2752 return 0;
2753
2754 return -1;
2755}
2756
2757static inline void
2758jme_phy_init(struct jme_adapter *jme)
2759{
2760 u16 reg26;
2761
2762 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2763 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2764}
2765
2766static inline void
2767jme_check_hw_ver(struct jme_adapter *jme)
2768{
2769 u32 chipmode;
2770
2771 chipmode = jread32(jme, JME_CHIPMODE);
2772
2773 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2774 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2775 jme->chip_main_rev = jme->chiprev & 0xF;
2776 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2777}
2778
2779static const struct net_device_ops jme_netdev_ops = {
2780 .ndo_open = jme_open,
2781 .ndo_stop = jme_close,
2782 .ndo_validate_addr = eth_validate_addr,
2783 .ndo_do_ioctl = jme_ioctl,
2784 .ndo_start_xmit = jme_start_xmit,
2785 .ndo_set_mac_address = jme_set_macaddr,
2786 .ndo_set_multicast_list = jme_set_multi,
2787 .ndo_change_mtu = jme_change_mtu,
2788 .ndo_tx_timeout = jme_tx_timeout,
2789 .ndo_vlan_rx_register = jme_vlan_rx_register,
2790};
2791
2792static int __devinit
2793jme_init_one(struct pci_dev *pdev,
2794 const struct pci_device_id *ent)
2795{
2796 int rc = 0, using_dac, i;
2797 struct net_device *netdev;
2798 struct jme_adapter *jme;
2799 u16 bmcr, bmsr;
2800 u32 apmc;
2801
2802 /*
2803 * set up PCI device basics
2804 */
2805 rc = pci_enable_device(pdev);
2806 if (rc) {
2807 pr_err("Cannot enable PCI device\n");
2808 goto err_out;
2809 }
2810
2811 using_dac = jme_pci_dma64(pdev);
2812 if (using_dac < 0) {
2813 pr_err("Cannot set PCI DMA Mask\n");
2814 rc = -EIO;
2815 goto err_out_disable_pdev;
2816 }
2817
2818 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2819 pr_err("No PCI resource region found\n");
2820 rc = -ENOMEM;
2821 goto err_out_disable_pdev;
2822 }
2823
2824 rc = pci_request_regions(pdev, DRV_NAME);
2825 if (rc) {
2826 pr_err("Cannot obtain PCI resource region\n");
2827 goto err_out_disable_pdev;
2828 }
2829
2830 pci_set_master(pdev);
2831
2832 /*
2833 * alloc and init net device
2834 */
2835 netdev = alloc_etherdev(sizeof(*jme));
2836 if (!netdev) {
2837 pr_err("Cannot allocate netdev structure\n");
2838 rc = -ENOMEM;
2839 goto err_out_release_regions;
2840 }
2841 netdev->netdev_ops = &jme_netdev_ops;
2842 netdev->ethtool_ops = &jme_ethtool_ops;
2843 netdev->watchdog_timeo = TX_TIMEOUT;
2844 netdev->features = NETIF_F_IP_CSUM |
2845 NETIF_F_IPV6_CSUM |
2846 NETIF_F_SG |
2847 NETIF_F_TSO |
2848 NETIF_F_TSO6 |
2849 NETIF_F_HW_VLAN_TX |
2850 NETIF_F_HW_VLAN_RX;
2851 if (using_dac)
2852 netdev->features |= NETIF_F_HIGHDMA;
2853
2854 SET_NETDEV_DEV(netdev, &pdev->dev);
2855 pci_set_drvdata(pdev, netdev);
2856
2857 /*
2858 * init adapter info
2859 */
2860 jme = netdev_priv(netdev);
2861 jme->pdev = pdev;
2862 jme->dev = netdev;
2863 jme->jme_rx = netif_rx;
2864 jme->jme_vlan_rx = vlan_hwaccel_rx;
2865 jme->old_mtu = netdev->mtu = 1500;
2866 jme->phylink = 0;
2867 jme->tx_ring_size = 1 << 10;
2868 jme->tx_ring_mask = jme->tx_ring_size - 1;
2869 jme->tx_wake_threshold = 1 << 9;
2870 jme->rx_ring_size = 1 << 9;
2871 jme->rx_ring_mask = jme->rx_ring_size - 1;
2872 jme->msg_enable = JME_DEF_MSG_ENABLE;
2873 jme->regs = ioremap(pci_resource_start(pdev, 0),
2874 pci_resource_len(pdev, 0));
2875 if (!(jme->regs)) {
2876 pr_err("Mapping PCI resource region error\n");
2877 rc = -ENOMEM;
2878 goto err_out_free_netdev;
2879 }
2880
2881 if (no_pseudohp) {
2882 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2883 jwrite32(jme, JME_APMC, apmc);
2884 } else if (force_pseudohp) {
2885 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2886 jwrite32(jme, JME_APMC, apmc);
2887 }
2888
2889 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2890
2891 spin_lock_init(&jme->phy_lock);
2892 spin_lock_init(&jme->macaddr_lock);
2893 spin_lock_init(&jme->rxmcs_lock);
2894
2895 atomic_set(&jme->link_changing, 1);
2896 atomic_set(&jme->rx_cleaning, 1);
2897 atomic_set(&jme->tx_cleaning, 1);
2898 atomic_set(&jme->rx_empty, 1);
2899
2900 tasklet_init(&jme->pcc_task,
2901 jme_pcc_tasklet,
2902 (unsigned long) jme);
2903 tasklet_init(&jme->linkch_task,
2904 jme_link_change_tasklet,
2905 (unsigned long) jme);
2906 tasklet_init(&jme->txclean_task,
2907 jme_tx_clean_tasklet,
2908 (unsigned long) jme);
2909 tasklet_init(&jme->rxclean_task,
2910 jme_rx_clean_tasklet,
2911 (unsigned long) jme);
2912 tasklet_init(&jme->rxempty_task,
2913 jme_rx_empty_tasklet,
2914 (unsigned long) jme);
2915 tasklet_disable_nosync(&jme->linkch_task);
2916 tasklet_disable_nosync(&jme->txclean_task);
2917 tasklet_disable_nosync(&jme->rxclean_task);
2918 tasklet_disable_nosync(&jme->rxempty_task);
2919 jme->dpi.cur = PCC_P1;
2920
2921 jme->reg_ghc = 0;
2922 jme->reg_rxcs = RXCS_DEFAULT;
2923 jme->reg_rxmcs = RXMCS_DEFAULT;
2924 jme->reg_txpfc = 0;
2925 jme->reg_pmcs = PMCS_MFEN;
2926 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2927 set_bit(JME_FLAG_TSO, &jme->flags);
2928
2929 /*
2930 * Get Max Read Req Size from PCI Config Space
2931 */
2932 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2933 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2934 switch (jme->mrrs) {
2935 case MRRS_128B:
2936 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2937 break;
2938 case MRRS_256B:
2939 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2940 break;
2941 default:
2942 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2943 break;
2944 }
2945
2946 /*
2947 * Must check before reset_mac_processor
2948 */
2949 jme_check_hw_ver(jme);
2950 jme->mii_if.dev = netdev;
2951 if (jme->fpgaver) {
2952 jme->mii_if.phy_id = 0;
2953 for (i = 1 ; i < 32 ; ++i) {
2954 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2955 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2956 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2957 jme->mii_if.phy_id = i;
2958 break;
2959 }
2960 }
2961
2962 if (!jme->mii_if.phy_id) {
2963 rc = -EIO;
2964 pr_err("Can not find phy_id\n");
2965 goto err_out_unmap;
2966 }
2967
2968 jme->reg_ghc |= GHC_LINK_POLL;
2969 } else {
2970 jme->mii_if.phy_id = 1;
2971 }
2972 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2973 jme->mii_if.supports_gmii = true;
2974 else
2975 jme->mii_if.supports_gmii = false;
2976 jme->mii_if.phy_id_mask = 0x1F;
2977 jme->mii_if.reg_num_mask = 0x1F;
2978 jme->mii_if.mdio_read = jme_mdio_read;
2979 jme->mii_if.mdio_write = jme_mdio_write;
2980
2981 jme_clear_pm(jme);
2982 jme_set_phyfifo_5level(jme);
2983 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
2984 if (!jme->fpgaver)
2985 jme_phy_init(jme);
2986 jme_phy_off(jme);
2987
2988 /*
2989 * Reset MAC processor and reload EEPROM for MAC Address
2990 */
2991 jme_reset_mac_processor(jme);
2992 rc = jme_reload_eeprom(jme);
2993 if (rc) {
2994 pr_err("Reload eeprom for reading MAC Address error\n");
2995 goto err_out_unmap;
2996 }
2997 jme_load_macaddr(netdev);
2998
2999 /*
3000 * Tell stack that we are not ready to work until open()
3001 */
3002 netif_carrier_off(netdev);
3003
3004 rc = register_netdev(netdev);
3005 if (rc) {
3006 pr_err("Cannot register net device\n");
3007 goto err_out_unmap;
3008 }
3009
3010 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3011 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3012 "JMC250 Gigabit Ethernet" :
3013 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3014 "JMC260 Fast Ethernet" : "Unknown",
3015 (jme->fpgaver != 0) ? " (FPGA)" : "",
3016 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3017 jme->pcirev, netdev->dev_addr);
3018
3019 return 0;
3020
3021err_out_unmap:
3022 iounmap(jme->regs);
3023err_out_free_netdev:
3024 pci_set_drvdata(pdev, NULL);
3025 free_netdev(netdev);
3026err_out_release_regions:
3027 pci_release_regions(pdev);
3028err_out_disable_pdev:
3029 pci_disable_device(pdev);
3030err_out:
3031 return rc;
3032}
3033
3034static void __devexit
3035jme_remove_one(struct pci_dev *pdev)
3036{
3037 struct net_device *netdev = pci_get_drvdata(pdev);
3038 struct jme_adapter *jme = netdev_priv(netdev);
3039
3040 unregister_netdev(netdev);
3041 iounmap(jme->regs);
3042 pci_set_drvdata(pdev, NULL);
3043 free_netdev(netdev);
3044 pci_release_regions(pdev);
3045 pci_disable_device(pdev);
3046
3047}
3048
3049static void
3050jme_shutdown(struct pci_dev *pdev)
3051{
3052 struct net_device *netdev = pci_get_drvdata(pdev);
3053 struct jme_adapter *jme = netdev_priv(netdev);
3054
3055 jme_powersave_phy(jme);
3056 pci_pme_active(pdev, true);
3057}
3058
3059#ifdef CONFIG_PM
3060static int
3061jme_suspend(struct pci_dev *pdev, pm_message_t state)
3062{
3063 struct net_device *netdev = pci_get_drvdata(pdev);
3064 struct jme_adapter *jme = netdev_priv(netdev);
3065
3066 atomic_dec(&jme->link_changing);
3067
3068 netif_device_detach(netdev);
3069 netif_stop_queue(netdev);
3070 jme_stop_irq(jme);
3071
3072 tasklet_disable(&jme->txclean_task);
3073 tasklet_disable(&jme->rxclean_task);
3074 tasklet_disable(&jme->rxempty_task);
3075
3076 if (netif_carrier_ok(netdev)) {
3077 if (test_bit(JME_FLAG_POLL, &jme->flags))
3078 jme_polling_mode(jme);
3079
3080 jme_stop_pcc_timer(jme);
3081 jme_reset_ghc_speed(jme);
3082 jme_disable_rx_engine(jme);
3083 jme_disable_tx_engine(jme);
3084 jme_reset_mac_processor(jme);
3085 jme_free_rx_resources(jme);
3086 jme_free_tx_resources(jme);
3087 netif_carrier_off(netdev);
3088 jme->phylink = 0;
3089 }
3090
3091 tasklet_enable(&jme->txclean_task);
3092 tasklet_hi_enable(&jme->rxclean_task);
3093 tasklet_hi_enable(&jme->rxempty_task);
3094
3095 pci_save_state(pdev);
3096 jme_powersave_phy(jme);
3097 pci_enable_wake(jme->pdev, PCI_D3hot, true);
3098 pci_set_power_state(pdev, PCI_D3hot);
3099
3100 return 0;
3101}
3102
3103static int
3104jme_resume(struct pci_dev *pdev)
3105{
3106 struct net_device *netdev = pci_get_drvdata(pdev);
3107 struct jme_adapter *jme = netdev_priv(netdev);
3108
3109 jme_clear_pm(jme);
3110 pci_restore_state(pdev);
3111
3112 jme_phy_on(jme);
3113 if (test_bit(JME_FLAG_SSET, &jme->flags))
3114 jme_set_settings(netdev, &jme->old_ecmd);
3115 else
3116 jme_reset_phy_processor(jme);
3117
3118 jme_start_irq(jme);
3119 netif_device_attach(netdev);
3120
3121 atomic_inc(&jme->link_changing);
3122
3123 jme_reset_link(jme);
3124
3125 return 0;
3126}
3127#endif
3128
3129static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3130 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3131 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3132 { }
3133};
3134
3135static struct pci_driver jme_driver = {
3136 .name = DRV_NAME,
3137 .id_table = jme_pci_tbl,
3138 .probe = jme_init_one,
3139 .remove = __devexit_p(jme_remove_one),
3140#ifdef CONFIG_PM
3141 .suspend = jme_suspend,
3142 .resume = jme_resume,
3143#endif /* CONFIG_PM */
3144 .shutdown = jme_shutdown,
3145};
3146
3147static int __init
3148jme_init_module(void)
3149{
3150 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3151 return pci_register_driver(&jme_driver);
3152}
3153
3154static void __exit
3155jme_cleanup_module(void)
3156{
3157 pci_unregister_driver(&jme_driver);
3158}
3159
3160module_init(jme_init_module);
3161module_exit(jme_cleanup_module);
3162
3163MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3164MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3165MODULE_LICENSE("GPL");
3166MODULE_VERSION(DRV_VERSION);
3167MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3168
JMicron Ethernet Linux driver