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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/crc32.h>
35#include <linux/delay.h>
36#include <linux/spinlock.h>
37#include <linux/in.h>
38#include <linux/ip.h>
39#include <linux/ipv6.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/if_vlan.h>
43#include <linux/slab.h>
44#include <net/ip6_checksum.h>
45#include "jme.h"
46
47static int force_pseudohp = -1;
48static int no_pseudohp = -1;
49static int no_extplug = -1;
50module_param(force_pseudohp, int, 0);
51MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53module_param(no_pseudohp, int, 0);
54MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55module_param(no_extplug, int, 0);
56MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
58
59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
61{
62 struct jme_adapter *jme = netdev_priv(netdev);
63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
64
65read_again:
66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
69
70 wmb();
71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72 udelay(20);
73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
75 break;
76 }
77
78 if (i == 0) {
79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
80 return 0;
81 }
82
83 if (again--)
84 goto read_again;
85
86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
87}
88
89static void
90jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
92{
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
99
100 wmb();
101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 break;
105 }
106
107 if (i == 0)
108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
109}
110
111static inline void
112jme_reset_phy_processor(struct jme_adapter *jme)
113{
114 u32 val;
115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120
121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126
127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
134}
135
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
138 const u32 *mask, u32 crc, int fnr)
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
162
163static inline void
164jme_mac_rxclk_off(struct jme_adapter *jme)
165{
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168}
169
170static inline void
171jme_mac_rxclk_on(struct jme_adapter *jme)
172{
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175}
176
177static inline void
178jme_mac_txclk_off(struct jme_adapter *jme)
179{
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
182}
183
184static inline void
185jme_mac_txclk_on(struct jme_adapter *jme)
186{
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190 else
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
193}
194
195static inline void
196jme_reset_ghc_speed(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_reset_250A2_workaround(struct jme_adapter *jme)
204{
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206 GPREG1_RSSPATCH);
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208}
209
210static inline void
211jme_assert_ghc_reset(struct jme_adapter *jme)
212{
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215}
216
217static inline void
218jme_clear_ghc_reset(struct jme_adapter *jme)
219{
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
222}
223
224static inline void
225jme_reset_mac_processor(struct jme_adapter *jme)
226{
227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
228 u32 crc = 0xCDCDCDCD;
229 u32 gpreg0;
230 int i;
231
232 jme_reset_ghc_speed(jme);
233 jme_reset_250A2_workaround(jme);
234
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
237 udelay(1);
238 jme_assert_ghc_reset(jme);
239 udelay(1);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
242 udelay(1);
243 jme_clear_ghc_reset(jme);
244 udelay(1);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
247 udelay(1);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
250
251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253 jwrite32(jme, JME_RXQDC, 0x00000000);
254 jwrite32(jme, JME_RXNDA, 0x00000000);
255 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257 jwrite32(jme, JME_TXQDC, 0x00000000);
258 jwrite32(jme, JME_TXNDA, 0x00000000);
259
260 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
262 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
263 jme_setup_wakeup_frame(jme, mask, crc, i);
264 if (jme->fpgaver)
265 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266 else
267 gpreg0 = GPREG0_DEFAULT;
268 jwrite32(jme, JME_GPREG0, gpreg0);
269}
270
271static inline void
272jme_clear_pm(struct jme_adapter *jme)
273{
274 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
275 pci_set_power_state(jme->pdev, PCI_D0);
276 pci_enable_wake(jme->pdev, PCI_D0, false);
277}
278
279static int
280jme_reload_eeprom(struct jme_adapter *jme)
281{
282 u32 val;
283 int i;
284
285 val = jread32(jme, JME_SMBCSR);
286
287 if (val & SMBCSR_EEPROMD) {
288 val |= SMBCSR_CNACK;
289 jwrite32(jme, JME_SMBCSR, val);
290 val |= SMBCSR_RELOAD;
291 jwrite32(jme, JME_SMBCSR, val);
292 mdelay(12);
293
294 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
295 mdelay(1);
296 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
297 break;
298 }
299
300 if (i == 0) {
301 pr_err("eeprom reload timeout\n");
302 return -EIO;
303 }
304 }
305
306 return 0;
307}
308
309static void
310jme_load_macaddr(struct net_device *netdev)
311{
312 struct jme_adapter *jme = netdev_priv(netdev);
313 unsigned char macaddr[6];
314 u32 val;
315
316 spin_lock_bh(&jme->macaddr_lock);
317 val = jread32(jme, JME_RXUMA_LO);
318 macaddr[0] = (val >> 0) & 0xFF;
319 macaddr[1] = (val >> 8) & 0xFF;
320 macaddr[2] = (val >> 16) & 0xFF;
321 macaddr[3] = (val >> 24) & 0xFF;
322 val = jread32(jme, JME_RXUMA_HI);
323 macaddr[4] = (val >> 0) & 0xFF;
324 macaddr[5] = (val >> 8) & 0xFF;
325 memcpy(netdev->dev_addr, macaddr, 6);
326 spin_unlock_bh(&jme->macaddr_lock);
327}
328
329static inline void
330jme_set_rx_pcc(struct jme_adapter *jme, int p)
331{
332 switch (p) {
333 case PCC_OFF:
334 jwrite32(jme, JME_PCCRX0,
335 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
336 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
337 break;
338 case PCC_P1:
339 jwrite32(jme, JME_PCCRX0,
340 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
341 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
342 break;
343 case PCC_P2:
344 jwrite32(jme, JME_PCCRX0,
345 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
346 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
347 break;
348 case PCC_P3:
349 jwrite32(jme, JME_PCCRX0,
350 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
351 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
352 break;
353 default:
354 break;
355 }
356 wmb();
357
358 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
359 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
360}
361
362static void
363jme_start_irq(struct jme_adapter *jme)
364{
365 register struct dynpcc_info *dpi = &(jme->dpi);
366
367 jme_set_rx_pcc(jme, PCC_P1);
368 dpi->cur = PCC_P1;
369 dpi->attempt = PCC_P1;
370 dpi->cnt = 0;
371
372 jwrite32(jme, JME_PCCTX,
373 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
374 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
375 PCCTXQ0_EN
376 );
377
378 /*
379 * Enable Interrupts
380 */
381 jwrite32(jme, JME_IENS, INTR_ENABLE);
382}
383
384static inline void
385jme_stop_irq(struct jme_adapter *jme)
386{
387 /*
388 * Disable Interrupts
389 */
390 jwrite32f(jme, JME_IENC, INTR_ENABLE);
391}
392
393static u32
394jme_linkstat_from_phy(struct jme_adapter *jme)
395{
396 u32 phylink, bmsr;
397
398 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
399 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
400 if (bmsr & BMSR_ANCOMP)
401 phylink |= PHY_LINK_AUTONEG_COMPLETE;
402
403 return phylink;
404}
405
406static inline void
407jme_set_phyfifo_5level(struct jme_adapter *jme)
408{
409 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
410}
411
412static inline void
413jme_set_phyfifo_8level(struct jme_adapter *jme)
414{
415 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
416}
417
418static int
419jme_check_link(struct net_device *netdev, int testonly)
420{
421 struct jme_adapter *jme = netdev_priv(netdev);
422 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
423 char linkmsg[64];
424 int rc = 0;
425
426 linkmsg[0] = '\0';
427
428 if (jme->fpgaver)
429 phylink = jme_linkstat_from_phy(jme);
430 else
431 phylink = jread32(jme, JME_PHY_LINK);
432
433 if (phylink & PHY_LINK_UP) {
434 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
435 /*
436 * If we did not enable AN
437 * Speed/Duplex Info should be obtained from SMI
438 */
439 phylink = PHY_LINK_UP;
440
441 bmcr = jme_mdio_read(jme->dev,
442 jme->mii_if.phy_id,
443 MII_BMCR);
444
445 phylink |= ((bmcr & BMCR_SPEED1000) &&
446 (bmcr & BMCR_SPEED100) == 0) ?
447 PHY_LINK_SPEED_1000M :
448 (bmcr & BMCR_SPEED100) ?
449 PHY_LINK_SPEED_100M :
450 PHY_LINK_SPEED_10M;
451
452 phylink |= (bmcr & BMCR_FULLDPLX) ?
453 PHY_LINK_DUPLEX : 0;
454
455 strcat(linkmsg, "Forced: ");
456 } else {
457 /*
458 * Keep polling for speed/duplex resolve complete
459 */
460 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
461 --cnt) {
462
463 udelay(1);
464
465 if (jme->fpgaver)
466 phylink = jme_linkstat_from_phy(jme);
467 else
468 phylink = jread32(jme, JME_PHY_LINK);
469 }
470 if (!cnt)
471 pr_err("Waiting speed resolve timeout\n");
472
473 strcat(linkmsg, "ANed: ");
474 }
475
476 if (jme->phylink == phylink) {
477 rc = 1;
478 goto out;
479 }
480 if (testonly)
481 goto out;
482
483 jme->phylink = phylink;
484
485 /*
486 * The speed/duplex setting of jme->reg_ghc already cleared
487 * by jme_reset_mac_processor()
488 */
489 switch (phylink & PHY_LINK_SPEED_MASK) {
490 case PHY_LINK_SPEED_10M:
491 jme->reg_ghc |= GHC_SPEED_10M;
492 strcat(linkmsg, "10 Mbps, ");
493 break;
494 case PHY_LINK_SPEED_100M:
495 jme->reg_ghc |= GHC_SPEED_100M;
496 strcat(linkmsg, "100 Mbps, ");
497 break;
498 case PHY_LINK_SPEED_1000M:
499 jme->reg_ghc |= GHC_SPEED_1000M;
500 strcat(linkmsg, "1000 Mbps, ");
501 break;
502 default:
503 break;
504 }
505
506 if (phylink & PHY_LINK_DUPLEX) {
507 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
508 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
509 jme->reg_ghc |= GHC_DPX;
510 } else {
511 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
512 TXMCS_BACKOFF |
513 TXMCS_CARRIERSENSE |
514 TXMCS_COLLISION);
515 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
516 }
517
518 jwrite32(jme, JME_GHC, jme->reg_ghc);
519
520 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
521 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
522 GPREG1_RSSPATCH);
523 if (!(phylink & PHY_LINK_DUPLEX))
524 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
525 switch (phylink & PHY_LINK_SPEED_MASK) {
526 case PHY_LINK_SPEED_10M:
527 jme_set_phyfifo_8level(jme);
528 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
529 break;
530 case PHY_LINK_SPEED_100M:
531 jme_set_phyfifo_5level(jme);
532 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
533 break;
534 case PHY_LINK_SPEED_1000M:
535 jme_set_phyfifo_8level(jme);
536 break;
537 default:
538 break;
539 }
540 }
541 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
542
543 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
544 "Full-Duplex, " :
545 "Half-Duplex, ");
546 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
547 "MDI-X" :
548 "MDI");
549 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
550 netif_carrier_on(netdev);
551 } else {
552 if (testonly)
553 goto out;
554
555 netif_info(jme, link, jme->dev, "Link is down\n");
556 jme->phylink = 0;
557 netif_carrier_off(netdev);
558 }
559
560out:
561 return rc;
562}
563
564static int
565jme_setup_tx_resources(struct jme_adapter *jme)
566{
567 struct jme_ring *txring = &(jme->txring[0]);
568
569 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
570 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
571 &(txring->dmaalloc),
572 GFP_ATOMIC);
573
574 if (!txring->alloc)
575 goto err_set_null;
576
577 /*
578 * 16 Bytes align
579 */
580 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
581 RING_DESC_ALIGN);
582 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
583 txring->next_to_use = 0;
584 atomic_set(&txring->next_to_clean, 0);
585 atomic_set(&txring->nr_free, jme->tx_ring_size);
586
587 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
588 jme->tx_ring_size, GFP_ATOMIC);
589 if (unlikely(!(txring->bufinf)))
590 goto err_free_txring;
591
592 /*
593 * Initialize Transmit Descriptors
594 */
595 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
596 memset(txring->bufinf, 0,
597 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
598
599 return 0;
600
601err_free_txring:
602 dma_free_coherent(&(jme->pdev->dev),
603 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
604 txring->alloc,
605 txring->dmaalloc);
606
607err_set_null:
608 txring->desc = NULL;
609 txring->dmaalloc = 0;
610 txring->dma = 0;
611 txring->bufinf = NULL;
612
613 return -ENOMEM;
614}
615
616static void
617jme_free_tx_resources(struct jme_adapter *jme)
618{
619 int i;
620 struct jme_ring *txring = &(jme->txring[0]);
621 struct jme_buffer_info *txbi;
622
623 if (txring->alloc) {
624 if (txring->bufinf) {
625 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
626 txbi = txring->bufinf + i;
627 if (txbi->skb) {
628 dev_kfree_skb(txbi->skb);
629 txbi->skb = NULL;
630 }
631 txbi->mapping = 0;
632 txbi->len = 0;
633 txbi->nr_desc = 0;
634 txbi->start_xmit = 0;
635 }
636 kfree(txring->bufinf);
637 }
638
639 dma_free_coherent(&(jme->pdev->dev),
640 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
641 txring->alloc,
642 txring->dmaalloc);
643
644 txring->alloc = NULL;
645 txring->desc = NULL;
646 txring->dmaalloc = 0;
647 txring->dma = 0;
648 txring->bufinf = NULL;
649 }
650 txring->next_to_use = 0;
651 atomic_set(&txring->next_to_clean, 0);
652 atomic_set(&txring->nr_free, 0);
653}
654
655static inline void
656jme_enable_tx_engine(struct jme_adapter *jme)
657{
658 /*
659 * Select Queue 0
660 */
661 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
662 wmb();
663
664 /*
665 * Setup TX Queue 0 DMA Bass Address
666 */
667 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
668 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
669 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
670
671 /*
672 * Setup TX Descptor Count
673 */
674 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
675
676 /*
677 * Enable TX Engine
678 */
679 wmb();
680 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
681 TXCS_SELECT_QUEUE0 |
682 TXCS_ENABLE);
683
684 /*
685 * Start clock for TX MAC Processor
686 */
687 jme_mac_txclk_on(jme);
688}
689
690static inline void
691jme_restart_tx_engine(struct jme_adapter *jme)
692{
693 /*
694 * Restart TX Engine
695 */
696 jwrite32(jme, JME_TXCS, jme->reg_txcs |
697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
699}
700
701static inline void
702jme_disable_tx_engine(struct jme_adapter *jme)
703{
704 int i;
705 u32 val;
706
707 /*
708 * Disable TX Engine
709 */
710 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
711 wmb();
712
713 val = jread32(jme, JME_TXCS);
714 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
715 mdelay(1);
716 val = jread32(jme, JME_TXCS);
717 rmb();
718 }
719
720 if (!i)
721 pr_err("Disable TX engine timeout\n");
722
723 /*
724 * Stop clock for TX MAC Processor
725 */
726 jme_mac_txclk_off(jme);
727}
728
729static void
730jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
731{
732 struct jme_ring *rxring = &(jme->rxring[0]);
733 register struct rxdesc *rxdesc = rxring->desc;
734 struct jme_buffer_info *rxbi = rxring->bufinf;
735 rxdesc += i;
736 rxbi += i;
737
738 rxdesc->dw[0] = 0;
739 rxdesc->dw[1] = 0;
740 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
741 rxdesc->desc1.bufaddrl = cpu_to_le32(
742 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
743 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
744 if (jme->dev->features & NETIF_F_HIGHDMA)
745 rxdesc->desc1.flags = RXFLAG_64BIT;
746 wmb();
747 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
748}
749
750static int
751jme_make_new_rx_buf(struct jme_adapter *jme, int i)
752{
753 struct jme_ring *rxring = &(jme->rxring[0]);
754 struct jme_buffer_info *rxbi = rxring->bufinf + i;
755 struct sk_buff *skb;
756
757 skb = netdev_alloc_skb(jme->dev,
758 jme->dev->mtu + RX_EXTRA_LEN);
759 if (unlikely(!skb))
760 return -ENOMEM;
761
762 rxbi->skb = skb;
763 rxbi->len = skb_tailroom(skb);
764 rxbi->mapping = pci_map_page(jme->pdev,
765 virt_to_page(skb->data),
766 offset_in_page(skb->data),
767 rxbi->len,
768 PCI_DMA_FROMDEVICE);
769
770 return 0;
771}
772
773static void
774jme_free_rx_buf(struct jme_adapter *jme, int i)
775{
776 struct jme_ring *rxring = &(jme->rxring[0]);
777 struct jme_buffer_info *rxbi = rxring->bufinf;
778 rxbi += i;
779
780 if (rxbi->skb) {
781 pci_unmap_page(jme->pdev,
782 rxbi->mapping,
783 rxbi->len,
784 PCI_DMA_FROMDEVICE);
785 dev_kfree_skb(rxbi->skb);
786 rxbi->skb = NULL;
787 rxbi->mapping = 0;
788 rxbi->len = 0;
789 }
790}
791
792static void
793jme_free_rx_resources(struct jme_adapter *jme)
794{
795 int i;
796 struct jme_ring *rxring = &(jme->rxring[0]);
797
798 if (rxring->alloc) {
799 if (rxring->bufinf) {
800 for (i = 0 ; i < jme->rx_ring_size ; ++i)
801 jme_free_rx_buf(jme, i);
802 kfree(rxring->bufinf);
803 }
804
805 dma_free_coherent(&(jme->pdev->dev),
806 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
807 rxring->alloc,
808 rxring->dmaalloc);
809 rxring->alloc = NULL;
810 rxring->desc = NULL;
811 rxring->dmaalloc = 0;
812 rxring->dma = 0;
813 rxring->bufinf = NULL;
814 }
815 rxring->next_to_use = 0;
816 atomic_set(&rxring->next_to_clean, 0);
817}
818
819static int
820jme_setup_rx_resources(struct jme_adapter *jme)
821{
822 int i;
823 struct jme_ring *rxring = &(jme->rxring[0]);
824
825 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
826 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
827 &(rxring->dmaalloc),
828 GFP_ATOMIC);
829 if (!rxring->alloc)
830 goto err_set_null;
831
832 /*
833 * 16 Bytes align
834 */
835 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
836 RING_DESC_ALIGN);
837 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
838 rxring->next_to_use = 0;
839 atomic_set(&rxring->next_to_clean, 0);
840
841 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
842 jme->rx_ring_size, GFP_ATOMIC);
843 if (unlikely(!(rxring->bufinf)))
844 goto err_free_rxring;
845
846 /*
847 * Initiallize Receive Descriptors
848 */
849 memset(rxring->bufinf, 0,
850 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
851 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
852 if (unlikely(jme_make_new_rx_buf(jme, i))) {
853 jme_free_rx_resources(jme);
854 return -ENOMEM;
855 }
856
857 jme_set_clean_rxdesc(jme, i);
858 }
859
860 return 0;
861
862err_free_rxring:
863 dma_free_coherent(&(jme->pdev->dev),
864 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
865 rxring->alloc,
866 rxring->dmaalloc);
867err_set_null:
868 rxring->desc = NULL;
869 rxring->dmaalloc = 0;
870 rxring->dma = 0;
871 rxring->bufinf = NULL;
872
873 return -ENOMEM;
874}
875
876static inline void
877jme_enable_rx_engine(struct jme_adapter *jme)
878{
879 /*
880 * Select Queue 0
881 */
882 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
883 RXCS_QUEUESEL_Q0);
884 wmb();
885
886 /*
887 * Setup RX DMA Bass Address
888 */
889 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
890 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
891 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
892
893 /*
894 * Setup RX Descriptor Count
895 */
896 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
897
898 /*
899 * Setup Unicast Filter
900 */
901 jme_set_unicastaddr(jme->dev);
902 jme_set_multi(jme->dev);
903
904 /*
905 * Enable RX Engine
906 */
907 wmb();
908 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
909 RXCS_QUEUESEL_Q0 |
910 RXCS_ENABLE |
911 RXCS_QST);
912
913 /*
914 * Start clock for RX MAC Processor
915 */
916 jme_mac_rxclk_on(jme);
917}
918
919static inline void
920jme_restart_rx_engine(struct jme_adapter *jme)
921{
922 /*
923 * Start RX Engine
924 */
925 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
926 RXCS_QUEUESEL_Q0 |
927 RXCS_ENABLE |
928 RXCS_QST);
929}
930
931static inline void
932jme_disable_rx_engine(struct jme_adapter *jme)
933{
934 int i;
935 u32 val;
936
937 /*
938 * Disable RX Engine
939 */
940 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
941 wmb();
942
943 val = jread32(jme, JME_RXCS);
944 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
945 mdelay(1);
946 val = jread32(jme, JME_RXCS);
947 rmb();
948 }
949
950 if (!i)
951 pr_err("Disable RX engine timeout\n");
952
953 /*
954 * Stop clock for RX MAC Processor
955 */
956 jme_mac_rxclk_off(jme);
957}
958
959static u16
960jme_udpsum(struct sk_buff *skb)
961{
962 u16 csum = 0xFFFFu;
963
964 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
965 return csum;
966 if (skb->protocol != htons(ETH_P_IP))
967 return csum;
968 skb_set_network_header(skb, ETH_HLEN);
969 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
970 (skb->len < (ETH_HLEN +
971 (ip_hdr(skb)->ihl << 2) +
972 sizeof(struct udphdr)))) {
973 skb_reset_network_header(skb);
974 return csum;
975 }
976 skb_set_transport_header(skb,
977 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
978 csum = udp_hdr(skb)->check;
979 skb_reset_transport_header(skb);
980 skb_reset_network_header(skb);
981
982 return csum;
983}
984
985static int
986jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
987{
988 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
989 return false;
990
991 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
992 == RXWBFLAG_TCPON)) {
993 if (flags & RXWBFLAG_IPV4)
994 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
995 return false;
996 }
997
998 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
999 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1000 if (flags & RXWBFLAG_IPV4)
1001 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1002 return false;
1003 }
1004
1005 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1006 == RXWBFLAG_IPV4)) {
1007 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1008 return false;
1009 }
1010
1011 return true;
1012}
1013
1014static void
1015jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1016{
1017 struct jme_ring *rxring = &(jme->rxring[0]);
1018 struct rxdesc *rxdesc = rxring->desc;
1019 struct jme_buffer_info *rxbi = rxring->bufinf;
1020 struct sk_buff *skb;
1021 int framesize;
1022
1023 rxdesc += idx;
1024 rxbi += idx;
1025
1026 skb = rxbi->skb;
1027 pci_dma_sync_single_for_cpu(jme->pdev,
1028 rxbi->mapping,
1029 rxbi->len,
1030 PCI_DMA_FROMDEVICE);
1031
1032 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1033 pci_dma_sync_single_for_device(jme->pdev,
1034 rxbi->mapping,
1035 rxbi->len,
1036 PCI_DMA_FROMDEVICE);
1037
1038 ++(NET_STAT(jme).rx_dropped);
1039 } else {
1040 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1041 - RX_PREPAD_SIZE;
1042
1043 skb_reserve(skb, RX_PREPAD_SIZE);
1044 skb_put(skb, framesize);
1045 skb->protocol = eth_type_trans(skb, jme->dev);
1046
1047 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1048 skb->ip_summed = CHECKSUM_UNNECESSARY;
1049 else
1050 skb_checksum_none_assert(skb);
1051
1052 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1053 if (jme->vlgrp) {
1054 jme->jme_vlan_rx(skb, jme->vlgrp,
1055 le16_to_cpu(rxdesc->descwb.vlan));
1056 NET_STAT(jme).rx_bytes += 4;
1057 } else {
1058 dev_kfree_skb(skb);
1059 }
1060 } else {
1061 jme->jme_rx(skb);
1062 }
1063
1064 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1065 cpu_to_le16(RXWBFLAG_DEST_MUL))
1066 ++(NET_STAT(jme).multicast);
1067
1068 NET_STAT(jme).rx_bytes += framesize;
1069 ++(NET_STAT(jme).rx_packets);
1070 }
1071
1072 jme_set_clean_rxdesc(jme, idx);
1073
1074}
1075
1076static int
1077jme_process_receive(struct jme_adapter *jme, int limit)
1078{
1079 struct jme_ring *rxring = &(jme->rxring[0]);
1080 struct rxdesc *rxdesc = rxring->desc;
1081 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1082
1083 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1084 goto out_inc;
1085
1086 if (unlikely(atomic_read(&jme->link_changing) != 1))
1087 goto out_inc;
1088
1089 if (unlikely(!netif_carrier_ok(jme->dev)))
1090 goto out_inc;
1091
1092 i = atomic_read(&rxring->next_to_clean);
1093 while (limit > 0) {
1094 rxdesc = rxring->desc;
1095 rxdesc += i;
1096
1097 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1098 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1099 goto out;
1100 --limit;
1101
1102 rmb();
1103 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1104
1105 if (unlikely(desccnt > 1 ||
1106 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1107
1108 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1109 ++(NET_STAT(jme).rx_crc_errors);
1110 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1111 ++(NET_STAT(jme).rx_fifo_errors);
1112 else
1113 ++(NET_STAT(jme).rx_errors);
1114
1115 if (desccnt > 1)
1116 limit -= desccnt - 1;
1117
1118 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1119 jme_set_clean_rxdesc(jme, j);
1120 j = (j + 1) & (mask);
1121 }
1122
1123 } else {
1124 jme_alloc_and_feed_skb(jme, i);
1125 }
1126
1127 i = (i + desccnt) & (mask);
1128 }
1129
1130out:
1131 atomic_set(&rxring->next_to_clean, i);
1132
1133out_inc:
1134 atomic_inc(&jme->rx_cleaning);
1135
1136 return limit > 0 ? limit : 0;
1137
1138}
1139
1140static void
1141jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1142{
1143 if (likely(atmp == dpi->cur)) {
1144 dpi->cnt = 0;
1145 return;
1146 }
1147
1148 if (dpi->attempt == atmp) {
1149 ++(dpi->cnt);
1150 } else {
1151 dpi->attempt = atmp;
1152 dpi->cnt = 0;
1153 }
1154
1155}
1156
1157static void
1158jme_dynamic_pcc(struct jme_adapter *jme)
1159{
1160 register struct dynpcc_info *dpi = &(jme->dpi);
1161
1162 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1163 jme_attempt_pcc(dpi, PCC_P3);
1164 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1165 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1166 jme_attempt_pcc(dpi, PCC_P2);
1167 else
1168 jme_attempt_pcc(dpi, PCC_P1);
1169
1170 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1171 if (dpi->attempt < dpi->cur)
1172 tasklet_schedule(&jme->rxclean_task);
1173 jme_set_rx_pcc(jme, dpi->attempt);
1174 dpi->cur = dpi->attempt;
1175 dpi->cnt = 0;
1176 }
1177}
1178
1179static void
1180jme_start_pcc_timer(struct jme_adapter *jme)
1181{
1182 struct dynpcc_info *dpi = &(jme->dpi);
1183 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1184 dpi->last_pkts = NET_STAT(jme).rx_packets;
1185 dpi->intr_cnt = 0;
1186 jwrite32(jme, JME_TMCSR,
1187 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1188}
1189
1190static inline void
1191jme_stop_pcc_timer(struct jme_adapter *jme)
1192{
1193 jwrite32(jme, JME_TMCSR, 0);
1194}
1195
1196static void
1197jme_shutdown_nic(struct jme_adapter *jme)
1198{
1199 u32 phylink;
1200
1201 phylink = jme_linkstat_from_phy(jme);
1202
1203 if (!(phylink & PHY_LINK_UP)) {
1204 /*
1205 * Disable all interrupt before issue timer
1206 */
1207 jme_stop_irq(jme);
1208 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1209 }
1210}
1211
1212static void
1213jme_pcc_tasklet(unsigned long arg)
1214{
1215 struct jme_adapter *jme = (struct jme_adapter *)arg;
1216 struct net_device *netdev = jme->dev;
1217
1218 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1219 jme_shutdown_nic(jme);
1220 return;
1221 }
1222
1223 if (unlikely(!netif_carrier_ok(netdev) ||
1224 (atomic_read(&jme->link_changing) != 1)
1225 )) {
1226 jme_stop_pcc_timer(jme);
1227 return;
1228 }
1229
1230 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1231 jme_dynamic_pcc(jme);
1232
1233 jme_start_pcc_timer(jme);
1234}
1235
1236static inline void
1237jme_polling_mode(struct jme_adapter *jme)
1238{
1239 jme_set_rx_pcc(jme, PCC_OFF);
1240}
1241
1242static inline void
1243jme_interrupt_mode(struct jme_adapter *jme)
1244{
1245 jme_set_rx_pcc(jme, PCC_P1);
1246}
1247
1248static inline int
1249jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1250{
1251 u32 apmc;
1252 apmc = jread32(jme, JME_APMC);
1253 return apmc & JME_APMC_PSEUDO_HP_EN;
1254}
1255
1256static void
1257jme_start_shutdown_timer(struct jme_adapter *jme)
1258{
1259 u32 apmc;
1260
1261 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1262 apmc &= ~JME_APMC_EPIEN_CTRL;
1263 if (!no_extplug) {
1264 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1265 wmb();
1266 }
1267 jwrite32f(jme, JME_APMC, apmc);
1268
1269 jwrite32f(jme, JME_TIMER2, 0);
1270 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1271 jwrite32(jme, JME_TMCSR,
1272 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1273}
1274
1275static void
1276jme_stop_shutdown_timer(struct jme_adapter *jme)
1277{
1278 u32 apmc;
1279
1280 jwrite32f(jme, JME_TMCSR, 0);
1281 jwrite32f(jme, JME_TIMER2, 0);
1282 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1283
1284 apmc = jread32(jme, JME_APMC);
1285 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1286 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1287 wmb();
1288 jwrite32f(jme, JME_APMC, apmc);
1289}
1290
1291static void
1292jme_link_change_tasklet(unsigned long arg)
1293{
1294 struct jme_adapter *jme = (struct jme_adapter *)arg;
1295 struct net_device *netdev = jme->dev;
1296 int rc;
1297
1298 while (!atomic_dec_and_test(&jme->link_changing)) {
1299 atomic_inc(&jme->link_changing);
1300 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1301 while (atomic_read(&jme->link_changing) != 1)
1302 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1303 }
1304
1305 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1306 goto out;
1307
1308 jme->old_mtu = netdev->mtu;
1309 netif_stop_queue(netdev);
1310 if (jme_pseudo_hotplug_enabled(jme))
1311 jme_stop_shutdown_timer(jme);
1312
1313 jme_stop_pcc_timer(jme);
1314 tasklet_disable(&jme->txclean_task);
1315 tasklet_disable(&jme->rxclean_task);
1316 tasklet_disable(&jme->rxempty_task);
1317
1318 if (netif_carrier_ok(netdev)) {
1319 jme_disable_rx_engine(jme);
1320 jme_disable_tx_engine(jme);
1321 jme_reset_mac_processor(jme);
1322 jme_free_rx_resources(jme);
1323 jme_free_tx_resources(jme);
1324
1325 if (test_bit(JME_FLAG_POLL, &jme->flags))
1326 jme_polling_mode(jme);
1327
1328 netif_carrier_off(netdev);
1329 }
1330
1331 jme_check_link(netdev, 0);
1332 if (netif_carrier_ok(netdev)) {
1333 rc = jme_setup_rx_resources(jme);
1334 if (rc) {
1335 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1336 goto out_enable_tasklet;
1337 }
1338
1339 rc = jme_setup_tx_resources(jme);
1340 if (rc) {
1341 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1342 goto err_out_free_rx_resources;
1343 }
1344
1345 jme_enable_rx_engine(jme);
1346 jme_enable_tx_engine(jme);
1347
1348 netif_start_queue(netdev);
1349
1350 if (test_bit(JME_FLAG_POLL, &jme->flags))
1351 jme_interrupt_mode(jme);
1352
1353 jme_start_pcc_timer(jme);
1354 } else if (jme_pseudo_hotplug_enabled(jme)) {
1355 jme_start_shutdown_timer(jme);
1356 }
1357
1358 goto out_enable_tasklet;
1359
1360err_out_free_rx_resources:
1361 jme_free_rx_resources(jme);
1362out_enable_tasklet:
1363 tasklet_enable(&jme->txclean_task);
1364 tasklet_hi_enable(&jme->rxclean_task);
1365 tasklet_hi_enable(&jme->rxempty_task);
1366out:
1367 atomic_inc(&jme->link_changing);
1368}
1369
1370static void
1371jme_rx_clean_tasklet(unsigned long arg)
1372{
1373 struct jme_adapter *jme = (struct jme_adapter *)arg;
1374 struct dynpcc_info *dpi = &(jme->dpi);
1375
1376 jme_process_receive(jme, jme->rx_ring_size);
1377 ++(dpi->intr_cnt);
1378
1379}
1380
1381static int
1382jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1383{
1384 struct jme_adapter *jme = jme_napi_priv(holder);
1385 int rest;
1386
1387 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1388
1389 while (atomic_read(&jme->rx_empty) > 0) {
1390 atomic_dec(&jme->rx_empty);
1391 ++(NET_STAT(jme).rx_dropped);
1392 jme_restart_rx_engine(jme);
1393 }
1394 atomic_inc(&jme->rx_empty);
1395
1396 if (rest) {
1397 JME_RX_COMPLETE(netdev, holder);
1398 jme_interrupt_mode(jme);
1399 }
1400
1401 JME_NAPI_WEIGHT_SET(budget, rest);
1402 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1403}
1404
1405static void
1406jme_rx_empty_tasklet(unsigned long arg)
1407{
1408 struct jme_adapter *jme = (struct jme_adapter *)arg;
1409
1410 if (unlikely(atomic_read(&jme->link_changing) != 1))
1411 return;
1412
1413 if (unlikely(!netif_carrier_ok(jme->dev)))
1414 return;
1415
1416 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1417
1418 jme_rx_clean_tasklet(arg);
1419
1420 while (atomic_read(&jme->rx_empty) > 0) {
1421 atomic_dec(&jme->rx_empty);
1422 ++(NET_STAT(jme).rx_dropped);
1423 jme_restart_rx_engine(jme);
1424 }
1425 atomic_inc(&jme->rx_empty);
1426}
1427
1428static void
1429jme_wake_queue_if_stopped(struct jme_adapter *jme)
1430{
1431 struct jme_ring *txring = &(jme->txring[0]);
1432
1433 smp_wmb();
1434 if (unlikely(netif_queue_stopped(jme->dev) &&
1435 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1436 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1437 netif_wake_queue(jme->dev);
1438 }
1439
1440}
1441
1442static void
1443jme_tx_clean_tasklet(unsigned long arg)
1444{
1445 struct jme_adapter *jme = (struct jme_adapter *)arg;
1446 struct jme_ring *txring = &(jme->txring[0]);
1447 struct txdesc *txdesc = txring->desc;
1448 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1449 int i, j, cnt = 0, max, err, mask;
1450
1451 tx_dbg(jme, "Into txclean\n");
1452
1453 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1454 goto out;
1455
1456 if (unlikely(atomic_read(&jme->link_changing) != 1))
1457 goto out;
1458
1459 if (unlikely(!netif_carrier_ok(jme->dev)))
1460 goto out;
1461
1462 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1463 mask = jme->tx_ring_mask;
1464
1465 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1466
1467 ctxbi = txbi + i;
1468
1469 if (likely(ctxbi->skb &&
1470 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1471
1472 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1473 i, ctxbi->nr_desc, jiffies);
1474
1475 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1476
1477 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1478 ttxbi = txbi + ((i + j) & (mask));
1479 txdesc[(i + j) & (mask)].dw[0] = 0;
1480
1481 pci_unmap_page(jme->pdev,
1482 ttxbi->mapping,
1483 ttxbi->len,
1484 PCI_DMA_TODEVICE);
1485
1486 ttxbi->mapping = 0;
1487 ttxbi->len = 0;
1488 }
1489
1490 dev_kfree_skb(ctxbi->skb);
1491
1492 cnt += ctxbi->nr_desc;
1493
1494 if (unlikely(err)) {
1495 ++(NET_STAT(jme).tx_carrier_errors);
1496 } else {
1497 ++(NET_STAT(jme).tx_packets);
1498 NET_STAT(jme).tx_bytes += ctxbi->len;
1499 }
1500
1501 ctxbi->skb = NULL;
1502 ctxbi->len = 0;
1503 ctxbi->start_xmit = 0;
1504
1505 } else {
1506 break;
1507 }
1508
1509 i = (i + ctxbi->nr_desc) & mask;
1510
1511 ctxbi->nr_desc = 0;
1512 }
1513
1514 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1515 atomic_set(&txring->next_to_clean, i);
1516 atomic_add(cnt, &txring->nr_free);
1517
1518 jme_wake_queue_if_stopped(jme);
1519
1520out:
1521 atomic_inc(&jme->tx_cleaning);
1522}
1523
1524static void
1525jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1526{
1527 /*
1528 * Disable interrupt
1529 */
1530 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1531
1532 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1533 /*
1534 * Link change event is critical
1535 * all other events are ignored
1536 */
1537 jwrite32(jme, JME_IEVE, intrstat);
1538 tasklet_schedule(&jme->linkch_task);
1539 goto out_reenable;
1540 }
1541
1542 if (intrstat & INTR_TMINTR) {
1543 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1544 tasklet_schedule(&jme->pcc_task);
1545 }
1546
1547 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1548 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1549 tasklet_schedule(&jme->txclean_task);
1550 }
1551
1552 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1553 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1554 INTR_PCCRX0 |
1555 INTR_RX0EMP)) |
1556 INTR_RX0);
1557 }
1558
1559 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1560 if (intrstat & INTR_RX0EMP)
1561 atomic_inc(&jme->rx_empty);
1562
1563 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1564 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1565 jme_polling_mode(jme);
1566 JME_RX_SCHEDULE(jme);
1567 }
1568 }
1569 } else {
1570 if (intrstat & INTR_RX0EMP) {
1571 atomic_inc(&jme->rx_empty);
1572 tasklet_hi_schedule(&jme->rxempty_task);
1573 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1574 tasklet_hi_schedule(&jme->rxclean_task);
1575 }
1576 }
1577
1578out_reenable:
1579 /*
1580 * Re-enable interrupt
1581 */
1582 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1583}
1584
1585static irqreturn_t
1586jme_intr(int irq, void *dev_id)
1587{
1588 struct net_device *netdev = dev_id;
1589 struct jme_adapter *jme = netdev_priv(netdev);
1590 u32 intrstat;
1591
1592 intrstat = jread32(jme, JME_IEVE);
1593
1594 /*
1595 * Check if it's really an interrupt for us
1596 */
1597 if (unlikely((intrstat & INTR_ENABLE) == 0))
1598 return IRQ_NONE;
1599
1600 /*
1601 * Check if the device still exist
1602 */
1603 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1604 return IRQ_NONE;
1605
1606 jme_intr_msi(jme, intrstat);
1607
1608 return IRQ_HANDLED;
1609}
1610
1611static irqreturn_t
1612jme_msi(int irq, void *dev_id)
1613{
1614 struct net_device *netdev = dev_id;
1615 struct jme_adapter *jme = netdev_priv(netdev);
1616 u32 intrstat;
1617
1618 intrstat = jread32(jme, JME_IEVE);
1619
1620 jme_intr_msi(jme, intrstat);
1621
1622 return IRQ_HANDLED;
1623}
1624
1625static void
1626jme_reset_link(struct jme_adapter *jme)
1627{
1628 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1629}
1630
1631static void
1632jme_restart_an(struct jme_adapter *jme)
1633{
1634 u32 bmcr;
1635
1636 spin_lock_bh(&jme->phy_lock);
1637 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1638 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1639 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1640 spin_unlock_bh(&jme->phy_lock);
1641}
1642
1643static int
1644jme_request_irq(struct jme_adapter *jme)
1645{
1646 int rc;
1647 struct net_device *netdev = jme->dev;
1648 irq_handler_t handler = jme_intr;
1649 int irq_flags = IRQF_SHARED;
1650
1651 if (!pci_enable_msi(jme->pdev)) {
1652 set_bit(JME_FLAG_MSI, &jme->flags);
1653 handler = jme_msi;
1654 irq_flags = 0;
1655 }
1656
1657 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1658 netdev);
1659 if (rc) {
1660 netdev_err(netdev,
1661 "Unable to request %s interrupt (return: %d)\n",
1662 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1663 rc);
1664
1665 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1666 pci_disable_msi(jme->pdev);
1667 clear_bit(JME_FLAG_MSI, &jme->flags);
1668 }
1669 } else {
1670 netdev->irq = jme->pdev->irq;
1671 }
1672
1673 return rc;
1674}
1675
1676static void
1677jme_free_irq(struct jme_adapter *jme)
1678{
1679 free_irq(jme->pdev->irq, jme->dev);
1680 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1681 pci_disable_msi(jme->pdev);
1682 clear_bit(JME_FLAG_MSI, &jme->flags);
1683 jme->dev->irq = jme->pdev->irq;
1684 }
1685}
1686
1687static inline void
1688jme_new_phy_on(struct jme_adapter *jme)
1689{
1690 u32 reg;
1691
1692 reg = jread32(jme, JME_PHY_PWR);
1693 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1694 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1695 jwrite32(jme, JME_PHY_PWR, reg);
1696
1697 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1698 reg &= ~PE1_GPREG0_PBG;
1699 reg |= PE1_GPREG0_ENBG;
1700 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1701}
1702
1703static inline void
1704jme_new_phy_off(struct jme_adapter *jme)
1705{
1706 u32 reg;
1707
1708 reg = jread32(jme, JME_PHY_PWR);
1709 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1710 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1711 jwrite32(jme, JME_PHY_PWR, reg);
1712
1713 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1714 reg &= ~PE1_GPREG0_PBG;
1715 reg |= PE1_GPREG0_PDD3COLD;
1716 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1717}
1718
1719static inline void
1720jme_phy_on(struct jme_adapter *jme)
1721{
1722 u32 bmcr;
1723
1724 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1725 bmcr &= ~BMCR_PDOWN;
1726 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1727
1728 if (new_phy_power_ctrl(jme->chip_main_rev))
1729 jme_new_phy_on(jme);
1730}
1731
1732static inline void
1733jme_phy_off(struct jme_adapter *jme)
1734{
1735 u32 bmcr;
1736
1737 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1738 bmcr |= BMCR_PDOWN;
1739 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1740
1741 if (new_phy_power_ctrl(jme->chip_main_rev))
1742 jme_new_phy_off(jme);
1743}
1744
1745static int
1746jme_open(struct net_device *netdev)
1747{
1748 struct jme_adapter *jme = netdev_priv(netdev);
1749 int rc;
1750
1751 jme_clear_pm(jme);
1752 JME_NAPI_ENABLE(jme);
1753
1754 tasklet_enable(&jme->linkch_task);
1755 tasklet_enable(&jme->txclean_task);
1756 tasklet_hi_enable(&jme->rxclean_task);
1757 tasklet_hi_enable(&jme->rxempty_task);
1758
1759 rc = jme_request_irq(jme);
1760 if (rc)
1761 goto err_out;
1762
1763 jme_start_irq(jme);
1764
1765 jme_phy_on(jme);
1766 if (test_bit(JME_FLAG_SSET, &jme->flags))
1767 jme_set_settings(netdev, &jme->old_ecmd);
1768 else
1769 jme_reset_phy_processor(jme);
1770
1771 jme_reset_link(jme);
1772
1773 return 0;
1774
1775err_out:
1776 netif_stop_queue(netdev);
1777 netif_carrier_off(netdev);
1778 return rc;
1779}
1780
1781static void
1782jme_set_100m_half(struct jme_adapter *jme)
1783{
1784 u32 bmcr, tmp;
1785
1786 jme_phy_on(jme);
1787 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1788 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1789 BMCR_SPEED1000 | BMCR_FULLDPLX);
1790 tmp |= BMCR_SPEED100;
1791
1792 if (bmcr != tmp)
1793 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1794
1795 if (jme->fpgaver)
1796 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1797 else
1798 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1799}
1800
1801#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1802static void
1803jme_wait_link(struct jme_adapter *jme)
1804{
1805 u32 phylink, to = JME_WAIT_LINK_TIME;
1806
1807 mdelay(1000);
1808 phylink = jme_linkstat_from_phy(jme);
1809 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1810 mdelay(10);
1811 phylink = jme_linkstat_from_phy(jme);
1812 }
1813}
1814
1815static void
1816jme_powersave_phy(struct jme_adapter *jme)
1817{
1818 if (jme->reg_pmcs) {
1819 jme_set_100m_half(jme);
1820
1821 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1822 jme_wait_link(jme);
1823
1824 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1825 } else {
1826 jme_phy_off(jme);
1827 }
1828}
1829
1830static int
1831jme_close(struct net_device *netdev)
1832{
1833 struct jme_adapter *jme = netdev_priv(netdev);
1834
1835 netif_stop_queue(netdev);
1836 netif_carrier_off(netdev);
1837
1838 jme_stop_irq(jme);
1839 jme_free_irq(jme);
1840
1841 JME_NAPI_DISABLE(jme);
1842
1843 tasklet_disable(&jme->linkch_task);
1844 tasklet_disable(&jme->txclean_task);
1845 tasklet_disable(&jme->rxclean_task);
1846 tasklet_disable(&jme->rxempty_task);
1847
1848 jme_disable_rx_engine(jme);
1849 jme_disable_tx_engine(jme);
1850 jme_reset_mac_processor(jme);
1851 jme_free_rx_resources(jme);
1852 jme_free_tx_resources(jme);
1853 jme->phylink = 0;
1854 jme_phy_off(jme);
1855
1856 return 0;
1857}
1858
1859static int
1860jme_alloc_txdesc(struct jme_adapter *jme,
1861 struct sk_buff *skb)
1862{
1863 struct jme_ring *txring = &(jme->txring[0]);
1864 int idx, nr_alloc, mask = jme->tx_ring_mask;
1865
1866 idx = txring->next_to_use;
1867 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1868
1869 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1870 return -1;
1871
1872 atomic_sub(nr_alloc, &txring->nr_free);
1873
1874 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1875
1876 return idx;
1877}
1878
1879static void
1880jme_fill_tx_map(struct pci_dev *pdev,
1881 struct txdesc *txdesc,
1882 struct jme_buffer_info *txbi,
1883 struct page *page,
1884 u32 page_offset,
1885 u32 len,
1886 u8 hidma)
1887{
1888 dma_addr_t dmaaddr;
1889
1890 dmaaddr = pci_map_page(pdev,
1891 page,
1892 page_offset,
1893 len,
1894 PCI_DMA_TODEVICE);
1895
1896 pci_dma_sync_single_for_device(pdev,
1897 dmaaddr,
1898 len,
1899 PCI_DMA_TODEVICE);
1900
1901 txdesc->dw[0] = 0;
1902 txdesc->dw[1] = 0;
1903 txdesc->desc2.flags = TXFLAG_OWN;
1904 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1905 txdesc->desc2.datalen = cpu_to_le16(len);
1906 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1907 txdesc->desc2.bufaddrl = cpu_to_le32(
1908 (__u64)dmaaddr & 0xFFFFFFFFUL);
1909
1910 txbi->mapping = dmaaddr;
1911 txbi->len = len;
1912}
1913
1914static void
1915jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1916{
1917 struct jme_ring *txring = &(jme->txring[0]);
1918 struct txdesc *txdesc = txring->desc, *ctxdesc;
1919 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1920 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1921 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1922 int mask = jme->tx_ring_mask;
1923 struct skb_frag_struct *frag;
1924 u32 len;
1925
1926 for (i = 0 ; i < nr_frags ; ++i) {
1927 frag = &skb_shinfo(skb)->frags[i];
1928 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1929 ctxbi = txbi + ((idx + i + 2) & (mask));
1930
1931 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1932 frag->page_offset, frag->size, hidma);
1933 }
1934
1935 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1936 ctxdesc = txdesc + ((idx + 1) & (mask));
1937 ctxbi = txbi + ((idx + 1) & (mask));
1938 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1939 offset_in_page(skb->data), len, hidma);
1940
1941}
1942
1943static int
1944jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1945{
1946 if (unlikely(skb_shinfo(skb)->gso_size &&
1947 skb_header_cloned(skb) &&
1948 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1949 dev_kfree_skb(skb);
1950 return -1;
1951 }
1952
1953 return 0;
1954}
1955
1956static int
1957jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1958{
1959 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1960 if (*mss) {
1961 *flags |= TXFLAG_LSEN;
1962
1963 if (skb->protocol == htons(ETH_P_IP)) {
1964 struct iphdr *iph = ip_hdr(skb);
1965
1966 iph->check = 0;
1967 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1968 iph->daddr, 0,
1969 IPPROTO_TCP,
1970 0);
1971 } else {
1972 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1973
1974 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1975 &ip6h->daddr, 0,
1976 IPPROTO_TCP,
1977 0);
1978 }
1979
1980 return 0;
1981 }
1982
1983 return 1;
1984}
1985
1986static void
1987jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1988{
1989 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1990 u8 ip_proto;
1991
1992 switch (skb->protocol) {
1993 case htons(ETH_P_IP):
1994 ip_proto = ip_hdr(skb)->protocol;
1995 break;
1996 case htons(ETH_P_IPV6):
1997 ip_proto = ipv6_hdr(skb)->nexthdr;
1998 break;
1999 default:
2000 ip_proto = 0;
2001 break;
2002 }
2003
2004 switch (ip_proto) {
2005 case IPPROTO_TCP:
2006 *flags |= TXFLAG_TCPCS;
2007 break;
2008 case IPPROTO_UDP:
2009 *flags |= TXFLAG_UDPCS;
2010 break;
2011 default:
2012 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2013 break;
2014 }
2015 }
2016}
2017
2018static inline void
2019jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2020{
2021 if (vlan_tx_tag_present(skb)) {
2022 *flags |= TXFLAG_TAGON;
2023 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2024 }
2025}
2026
2027static int
2028jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2029{
2030 struct jme_ring *txring = &(jme->txring[0]);
2031 struct txdesc *txdesc;
2032 struct jme_buffer_info *txbi;
2033 u8 flags;
2034
2035 txdesc = (struct txdesc *)txring->desc + idx;
2036 txbi = txring->bufinf + idx;
2037
2038 txdesc->dw[0] = 0;
2039 txdesc->dw[1] = 0;
2040 txdesc->dw[2] = 0;
2041 txdesc->dw[3] = 0;
2042 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2043 /*
2044 * Set OWN bit at final.
2045 * When kernel transmit faster than NIC.
2046 * And NIC trying to send this descriptor before we tell
2047 * it to start sending this TX queue.
2048 * Other fields are already filled correctly.
2049 */
2050 wmb();
2051 flags = TXFLAG_OWN | TXFLAG_INT;
2052 /*
2053 * Set checksum flags while not tso
2054 */
2055 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2056 jme_tx_csum(jme, skb, &flags);
2057 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2058 jme_map_tx_skb(jme, skb, idx);
2059 txdesc->desc1.flags = flags;
2060 /*
2061 * Set tx buffer info after telling NIC to send
2062 * For better tx_clean timing
2063 */
2064 wmb();
2065 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2066 txbi->skb = skb;
2067 txbi->len = skb->len;
2068 txbi->start_xmit = jiffies;
2069 if (!txbi->start_xmit)
2070 txbi->start_xmit = (0UL-1);
2071
2072 return 0;
2073}
2074
2075static void
2076jme_stop_queue_if_full(struct jme_adapter *jme)
2077{
2078 struct jme_ring *txring = &(jme->txring[0]);
2079 struct jme_buffer_info *txbi = txring->bufinf;
2080 int idx = atomic_read(&txring->next_to_clean);
2081
2082 txbi += idx;
2083
2084 smp_wmb();
2085 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2086 netif_stop_queue(jme->dev);
2087 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2088 smp_wmb();
2089 if (atomic_read(&txring->nr_free)
2090 >= (jme->tx_wake_threshold)) {
2091 netif_wake_queue(jme->dev);
2092 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2093 }
2094 }
2095
2096 if (unlikely(txbi->start_xmit &&
2097 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2098 txbi->skb)) {
2099 netif_stop_queue(jme->dev);
2100 netif_info(jme, tx_queued, jme->dev,
2101 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2102 }
2103}
2104
2105/*
2106 * This function is already protected by netif_tx_lock()
2107 */
2108
2109static netdev_tx_t
2110jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2111{
2112 struct jme_adapter *jme = netdev_priv(netdev);
2113 int idx;
2114
2115 if (unlikely(jme_expand_header(jme, skb))) {
2116 ++(NET_STAT(jme).tx_dropped);
2117 return NETDEV_TX_OK;
2118 }
2119
2120 idx = jme_alloc_txdesc(jme, skb);
2121
2122 if (unlikely(idx < 0)) {
2123 netif_stop_queue(netdev);
2124 netif_err(jme, tx_err, jme->dev,
2125 "BUG! Tx ring full when queue awake!\n");
2126
2127 return NETDEV_TX_BUSY;
2128 }
2129
2130 jme_fill_tx_desc(jme, skb, idx);
2131
2132 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2133 TXCS_SELECT_QUEUE0 |
2134 TXCS_QUEUE0S |
2135 TXCS_ENABLE);
2136
2137 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2138 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2139 jme_stop_queue_if_full(jme);
2140
2141 return NETDEV_TX_OK;
2142}
2143
2144static void
2145jme_set_unicastaddr(struct net_device *netdev)
2146{
2147 struct jme_adapter *jme = netdev_priv(netdev);
2148 u32 val;
2149
2150 val = (netdev->dev_addr[3] & 0xff) << 24 |
2151 (netdev->dev_addr[2] & 0xff) << 16 |
2152 (netdev->dev_addr[1] & 0xff) << 8 |
2153 (netdev->dev_addr[0] & 0xff);
2154 jwrite32(jme, JME_RXUMA_LO, val);
2155 val = (netdev->dev_addr[5] & 0xff) << 8 |
2156 (netdev->dev_addr[4] & 0xff);
2157 jwrite32(jme, JME_RXUMA_HI, val);
2158}
2159
2160static int
2161jme_set_macaddr(struct net_device *netdev, void *p)
2162{
2163 struct jme_adapter *jme = netdev_priv(netdev);
2164 struct sockaddr *addr = p;
2165
2166 if (netif_running(netdev))
2167 return -EBUSY;
2168
2169 spin_lock_bh(&jme->macaddr_lock);
2170 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2171 jme_set_unicastaddr(netdev);
2172 spin_unlock_bh(&jme->macaddr_lock);
2173
2174 return 0;
2175}
2176
2177static void
2178jme_set_multi(struct net_device *netdev)
2179{
2180 struct jme_adapter *jme = netdev_priv(netdev);
2181 u32 mc_hash[2] = {};
2182
2183 spin_lock_bh(&jme->rxmcs_lock);
2184
2185 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2186
2187 if (netdev->flags & IFF_PROMISC) {
2188 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2189 } else if (netdev->flags & IFF_ALLMULTI) {
2190 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2191 } else if (netdev->flags & IFF_MULTICAST) {
2192 struct netdev_hw_addr *ha;
2193 int bit_nr;
2194
2195 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2196 netdev_for_each_mc_addr(ha, netdev) {
2197 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2198 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2199 }
2200
2201 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2202 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2203 }
2204
2205 wmb();
2206 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2207
2208 spin_unlock_bh(&jme->rxmcs_lock);
2209}
2210
2211static int
2212jme_change_mtu(struct net_device *netdev, int new_mtu)
2213{
2214 struct jme_adapter *jme = netdev_priv(netdev);
2215
2216 if (new_mtu == jme->old_mtu)
2217 return 0;
2218
2219 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2220 ((new_mtu) < IPV6_MIN_MTU))
2221 return -EINVAL;
2222
2223 if (new_mtu > 4000) {
2224 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2225 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2226 jme_restart_rx_engine(jme);
2227 } else {
2228 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2229 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2230 jme_restart_rx_engine(jme);
2231 }
2232
2233 if (new_mtu > 1900) {
2234 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2235 NETIF_F_TSO | NETIF_F_TSO6);
2236 } else {
2237 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2238 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2239 if (test_bit(JME_FLAG_TSO, &jme->flags))
2240 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2241 }
2242
2243 netdev->mtu = new_mtu;
2244 jme_reset_link(jme);
2245
2246 return 0;
2247}
2248
2249static void
2250jme_tx_timeout(struct net_device *netdev)
2251{
2252 struct jme_adapter *jme = netdev_priv(netdev);
2253
2254 jme->phylink = 0;
2255 jme_reset_phy_processor(jme);
2256 if (test_bit(JME_FLAG_SSET, &jme->flags))
2257 jme_set_settings(netdev, &jme->old_ecmd);
2258
2259 /*
2260 * Force to Reset the link again
2261 */
2262 jme_reset_link(jme);
2263}
2264
2265static inline void jme_pause_rx(struct jme_adapter *jme)
2266{
2267 atomic_dec(&jme->link_changing);
2268
2269 jme_set_rx_pcc(jme, PCC_OFF);
2270 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2271 JME_NAPI_DISABLE(jme);
2272 } else {
2273 tasklet_disable(&jme->rxclean_task);
2274 tasklet_disable(&jme->rxempty_task);
2275 }
2276}
2277
2278static inline void jme_resume_rx(struct jme_adapter *jme)
2279{
2280 struct dynpcc_info *dpi = &(jme->dpi);
2281
2282 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2283 JME_NAPI_ENABLE(jme);
2284 } else {
2285 tasklet_hi_enable(&jme->rxclean_task);
2286 tasklet_hi_enable(&jme->rxempty_task);
2287 }
2288 dpi->cur = PCC_P1;
2289 dpi->attempt = PCC_P1;
2290 dpi->cnt = 0;
2291 jme_set_rx_pcc(jme, PCC_P1);
2292
2293 atomic_inc(&jme->link_changing);
2294}
2295
2296static void
2297jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2298{
2299 struct jme_adapter *jme = netdev_priv(netdev);
2300
2301 jme_pause_rx(jme);
2302 jme->vlgrp = grp;
2303 jme_resume_rx(jme);
2304}
2305
2306static void
2307jme_get_drvinfo(struct net_device *netdev,
2308 struct ethtool_drvinfo *info)
2309{
2310 struct jme_adapter *jme = netdev_priv(netdev);
2311
2312 strcpy(info->driver, DRV_NAME);
2313 strcpy(info->version, DRV_VERSION);
2314 strcpy(info->bus_info, pci_name(jme->pdev));
2315}
2316
2317static int
2318jme_get_regs_len(struct net_device *netdev)
2319{
2320 return JME_REG_LEN;
2321}
2322
2323static void
2324mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2325{
2326 int i;
2327
2328 for (i = 0 ; i < len ; i += 4)
2329 p[i >> 2] = jread32(jme, reg + i);
2330}
2331
2332static void
2333mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2334{
2335 int i;
2336 u16 *p16 = (u16 *)p;
2337
2338 for (i = 0 ; i < reg_nr ; ++i)
2339 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2340}
2341
2342static void
2343jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2344{
2345 struct jme_adapter *jme = netdev_priv(netdev);
2346 u32 *p32 = (u32 *)p;
2347
2348 memset(p, 0xFF, JME_REG_LEN);
2349
2350 regs->version = 1;
2351 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2352
2353 p32 += 0x100 >> 2;
2354 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2355
2356 p32 += 0x100 >> 2;
2357 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2358
2359 p32 += 0x100 >> 2;
2360 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2361
2362 p32 += 0x100 >> 2;
2363 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2364}
2365
2366static int
2367jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2368{
2369 struct jme_adapter *jme = netdev_priv(netdev);
2370
2371 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2372 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2373
2374 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2375 ecmd->use_adaptive_rx_coalesce = false;
2376 ecmd->rx_coalesce_usecs = 0;
2377 ecmd->rx_max_coalesced_frames = 0;
2378 return 0;
2379 }
2380
2381 ecmd->use_adaptive_rx_coalesce = true;
2382
2383 switch (jme->dpi.cur) {
2384 case PCC_P1:
2385 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2386 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2387 break;
2388 case PCC_P2:
2389 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2390 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2391 break;
2392 case PCC_P3:
2393 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2394 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2395 break;
2396 default:
2397 break;
2398 }
2399
2400 return 0;
2401}
2402
2403static int
2404jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2405{
2406 struct jme_adapter *jme = netdev_priv(netdev);
2407 struct dynpcc_info *dpi = &(jme->dpi);
2408
2409 if (netif_running(netdev))
2410 return -EBUSY;
2411
2412 if (ecmd->use_adaptive_rx_coalesce &&
2413 test_bit(JME_FLAG_POLL, &jme->flags)) {
2414 clear_bit(JME_FLAG_POLL, &jme->flags);
2415 jme->jme_rx = netif_rx;
2416 jme->jme_vlan_rx = vlan_hwaccel_rx;
2417 dpi->cur = PCC_P1;
2418 dpi->attempt = PCC_P1;
2419 dpi->cnt = 0;
2420 jme_set_rx_pcc(jme, PCC_P1);
2421 jme_interrupt_mode(jme);
2422 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2423 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2424 set_bit(JME_FLAG_POLL, &jme->flags);
2425 jme->jme_rx = netif_receive_skb;
2426 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2427 jme_interrupt_mode(jme);
2428 }
2429
2430 return 0;
2431}
2432
2433static void
2434jme_get_pauseparam(struct net_device *netdev,
2435 struct ethtool_pauseparam *ecmd)
2436{
2437 struct jme_adapter *jme = netdev_priv(netdev);
2438 u32 val;
2439
2440 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2441 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2442
2443 spin_lock_bh(&jme->phy_lock);
2444 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2445 spin_unlock_bh(&jme->phy_lock);
2446
2447 ecmd->autoneg =
2448 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2449}
2450
2451static int
2452jme_set_pauseparam(struct net_device *netdev,
2453 struct ethtool_pauseparam *ecmd)
2454{
2455 struct jme_adapter *jme = netdev_priv(netdev);
2456 u32 val;
2457
2458 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2459 (ecmd->tx_pause != 0)) {
2460
2461 if (ecmd->tx_pause)
2462 jme->reg_txpfc |= TXPFC_PF_EN;
2463 else
2464 jme->reg_txpfc &= ~TXPFC_PF_EN;
2465
2466 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2467 }
2468
2469 spin_lock_bh(&jme->rxmcs_lock);
2470 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2471 (ecmd->rx_pause != 0)) {
2472
2473 if (ecmd->rx_pause)
2474 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2475 else
2476 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2477
2478 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2479 }
2480 spin_unlock_bh(&jme->rxmcs_lock);
2481
2482 spin_lock_bh(&jme->phy_lock);
2483 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2484 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2485 (ecmd->autoneg != 0)) {
2486
2487 if (ecmd->autoneg)
2488 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2489 else
2490 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2491
2492 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2493 MII_ADVERTISE, val);
2494 }
2495 spin_unlock_bh(&jme->phy_lock);
2496
2497 return 0;
2498}
2499
2500static void
2501jme_get_wol(struct net_device *netdev,
2502 struct ethtool_wolinfo *wol)
2503{
2504 struct jme_adapter *jme = netdev_priv(netdev);
2505
2506 wol->supported = WAKE_MAGIC | WAKE_PHY;
2507
2508 wol->wolopts = 0;
2509
2510 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2511 wol->wolopts |= WAKE_PHY;
2512
2513 if (jme->reg_pmcs & PMCS_MFEN)
2514 wol->wolopts |= WAKE_MAGIC;
2515
2516}
2517
2518static int
2519jme_set_wol(struct net_device *netdev,
2520 struct ethtool_wolinfo *wol)
2521{
2522 struct jme_adapter *jme = netdev_priv(netdev);
2523
2524 if (wol->wolopts & (WAKE_MAGICSECURE |
2525 WAKE_UCAST |
2526 WAKE_MCAST |
2527 WAKE_BCAST |
2528 WAKE_ARP))
2529 return -EOPNOTSUPP;
2530
2531 jme->reg_pmcs = 0;
2532
2533 if (wol->wolopts & WAKE_PHY)
2534 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2535
2536 if (wol->wolopts & WAKE_MAGIC)
2537 jme->reg_pmcs |= PMCS_MFEN;
2538
2539 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2540
2541 return 0;
2542}
2543
2544static int
2545jme_get_settings(struct net_device *netdev,
2546 struct ethtool_cmd *ecmd)
2547{
2548 struct jme_adapter *jme = netdev_priv(netdev);
2549 int rc;
2550
2551 spin_lock_bh(&jme->phy_lock);
2552 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2553 spin_unlock_bh(&jme->phy_lock);
2554 return rc;
2555}
2556
2557static int
2558jme_set_settings(struct net_device *netdev,
2559 struct ethtool_cmd *ecmd)
2560{
2561 struct jme_adapter *jme = netdev_priv(netdev);
2562 int rc, fdc = 0;
2563
2564 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2565 return -EINVAL;
2566
2567 /*
2568 * Check If user changed duplex only while force_media.
2569 * Hardware would not generate link change interrupt.
2570 */
2571 if (jme->mii_if.force_media &&
2572 ecmd->autoneg != AUTONEG_ENABLE &&
2573 (jme->mii_if.full_duplex != ecmd->duplex))
2574 fdc = 1;
2575
2576 spin_lock_bh(&jme->phy_lock);
2577 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2578 spin_unlock_bh(&jme->phy_lock);
2579
2580 if (!rc) {
2581 if (fdc)
2582 jme_reset_link(jme);
2583 jme->old_ecmd = *ecmd;
2584 set_bit(JME_FLAG_SSET, &jme->flags);
2585 }
2586
2587 return rc;
2588}
2589
2590static int
2591jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2592{
2593 int rc;
2594 struct jme_adapter *jme = netdev_priv(netdev);
2595 struct mii_ioctl_data *mii_data = if_mii(rq);
2596 unsigned int duplex_chg;
2597
2598 if (cmd == SIOCSMIIREG) {
2599 u16 val = mii_data->val_in;
2600 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2601 (val & BMCR_SPEED1000))
2602 return -EINVAL;
2603 }
2604
2605 spin_lock_bh(&jme->phy_lock);
2606 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2607 spin_unlock_bh(&jme->phy_lock);
2608
2609 if (!rc && (cmd == SIOCSMIIREG)) {
2610 if (duplex_chg)
2611 jme_reset_link(jme);
2612 jme_get_settings(netdev, &jme->old_ecmd);
2613 set_bit(JME_FLAG_SSET, &jme->flags);
2614 }
2615
2616 return rc;
2617}
2618
2619static u32
2620jme_get_link(struct net_device *netdev)
2621{
2622 struct jme_adapter *jme = netdev_priv(netdev);
2623 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2624}
2625
2626static u32
2627jme_get_msglevel(struct net_device *netdev)
2628{
2629 struct jme_adapter *jme = netdev_priv(netdev);
2630 return jme->msg_enable;
2631}
2632
2633static void
2634jme_set_msglevel(struct net_device *netdev, u32 value)
2635{
2636 struct jme_adapter *jme = netdev_priv(netdev);
2637 jme->msg_enable = value;
2638}
2639
2640static u32
2641jme_get_rx_csum(struct net_device *netdev)
2642{
2643 struct jme_adapter *jme = netdev_priv(netdev);
2644 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2645}
2646
2647static int
2648jme_set_rx_csum(struct net_device *netdev, u32 on)
2649{
2650 struct jme_adapter *jme = netdev_priv(netdev);
2651
2652 spin_lock_bh(&jme->rxmcs_lock);
2653 if (on)
2654 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2655 else
2656 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2657 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2658 spin_unlock_bh(&jme->rxmcs_lock);
2659
2660 return 0;
2661}
2662
2663static int
2664jme_set_tx_csum(struct net_device *netdev, u32 on)
2665{
2666 struct jme_adapter *jme = netdev_priv(netdev);
2667
2668 if (on) {
2669 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2670 if (netdev->mtu <= 1900)
2671 netdev->features |=
2672 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2673 } else {
2674 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2675 netdev->features &=
2676 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2677 }
2678
2679 return 0;
2680}
2681
2682static int
2683jme_set_tso(struct net_device *netdev, u32 on)
2684{
2685 struct jme_adapter *jme = netdev_priv(netdev);
2686
2687 if (on) {
2688 set_bit(JME_FLAG_TSO, &jme->flags);
2689 if (netdev->mtu <= 1900)
2690 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2691 } else {
2692 clear_bit(JME_FLAG_TSO, &jme->flags);
2693 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2694 }
2695
2696 return 0;
2697}
2698
2699static int
2700jme_nway_reset(struct net_device *netdev)
2701{
2702 struct jme_adapter *jme = netdev_priv(netdev);
2703 jme_restart_an(jme);
2704 return 0;
2705}
2706
2707static u8
2708jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2709{
2710 u32 val;
2711 int to;
2712
2713 val = jread32(jme, JME_SMBCSR);
2714 to = JME_SMB_BUSY_TIMEOUT;
2715 while ((val & SMBCSR_BUSY) && --to) {
2716 msleep(1);
2717 val = jread32(jme, JME_SMBCSR);
2718 }
2719 if (!to) {
2720 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2721 return 0xFF;
2722 }
2723
2724 jwrite32(jme, JME_SMBINTF,
2725 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2726 SMBINTF_HWRWN_READ |
2727 SMBINTF_HWCMD);
2728
2729 val = jread32(jme, JME_SMBINTF);
2730 to = JME_SMB_BUSY_TIMEOUT;
2731 while ((val & SMBINTF_HWCMD) && --to) {
2732 msleep(1);
2733 val = jread32(jme, JME_SMBINTF);
2734 }
2735 if (!to) {
2736 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2737 return 0xFF;
2738 }
2739
2740 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2741}
2742
2743static void
2744jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2745{
2746 u32 val;
2747 int to;
2748
2749 val = jread32(jme, JME_SMBCSR);
2750 to = JME_SMB_BUSY_TIMEOUT;
2751 while ((val & SMBCSR_BUSY) && --to) {
2752 msleep(1);
2753 val = jread32(jme, JME_SMBCSR);
2754 }
2755 if (!to) {
2756 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2757 return;
2758 }
2759
2760 jwrite32(jme, JME_SMBINTF,
2761 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2762 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2763 SMBINTF_HWRWN_WRITE |
2764 SMBINTF_HWCMD);
2765
2766 val = jread32(jme, JME_SMBINTF);
2767 to = JME_SMB_BUSY_TIMEOUT;
2768 while ((val & SMBINTF_HWCMD) && --to) {
2769 msleep(1);
2770 val = jread32(jme, JME_SMBINTF);
2771 }
2772 if (!to) {
2773 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2774 return;
2775 }
2776
2777 mdelay(2);
2778}
2779
2780static int
2781jme_get_eeprom_len(struct net_device *netdev)
2782{
2783 struct jme_adapter *jme = netdev_priv(netdev);
2784 u32 val;
2785 val = jread32(jme, JME_SMBCSR);
2786 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2787}
2788
2789static int
2790jme_get_eeprom(struct net_device *netdev,
2791 struct ethtool_eeprom *eeprom, u8 *data)
2792{
2793 struct jme_adapter *jme = netdev_priv(netdev);
2794 int i, offset = eeprom->offset, len = eeprom->len;
2795
2796 /*
2797 * ethtool will check the boundary for us
2798 */
2799 eeprom->magic = JME_EEPROM_MAGIC;
2800 for (i = 0 ; i < len ; ++i)
2801 data[i] = jme_smb_read(jme, i + offset);
2802
2803 return 0;
2804}
2805
2806static int
2807jme_set_eeprom(struct net_device *netdev,
2808 struct ethtool_eeprom *eeprom, u8 *data)
2809{
2810 struct jme_adapter *jme = netdev_priv(netdev);
2811 int i, offset = eeprom->offset, len = eeprom->len;
2812
2813 if (eeprom->magic != JME_EEPROM_MAGIC)
2814 return -EINVAL;
2815
2816 /*
2817 * ethtool will check the boundary for us
2818 */
2819 for (i = 0 ; i < len ; ++i)
2820 jme_smb_write(jme, i + offset, data[i]);
2821
2822 return 0;
2823}
2824
2825static const struct ethtool_ops jme_ethtool_ops = {
2826 .get_drvinfo = jme_get_drvinfo,
2827 .get_regs_len = jme_get_regs_len,
2828 .get_regs = jme_get_regs,
2829 .get_coalesce = jme_get_coalesce,
2830 .set_coalesce = jme_set_coalesce,
2831 .get_pauseparam = jme_get_pauseparam,
2832 .set_pauseparam = jme_set_pauseparam,
2833 .get_wol = jme_get_wol,
2834 .set_wol = jme_set_wol,
2835 .get_settings = jme_get_settings,
2836 .set_settings = jme_set_settings,
2837 .get_link = jme_get_link,
2838 .get_msglevel = jme_get_msglevel,
2839 .set_msglevel = jme_set_msglevel,
2840 .get_rx_csum = jme_get_rx_csum,
2841 .set_rx_csum = jme_set_rx_csum,
2842 .set_tx_csum = jme_set_tx_csum,
2843 .set_tso = jme_set_tso,
2844 .set_sg = ethtool_op_set_sg,
2845 .nway_reset = jme_nway_reset,
2846 .get_eeprom_len = jme_get_eeprom_len,
2847 .get_eeprom = jme_get_eeprom,
2848 .set_eeprom = jme_set_eeprom,
2849};
2850
2851static int
2852jme_pci_dma64(struct pci_dev *pdev)
2853{
2854 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2855 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2856 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2857 return 1;
2858
2859 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2860 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2861 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2862 return 1;
2863
2864 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2865 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2866 return 0;
2867
2868 return -1;
2869}
2870
2871static inline void
2872jme_phy_init(struct jme_adapter *jme)
2873{
2874 u16 reg26;
2875
2876 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2877 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2878}
2879
2880static inline void
2881jme_check_hw_ver(struct jme_adapter *jme)
2882{
2883 u32 chipmode;
2884
2885 chipmode = jread32(jme, JME_CHIPMODE);
2886
2887 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2888 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2889 jme->chip_main_rev = jme->chiprev & 0xF;
2890 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2891}
2892
2893static const struct net_device_ops jme_netdev_ops = {
2894 .ndo_open = jme_open,
2895 .ndo_stop = jme_close,
2896 .ndo_validate_addr = eth_validate_addr,
2897 .ndo_do_ioctl = jme_ioctl,
2898 .ndo_start_xmit = jme_start_xmit,
2899 .ndo_set_mac_address = jme_set_macaddr,
2900 .ndo_set_multicast_list = jme_set_multi,
2901 .ndo_change_mtu = jme_change_mtu,
2902 .ndo_tx_timeout = jme_tx_timeout,
2903 .ndo_vlan_rx_register = jme_vlan_rx_register,
2904};
2905
2906static int __devinit
2907jme_init_one(struct pci_dev *pdev,
2908 const struct pci_device_id *ent)
2909{
2910 int rc = 0, using_dac, i;
2911 struct net_device *netdev;
2912 struct jme_adapter *jme;
2913 u16 bmcr, bmsr;
2914 u32 apmc;
2915
2916 /*
2917 * set up PCI device basics
2918 */
2919 rc = pci_enable_device(pdev);
2920 if (rc) {
2921 pr_err("Cannot enable PCI device\n");
2922 goto err_out;
2923 }
2924
2925 using_dac = jme_pci_dma64(pdev);
2926 if (using_dac < 0) {
2927 pr_err("Cannot set PCI DMA Mask\n");
2928 rc = -EIO;
2929 goto err_out_disable_pdev;
2930 }
2931
2932 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2933 pr_err("No PCI resource region found\n");
2934 rc = -ENOMEM;
2935 goto err_out_disable_pdev;
2936 }
2937
2938 rc = pci_request_regions(pdev, DRV_NAME);
2939 if (rc) {
2940 pr_err("Cannot obtain PCI resource region\n");
2941 goto err_out_disable_pdev;
2942 }
2943
2944 pci_set_master(pdev);
2945
2946 /*
2947 * alloc and init net device
2948 */
2949 netdev = alloc_etherdev(sizeof(*jme));
2950 if (!netdev) {
2951 pr_err("Cannot allocate netdev structure\n");
2952 rc = -ENOMEM;
2953 goto err_out_release_regions;
2954 }
2955 netdev->netdev_ops = &jme_netdev_ops;
2956 netdev->ethtool_ops = &jme_ethtool_ops;
2957 netdev->watchdog_timeo = TX_TIMEOUT;
2958 netdev->features = NETIF_F_IP_CSUM |
2959 NETIF_F_IPV6_CSUM |
2960 NETIF_F_SG |
2961 NETIF_F_TSO |
2962 NETIF_F_TSO6 |
2963 NETIF_F_HW_VLAN_TX |
2964 NETIF_F_HW_VLAN_RX;
2965 if (using_dac)
2966 netdev->features |= NETIF_F_HIGHDMA;
2967
2968 SET_NETDEV_DEV(netdev, &pdev->dev);
2969 pci_set_drvdata(pdev, netdev);
2970
2971 /*
2972 * init adapter info
2973 */
2974 jme = netdev_priv(netdev);
2975 jme->pdev = pdev;
2976 jme->dev = netdev;
2977 jme->jme_rx = netif_rx;
2978 jme->jme_vlan_rx = vlan_hwaccel_rx;
2979 jme->old_mtu = netdev->mtu = 1500;
2980 jme->phylink = 0;
2981 jme->tx_ring_size = 1 << 10;
2982 jme->tx_ring_mask = jme->tx_ring_size - 1;
2983 jme->tx_wake_threshold = 1 << 9;
2984 jme->rx_ring_size = 1 << 9;
2985 jme->rx_ring_mask = jme->rx_ring_size - 1;
2986 jme->msg_enable = JME_DEF_MSG_ENABLE;
2987 jme->regs = ioremap(pci_resource_start(pdev, 0),
2988 pci_resource_len(pdev, 0));
2989 if (!(jme->regs)) {
2990 pr_err("Mapping PCI resource region error\n");
2991 rc = -ENOMEM;
2992 goto err_out_free_netdev;
2993 }
2994
2995 if (no_pseudohp) {
2996 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2997 jwrite32(jme, JME_APMC, apmc);
2998 } else if (force_pseudohp) {
2999 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3000 jwrite32(jme, JME_APMC, apmc);
3001 }
3002
3003 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3004
3005 spin_lock_init(&jme->phy_lock);
3006 spin_lock_init(&jme->macaddr_lock);
3007 spin_lock_init(&jme->rxmcs_lock);
3008
3009 atomic_set(&jme->link_changing, 1);
3010 atomic_set(&jme->rx_cleaning, 1);
3011 atomic_set(&jme->tx_cleaning, 1);
3012 atomic_set(&jme->rx_empty, 1);
3013
3014 tasklet_init(&jme->pcc_task,
3015 jme_pcc_tasklet,
3016 (unsigned long) jme);
3017 tasklet_init(&jme->linkch_task,
3018 jme_link_change_tasklet,
3019 (unsigned long) jme);
3020 tasklet_init(&jme->txclean_task,
3021 jme_tx_clean_tasklet,
3022 (unsigned long) jme);
3023 tasklet_init(&jme->rxclean_task,
3024 jme_rx_clean_tasklet,
3025 (unsigned long) jme);
3026 tasklet_init(&jme->rxempty_task,
3027 jme_rx_empty_tasklet,
3028 (unsigned long) jme);
3029 tasklet_disable_nosync(&jme->linkch_task);
3030 tasklet_disable_nosync(&jme->txclean_task);
3031 tasklet_disable_nosync(&jme->rxclean_task);
3032 tasklet_disable_nosync(&jme->rxempty_task);
3033 jme->dpi.cur = PCC_P1;
3034
3035 jme->reg_ghc = 0;
3036 jme->reg_rxcs = RXCS_DEFAULT;
3037 jme->reg_rxmcs = RXMCS_DEFAULT;
3038 jme->reg_txpfc = 0;
3039 jme->reg_pmcs = PMCS_MFEN;
3040 jme->reg_gpreg1 = GPREG1_DEFAULT;
3041 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3042 set_bit(JME_FLAG_TSO, &jme->flags);
3043
3044 /*
3045 * Get Max Read Req Size from PCI Config Space
3046 */
3047 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3048 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3049 switch (jme->mrrs) {
3050 case MRRS_128B:
3051 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3052 break;
3053 case MRRS_256B:
3054 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3055 break;
3056 default:
3057 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3058 break;
3059 }
3060
3061 /*
3062 * Must check before reset_mac_processor
3063 */
3064 jme_check_hw_ver(jme);
3065 jme->mii_if.dev = netdev;
3066 if (jme->fpgaver) {
3067 jme->mii_if.phy_id = 0;
3068 for (i = 1 ; i < 32 ; ++i) {
3069 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3070 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3071 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3072 jme->mii_if.phy_id = i;
3073 break;
3074 }
3075 }
3076
3077 if (!jme->mii_if.phy_id) {
3078 rc = -EIO;
3079 pr_err("Can not find phy_id\n");
3080 goto err_out_unmap;
3081 }
3082
3083 jme->reg_ghc |= GHC_LINK_POLL;
3084 } else {
3085 jme->mii_if.phy_id = 1;
3086 }
3087 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3088 jme->mii_if.supports_gmii = true;
3089 else
3090 jme->mii_if.supports_gmii = false;
3091 jme->mii_if.phy_id_mask = 0x1F;
3092 jme->mii_if.reg_num_mask = 0x1F;
3093 jme->mii_if.mdio_read = jme_mdio_read;
3094 jme->mii_if.mdio_write = jme_mdio_write;
3095
3096 jme_clear_pm(jme);
3097 jme_set_phyfifo_5level(jme);
3098 jme->pcirev = pdev->revision;
3099 if (!jme->fpgaver)
3100 jme_phy_init(jme);
3101 jme_phy_off(jme);
3102
3103 /*
3104 * Reset MAC processor and reload EEPROM for MAC Address
3105 */
3106 jme_reset_mac_processor(jme);
3107 rc = jme_reload_eeprom(jme);
3108 if (rc) {
3109 pr_err("Reload eeprom for reading MAC Address error\n");
3110 goto err_out_unmap;
3111 }
3112 jme_load_macaddr(netdev);
3113
3114 /*
3115 * Tell stack that we are not ready to work until open()
3116 */
3117 netif_carrier_off(netdev);
3118
3119 rc = register_netdev(netdev);
3120 if (rc) {
3121 pr_err("Cannot register net device\n");
3122 goto err_out_unmap;
3123 }
3124
3125 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3126 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3127 "JMC250 Gigabit Ethernet" :
3128 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3129 "JMC260 Fast Ethernet" : "Unknown",
3130 (jme->fpgaver != 0) ? " (FPGA)" : "",
3131 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3132 jme->pcirev, netdev->dev_addr);
3133
3134 return 0;
3135
3136err_out_unmap:
3137 iounmap(jme->regs);
3138err_out_free_netdev:
3139 pci_set_drvdata(pdev, NULL);
3140 free_netdev(netdev);
3141err_out_release_regions:
3142 pci_release_regions(pdev);
3143err_out_disable_pdev:
3144 pci_disable_device(pdev);
3145err_out:
3146 return rc;
3147}
3148
3149static void __devexit
3150jme_remove_one(struct pci_dev *pdev)
3151{
3152 struct net_device *netdev = pci_get_drvdata(pdev);
3153 struct jme_adapter *jme = netdev_priv(netdev);
3154
3155 unregister_netdev(netdev);
3156 iounmap(jme->regs);
3157 pci_set_drvdata(pdev, NULL);
3158 free_netdev(netdev);
3159 pci_release_regions(pdev);
3160 pci_disable_device(pdev);
3161
3162}
3163
3164static void
3165jme_shutdown(struct pci_dev *pdev)
3166{
3167 struct net_device *netdev = pci_get_drvdata(pdev);
3168 struct jme_adapter *jme = netdev_priv(netdev);
3169
3170 jme_powersave_phy(jme);
3171 pci_pme_active(pdev, true);
3172}
3173
3174#ifdef CONFIG_PM
3175static int
3176jme_suspend(struct pci_dev *pdev, pm_message_t state)
3177{
3178 struct net_device *netdev = pci_get_drvdata(pdev);
3179 struct jme_adapter *jme = netdev_priv(netdev);
3180
3181 atomic_dec(&jme->link_changing);
3182
3183 netif_device_detach(netdev);
3184 netif_stop_queue(netdev);
3185 jme_stop_irq(jme);
3186
3187 tasklet_disable(&jme->txclean_task);
3188 tasklet_disable(&jme->rxclean_task);
3189 tasklet_disable(&jme->rxempty_task);
3190
3191 if (netif_carrier_ok(netdev)) {
3192 if (test_bit(JME_FLAG_POLL, &jme->flags))
3193 jme_polling_mode(jme);
3194
3195 jme_stop_pcc_timer(jme);
3196 jme_disable_rx_engine(jme);
3197 jme_disable_tx_engine(jme);
3198 jme_reset_mac_processor(jme);
3199 jme_free_rx_resources(jme);
3200 jme_free_tx_resources(jme);
3201 netif_carrier_off(netdev);
3202 jme->phylink = 0;
3203 }
3204
3205 tasklet_enable(&jme->txclean_task);
3206 tasklet_hi_enable(&jme->rxclean_task);
3207 tasklet_hi_enable(&jme->rxempty_task);
3208
3209 pci_save_state(pdev);
3210 jme_powersave_phy(jme);
3211 pci_enable_wake(jme->pdev, PCI_D3hot, true);
3212 pci_set_power_state(pdev, PCI_D3hot);
3213
3214 return 0;
3215}
3216
3217static int
3218jme_resume(struct pci_dev *pdev)
3219{
3220 struct net_device *netdev = pci_get_drvdata(pdev);
3221 struct jme_adapter *jme = netdev_priv(netdev);
3222
3223 jme_clear_pm(jme);
3224 pci_restore_state(pdev);
3225
3226 jme_phy_on(jme);
3227 if (test_bit(JME_FLAG_SSET, &jme->flags))
3228 jme_set_settings(netdev, &jme->old_ecmd);
3229 else
3230 jme_reset_phy_processor(jme);
3231
3232 jme_start_irq(jme);
3233 netif_device_attach(netdev);
3234
3235 atomic_inc(&jme->link_changing);
3236
3237 jme_reset_link(jme);
3238
3239 return 0;
3240}
3241#endif
3242
3243static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3244 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3245 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3246 { }
3247};
3248
3249static struct pci_driver jme_driver = {
3250 .name = DRV_NAME,
3251 .id_table = jme_pci_tbl,
3252 .probe = jme_init_one,
3253 .remove = __devexit_p(jme_remove_one),
3254#ifdef CONFIG_PM
3255 .suspend = jme_suspend,
3256 .resume = jme_resume,
3257#endif /* CONFIG_PM */
3258 .shutdown = jme_shutdown,
3259};
3260
3261static int __init
3262jme_init_module(void)
3263{
3264 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3265 return pci_register_driver(&jme_driver);
3266}
3267
3268static void __exit
3269jme_cleanup_module(void)
3270{
3271 pci_unregister_driver(&jme_driver);
3272}
3273
3274module_init(jme_init_module);
3275module_exit(jme_cleanup_module);
3276
3277MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3278MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3279MODULE_LICENSE("GPL");
3280MODULE_VERSION(DRV_VERSION);
3281MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3282
JMicron Ethernet Linux driver