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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/mii.h>
31#include <linux/crc32.h>
32#include <linux/delay.h>
33#include <linux/spinlock.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
38#include <linux/udp.h>
39#include <linux/if_vlan.h>
40#include <net/ip6_checksum.h>
41#include "jme.h"
42
43static int force_pseudohp = -1;
44static int no_pseudohp = -1;
45static int no_extplug = -1;
46module_param(force_pseudohp, int, 0);
47MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49module_param(no_pseudohp, int, 0);
50MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51module_param(no_extplug, int, 0);
52MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
54
55static int
56jme_mdio_read(struct net_device *netdev, int phy, int reg)
57{
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
60
61read_again:
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
65
66 wmb();
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
68 udelay(20);
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
71 break;
72 }
73
74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
76 return 0;
77 }
78
79 if (again--)
80 goto read_again;
81
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
83}
84
85static void
86jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
88{
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
95
96 wmb();
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100 break;
101 }
102
103 if (i == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
105
106 return;
107}
108
109static inline void
110jme_reset_phy_processor(struct jme_adapter *jme)
111{
112 u32 val;
113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
133 return;
134}
135
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
162
163static inline void
164jme_reset_mac_processor(struct jme_adapter *jme)
165{
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194}
195
196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
204jme_clear_pm(struct jme_adapter *jme)
205{
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209}
210
211static int
212jme_reload_eeprom(struct jme_adapter *jme)
213{
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239}
240
241static void
242jme_load_macaddr(struct net_device *netdev)
243{
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259}
260
261static inline void
262jme_set_rx_pcc(struct jme_adapter *jme, int p)
263{
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
292}
293
294static void
295jme_start_irq(struct jme_adapter *jme)
296{
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314}
315
316static inline void
317jme_stop_irq(struct jme_adapter *jme)
318{
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323}
324
325static u32
326jme_linkstat_from_phy(struct jme_adapter *jme)
327{
328 u32 phylink, bmsr;
329
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if (bmsr & BMSR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335 return phylink;
336}
337
338static inline void
339jme_set_phyfifoa(struct jme_adapter *jme)
340{
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342}
343
344static inline void
345jme_set_phyfifob(struct jme_adapter *jme)
346{
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348}
349
350static int
351jme_check_link(struct net_device *netdev, int testonly)
352{
353 struct jme_adapter *jme = netdev_priv(netdev);
354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
355 char linkmsg[64];
356 int rc = 0;
357
358 linkmsg[0] = '\0';
359
360 if (jme->fpgaver)
361 phylink = jme_linkstat_from_phy(jme);
362 else
363 phylink = jread32(jme, JME_PHY_LINK);
364
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
367 /*
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
370 */
371 phylink = PHY_LINK_UP;
372
373 bmcr = jme_mdio_read(jme->dev,
374 jme->mii_if.phy_id,
375 MII_BMCR);
376
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
382 PHY_LINK_SPEED_10M;
383
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
385 PHY_LINK_DUPLEX : 0;
386
387 strcat(linkmsg, "Forced: ");
388 } else {
389 /*
390 * Keep polling for speed/duplex resolve complete
391 */
392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
393 --cnt) {
394
395 udelay(1);
396
397 if (jme->fpgaver)
398 phylink = jme_linkstat_from_phy(jme);
399 else
400 phylink = jread32(jme, JME_PHY_LINK);
401 }
402 if (!cnt)
403 jeprintk(jme->pdev,
404 "Waiting speed resolve timeout.\n");
405
406 strcat(linkmsg, "ANed: ");
407 }
408
409 if (jme->phylink == phylink) {
410 rc = 1;
411 goto out;
412 }
413 if (testonly)
414 goto out;
415
416 jme->phylink = phylink;
417
418 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
419 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
420 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
421 switch (phylink & PHY_LINK_SPEED_MASK) {
422 case PHY_LINK_SPEED_10M:
423 ghc |= GHC_SPEED_10M |
424 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
425 strcat(linkmsg, "10 Mbps, ");
426 break;
427 case PHY_LINK_SPEED_100M:
428 ghc |= GHC_SPEED_100M |
429 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
430 strcat(linkmsg, "100 Mbps, ");
431 break;
432 case PHY_LINK_SPEED_1000M:
433 ghc |= GHC_SPEED_1000M |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
435 strcat(linkmsg, "1000 Mbps, ");
436 break;
437 default:
438 break;
439 }
440
441 if (phylink & PHY_LINK_DUPLEX) {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
443 ghc |= GHC_DPX;
444 } else {
445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
446 TXMCS_BACKOFF |
447 TXMCS_CARRIERSENSE |
448 TXMCS_COLLISION);
449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
451 TXTRHD_TXREN |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
453 }
454
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifoa(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
463 break;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifob(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
467 break;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifoa(jme);
470 break;
471 default:
472 break;
473 }
474 }
475
476 jwrite32(jme, JME_GPREG1, gpreg1);
477 jwrite32(jme, JME_GHC, ghc);
478 jme->reg_ghc = ghc;
479
480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
481 "Full-Duplex, " :
482 "Half-Duplex, ");
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
484 "MDI-X" :
485 "MDI");
486 msg_link(jme, "Link is up at %s.\n", linkmsg);
487 netif_carrier_on(netdev);
488 } else {
489 if (testonly)
490 goto out;
491
492 msg_link(jme, "Link is down.\n");
493 jme->phylink = 0;
494 netif_carrier_off(netdev);
495 }
496
497out:
498 return rc;
499}
500
501static int
502jme_setup_tx_resources(struct jme_adapter *jme)
503{
504 struct jme_ring *txring = &(jme->txring[0]);
505
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
508 &(txring->dmaalloc),
509 GFP_ATOMIC);
510
511 if (!txring->alloc)
512 goto err_set_null;
513
514 /*
515 * 16 Bytes align
516 */
517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
518 RING_DESC_ALIGN);
519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
520 txring->next_to_use = 0;
521 atomic_set(&txring->next_to_clean, 0);
522 atomic_set(&txring->nr_free, jme->tx_ring_size);
523
524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
528
529 /*
530 * Initialize Transmit Descriptors
531 */
532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
533 memset(txring->bufinf, 0,
534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
535
536 return 0;
537
538err_free_txring:
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
541 txring->alloc,
542 txring->dmaalloc);
543
544err_set_null:
545 txring->desc = NULL;
546 txring->dmaalloc = 0;
547 txring->dma = 0;
548 txring->bufinf = NULL;
549
550 return -ENOMEM;
551}
552
553static void
554jme_free_tx_resources(struct jme_adapter *jme)
555{
556 int i;
557 struct jme_ring *txring = &(jme->txring[0]);
558 struct jme_buffer_info *txbi;
559
560 if (txring->alloc) {
561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
564 if (txbi->skb) {
565 dev_kfree_skb(txbi->skb);
566 txbi->skb = NULL;
567 }
568 txbi->mapping = 0;
569 txbi->len = 0;
570 txbi->nr_desc = 0;
571 txbi->start_xmit = 0;
572 }
573 kfree(txring->bufinf);
574 }
575
576 dma_free_coherent(&(jme->pdev->dev),
577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
578 txring->alloc,
579 txring->dmaalloc);
580
581 txring->alloc = NULL;
582 txring->desc = NULL;
583 txring->dmaalloc = 0;
584 txring->dma = 0;
585 txring->bufinf = NULL;
586 }
587 txring->next_to_use = 0;
588 atomic_set(&txring->next_to_clean, 0);
589 atomic_set(&txring->nr_free, 0);
590}
591
592static inline void
593jme_enable_tx_engine(struct jme_adapter *jme)
594{
595 /*
596 * Select Queue 0
597 */
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
599 wmb();
600
601 /*
602 * Setup TX Queue 0 DMA Bass Address
603 */
604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
607
608 /*
609 * Setup TX Descptor Count
610 */
611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
612
613 /*
614 * Enable TX Engine
615 */
616 wmb();
617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
618 TXCS_SELECT_QUEUE0 |
619 TXCS_ENABLE);
620
621}
622
623static inline void
624jme_restart_tx_engine(struct jme_adapter *jme)
625{
626 /*
627 * Restart TX Engine
628 */
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
630 TXCS_SELECT_QUEUE0 |
631 TXCS_ENABLE);
632}
633
634static inline void
635jme_disable_tx_engine(struct jme_adapter *jme)
636{
637 int i;
638 u32 val;
639
640 /*
641 * Disable TX Engine
642 */
643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
644 wmb();
645
646 val = jread32(jme, JME_TXCS);
647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
648 mdelay(1);
649 val = jread32(jme, JME_TXCS);
650 rmb();
651 }
652
653 if (!i)
654 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
655}
656
657static void
658jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
659{
660 struct jme_ring *rxring = &(jme->rxring[0]);
661 register struct rxdesc *rxdesc = rxring->desc;
662 struct jme_buffer_info *rxbi = rxring->bufinf;
663 rxdesc += i;
664 rxbi += i;
665
666 rxdesc->dw[0] = 0;
667 rxdesc->dw[1] = 0;
668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
672 if (jme->dev->features & NETIF_F_HIGHDMA)
673 rxdesc->desc1.flags = RXFLAG_64BIT;
674 wmb();
675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
676}
677
678static int
679jme_make_new_rx_buf(struct jme_adapter *jme, int i)
680{
681 struct jme_ring *rxring = &(jme->rxring[0]);
682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
683 struct sk_buff *skb;
684
685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
687 if (unlikely(!skb))
688 return -ENOMEM;
689#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
690 skb->dev = jme->dev;
691#endif
692
693 rxbi->skb = skb;
694 rxbi->len = skb_tailroom(skb);
695 rxbi->mapping = pci_map_page(jme->pdev,
696 virt_to_page(skb->data),
697 offset_in_page(skb->data),
698 rxbi->len,
699 PCI_DMA_FROMDEVICE);
700
701 return 0;
702}
703
704static void
705jme_free_rx_buf(struct jme_adapter *jme, int i)
706{
707 struct jme_ring *rxring = &(jme->rxring[0]);
708 struct jme_buffer_info *rxbi = rxring->bufinf;
709 rxbi += i;
710
711 if (rxbi->skb) {
712 pci_unmap_page(jme->pdev,
713 rxbi->mapping,
714 rxbi->len,
715 PCI_DMA_FROMDEVICE);
716 dev_kfree_skb(rxbi->skb);
717 rxbi->skb = NULL;
718 rxbi->mapping = 0;
719 rxbi->len = 0;
720 }
721}
722
723static void
724jme_free_rx_resources(struct jme_adapter *jme)
725{
726 int i;
727 struct jme_ring *rxring = &(jme->rxring[0]);
728
729 if (rxring->alloc) {
730 if (rxring->bufinf) {
731 for (i = 0 ; i < jme->rx_ring_size ; ++i)
732 jme_free_rx_buf(jme, i);
733 kfree(rxring->bufinf);
734 }
735
736 dma_free_coherent(&(jme->pdev->dev),
737 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
738 rxring->alloc,
739 rxring->dmaalloc);
740 rxring->alloc = NULL;
741 rxring->desc = NULL;
742 rxring->dmaalloc = 0;
743 rxring->dma = 0;
744 rxring->bufinf = NULL;
745 }
746 rxring->next_to_use = 0;
747 atomic_set(&rxring->next_to_clean, 0);
748}
749
750static int
751jme_setup_rx_resources(struct jme_adapter *jme)
752{
753 int i;
754 struct jme_ring *rxring = &(jme->rxring[0]);
755
756 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
757 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
758 &(rxring->dmaalloc),
759 GFP_ATOMIC);
760 if (!rxring->alloc)
761 goto err_set_null;
762
763 /*
764 * 16 Bytes align
765 */
766 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
767 RING_DESC_ALIGN);
768 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
769 rxring->next_to_use = 0;
770 atomic_set(&rxring->next_to_clean, 0);
771
772 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
773 jme->rx_ring_size, GFP_ATOMIC);
774 if (unlikely(!(rxring->bufinf)))
775 goto err_free_rxring;
776
777 /*
778 * Initiallize Receive Descriptors
779 */
780 memset(rxring->bufinf, 0,
781 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
782 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
783 if (unlikely(jme_make_new_rx_buf(jme, i))) {
784 jme_free_rx_resources(jme);
785 return -ENOMEM;
786 }
787
788 jme_set_clean_rxdesc(jme, i);
789 }
790
791 return 0;
792
793err_free_rxring:
794 dma_free_coherent(&(jme->pdev->dev),
795 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
796 rxring->alloc,
797 rxring->dmaalloc);
798err_set_null:
799 rxring->desc = NULL;
800 rxring->dmaalloc = 0;
801 rxring->dma = 0;
802 rxring->bufinf = NULL;
803
804 return -ENOMEM;
805}
806
807static inline void
808jme_enable_rx_engine(struct jme_adapter *jme)
809{
810 /*
811 * Select Queue 0
812 */
813 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
814 RXCS_QUEUESEL_Q0);
815 wmb();
816
817 /*
818 * Setup RX DMA Bass Address
819 */
820 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
821 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
822 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
823
824 /*
825 * Setup RX Descriptor Count
826 */
827 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
828
829 /*
830 * Setup Unicast Filter
831 */
832 jme_set_multi(jme->dev);
833
834 /*
835 * Enable RX Engine
836 */
837 wmb();
838 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
839 RXCS_QUEUESEL_Q0 |
840 RXCS_ENABLE |
841 RXCS_QST);
842}
843
844static inline void
845jme_restart_rx_engine(struct jme_adapter *jme)
846{
847 /*
848 * Start RX Engine
849 */
850 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
851 RXCS_QUEUESEL_Q0 |
852 RXCS_ENABLE |
853 RXCS_QST);
854}
855
856static inline void
857jme_disable_rx_engine(struct jme_adapter *jme)
858{
859 int i;
860 u32 val;
861
862 /*
863 * Disable RX Engine
864 */
865 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
866 wmb();
867
868 val = jread32(jme, JME_RXCS);
869 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
870 mdelay(1);
871 val = jread32(jme, JME_RXCS);
872 rmb();
873 }
874
875 if (!i)
876 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
877
878}
879
880static int
881jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
882{
883 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
884 return false;
885
886 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
887 == RXWBFLAG_TCPON)) {
888 if (flags & RXWBFLAG_IPV4)
889 msg_rx_err(jme, "TCP Checksum error\n");
890 return false;
891 }
892
893 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
894 == RXWBFLAG_UDPON)) {
895 if (flags & RXWBFLAG_IPV4)
896 msg_rx_err(jme, "UDP Checksum error.\n");
897 return false;
898 }
899
900 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
901 == RXWBFLAG_IPV4)) {
902 msg_rx_err(jme, "IPv4 Checksum error.\n");
903 return false;
904 }
905
906 return true;
907}
908
909static void
910jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
911{
912 struct jme_ring *rxring = &(jme->rxring[0]);
913 struct rxdesc *rxdesc = rxring->desc;
914 struct jme_buffer_info *rxbi = rxring->bufinf;
915 struct sk_buff *skb;
916 int framesize;
917
918 rxdesc += idx;
919 rxbi += idx;
920
921 skb = rxbi->skb;
922 pci_dma_sync_single_for_cpu(jme->pdev,
923 rxbi->mapping,
924 rxbi->len,
925 PCI_DMA_FROMDEVICE);
926
927 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
928 pci_dma_sync_single_for_device(jme->pdev,
929 rxbi->mapping,
930 rxbi->len,
931 PCI_DMA_FROMDEVICE);
932
933 ++(NET_STAT(jme).rx_dropped);
934 } else {
935 framesize = le16_to_cpu(rxdesc->descwb.framesize)
936 - RX_PREPAD_SIZE;
937
938 skb_reserve(skb, RX_PREPAD_SIZE);
939 skb_put(skb, framesize);
940 skb->protocol = eth_type_trans(skb, jme->dev);
941
942 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
943 skb->ip_summed = CHECKSUM_UNNECESSARY;
944 else
945 skb->ip_summed = CHECKSUM_NONE;
946
947 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
948 if (jme->vlgrp) {
949 jme->jme_vlan_rx(skb, jme->vlgrp,
950 le16_to_cpu(rxdesc->descwb.vlan));
951 NET_STAT(jme).rx_bytes += 4;
952 }
953 } else {
954 jme->jme_rx(skb);
955 }
956
957 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
958 cpu_to_le16(RXWBFLAG_DEST_MUL))
959 ++(NET_STAT(jme).multicast);
960
961 NET_STAT(jme).rx_bytes += framesize;
962 ++(NET_STAT(jme).rx_packets);
963 }
964
965 jme_set_clean_rxdesc(jme, idx);
966
967}
968
969static int
970jme_process_receive(struct jme_adapter *jme, int limit)
971{
972 struct jme_ring *rxring = &(jme->rxring[0]);
973 struct rxdesc *rxdesc = rxring->desc;
974 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
975
976 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
977 goto out_inc;
978
979 if (unlikely(atomic_read(&jme->link_changing) != 1))
980 goto out_inc;
981
982 if (unlikely(!netif_carrier_ok(jme->dev)))
983 goto out_inc;
984
985 i = atomic_read(&rxring->next_to_clean);
986 while (limit > 0) {
987 rxdesc = rxring->desc;
988 rxdesc += i;
989
990 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
991 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
992 goto out;
993 --limit;
994
995 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
996
997 if (unlikely(desccnt > 1 ||
998 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
999
1000 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1001 ++(NET_STAT(jme).rx_crc_errors);
1002 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1003 ++(NET_STAT(jme).rx_fifo_errors);
1004 else
1005 ++(NET_STAT(jme).rx_errors);
1006
1007 if (desccnt > 1)
1008 limit -= desccnt - 1;
1009
1010 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1011 jme_set_clean_rxdesc(jme, j);
1012 j = (j + 1) & (mask);
1013 }
1014
1015 } else {
1016 jme_alloc_and_feed_skb(jme, i);
1017 }
1018
1019 i = (i + desccnt) & (mask);
1020 }
1021
1022out:
1023 atomic_set(&rxring->next_to_clean, i);
1024
1025out_inc:
1026 atomic_inc(&jme->rx_cleaning);
1027
1028 return limit > 0 ? limit : 0;
1029
1030}
1031
1032static void
1033jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1034{
1035 if (likely(atmp == dpi->cur)) {
1036 dpi->cnt = 0;
1037 return;
1038 }
1039
1040 if (dpi->attempt == atmp) {
1041 ++(dpi->cnt);
1042 } else {
1043 dpi->attempt = atmp;
1044 dpi->cnt = 0;
1045 }
1046
1047}
1048
1049static void
1050jme_dynamic_pcc(struct jme_adapter *jme)
1051{
1052 register struct dynpcc_info *dpi = &(jme->dpi);
1053
1054 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1055 jme_attempt_pcc(dpi, PCC_P3);
1056 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1057 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1058 jme_attempt_pcc(dpi, PCC_P2);
1059 else
1060 jme_attempt_pcc(dpi, PCC_P1);
1061
1062 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1063 if (dpi->attempt < dpi->cur)
1064 tasklet_schedule(&jme->rxclean_task);
1065 jme_set_rx_pcc(jme, dpi->attempt);
1066 dpi->cur = dpi->attempt;
1067 dpi->cnt = 0;
1068 }
1069}
1070
1071static void
1072jme_start_pcc_timer(struct jme_adapter *jme)
1073{
1074 struct dynpcc_info *dpi = &(jme->dpi);
1075 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1076 dpi->last_pkts = NET_STAT(jme).rx_packets;
1077 dpi->intr_cnt = 0;
1078 jwrite32(jme, JME_TMCSR,
1079 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1080}
1081
1082static inline void
1083jme_stop_pcc_timer(struct jme_adapter *jme)
1084{
1085 jwrite32(jme, JME_TMCSR, 0);
1086}
1087
1088static void
1089jme_shutdown_nic(struct jme_adapter *jme)
1090{
1091 u32 phylink;
1092
1093 phylink = jme_linkstat_from_phy(jme);
1094
1095 if (!(phylink & PHY_LINK_UP)) {
1096 /*
1097 * Disable all interrupt before issue timer
1098 */
1099 jme_stop_irq(jme);
1100 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1101 }
1102}
1103
1104static void
1105jme_pcc_tasklet(unsigned long arg)
1106{
1107 struct jme_adapter *jme = (struct jme_adapter *)arg;
1108 struct net_device *netdev = jme->dev;
1109
1110 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1111 jme_shutdown_nic(jme);
1112 return;
1113 }
1114
1115 if (unlikely(!netif_carrier_ok(netdev) ||
1116 (atomic_read(&jme->link_changing) != 1)
1117 )) {
1118 jme_stop_pcc_timer(jme);
1119 return;
1120 }
1121
1122 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1123 jme_dynamic_pcc(jme);
1124
1125 jme_start_pcc_timer(jme);
1126}
1127
1128static inline void
1129jme_polling_mode(struct jme_adapter *jme)
1130{
1131 jme_set_rx_pcc(jme, PCC_OFF);
1132}
1133
1134static inline void
1135jme_interrupt_mode(struct jme_adapter *jme)
1136{
1137 jme_set_rx_pcc(jme, PCC_P1);
1138}
1139
1140static inline int
1141jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1142{
1143 u32 apmc;
1144 apmc = jread32(jme, JME_APMC);
1145 return apmc & JME_APMC_PSEUDO_HP_EN;
1146}
1147
1148static void
1149jme_start_shutdown_timer(struct jme_adapter *jme)
1150{
1151 u32 apmc;
1152
1153 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1154 apmc &= ~JME_APMC_EPIEN_CTRL;
1155 if (!no_extplug) {
1156 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1157 wmb();
1158 }
1159 jwrite32f(jme, JME_APMC, apmc);
1160
1161 jwrite32f(jme, JME_TIMER2, 0);
1162 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1163 jwrite32(jme, JME_TMCSR,
1164 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1165}
1166
1167static void
1168jme_stop_shutdown_timer(struct jme_adapter *jme)
1169{
1170 u32 apmc;
1171
1172 jwrite32f(jme, JME_TMCSR, 0);
1173 jwrite32f(jme, JME_TIMER2, 0);
1174 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1175
1176 apmc = jread32(jme, JME_APMC);
1177 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1178 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1179 wmb();
1180 jwrite32f(jme, JME_APMC, apmc);
1181}
1182
1183static void
1184jme_link_change_tasklet(unsigned long arg)
1185{
1186 struct jme_adapter *jme = (struct jme_adapter *)arg;
1187 struct net_device *netdev = jme->dev;
1188 int rc;
1189
1190 while (!atomic_dec_and_test(&jme->link_changing)) {
1191 atomic_inc(&jme->link_changing);
1192 msg_intr(jme, "Get link change lock failed.\n");
1193 while (atomic_read(&jme->link_changing) != 1)
1194 msg_intr(jme, "Waiting link change lock.\n");
1195 }
1196
1197 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1198 goto out;
1199
1200 jme->old_mtu = netdev->mtu;
1201 netif_stop_queue(netdev);
1202 if (jme_pseudo_hotplug_enabled(jme))
1203 jme_stop_shutdown_timer(jme);
1204
1205 jme_stop_pcc_timer(jme);
1206 tasklet_disable(&jme->txclean_task);
1207 tasklet_disable(&jme->rxclean_task);
1208 tasklet_disable(&jme->rxempty_task);
1209
1210 if (netif_carrier_ok(netdev)) {
1211 jme_reset_ghc_speed(jme);
1212 jme_disable_rx_engine(jme);
1213 jme_disable_tx_engine(jme);
1214 jme_reset_mac_processor(jme);
1215 jme_free_rx_resources(jme);
1216 jme_free_tx_resources(jme);
1217
1218 if (test_bit(JME_FLAG_POLL, &jme->flags))
1219 jme_polling_mode(jme);
1220
1221 netif_carrier_off(netdev);
1222 }
1223
1224 jme_check_link(netdev, 0);
1225 if (netif_carrier_ok(netdev)) {
1226 rc = jme_setup_rx_resources(jme);
1227 if (rc) {
1228 jeprintk(jme->pdev, "Allocating resources for RX error"
1229 ", Device STOPPED!\n");
1230 goto out_enable_tasklet;
1231 }
1232
1233 rc = jme_setup_tx_resources(jme);
1234 if (rc) {
1235 jeprintk(jme->pdev, "Allocating resources for TX error"
1236 ", Device STOPPED!\n");
1237 goto err_out_free_rx_resources;
1238 }
1239
1240 jme_enable_rx_engine(jme);
1241 jme_enable_tx_engine(jme);
1242
1243 netif_start_queue(netdev);
1244
1245 if (test_bit(JME_FLAG_POLL, &jme->flags))
1246 jme_interrupt_mode(jme);
1247
1248 jme_start_pcc_timer(jme);
1249 } else if (jme_pseudo_hotplug_enabled(jme)) {
1250 jme_start_shutdown_timer(jme);
1251 }
1252
1253 goto out_enable_tasklet;
1254
1255err_out_free_rx_resources:
1256 jme_free_rx_resources(jme);
1257out_enable_tasklet:
1258 tasklet_enable(&jme->txclean_task);
1259 tasklet_hi_enable(&jme->rxclean_task);
1260 tasklet_hi_enable(&jme->rxempty_task);
1261out:
1262 atomic_inc(&jme->link_changing);
1263}
1264
1265static void
1266jme_rx_clean_tasklet(unsigned long arg)
1267{
1268 struct jme_adapter *jme = (struct jme_adapter *)arg;
1269 struct dynpcc_info *dpi = &(jme->dpi);
1270
1271 jme_process_receive(jme, jme->rx_ring_size);
1272 ++(dpi->intr_cnt);
1273
1274}
1275
1276static int
1277jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1278{
1279 struct jme_adapter *jme = jme_napi_priv(holder);
1280 DECLARE_NETDEV
1281 int rest;
1282
1283 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1284
1285 while (atomic_read(&jme->rx_empty) > 0) {
1286 atomic_dec(&jme->rx_empty);
1287 ++(NET_STAT(jme).rx_dropped);
1288 jme_restart_rx_engine(jme);
1289 }
1290 atomic_inc(&jme->rx_empty);
1291
1292 if (rest) {
1293 JME_RX_COMPLETE(netdev, holder);
1294 jme_interrupt_mode(jme);
1295 }
1296
1297 JME_NAPI_WEIGHT_SET(budget, rest);
1298 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1299}
1300
1301static void
1302jme_rx_empty_tasklet(unsigned long arg)
1303{
1304 struct jme_adapter *jme = (struct jme_adapter *)arg;
1305
1306 if (unlikely(atomic_read(&jme->link_changing) != 1))
1307 return;
1308
1309 if (unlikely(!netif_carrier_ok(jme->dev)))
1310 return;
1311
1312 msg_rx_status(jme, "RX Queue Full!\n");
1313
1314 jme_rx_clean_tasklet(arg);
1315
1316 while (atomic_read(&jme->rx_empty) > 0) {
1317 atomic_dec(&jme->rx_empty);
1318 ++(NET_STAT(jme).rx_dropped);
1319 jme_restart_rx_engine(jme);
1320 }
1321 atomic_inc(&jme->rx_empty);
1322}
1323
1324static void
1325jme_wake_queue_if_stopped(struct jme_adapter *jme)
1326{
1327 struct jme_ring *txring = &(jme->txring[0]);
1328
1329 smp_wmb();
1330 if (unlikely(netif_queue_stopped(jme->dev) &&
1331 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1332 msg_tx_done(jme, "TX Queue Waked.\n");
1333 netif_wake_queue(jme->dev);
1334 }
1335
1336}
1337
1338static void
1339jme_tx_clean_tasklet(unsigned long arg)
1340{
1341 struct jme_adapter *jme = (struct jme_adapter *)arg;
1342 struct jme_ring *txring = &(jme->txring[0]);
1343 struct txdesc *txdesc = txring->desc;
1344 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1345 int i, j, cnt = 0, max, err, mask;
1346
1347 tx_dbg(jme, "Into txclean.\n");
1348
1349 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1350 goto out;
1351
1352 if (unlikely(atomic_read(&jme->link_changing) != 1))
1353 goto out;
1354
1355 if (unlikely(!netif_carrier_ok(jme->dev)))
1356 goto out;
1357
1358 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1359 mask = jme->tx_ring_mask;
1360
1361 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1362
1363 ctxbi = txbi + i;
1364
1365 if (likely(ctxbi->skb &&
1366 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1367
1368 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1369 i, ctxbi->nr_desc, jiffies);
1370
1371 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1372
1373 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1374 ttxbi = txbi + ((i + j) & (mask));
1375 txdesc[(i + j) & (mask)].dw[0] = 0;
1376
1377 pci_unmap_page(jme->pdev,
1378 ttxbi->mapping,
1379 ttxbi->len,
1380 PCI_DMA_TODEVICE);
1381
1382 ttxbi->mapping = 0;
1383 ttxbi->len = 0;
1384 }
1385
1386 dev_kfree_skb(ctxbi->skb);
1387
1388 cnt += ctxbi->nr_desc;
1389
1390 if (unlikely(err)) {
1391 ++(NET_STAT(jme).tx_carrier_errors);
1392 } else {
1393 ++(NET_STAT(jme).tx_packets);
1394 NET_STAT(jme).tx_bytes += ctxbi->len;
1395 }
1396
1397 ctxbi->skb = NULL;
1398 ctxbi->len = 0;
1399 ctxbi->start_xmit = 0;
1400
1401 } else {
1402 break;
1403 }
1404
1405 i = (i + ctxbi->nr_desc) & mask;
1406
1407 ctxbi->nr_desc = 0;
1408 }
1409
1410 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1411 atomic_set(&txring->next_to_clean, i);
1412 atomic_add(cnt, &txring->nr_free);
1413
1414 jme_wake_queue_if_stopped(jme);
1415
1416out:
1417 atomic_inc(&jme->tx_cleaning);
1418}
1419
1420static void
1421jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1422{
1423 /*
1424 * Disable interrupt
1425 */
1426 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1427
1428 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1429 /*
1430 * Link change event is critical
1431 * all other events are ignored
1432 */
1433 jwrite32(jme, JME_IEVE, intrstat);
1434 tasklet_schedule(&jme->linkch_task);
1435 goto out_reenable;
1436 }
1437
1438 if (intrstat & INTR_TMINTR) {
1439 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1440 tasklet_schedule(&jme->pcc_task);
1441 }
1442
1443 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1444 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1445 tasklet_schedule(&jme->txclean_task);
1446 }
1447
1448 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1449 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1450 INTR_PCCRX0 |
1451 INTR_RX0EMP)) |
1452 INTR_RX0);
1453 }
1454
1455 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1456 if (intrstat & INTR_RX0EMP)
1457 atomic_inc(&jme->rx_empty);
1458
1459 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1460 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1461 jme_polling_mode(jme);
1462 JME_RX_SCHEDULE(jme);
1463 }
1464 }
1465 } else {
1466 if (intrstat & INTR_RX0EMP) {
1467 atomic_inc(&jme->rx_empty);
1468 tasklet_hi_schedule(&jme->rxempty_task);
1469 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1470 tasklet_hi_schedule(&jme->rxclean_task);
1471 }
1472 }
1473
1474out_reenable:
1475 /*
1476 * Re-enable interrupt
1477 */
1478 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1479}
1480
1481#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1482static irqreturn_t
1483jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1484#else
1485static irqreturn_t
1486jme_intr(int irq, void *dev_id)
1487#endif
1488{
1489 struct net_device *netdev = dev_id;
1490 struct jme_adapter *jme = netdev_priv(netdev);
1491 u32 intrstat;
1492
1493 intrstat = jread32(jme, JME_IEVE);
1494
1495 /*
1496 * Check if it's really an interrupt for us
1497 */
1498 if (unlikely((intrstat & INTR_ENABLE) == 0))
1499 return IRQ_NONE;
1500
1501 /*
1502 * Check if the device still exist
1503 */
1504 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1505 return IRQ_NONE;
1506
1507 jme_intr_msi(jme, intrstat);
1508
1509 return IRQ_HANDLED;
1510}
1511
1512#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1513static irqreturn_t
1514jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1515#else
1516static irqreturn_t
1517jme_msi(int irq, void *dev_id)
1518#endif
1519{
1520 struct net_device *netdev = dev_id;
1521 struct jme_adapter *jme = netdev_priv(netdev);
1522 u32 intrstat;
1523
1524 intrstat = jread32(jme, JME_IEVE);
1525
1526 jme_intr_msi(jme, intrstat);
1527
1528 return IRQ_HANDLED;
1529}
1530
1531static void
1532jme_reset_link(struct jme_adapter *jme)
1533{
1534 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1535}
1536
1537static void
1538jme_restart_an(struct jme_adapter *jme)
1539{
1540 u32 bmcr;
1541
1542 spin_lock_bh(&jme->phy_lock);
1543 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1544 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1545 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1546 spin_unlock_bh(&jme->phy_lock);
1547}
1548
1549static int
1550jme_request_irq(struct jme_adapter *jme)
1551{
1552 int rc;
1553 struct net_device *netdev = jme->dev;
1554#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1555 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1556 int irq_flags = SA_SHIRQ;
1557#else
1558 irq_handler_t handler = jme_intr;
1559 int irq_flags = IRQF_SHARED;
1560#endif
1561
1562 if (!pci_enable_msi(jme->pdev)) {
1563 set_bit(JME_FLAG_MSI, &jme->flags);
1564 handler = jme_msi;
1565 irq_flags = 0;
1566 }
1567
1568 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1569 netdev);
1570 if (rc) {
1571 jeprintk(jme->pdev,
1572 "Unable to request %s interrupt (return: %d)\n",
1573 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1574 rc);
1575
1576 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1577 pci_disable_msi(jme->pdev);
1578 clear_bit(JME_FLAG_MSI, &jme->flags);
1579 }
1580 } else {
1581 netdev->irq = jme->pdev->irq;
1582 }
1583
1584 return rc;
1585}
1586
1587static void
1588jme_free_irq(struct jme_adapter *jme)
1589{
1590 free_irq(jme->pdev->irq, jme->dev);
1591 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1592 pci_disable_msi(jme->pdev);
1593 clear_bit(JME_FLAG_MSI, &jme->flags);
1594 jme->dev->irq = jme->pdev->irq;
1595 }
1596}
1597
1598static int
1599jme_open(struct net_device *netdev)
1600{
1601 struct jme_adapter *jme = netdev_priv(netdev);
1602 int rc;
1603
1604 jme_clear_pm(jme);
1605 JME_NAPI_ENABLE(jme);
1606
1607 tasklet_enable(&jme->linkch_task);
1608 tasklet_enable(&jme->txclean_task);
1609 tasklet_hi_enable(&jme->rxclean_task);
1610 tasklet_hi_enable(&jme->rxempty_task);
1611
1612 rc = jme_request_irq(jme);
1613 if (rc)
1614 goto err_out;
1615
1616 jme_start_irq(jme);
1617
1618 if (test_bit(JME_FLAG_SSET, &jme->flags))
1619 jme_set_settings(netdev, &jme->old_ecmd);
1620 else
1621 jme_reset_phy_processor(jme);
1622
1623 jme_reset_link(jme);
1624
1625 return 0;
1626
1627err_out:
1628 netif_stop_queue(netdev);
1629 netif_carrier_off(netdev);
1630 return rc;
1631}
1632
1633#ifdef CONFIG_PM
1634static void
1635jme_set_100m_half(struct jme_adapter *jme)
1636{
1637 u32 bmcr, tmp;
1638
1639 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1640 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1641 BMCR_SPEED1000 | BMCR_FULLDPLX);
1642 tmp |= BMCR_SPEED100;
1643
1644 if (bmcr != tmp)
1645 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1646
1647 if (jme->fpgaver)
1648 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1649 else
1650 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1651}
1652
1653#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1654static void
1655jme_wait_link(struct jme_adapter *jme)
1656{
1657 u32 phylink, to = JME_WAIT_LINK_TIME;
1658
1659 mdelay(1000);
1660 phylink = jme_linkstat_from_phy(jme);
1661 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1662 mdelay(10);
1663 phylink = jme_linkstat_from_phy(jme);
1664 }
1665}
1666#endif
1667
1668static inline void
1669jme_phy_off(struct jme_adapter *jme)
1670{
1671 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1672}
1673
1674static int
1675jme_close(struct net_device *netdev)
1676{
1677 struct jme_adapter *jme = netdev_priv(netdev);
1678
1679 netif_stop_queue(netdev);
1680 netif_carrier_off(netdev);
1681
1682 jme_stop_irq(jme);
1683 jme_free_irq(jme);
1684
1685 JME_NAPI_DISABLE(jme);
1686
1687 tasklet_disable(&jme->linkch_task);
1688 tasklet_disable(&jme->txclean_task);
1689 tasklet_disable(&jme->rxclean_task);
1690 tasklet_disable(&jme->rxempty_task);
1691
1692 jme_reset_ghc_speed(jme);
1693 jme_disable_rx_engine(jme);
1694 jme_disable_tx_engine(jme);
1695 jme_reset_mac_processor(jme);
1696 jme_free_rx_resources(jme);
1697 jme_free_tx_resources(jme);
1698 jme->phylink = 0;
1699 jme_phy_off(jme);
1700
1701 return 0;
1702}
1703
1704static int
1705jme_alloc_txdesc(struct jme_adapter *jme,
1706 struct sk_buff *skb)
1707{
1708 struct jme_ring *txring = &(jme->txring[0]);
1709 int idx, nr_alloc, mask = jme->tx_ring_mask;
1710
1711 idx = txring->next_to_use;
1712 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1713
1714 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1715 return -1;
1716
1717 atomic_sub(nr_alloc, &txring->nr_free);
1718
1719 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1720
1721 return idx;
1722}
1723
1724static void
1725jme_fill_tx_map(struct pci_dev *pdev,
1726 struct txdesc *txdesc,
1727 struct jme_buffer_info *txbi,
1728 struct page *page,
1729 u32 page_offset,
1730 u32 len,
1731 u8 hidma)
1732{
1733 dma_addr_t dmaaddr;
1734
1735 dmaaddr = pci_map_page(pdev,
1736 page,
1737 page_offset,
1738 len,
1739 PCI_DMA_TODEVICE);
1740
1741 pci_dma_sync_single_for_device(pdev,
1742 dmaaddr,
1743 len,
1744 PCI_DMA_TODEVICE);
1745
1746 txdesc->dw[0] = 0;
1747 txdesc->dw[1] = 0;
1748 txdesc->desc2.flags = TXFLAG_OWN;
1749 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1750 txdesc->desc2.datalen = cpu_to_le16(len);
1751 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1752 txdesc->desc2.bufaddrl = cpu_to_le32(
1753 (__u64)dmaaddr & 0xFFFFFFFFUL);
1754
1755 txbi->mapping = dmaaddr;
1756 txbi->len = len;
1757}
1758
1759static void
1760jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1761{
1762 struct jme_ring *txring = &(jme->txring[0]);
1763 struct txdesc *txdesc = txring->desc, *ctxdesc;
1764 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1765 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1766 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1767 int mask = jme->tx_ring_mask;
1768 struct skb_frag_struct *frag;
1769 u32 len;
1770
1771 for (i = 0 ; i < nr_frags ; ++i) {
1772 frag = &skb_shinfo(skb)->frags[i];
1773 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1774 ctxbi = txbi + ((idx + i + 2) & (mask));
1775
1776 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1777 frag->page_offset, frag->size, hidma);
1778 }
1779
1780 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1781 ctxdesc = txdesc + ((idx + 1) & (mask));
1782 ctxbi = txbi + ((idx + 1) & (mask));
1783 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1784 offset_in_page(skb->data), len, hidma);
1785
1786}
1787
1788static int
1789jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1790{
1791 if (unlikely(
1792#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1793 skb_shinfo(skb)->tso_size
1794#else
1795 skb_shinfo(skb)->gso_size
1796#endif
1797 && skb_header_cloned(skb) &&
1798 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1799 dev_kfree_skb(skb);
1800 return -1;
1801 }
1802
1803 return 0;
1804}
1805
1806static int
1807jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1808{
1809#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1810 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1811#else
1812 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1813#endif
1814 if (*mss) {
1815 *flags |= TXFLAG_LSEN;
1816
1817 if (skb->protocol == htons(ETH_P_IP)) {
1818 struct iphdr *iph = ip_hdr(skb);
1819
1820 iph->check = 0;
1821 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1822 iph->daddr, 0,
1823 IPPROTO_TCP,
1824 0);
1825 } else {
1826 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1827
1828 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1829 &ip6h->daddr, 0,
1830 IPPROTO_TCP,
1831 0);
1832 }
1833
1834 return 0;
1835 }
1836
1837 return 1;
1838}
1839
1840static void
1841jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1842{
1843#ifdef CHECKSUM_PARTIAL
1844 if (skb->ip_summed == CHECKSUM_PARTIAL)
1845#else
1846 if (skb->ip_summed == CHECKSUM_HW)
1847#endif
1848 {
1849 u8 ip_proto;
1850
1851#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1852 if (skb->protocol == htons(ETH_P_IP))
1853 ip_proto = ip_hdr(skb)->protocol;
1854 else if (skb->protocol == htons(ETH_P_IPV6))
1855 ip_proto = ipv6_hdr(skb)->nexthdr;
1856 else
1857 ip_proto = 0;
1858#else
1859 switch (skb->protocol) {
1860 case htons(ETH_P_IP):
1861 ip_proto = ip_hdr(skb)->protocol;
1862 break;
1863 case htons(ETH_P_IPV6):
1864 ip_proto = ipv6_hdr(skb)->nexthdr;
1865 break;
1866 default:
1867 ip_proto = 0;
1868 break;
1869 }
1870#endif
1871
1872 switch (ip_proto) {
1873 case IPPROTO_TCP:
1874 *flags |= TXFLAG_TCPCS;
1875 break;
1876 case IPPROTO_UDP:
1877 *flags |= TXFLAG_UDPCS;
1878 break;
1879 default:
1880 msg_tx_err(jme, "Error upper layer protocol.\n");
1881 break;
1882 }
1883 }
1884}
1885
1886static inline void
1887jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1888{
1889 if (vlan_tx_tag_present(skb)) {
1890 *flags |= TXFLAG_TAGON;
1891 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1892 }
1893}
1894
1895static int
1896jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1897{
1898 struct jme_ring *txring = &(jme->txring[0]);
1899 struct txdesc *txdesc;
1900 struct jme_buffer_info *txbi;
1901 u8 flags;
1902
1903 txdesc = (struct txdesc *)txring->desc + idx;
1904 txbi = txring->bufinf + idx;
1905
1906 txdesc->dw[0] = 0;
1907 txdesc->dw[1] = 0;
1908 txdesc->dw[2] = 0;
1909 txdesc->dw[3] = 0;
1910 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1911 /*
1912 * Set OWN bit at final.
1913 * When kernel transmit faster than NIC.
1914 * And NIC trying to send this descriptor before we tell
1915 * it to start sending this TX queue.
1916 * Other fields are already filled correctly.
1917 */
1918 wmb();
1919 flags = TXFLAG_OWN | TXFLAG_INT;
1920 /*
1921 * Set checksum flags while not tso
1922 */
1923 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1924 jme_tx_csum(jme, skb, &flags);
1925 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1926 jme_map_tx_skb(jme, skb, idx);
1927 txdesc->desc1.flags = flags;
1928 /*
1929 * Set tx buffer info after telling NIC to send
1930 * For better tx_clean timing
1931 */
1932 wmb();
1933 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1934 txbi->skb = skb;
1935 txbi->len = skb->len;
1936 txbi->start_xmit = jiffies;
1937 if (!txbi->start_xmit)
1938 txbi->start_xmit = (0UL-1);
1939
1940 return 0;
1941}
1942
1943static void
1944jme_stop_queue_if_full(struct jme_adapter *jme)
1945{
1946 struct jme_ring *txring = &(jme->txring[0]);
1947 struct jme_buffer_info *txbi = txring->bufinf;
1948 int idx = atomic_read(&txring->next_to_clean);
1949
1950 txbi += idx;
1951
1952 smp_wmb();
1953 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1954 netif_stop_queue(jme->dev);
1955 msg_tx_queued(jme, "TX Queue Paused.\n");
1956 smp_wmb();
1957 if (atomic_read(&txring->nr_free)
1958 >= (jme->tx_wake_threshold)) {
1959 netif_wake_queue(jme->dev);
1960 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1961 }
1962 }
1963
1964 if (unlikely(txbi->start_xmit &&
1965 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1966 txbi->skb)) {
1967 netif_stop_queue(jme->dev);
1968 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1969 }
1970}
1971
1972/*
1973 * This function is already protected by netif_tx_lock()
1974 */
1975
1976static int
1977jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1978{
1979 struct jme_adapter *jme = netdev_priv(netdev);
1980 int idx;
1981
1982 if (unlikely(jme_expand_header(jme, skb))) {
1983 ++(NET_STAT(jme).tx_dropped);
1984 return NETDEV_TX_OK;
1985 }
1986
1987 idx = jme_alloc_txdesc(jme, skb);
1988
1989 if (unlikely(idx < 0)) {
1990 netif_stop_queue(netdev);
1991 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1992
1993 return NETDEV_TX_BUSY;
1994 }
1995
1996 jme_fill_tx_desc(jme, skb, idx);
1997
1998 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1999 TXCS_SELECT_QUEUE0 |
2000 TXCS_QUEUE0S |
2001 TXCS_ENABLE);
2002#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2003 netdev->trans_start = jiffies;
2004#endif
2005
2006 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
2007 skb_shinfo(skb)->nr_frags + 2,
2008 jiffies);
2009 jme_stop_queue_if_full(jme);
2010
2011 return NETDEV_TX_OK;
2012}
2013
2014static int
2015jme_set_macaddr(struct net_device *netdev, void *p)
2016{
2017 struct jme_adapter *jme = netdev_priv(netdev);
2018 struct sockaddr *addr = p;
2019 u32 val;
2020
2021 if (netif_running(netdev))
2022 return -EBUSY;
2023
2024 spin_lock_bh(&jme->macaddr_lock);
2025 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2026
2027 val = (addr->sa_data[3] & 0xff) << 24 |
2028 (addr->sa_data[2] & 0xff) << 16 |
2029 (addr->sa_data[1] & 0xff) << 8 |
2030 (addr->sa_data[0] & 0xff);
2031 jwrite32(jme, JME_RXUMA_LO, val);
2032 val = (addr->sa_data[5] & 0xff) << 8 |
2033 (addr->sa_data[4] & 0xff);
2034 jwrite32(jme, JME_RXUMA_HI, val);
2035 spin_unlock_bh(&jme->macaddr_lock);
2036
2037 return 0;
2038}
2039
2040static void
2041jme_set_multi(struct net_device *netdev)
2042{
2043 struct jme_adapter *jme = netdev_priv(netdev);
2044 u32 mc_hash[2] = {};
2045 int i;
2046
2047 spin_lock_bh(&jme->rxmcs_lock);
2048
2049 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2050
2051 if (netdev->flags & IFF_PROMISC) {
2052 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2053 } else if (netdev->flags & IFF_ALLMULTI) {
2054 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2055 } else if (netdev->flags & IFF_MULTICAST) {
2056 struct dev_mc_list *mclist;
2057 int bit_nr;
2058
2059 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2060 for (i = 0, mclist = netdev->mc_list;
2061 mclist && i < netdev->mc_count;
2062 ++i, mclist = mclist->next) {
2063
2064 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2065 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2066 }
2067
2068 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2069 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2070 }
2071
2072 wmb();
2073 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2074
2075 spin_unlock_bh(&jme->rxmcs_lock);
2076}
2077
2078static int
2079jme_change_mtu(struct net_device *netdev, int new_mtu)
2080{
2081 struct jme_adapter *jme = netdev_priv(netdev);
2082
2083 if (new_mtu == jme->old_mtu)
2084 return 0;
2085
2086 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2087 ((new_mtu) < IPV6_MIN_MTU))
2088 return -EINVAL;
2089
2090 if (new_mtu > 4000) {
2091 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2092 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2093 jme_restart_rx_engine(jme);
2094 } else {
2095 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2096 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2097 jme_restart_rx_engine(jme);
2098 }
2099
2100 if (new_mtu > 1900) {
2101 netdev->features &= ~(NETIF_F_HW_CSUM |
2102 NETIF_F_TSO
2103#ifdef NETIF_F_TSO6
2104 | NETIF_F_TSO6
2105#endif
2106 );
2107 } else {
2108 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2109 netdev->features |= NETIF_F_HW_CSUM;
2110 if (test_bit(JME_FLAG_TSO, &jme->flags))
2111 netdev->features |= NETIF_F_TSO
2112#ifdef NETIF_F_TSO6
2113 | NETIF_F_TSO6
2114#endif
2115 ;
2116 }
2117
2118 netdev->mtu = new_mtu;
2119 jme_reset_link(jme);
2120
2121 return 0;
2122}
2123
2124static void
2125jme_tx_timeout(struct net_device *netdev)
2126{
2127 struct jme_adapter *jme = netdev_priv(netdev);
2128
2129 jme->phylink = 0;
2130 jme_reset_phy_processor(jme);
2131 if (test_bit(JME_FLAG_SSET, &jme->flags))
2132 jme_set_settings(netdev, &jme->old_ecmd);
2133
2134 /*
2135 * Force to Reset the link again
2136 */
2137 jme_reset_link(jme);
2138}
2139
2140static void
2141jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2142{
2143 struct jme_adapter *jme = netdev_priv(netdev);
2144
2145 jme->vlgrp = grp;
2146}
2147
2148static void
2149jme_get_drvinfo(struct net_device *netdev,
2150 struct ethtool_drvinfo *info)
2151{
2152 struct jme_adapter *jme = netdev_priv(netdev);
2153
2154 strcpy(info->driver, DRV_NAME);
2155 strcpy(info->version, DRV_VERSION);
2156 strcpy(info->bus_info, pci_name(jme->pdev));
2157}
2158
2159static int
2160jme_get_regs_len(struct net_device *netdev)
2161{
2162 return JME_REG_LEN;
2163}
2164
2165static void
2166mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2167{
2168 int i;
2169
2170 for (i = 0 ; i < len ; i += 4)
2171 p[i >> 2] = jread32(jme, reg + i);
2172}
2173
2174static void
2175mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2176{
2177 int i;
2178 u16 *p16 = (u16 *)p;
2179
2180 for (i = 0 ; i < reg_nr ; ++i)
2181 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2182}
2183
2184static void
2185jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2186{
2187 struct jme_adapter *jme = netdev_priv(netdev);
2188 u32 *p32 = (u32 *)p;
2189
2190 memset(p, 0xFF, JME_REG_LEN);
2191
2192 regs->version = 1;
2193 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2194
2195 p32 += 0x100 >> 2;
2196 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2197
2198 p32 += 0x100 >> 2;
2199 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2200
2201 p32 += 0x100 >> 2;
2202 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2203
2204 p32 += 0x100 >> 2;
2205 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2206}
2207
2208static int
2209jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2210{
2211 struct jme_adapter *jme = netdev_priv(netdev);
2212
2213 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2214 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2215
2216 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2217 ecmd->use_adaptive_rx_coalesce = false;
2218 ecmd->rx_coalesce_usecs = 0;
2219 ecmd->rx_max_coalesced_frames = 0;
2220 return 0;
2221 }
2222
2223 ecmd->use_adaptive_rx_coalesce = true;
2224
2225 switch (jme->dpi.cur) {
2226 case PCC_P1:
2227 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2228 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2229 break;
2230 case PCC_P2:
2231 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2232 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2233 break;
2234 case PCC_P3:
2235 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2236 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2237 break;
2238 default:
2239 break;
2240 }
2241
2242 return 0;
2243}
2244
2245static int
2246jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2247{
2248 struct jme_adapter *jme = netdev_priv(netdev);
2249 struct dynpcc_info *dpi = &(jme->dpi);
2250
2251 if (netif_running(netdev))
2252 return -EBUSY;
2253
2254 if (ecmd->use_adaptive_rx_coalesce
2255 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2256 clear_bit(JME_FLAG_POLL, &jme->flags);
2257 jme->jme_rx = netif_rx;
2258 jme->jme_vlan_rx = vlan_hwaccel_rx;
2259 dpi->cur = PCC_P1;
2260 dpi->attempt = PCC_P1;
2261 dpi->cnt = 0;
2262 jme_set_rx_pcc(jme, PCC_P1);
2263 jme_interrupt_mode(jme);
2264 } else if (!(ecmd->use_adaptive_rx_coalesce)
2265 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2266 set_bit(JME_FLAG_POLL, &jme->flags);
2267 jme->jme_rx = netif_receive_skb;
2268 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2269 jme_interrupt_mode(jme);
2270 }
2271
2272 return 0;
2273}
2274
2275static void
2276jme_get_pauseparam(struct net_device *netdev,
2277 struct ethtool_pauseparam *ecmd)
2278{
2279 struct jme_adapter *jme = netdev_priv(netdev);
2280 u32 val;
2281
2282 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2283 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2284
2285 spin_lock_bh(&jme->phy_lock);
2286 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2287 spin_unlock_bh(&jme->phy_lock);
2288
2289 ecmd->autoneg =
2290 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2291}
2292
2293static int
2294jme_set_pauseparam(struct net_device *netdev,
2295 struct ethtool_pauseparam *ecmd)
2296{
2297 struct jme_adapter *jme = netdev_priv(netdev);
2298 u32 val;
2299
2300 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2301 (ecmd->tx_pause != 0)) {
2302
2303 if (ecmd->tx_pause)
2304 jme->reg_txpfc |= TXPFC_PF_EN;
2305 else
2306 jme->reg_txpfc &= ~TXPFC_PF_EN;
2307
2308 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2309 }
2310
2311 spin_lock_bh(&jme->rxmcs_lock);
2312 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2313 (ecmd->rx_pause != 0)) {
2314
2315 if (ecmd->rx_pause)
2316 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2317 else
2318 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2319
2320 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2321 }
2322 spin_unlock_bh(&jme->rxmcs_lock);
2323
2324 spin_lock_bh(&jme->phy_lock);
2325 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2326 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2327 (ecmd->autoneg != 0)) {
2328
2329 if (ecmd->autoneg)
2330 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2331 else
2332 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2333
2334 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2335 MII_ADVERTISE, val);
2336 }
2337 spin_unlock_bh(&jme->phy_lock);
2338
2339 return 0;
2340}
2341
2342static void
2343jme_get_wol(struct net_device *netdev,
2344 struct ethtool_wolinfo *wol)
2345{
2346 struct jme_adapter *jme = netdev_priv(netdev);
2347
2348 wol->supported = WAKE_MAGIC | WAKE_PHY;
2349
2350 wol->wolopts = 0;
2351
2352 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2353 wol->wolopts |= WAKE_PHY;
2354
2355 if (jme->reg_pmcs & PMCS_MFEN)
2356 wol->wolopts |= WAKE_MAGIC;
2357
2358}
2359
2360static int
2361jme_set_wol(struct net_device *netdev,
2362 struct ethtool_wolinfo *wol)
2363{
2364 struct jme_adapter *jme = netdev_priv(netdev);
2365
2366 if (wol->wolopts & (WAKE_MAGICSECURE |
2367 WAKE_UCAST |
2368 WAKE_MCAST |
2369 WAKE_BCAST |
2370 WAKE_ARP))
2371 return -EOPNOTSUPP;
2372
2373 jme->reg_pmcs = 0;
2374
2375 if (wol->wolopts & WAKE_PHY)
2376 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2377
2378 if (wol->wolopts & WAKE_MAGIC)
2379 jme->reg_pmcs |= PMCS_MFEN;
2380
2381 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2382
2383 return 0;
2384}
2385
2386static int
2387jme_get_settings(struct net_device *netdev,
2388 struct ethtool_cmd *ecmd)
2389{
2390 struct jme_adapter *jme = netdev_priv(netdev);
2391 int rc;
2392
2393 spin_lock_bh(&jme->phy_lock);
2394 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2395 spin_unlock_bh(&jme->phy_lock);
2396 return rc;
2397}
2398
2399static int
2400jme_set_settings(struct net_device *netdev,
2401 struct ethtool_cmd *ecmd)
2402{
2403 struct jme_adapter *jme = netdev_priv(netdev);
2404 int rc, fdc = 0;
2405
2406 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2407 return -EINVAL;
2408
2409 if (jme->mii_if.force_media &&
2410 ecmd->autoneg != AUTONEG_ENABLE &&
2411 (jme->mii_if.full_duplex != ecmd->duplex))
2412 fdc = 1;
2413
2414 spin_lock_bh(&jme->phy_lock);
2415 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2416 spin_unlock_bh(&jme->phy_lock);
2417
2418 if (!rc && fdc)
2419 jme_reset_link(jme);
2420
2421 if (!rc) {
2422 set_bit(JME_FLAG_SSET, &jme->flags);
2423 jme->old_ecmd = *ecmd;
2424 }
2425
2426 return rc;
2427}
2428
2429static u32
2430jme_get_link(struct net_device *netdev)
2431{
2432 struct jme_adapter *jme = netdev_priv(netdev);
2433 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2434}
2435
2436static u32
2437jme_get_msglevel(struct net_device *netdev)
2438{
2439 struct jme_adapter *jme = netdev_priv(netdev);
2440 return jme->msg_enable;
2441}
2442
2443static void
2444jme_set_msglevel(struct net_device *netdev, u32 value)
2445{
2446 struct jme_adapter *jme = netdev_priv(netdev);
2447 jme->msg_enable = value;
2448}
2449
2450static u32
2451jme_get_rx_csum(struct net_device *netdev)
2452{
2453 struct jme_adapter *jme = netdev_priv(netdev);
2454 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2455}
2456
2457static int
2458jme_set_rx_csum(struct net_device *netdev, u32 on)
2459{
2460 struct jme_adapter *jme = netdev_priv(netdev);
2461
2462 spin_lock_bh(&jme->rxmcs_lock);
2463 if (on)
2464 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2465 else
2466 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2467 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2468 spin_unlock_bh(&jme->rxmcs_lock);
2469
2470 return 0;
2471}
2472
2473static int
2474jme_set_tx_csum(struct net_device *netdev, u32 on)
2475{
2476 struct jme_adapter *jme = netdev_priv(netdev);
2477
2478 if (on) {
2479 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2480 if (netdev->mtu <= 1900)
2481 netdev->features |= NETIF_F_HW_CSUM;
2482 } else {
2483 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2484 netdev->features &= ~NETIF_F_HW_CSUM;
2485 }
2486
2487 return 0;
2488}
2489
2490static int
2491jme_set_tso(struct net_device *netdev, u32 on)
2492{
2493 struct jme_adapter *jme = netdev_priv(netdev);
2494
2495 if (on) {
2496 set_bit(JME_FLAG_TSO, &jme->flags);
2497 if (netdev->mtu <= 1900)
2498 netdev->features |= NETIF_F_TSO
2499#ifdef NETIF_F_TSO6
2500 | NETIF_F_TSO6
2501#endif
2502 ;
2503 } else {
2504 clear_bit(JME_FLAG_TSO, &jme->flags);
2505 netdev->features &= ~(NETIF_F_TSO
2506#ifdef NETIF_F_TSO6
2507 | NETIF_F_TSO6
2508#endif
2509 );
2510 }
2511
2512 return 0;
2513}
2514
2515static int
2516jme_nway_reset(struct net_device *netdev)
2517{
2518 struct jme_adapter *jme = netdev_priv(netdev);
2519 jme_restart_an(jme);
2520 return 0;
2521}
2522
2523static u8
2524jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2525{
2526 u32 val;
2527 int to;
2528
2529 val = jread32(jme, JME_SMBCSR);
2530 to = JME_SMB_BUSY_TIMEOUT;
2531 while ((val & SMBCSR_BUSY) && --to) {
2532 msleep(1);
2533 val = jread32(jme, JME_SMBCSR);
2534 }
2535 if (!to) {
2536 msg_hw(jme, "SMB Bus Busy.\n");
2537 return 0xFF;
2538 }
2539
2540 jwrite32(jme, JME_SMBINTF,
2541 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2542 SMBINTF_HWRWN_READ |
2543 SMBINTF_HWCMD);
2544
2545 val = jread32(jme, JME_SMBINTF);
2546 to = JME_SMB_BUSY_TIMEOUT;
2547 while ((val & SMBINTF_HWCMD) && --to) {
2548 msleep(1);
2549 val = jread32(jme, JME_SMBINTF);
2550 }
2551 if (!to) {
2552 msg_hw(jme, "SMB Bus Busy.\n");
2553 return 0xFF;
2554 }
2555
2556 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2557}
2558
2559static void
2560jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2561{
2562 u32 val;
2563 int to;
2564
2565 val = jread32(jme, JME_SMBCSR);
2566 to = JME_SMB_BUSY_TIMEOUT;
2567 while ((val & SMBCSR_BUSY) && --to) {
2568 msleep(1);
2569 val = jread32(jme, JME_SMBCSR);
2570 }
2571 if (!to) {
2572 msg_hw(jme, "SMB Bus Busy.\n");
2573 return;
2574 }
2575
2576 jwrite32(jme, JME_SMBINTF,
2577 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2578 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2579 SMBINTF_HWRWN_WRITE |
2580 SMBINTF_HWCMD);
2581
2582 val = jread32(jme, JME_SMBINTF);
2583 to = JME_SMB_BUSY_TIMEOUT;
2584 while ((val & SMBINTF_HWCMD) && --to) {
2585 msleep(1);
2586 val = jread32(jme, JME_SMBINTF);
2587 }
2588 if (!to) {
2589 msg_hw(jme, "SMB Bus Busy.\n");
2590 return;
2591 }
2592
2593 mdelay(2);
2594}
2595
2596static int
2597jme_get_eeprom_len(struct net_device *netdev)
2598{
2599 struct jme_adapter *jme = netdev_priv(netdev);
2600 u32 val;
2601 val = jread32(jme, JME_SMBCSR);
2602 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2603}
2604
2605static int
2606jme_get_eeprom(struct net_device *netdev,
2607 struct ethtool_eeprom *eeprom, u8 *data)
2608{
2609 struct jme_adapter *jme = netdev_priv(netdev);
2610 int i, offset = eeprom->offset, len = eeprom->len;
2611
2612 /*
2613 * ethtool will check the boundary for us
2614 */
2615 eeprom->magic = JME_EEPROM_MAGIC;
2616 for (i = 0 ; i < len ; ++i)
2617 data[i] = jme_smb_read(jme, i + offset);
2618
2619 return 0;
2620}
2621
2622static int
2623jme_set_eeprom(struct net_device *netdev,
2624 struct ethtool_eeprom *eeprom, u8 *data)
2625{
2626 struct jme_adapter *jme = netdev_priv(netdev);
2627 int i, offset = eeprom->offset, len = eeprom->len;
2628
2629 if (eeprom->magic != JME_EEPROM_MAGIC)
2630 return -EINVAL;
2631
2632 /*
2633 * ethtool will check the boundary for us
2634 */
2635 for (i = 0 ; i < len ; ++i)
2636 jme_smb_write(jme, i + offset, data[i]);
2637
2638 return 0;
2639}
2640
2641#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2642static struct ethtool_ops jme_ethtool_ops = {
2643#else
2644static const struct ethtool_ops jme_ethtool_ops = {
2645#endif
2646 .get_drvinfo = jme_get_drvinfo,
2647 .get_regs_len = jme_get_regs_len,
2648 .get_regs = jme_get_regs,
2649 .get_coalesce = jme_get_coalesce,
2650 .set_coalesce = jme_set_coalesce,
2651 .get_pauseparam = jme_get_pauseparam,
2652 .set_pauseparam = jme_set_pauseparam,
2653 .get_wol = jme_get_wol,
2654 .set_wol = jme_set_wol,
2655 .get_settings = jme_get_settings,
2656 .set_settings = jme_set_settings,
2657 .get_link = jme_get_link,
2658 .get_msglevel = jme_get_msglevel,
2659 .set_msglevel = jme_set_msglevel,
2660 .get_rx_csum = jme_get_rx_csum,
2661 .set_rx_csum = jme_set_rx_csum,
2662 .set_tx_csum = jme_set_tx_csum,
2663 .set_tso = jme_set_tso,
2664 .set_sg = ethtool_op_set_sg,
2665 .nway_reset = jme_nway_reset,
2666 .get_eeprom_len = jme_get_eeprom_len,
2667 .get_eeprom = jme_get_eeprom,
2668 .set_eeprom = jme_set_eeprom,
2669};
2670
2671static int
2672jme_pci_dma64(struct pci_dev *pdev)
2673{
2674 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2675#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2676 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2677#else
2678 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2679#endif
2680 )
2681#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2682 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2683#else
2684 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2685#endif
2686 return 1;
2687
2688 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2689#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2690 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2691#else
2692 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2693#endif
2694 )
2695#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2696 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2697#else
2698 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2699#endif
2700 return 1;
2701
2702#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2703 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2704 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2705#else
2706 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2707 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2708#endif
2709 return 0;
2710
2711 return -1;
2712}
2713
2714static inline void
2715jme_phy_init(struct jme_adapter *jme)
2716{
2717 u16 reg26;
2718
2719 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2720 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2721}
2722
2723static inline void
2724jme_check_hw_ver(struct jme_adapter *jme)
2725{
2726 u32 chipmode;
2727
2728 chipmode = jread32(jme, JME_CHIPMODE);
2729
2730 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2731 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2732}
2733
2734#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2735static const struct net_device_ops jme_netdev_ops = {
2736 .ndo_open = jme_open,
2737 .ndo_stop = jme_close,
2738 .ndo_validate_addr = eth_validate_addr,
2739 .ndo_start_xmit = jme_start_xmit,
2740 .ndo_set_mac_address = jme_set_macaddr,
2741 .ndo_set_multicast_list = jme_set_multi,
2742 .ndo_change_mtu = jme_change_mtu,
2743 .ndo_tx_timeout = jme_tx_timeout,
2744 .ndo_vlan_rx_register = jme_vlan_rx_register,
2745};
2746#endif
2747
2748static int __devinit
2749jme_init_one(struct pci_dev *pdev,
2750 const struct pci_device_id *ent)
2751{
2752 int rc = 0, using_dac, i;
2753 struct net_device *netdev;
2754 struct jme_adapter *jme;
2755 u16 bmcr, bmsr;
2756 u32 apmc;
2757
2758 /*
2759 * set up PCI device basics
2760 */
2761 rc = pci_enable_device(pdev);
2762 if (rc) {
2763 jeprintk(pdev, "Cannot enable PCI device.\n");
2764 goto err_out;
2765 }
2766
2767 using_dac = jme_pci_dma64(pdev);
2768 if (using_dac < 0) {
2769 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2770 rc = -EIO;
2771 goto err_out_disable_pdev;
2772 }
2773
2774 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2775 jeprintk(pdev, "No PCI resource region found.\n");
2776 rc = -ENOMEM;
2777 goto err_out_disable_pdev;
2778 }
2779
2780 rc = pci_request_regions(pdev, DRV_NAME);
2781 if (rc) {
2782 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2783 goto err_out_disable_pdev;
2784 }
2785
2786 pci_set_master(pdev);
2787
2788 /*
2789 * alloc and init net device
2790 */
2791 netdev = alloc_etherdev(sizeof(*jme));
2792 if (!netdev) {
2793 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2794 rc = -ENOMEM;
2795 goto err_out_release_regions;
2796 }
2797#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2798 netdev->netdev_ops = &jme_netdev_ops;
2799#else
2800 netdev->open = jme_open;
2801 netdev->stop = jme_close;
2802 netdev->hard_start_xmit = jme_start_xmit;
2803 netdev->set_mac_address = jme_set_macaddr;
2804 netdev->set_multicast_list = jme_set_multi;
2805 netdev->change_mtu = jme_change_mtu;
2806 netdev->tx_timeout = jme_tx_timeout;
2807 netdev->vlan_rx_register = jme_vlan_rx_register;
2808 NETDEV_GET_STATS(netdev, &jme_get_stats);
2809#endif
2810 netdev->ethtool_ops = &jme_ethtool_ops;
2811 netdev->watchdog_timeo = TX_TIMEOUT;
2812 netdev->features = NETIF_F_HW_CSUM |
2813 NETIF_F_SG |
2814 NETIF_F_TSO |
2815#ifdef NETIF_F_TSO6
2816 NETIF_F_TSO6 |
2817#endif
2818 NETIF_F_HW_VLAN_TX |
2819 NETIF_F_HW_VLAN_RX;
2820 if (using_dac)
2821 netdev->features |= NETIF_F_HIGHDMA;
2822
2823 SET_NETDEV_DEV(netdev, &pdev->dev);
2824 pci_set_drvdata(pdev, netdev);
2825
2826 /*
2827 * init adapter info
2828 */
2829 jme = netdev_priv(netdev);
2830 jme->pdev = pdev;
2831 jme->dev = netdev;
2832 jme->jme_rx = netif_rx;
2833 jme->jme_vlan_rx = vlan_hwaccel_rx;
2834 jme->old_mtu = netdev->mtu = 1500;
2835 jme->phylink = 0;
2836 jme->tx_ring_size = 1 << 10;
2837 jme->tx_ring_mask = jme->tx_ring_size - 1;
2838 jme->tx_wake_threshold = 1 << 9;
2839 jme->rx_ring_size = 1 << 9;
2840 jme->rx_ring_mask = jme->rx_ring_size - 1;
2841 jme->msg_enable = JME_DEF_MSG_ENABLE;
2842 jme->regs = ioremap(pci_resource_start(pdev, 0),
2843 pci_resource_len(pdev, 0));
2844 if (!(jme->regs)) {
2845 jeprintk(pdev, "Mapping PCI resource region error.\n");
2846 rc = -ENOMEM;
2847 goto err_out_free_netdev;
2848 }
2849
2850 if (no_pseudohp) {
2851 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2852 jwrite32(jme, JME_APMC, apmc);
2853 } else if (force_pseudohp) {
2854 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2855 jwrite32(jme, JME_APMC, apmc);
2856 }
2857
2858 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2859
2860 spin_lock_init(&jme->phy_lock);
2861 spin_lock_init(&jme->macaddr_lock);
2862 spin_lock_init(&jme->rxmcs_lock);
2863
2864 atomic_set(&jme->link_changing, 1);
2865 atomic_set(&jme->rx_cleaning, 1);
2866 atomic_set(&jme->tx_cleaning, 1);
2867 atomic_set(&jme->rx_empty, 1);
2868
2869 tasklet_init(&jme->pcc_task,
2870 &jme_pcc_tasklet,
2871 (unsigned long) jme);
2872 tasklet_init(&jme->linkch_task,
2873 &jme_link_change_tasklet,
2874 (unsigned long) jme);
2875 tasklet_init(&jme->txclean_task,
2876 &jme_tx_clean_tasklet,
2877 (unsigned long) jme);
2878 tasklet_init(&jme->rxclean_task,
2879 &jme_rx_clean_tasklet,
2880 (unsigned long) jme);
2881 tasklet_init(&jme->rxempty_task,
2882 &jme_rx_empty_tasklet,
2883 (unsigned long) jme);
2884 tasklet_disable_nosync(&jme->linkch_task);
2885 tasklet_disable_nosync(&jme->txclean_task);
2886 tasklet_disable_nosync(&jme->rxclean_task);
2887 tasklet_disable_nosync(&jme->rxempty_task);
2888 jme->dpi.cur = PCC_P1;
2889
2890 jme->reg_ghc = 0;
2891 jme->reg_rxcs = RXCS_DEFAULT;
2892 jme->reg_rxmcs = RXMCS_DEFAULT;
2893 jme->reg_txpfc = 0;
2894 jme->reg_pmcs = PMCS_MFEN;
2895 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2896 set_bit(JME_FLAG_TSO, &jme->flags);
2897
2898 /*
2899 * Get Max Read Req Size from PCI Config Space
2900 */
2901 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2902 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2903 switch (jme->mrrs) {
2904 case MRRS_128B:
2905 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2906 break;
2907 case MRRS_256B:
2908 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2909 break;
2910 default:
2911 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2912 break;
2913 };
2914
2915 /*
2916 * Must check before reset_mac_processor
2917 */
2918 jme_check_hw_ver(jme);
2919 jme->mii_if.dev = netdev;
2920 if (jme->fpgaver) {
2921 jme->mii_if.phy_id = 0;
2922 for (i = 1 ; i < 32 ; ++i) {
2923 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2924 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2925 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2926 jme->mii_if.phy_id = i;
2927 break;
2928 }
2929 }
2930
2931 if (!jme->mii_if.phy_id) {
2932 rc = -EIO;
2933 jeprintk(pdev, "Can not find phy_id.\n");
2934 goto err_out_unmap;
2935 }
2936
2937 jme->reg_ghc |= GHC_LINK_POLL;
2938 } else {
2939 jme->mii_if.phy_id = 1;
2940 }
2941 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2942 jme->mii_if.supports_gmii = true;
2943 else
2944 jme->mii_if.supports_gmii = false;
2945 jme->mii_if.mdio_read = jme_mdio_read;
2946 jme->mii_if.mdio_write = jme_mdio_write;
2947
2948 jme_clear_pm(jme);
2949 jme_set_phyfifoa(jme);
2950 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2951 if (!jme->fpgaver)
2952 jme_phy_init(jme);
2953 jme_phy_off(jme);
2954
2955 /*
2956 * Reset MAC processor and reload EEPROM for MAC Address
2957 */
2958 jme_reset_mac_processor(jme);
2959 rc = jme_reload_eeprom(jme);
2960 if (rc) {
2961 jeprintk(pdev,
2962 "Reload eeprom for reading MAC Address error.\n");
2963 goto err_out_unmap;
2964 }
2965 jme_load_macaddr(netdev);
2966
2967 /*
2968 * Tell stack that we are not ready to work until open()
2969 */
2970 netif_carrier_off(netdev);
2971 netif_stop_queue(netdev);
2972
2973 /*
2974 * Register netdev
2975 */
2976 rc = register_netdev(netdev);
2977 if (rc) {
2978 jeprintk(pdev, "Cannot register net device.\n");
2979 goto err_out_unmap;
2980 }
2981
2982 msg_probe(jme, "%s%s ver:%x rev:%x "
2983 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
2984 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2985 "JMC250 Gigabit Ethernet" :
2986 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2987 "JMC260 Fast Ethernet" : "Unknown",
2988 (jme->fpgaver != 0) ? " (FPGA)" : "",
2989 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2990 jme->rev,
2991 netdev->dev_addr[0],
2992 netdev->dev_addr[1],
2993 netdev->dev_addr[2],
2994 netdev->dev_addr[3],
2995 netdev->dev_addr[4],
2996 netdev->dev_addr[5]);
2997
2998 return 0;
2999
3000err_out_unmap:
3001 iounmap(jme->regs);
3002err_out_free_netdev:
3003 pci_set_drvdata(pdev, NULL);
3004 free_netdev(netdev);
3005err_out_release_regions:
3006 pci_release_regions(pdev);
3007err_out_disable_pdev:
3008 pci_disable_device(pdev);
3009err_out:
3010 return rc;
3011}
3012
3013static void __devexit
3014jme_remove_one(struct pci_dev *pdev)
3015{
3016 struct net_device *netdev = pci_get_drvdata(pdev);
3017 struct jme_adapter *jme = netdev_priv(netdev);
3018
3019 unregister_netdev(netdev);
3020 iounmap(jme->regs);
3021 pci_set_drvdata(pdev, NULL);
3022 free_netdev(netdev);
3023 pci_release_regions(pdev);
3024 pci_disable_device(pdev);
3025
3026}
3027
3028#ifdef CONFIG_PM
3029static int
3030jme_suspend(struct pci_dev *pdev, pm_message_t state)
3031{
3032 struct net_device *netdev = pci_get_drvdata(pdev);
3033 struct jme_adapter *jme = netdev_priv(netdev);
3034
3035 atomic_dec(&jme->link_changing);
3036
3037 netif_device_detach(netdev);
3038 netif_stop_queue(netdev);
3039 jme_stop_irq(jme);
3040
3041 tasklet_disable(&jme->txclean_task);
3042 tasklet_disable(&jme->rxclean_task);
3043 tasklet_disable(&jme->rxempty_task);
3044
3045 if (netif_carrier_ok(netdev)) {
3046 if (test_bit(JME_FLAG_POLL, &jme->flags))
3047 jme_polling_mode(jme);
3048
3049 jme_stop_pcc_timer(jme);
3050 jme_reset_ghc_speed(jme);
3051 jme_disable_rx_engine(jme);
3052 jme_disable_tx_engine(jme);
3053 jme_reset_mac_processor(jme);
3054 jme_free_rx_resources(jme);
3055 jme_free_tx_resources(jme);
3056 netif_carrier_off(netdev);
3057 jme->phylink = 0;
3058 }
3059
3060 tasklet_enable(&jme->txclean_task);
3061 tasklet_hi_enable(&jme->rxclean_task);
3062 tasklet_hi_enable(&jme->rxempty_task);
3063
3064 pci_save_state(pdev);
3065 if (jme->reg_pmcs) {
3066 jme_set_100m_half(jme);
3067
3068 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3069 jme_wait_link(jme);
3070
3071 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3072
3073 pci_enable_wake(pdev, PCI_D3cold, true);
3074 } else {
3075 jme_phy_off(jme);
3076 }
3077 pci_set_power_state(pdev, PCI_D3cold);
3078
3079 return 0;
3080}
3081
3082static int
3083jme_resume(struct pci_dev *pdev)
3084{
3085 struct net_device *netdev = pci_get_drvdata(pdev);
3086 struct jme_adapter *jme = netdev_priv(netdev);
3087
3088 jme_clear_pm(jme);
3089 pci_restore_state(pdev);
3090
3091 if (test_bit(JME_FLAG_SSET, &jme->flags))
3092 jme_set_settings(netdev, &jme->old_ecmd);
3093 else
3094 jme_reset_phy_processor(jme);
3095
3096 jme_start_irq(jme);
3097 netif_device_attach(netdev);
3098
3099 atomic_inc(&jme->link_changing);
3100
3101 jme_reset_link(jme);
3102
3103 return 0;
3104}
3105#endif
3106
3107static struct pci_device_id jme_pci_tbl[] = {
3108 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3109 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3110 { }
3111};
3112
3113static struct pci_driver jme_driver = {
3114 .name = DRV_NAME,
3115 .id_table = jme_pci_tbl,
3116 .probe = jme_init_one,
3117 .remove = __devexit_p(jme_remove_one),
3118#ifdef CONFIG_PM
3119 .suspend = jme_suspend,
3120 .resume = jme_resume,
3121#endif /* CONFIG_PM */
3122};
3123
3124static int __init
3125jme_init_module(void)
3126{
3127 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3128 "driver version %s\n", DRV_VERSION);
3129 return pci_register_driver(&jme_driver);
3130}
3131
3132static void __exit
3133jme_cleanup_module(void)
3134{
3135 pci_unregister_driver(&jme_driver);
3136}
3137
3138module_init(jme_init_module);
3139module_exit(jme_cleanup_module);
3140
3141MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3142MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3143MODULE_LICENSE("GPL");
3144MODULE_VERSION(DRV_VERSION);
3145MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3146
JMicron Ethernet Linux driver