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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/version.h>
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
38#include <linux/delay.h>
39#include <linux/spinlock.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/if_vlan.h>
46#include <linux/slab.h>
47#include <net/ip6_checksum.h>
48#include "jme.h"
49
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
61
62static int
63jme_mdio_read(struct net_device *netdev, int phy, int reg)
64{
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
67
68read_again:
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
70 smi_phy_addr(phy) |
71 smi_reg_addr(reg));
72
73 wmb();
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
75 udelay(20);
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
78 break;
79 }
80
81 if (i == 0) {
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
83 return 0;
84 }
85
86 if (again--)
87 goto read_again;
88
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
90}
91
92static void
93jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
95{
96 struct jme_adapter *jme = netdev_priv(netdev);
97 int i;
98
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
102
103 wmb();
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 udelay(20);
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
107 break;
108 }
109
110 if (i == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
112}
113
114static inline void
115jme_reset_phy_processor(struct jme_adapter *jme)
116{
117 u32 val;
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
123
124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
125 jme_mdio_write(jme->dev,
126 jme->mii_if.phy_id,
127 MII_CTRL1000,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
129
130 val = jme_mdio_read(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR);
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_BMCR, val | BMCR_RESET);
137}
138
139static void
140jme_setup_wakeup_frame(struct jme_adapter *jme,
141 const u32 *mask, u32 crc, int fnr)
142{
143 int i;
144
145 /*
146 * Setup CRC pattern
147 */
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 wmb();
150 jwrite32(jme, JME_WFODP, crc);
151 wmb();
152
153 /*
154 * Setup Mask
155 */
156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
160 wmb();
161 jwrite32(jme, JME_WFODP, mask[i]);
162 wmb();
163 }
164}
165
166static inline void
167jme_mac_rxclk_off(struct jme_adapter *jme)
168{
169 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
170 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
171}
172
173static inline void
174jme_mac_rxclk_on(struct jme_adapter *jme)
175{
176 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
177 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
178}
179
180static inline void
181jme_mac_txclk_off(struct jme_adapter *jme)
182{
183 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
184 jwrite32f(jme, JME_GHC, jme->reg_ghc);
185}
186
187static inline void
188jme_mac_txclk_on(struct jme_adapter *jme)
189{
190 u32 speed = jme->reg_ghc & GHC_SPEED;
191 if (speed == GHC_SPEED_1000M)
192 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
193 else
194 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
195 jwrite32f(jme, JME_GHC, jme->reg_ghc);
196}
197
198static inline void
199jme_reset_ghc_speed(struct jme_adapter *jme)
200{
201 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
202 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203}
204
205static inline void
206jme_reset_250A2_workaround(struct jme_adapter *jme)
207{
208 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
209 GPREG1_RSSPATCH);
210 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
211}
212
213static inline void
214jme_assert_ghc_reset(struct jme_adapter *jme)
215{
216 jme->reg_ghc |= GHC_SWRST;
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_clear_ghc_reset(struct jme_adapter *jme)
222{
223 jme->reg_ghc &= ~GHC_SWRST;
224 jwrite32f(jme, JME_GHC, jme->reg_ghc);
225}
226
227static inline void
228jme_reset_mac_processor(struct jme_adapter *jme)
229{
230 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
231 u32 crc = 0xCDCDCDCD;
232 u32 gpreg0;
233 int i;
234
235 jme_reset_ghc_speed(jme);
236 jme_reset_250A2_workaround(jme);
237
238 jme_mac_rxclk_on(jme);
239 jme_mac_txclk_on(jme);
240 udelay(1);
241 jme_assert_ghc_reset(jme);
242 udelay(1);
243 jme_mac_rxclk_off(jme);
244 jme_mac_txclk_off(jme);
245 udelay(1);
246 jme_clear_ghc_reset(jme);
247 udelay(1);
248 jme_mac_rxclk_on(jme);
249 jme_mac_txclk_on(jme);
250 udelay(1);
251 jme_mac_rxclk_off(jme);
252 jme_mac_txclk_off(jme);
253
254 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
255 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
256 jwrite32(jme, JME_RXQDC, 0x00000000);
257 jwrite32(jme, JME_RXNDA, 0x00000000);
258 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
259 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
260 jwrite32(jme, JME_TXQDC, 0x00000000);
261 jwrite32(jme, JME_TXNDA, 0x00000000);
262
263 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
264 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
265 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
266 jme_setup_wakeup_frame(jme, mask, crc, i);
267 if (jme->fpgaver)
268 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
269 else
270 gpreg0 = GPREG0_DEFAULT;
271 jwrite32(jme, JME_GPREG0, gpreg0);
272}
273
274static inline void
275jme_clear_pm(struct jme_adapter *jme)
276{
277 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
278 pci_set_power_state(jme->pdev, PCI_D0);
279 pci_enable_wake(jme->pdev, PCI_D0, false);
280}
281
282static int
283jme_reload_eeprom(struct jme_adapter *jme)
284{
285 u32 val;
286 int i;
287
288 val = jread32(jme, JME_SMBCSR);
289
290 if (val & SMBCSR_EEPROMD) {
291 val |= SMBCSR_CNACK;
292 jwrite32(jme, JME_SMBCSR, val);
293 val |= SMBCSR_RELOAD;
294 jwrite32(jme, JME_SMBCSR, val);
295 mdelay(12);
296
297 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
298 mdelay(1);
299 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
300 break;
301 }
302
303 if (i == 0) {
304 pr_err("eeprom reload timeout\n");
305 return -EIO;
306 }
307 }
308
309 return 0;
310}
311
312static void
313jme_load_macaddr(struct net_device *netdev)
314{
315 struct jme_adapter *jme = netdev_priv(netdev);
316 unsigned char macaddr[6];
317 u32 val;
318
319 spin_lock_bh(&jme->macaddr_lock);
320 val = jread32(jme, JME_RXUMA_LO);
321 macaddr[0] = (val >> 0) & 0xFF;
322 macaddr[1] = (val >> 8) & 0xFF;
323 macaddr[2] = (val >> 16) & 0xFF;
324 macaddr[3] = (val >> 24) & 0xFF;
325 val = jread32(jme, JME_RXUMA_HI);
326 macaddr[4] = (val >> 0) & 0xFF;
327 macaddr[5] = (val >> 8) & 0xFF;
328 memcpy(netdev->dev_addr, macaddr, 6);
329 spin_unlock_bh(&jme->macaddr_lock);
330}
331
332static inline void
333jme_set_rx_pcc(struct jme_adapter *jme, int p)
334{
335 switch (p) {
336 case PCC_OFF:
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340 break;
341 case PCC_P1:
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345 break;
346 case PCC_P2:
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350 break;
351 case PCC_P3:
352 jwrite32(jme, JME_PCCRX0,
353 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
354 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
355 break;
356 default:
357 break;
358 }
359 wmb();
360
361 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
362 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
363}
364
365static void
366jme_start_irq(struct jme_adapter *jme)
367{
368 register struct dynpcc_info *dpi = &(jme->dpi);
369
370 jme_set_rx_pcc(jme, PCC_P1);
371 dpi->cur = PCC_P1;
372 dpi->attempt = PCC_P1;
373 dpi->cnt = 0;
374
375 jwrite32(jme, JME_PCCTX,
376 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
377 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
378 PCCTXQ0_EN
379 );
380
381 /*
382 * Enable Interrupts
383 */
384 jwrite32(jme, JME_IENS, INTR_ENABLE);
385}
386
387static inline void
388jme_stop_irq(struct jme_adapter *jme)
389{
390 /*
391 * Disable Interrupts
392 */
393 jwrite32f(jme, JME_IENC, INTR_ENABLE);
394}
395
396static u32
397jme_linkstat_from_phy(struct jme_adapter *jme)
398{
399 u32 phylink, bmsr;
400
401 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
402 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
403 if (bmsr & BMSR_ANCOMP)
404 phylink |= PHY_LINK_AUTONEG_COMPLETE;
405
406 return phylink;
407}
408
409static inline void
410jme_set_phyfifo_5level(struct jme_adapter *jme)
411{
412 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
413}
414
415static inline void
416jme_set_phyfifo_8level(struct jme_adapter *jme)
417{
418 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
419}
420
421static int
422jme_check_link(struct net_device *netdev, int testonly)
423{
424 struct jme_adapter *jme = netdev_priv(netdev);
425 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
426 char linkmsg[64];
427 int rc = 0;
428
429 linkmsg[0] = '\0';
430
431 if (jme->fpgaver)
432 phylink = jme_linkstat_from_phy(jme);
433 else
434 phylink = jread32(jme, JME_PHY_LINK);
435
436 if (phylink & PHY_LINK_UP) {
437 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
438 /*
439 * If we did not enable AN
440 * Speed/Duplex Info should be obtained from SMI
441 */
442 phylink = PHY_LINK_UP;
443
444 bmcr = jme_mdio_read(jme->dev,
445 jme->mii_if.phy_id,
446 MII_BMCR);
447
448 phylink |= ((bmcr & BMCR_SPEED1000) &&
449 (bmcr & BMCR_SPEED100) == 0) ?
450 PHY_LINK_SPEED_1000M :
451 (bmcr & BMCR_SPEED100) ?
452 PHY_LINK_SPEED_100M :
453 PHY_LINK_SPEED_10M;
454
455 phylink |= (bmcr & BMCR_FULLDPLX) ?
456 PHY_LINK_DUPLEX : 0;
457
458 strcat(linkmsg, "Forced: ");
459 } else {
460 /*
461 * Keep polling for speed/duplex resolve complete
462 */
463 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
464 --cnt) {
465
466 udelay(1);
467
468 if (jme->fpgaver)
469 phylink = jme_linkstat_from_phy(jme);
470 else
471 phylink = jread32(jme, JME_PHY_LINK);
472 }
473 if (!cnt)
474 pr_err("Waiting speed resolve timeout\n");
475
476 strcat(linkmsg, "ANed: ");
477 }
478
479 if (jme->phylink == phylink) {
480 rc = 1;
481 goto out;
482 }
483 if (testonly)
484 goto out;
485
486 jme->phylink = phylink;
487
488 /*
489 * The speed/duplex setting of jme->reg_ghc already cleared
490 * by jme_reset_mac_processor()
491 */
492 switch (phylink & PHY_LINK_SPEED_MASK) {
493 case PHY_LINK_SPEED_10M:
494 jme->reg_ghc |= GHC_SPEED_10M;
495 strcat(linkmsg, "10 Mbps, ");
496 break;
497 case PHY_LINK_SPEED_100M:
498 jme->reg_ghc |= GHC_SPEED_100M;
499 strcat(linkmsg, "100 Mbps, ");
500 break;
501 case PHY_LINK_SPEED_1000M:
502 jme->reg_ghc |= GHC_SPEED_1000M;
503 strcat(linkmsg, "1000 Mbps, ");
504 break;
505 default:
506 break;
507 }
508
509 if (phylink & PHY_LINK_DUPLEX) {
510 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
511 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
512 jme->reg_ghc |= GHC_DPX;
513 } else {
514 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
515 TXMCS_BACKOFF |
516 TXMCS_CARRIERSENSE |
517 TXMCS_COLLISION);
518 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
519 }
520
521 jwrite32(jme, JME_GHC, jme->reg_ghc);
522
523 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
524 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
525 GPREG1_RSSPATCH);
526 if (!(phylink & PHY_LINK_DUPLEX))
527 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
528 switch (phylink & PHY_LINK_SPEED_MASK) {
529 case PHY_LINK_SPEED_10M:
530 jme_set_phyfifo_8level(jme);
531 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
532 break;
533 case PHY_LINK_SPEED_100M:
534 jme_set_phyfifo_5level(jme);
535 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
536 break;
537 case PHY_LINK_SPEED_1000M:
538 jme_set_phyfifo_8level(jme);
539 break;
540 default:
541 break;
542 }
543 }
544 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
545
546 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
547 "Full-Duplex, " :
548 "Half-Duplex, ");
549 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
550 "MDI-X" :
551 "MDI");
552 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
553 netif_carrier_on(netdev);
554 } else {
555 if (testonly)
556 goto out;
557
558 netif_info(jme, link, jme->dev, "Link is down\n");
559 jme->phylink = 0;
560 netif_carrier_off(netdev);
561 }
562
563out:
564 return rc;
565}
566
567static int
568jme_setup_tx_resources(struct jme_adapter *jme)
569{
570 struct jme_ring *txring = &(jme->txring[0]);
571
572 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
574 &(txring->dmaalloc),
575 GFP_ATOMIC);
576
577 if (!txring->alloc)
578 goto err_set_null;
579
580 /*
581 * 16 Bytes align
582 */
583 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
584 RING_DESC_ALIGN);
585 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
586 txring->next_to_use = 0;
587 atomic_set(&txring->next_to_clean, 0);
588 atomic_set(&txring->nr_free, jme->tx_ring_size);
589
590 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
591 jme->tx_ring_size, GFP_ATOMIC);
592 if (unlikely(!(txring->bufinf)))
593 goto err_free_txring;
594
595 /*
596 * Initialize Transmit Descriptors
597 */
598 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
599 memset(txring->bufinf, 0,
600 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
601
602 return 0;
603
604err_free_txring:
605 dma_free_coherent(&(jme->pdev->dev),
606 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
607 txring->alloc,
608 txring->dmaalloc);
609
610err_set_null:
611 txring->desc = NULL;
612 txring->dmaalloc = 0;
613 txring->dma = 0;
614 txring->bufinf = NULL;
615
616 return -ENOMEM;
617}
618
619static void
620jme_free_tx_resources(struct jme_adapter *jme)
621{
622 int i;
623 struct jme_ring *txring = &(jme->txring[0]);
624 struct jme_buffer_info *txbi;
625
626 if (txring->alloc) {
627 if (txring->bufinf) {
628 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
629 txbi = txring->bufinf + i;
630 if (txbi->skb) {
631 dev_kfree_skb(txbi->skb);
632 txbi->skb = NULL;
633 }
634 txbi->mapping = 0;
635 txbi->len = 0;
636 txbi->nr_desc = 0;
637 txbi->start_xmit = 0;
638 }
639 kfree(txring->bufinf);
640 }
641
642 dma_free_coherent(&(jme->pdev->dev),
643 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
644 txring->alloc,
645 txring->dmaalloc);
646
647 txring->alloc = NULL;
648 txring->desc = NULL;
649 txring->dmaalloc = 0;
650 txring->dma = 0;
651 txring->bufinf = NULL;
652 }
653 txring->next_to_use = 0;
654 atomic_set(&txring->next_to_clean, 0);
655 atomic_set(&txring->nr_free, 0);
656}
657
658static inline void
659jme_enable_tx_engine(struct jme_adapter *jme)
660{
661 /*
662 * Select Queue 0
663 */
664 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
665 wmb();
666
667 /*
668 * Setup TX Queue 0 DMA Bass Address
669 */
670 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
671 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
672 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
673
674 /*
675 * Setup TX Descptor Count
676 */
677 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
678
679 /*
680 * Enable TX Engine
681 */
682 wmb();
683 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
684 TXCS_SELECT_QUEUE0 |
685 TXCS_ENABLE);
686
687 /*
688 * Start clock for TX MAC Processor
689 */
690 jme_mac_txclk_on(jme);
691}
692
693static inline void
694jme_restart_tx_engine(struct jme_adapter *jme)
695{
696 /*
697 * Restart TX Engine
698 */
699 jwrite32(jme, JME_TXCS, jme->reg_txcs |
700 TXCS_SELECT_QUEUE0 |
701 TXCS_ENABLE);
702}
703
704static inline void
705jme_disable_tx_engine(struct jme_adapter *jme)
706{
707 int i;
708 u32 val;
709
710 /*
711 * Disable TX Engine
712 */
713 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
714 wmb();
715
716 val = jread32(jme, JME_TXCS);
717 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
718 mdelay(1);
719 val = jread32(jme, JME_TXCS);
720 rmb();
721 }
722
723 if (!i)
724 pr_err("Disable TX engine timeout\n");
725
726 /*
727 * Stop clock for TX MAC Processor
728 */
729 jme_mac_txclk_off(jme);
730}
731
732static void
733jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
734{
735 struct jme_ring *rxring = &(jme->rxring[0]);
736 register struct rxdesc *rxdesc = rxring->desc;
737 struct jme_buffer_info *rxbi = rxring->bufinf;
738 rxdesc += i;
739 rxbi += i;
740
741 rxdesc->dw[0] = 0;
742 rxdesc->dw[1] = 0;
743 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
744 rxdesc->desc1.bufaddrl = cpu_to_le32(
745 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
746 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
747 if (jme->dev->features & NETIF_F_HIGHDMA)
748 rxdesc->desc1.flags = RXFLAG_64BIT;
749 wmb();
750 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
751}
752
753static int
754jme_make_new_rx_buf(struct jme_adapter *jme, int i)
755{
756 struct jme_ring *rxring = &(jme->rxring[0]);
757 struct jme_buffer_info *rxbi = rxring->bufinf + i;
758 struct sk_buff *skb;
759
760 skb = netdev_alloc_skb(jme->dev,
761 jme->dev->mtu + RX_EXTRA_LEN);
762 if (unlikely(!skb))
763 return -ENOMEM;
764#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
765 skb->dev = jme->dev;
766#endif
767
768 rxbi->skb = skb;
769 rxbi->len = skb_tailroom(skb);
770 rxbi->mapping = pci_map_page(jme->pdev,
771 virt_to_page(skb->data),
772 offset_in_page(skb->data),
773 rxbi->len,
774 PCI_DMA_FROMDEVICE);
775
776 return 0;
777}
778
779static void
780jme_free_rx_buf(struct jme_adapter *jme, int i)
781{
782 struct jme_ring *rxring = &(jme->rxring[0]);
783 struct jme_buffer_info *rxbi = rxring->bufinf;
784 rxbi += i;
785
786 if (rxbi->skb) {
787 pci_unmap_page(jme->pdev,
788 rxbi->mapping,
789 rxbi->len,
790 PCI_DMA_FROMDEVICE);
791 dev_kfree_skb(rxbi->skb);
792 rxbi->skb = NULL;
793 rxbi->mapping = 0;
794 rxbi->len = 0;
795 }
796}
797
798static void
799jme_free_rx_resources(struct jme_adapter *jme)
800{
801 int i;
802 struct jme_ring *rxring = &(jme->rxring[0]);
803
804 if (rxring->alloc) {
805 if (rxring->bufinf) {
806 for (i = 0 ; i < jme->rx_ring_size ; ++i)
807 jme_free_rx_buf(jme, i);
808 kfree(rxring->bufinf);
809 }
810
811 dma_free_coherent(&(jme->pdev->dev),
812 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
813 rxring->alloc,
814 rxring->dmaalloc);
815 rxring->alloc = NULL;
816 rxring->desc = NULL;
817 rxring->dmaalloc = 0;
818 rxring->dma = 0;
819 rxring->bufinf = NULL;
820 }
821 rxring->next_to_use = 0;
822 atomic_set(&rxring->next_to_clean, 0);
823}
824
825static int
826jme_setup_rx_resources(struct jme_adapter *jme)
827{
828 int i;
829 struct jme_ring *rxring = &(jme->rxring[0]);
830
831 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
832 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
833 &(rxring->dmaalloc),
834 GFP_ATOMIC);
835 if (!rxring->alloc)
836 goto err_set_null;
837
838 /*
839 * 16 Bytes align
840 */
841 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
842 RING_DESC_ALIGN);
843 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
844 rxring->next_to_use = 0;
845 atomic_set(&rxring->next_to_clean, 0);
846
847 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
848 jme->rx_ring_size, GFP_ATOMIC);
849 if (unlikely(!(rxring->bufinf)))
850 goto err_free_rxring;
851
852 /*
853 * Initiallize Receive Descriptors
854 */
855 memset(rxring->bufinf, 0,
856 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
857 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
858 if (unlikely(jme_make_new_rx_buf(jme, i))) {
859 jme_free_rx_resources(jme);
860 return -ENOMEM;
861 }
862
863 jme_set_clean_rxdesc(jme, i);
864 }
865
866 return 0;
867
868err_free_rxring:
869 dma_free_coherent(&(jme->pdev->dev),
870 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
871 rxring->alloc,
872 rxring->dmaalloc);
873err_set_null:
874 rxring->desc = NULL;
875 rxring->dmaalloc = 0;
876 rxring->dma = 0;
877 rxring->bufinf = NULL;
878
879 return -ENOMEM;
880}
881
882static inline void
883jme_enable_rx_engine(struct jme_adapter *jme)
884{
885 /*
886 * Select Queue 0
887 */
888 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
889 RXCS_QUEUESEL_Q0);
890 wmb();
891
892 /*
893 * Setup RX DMA Bass Address
894 */
895 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
896 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
897 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
898
899 /*
900 * Setup RX Descriptor Count
901 */
902 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
903
904 /*
905 * Setup Unicast Filter
906 */
907 jme_set_unicastaddr(jme->dev);
908 jme_set_multi(jme->dev);
909
910 /*
911 * Enable RX Engine
912 */
913 wmb();
914 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
915 RXCS_QUEUESEL_Q0 |
916 RXCS_ENABLE |
917 RXCS_QST);
918
919 /*
920 * Start clock for RX MAC Processor
921 */
922 jme_mac_rxclk_on(jme);
923}
924
925static inline void
926jme_restart_rx_engine(struct jme_adapter *jme)
927{
928 /*
929 * Start RX Engine
930 */
931 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
932 RXCS_QUEUESEL_Q0 |
933 RXCS_ENABLE |
934 RXCS_QST);
935}
936
937static inline void
938jme_disable_rx_engine(struct jme_adapter *jme)
939{
940 int i;
941 u32 val;
942
943 /*
944 * Disable RX Engine
945 */
946 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
947 wmb();
948
949 val = jread32(jme, JME_RXCS);
950 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
951 mdelay(1);
952 val = jread32(jme, JME_RXCS);
953 rmb();
954 }
955
956 if (!i)
957 pr_err("Disable RX engine timeout\n");
958
959 /*
960 * Stop clock for RX MAC Processor
961 */
962 jme_mac_rxclk_off(jme);
963}
964
965static u16
966jme_udpsum(struct sk_buff *skb)
967{
968 u16 csum = 0xFFFFu;
969
970 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
971 return csum;
972 if (skb->protocol != htons(ETH_P_IP))
973 return csum;
974 skb_set_network_header(skb, ETH_HLEN);
975 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
976 (skb->len < (ETH_HLEN +
977 (ip_hdr(skb)->ihl << 2) +
978 sizeof(struct udphdr)))) {
979 skb_reset_network_header(skb);
980 return csum;
981 }
982 skb_set_transport_header(skb,
983 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
984 csum = udp_hdr(skb)->check;
985 skb_reset_transport_header(skb);
986 skb_reset_network_header(skb);
987
988 return csum;
989}
990
991static int
992jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
993{
994 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
995 return false;
996
997 /* Hardware Workaround , packet is IPv6 but checksum fail */
998 if (flags & RXWBFLAG_IPV6) {
999
1000 printk("this is IPV6 packet : len=%d ", skb->len);
1001 if ((flags & RXWBFLAG_TCPON) && (!(flags & RXWBFLAG_TCPCS)))
1002 return false;
1003 if ((flags & RXWBFLAG_UDPON) && (!(flags & RXWBFLAG_UDPCS)))
1004 return false;
1005 }
1006
1007 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1008 == RXWBFLAG_TCPON)) {
1009 if (flags & RXWBFLAG_IPV4)
1010 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1011 return false;
1012 }
1013
1014 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1015 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1016 if (flags & RXWBFLAG_IPV4)
1017 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1018 return false;
1019 }
1020
1021 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1022 == RXWBFLAG_IPV4)) {
1023 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1024 return false;
1025 }
1026
1027 return true;
1028}
1029
1030static void
1031jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1032{
1033 struct jme_ring *rxring = &(jme->rxring[0]);
1034 struct rxdesc *rxdesc = rxring->desc;
1035 struct jme_buffer_info *rxbi = rxring->bufinf;
1036 struct sk_buff *skb;
1037 int framesize;
1038
1039 rxdesc += idx;
1040 rxbi += idx;
1041
1042 skb = rxbi->skb;
1043 pci_dma_sync_single_for_cpu(jme->pdev,
1044 rxbi->mapping,
1045 rxbi->len,
1046 PCI_DMA_FROMDEVICE);
1047
1048 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1049 pci_dma_sync_single_for_device(jme->pdev,
1050 rxbi->mapping,
1051 rxbi->len,
1052 PCI_DMA_FROMDEVICE);
1053
1054 ++(NET_STAT(jme).rx_dropped);
1055 } else {
1056 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1057 - RX_PREPAD_SIZE;
1058
1059 skb_reserve(skb, RX_PREPAD_SIZE);
1060 skb_put(skb, framesize);
1061 skb->protocol = eth_type_trans(skb, jme->dev);
1062
1063 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1064 skb->ip_summed = CHECKSUM_UNNECESSARY;
1065 else
1066#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
1067 skb->ip_summed = CHECKSUM_NONE;
1068#else
1069 skb_checksum_none_assert(skb);
1070#endif
1071 printk("flag=%04x , skb->ip_summed =%d \n",le16_to_cpu(rxdesc->descwb.flags), skb->ip_summed);
1072
1073 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1074 if (jme->vlgrp) {
1075 jme->jme_vlan_rx(skb, jme->vlgrp,
1076 le16_to_cpu(rxdesc->descwb.vlan));
1077 NET_STAT(jme).rx_bytes += 4;
1078 } else {
1079 dev_kfree_skb(skb);
1080 }
1081 } else {
1082 jme->jme_rx(skb);
1083 }
1084
1085 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1086 cpu_to_le16(RXWBFLAG_DEST_MUL))
1087 ++(NET_STAT(jme).multicast);
1088
1089 NET_STAT(jme).rx_bytes += framesize;
1090 ++(NET_STAT(jme).rx_packets);
1091 }
1092
1093 jme_set_clean_rxdesc(jme, idx);
1094
1095}
1096
1097static int
1098jme_process_receive(struct jme_adapter *jme, int limit)
1099{
1100 struct jme_ring *rxring = &(jme->rxring[0]);
1101 struct rxdesc *rxdesc = rxring->desc;
1102 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1103
1104 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1105 goto out_inc;
1106
1107 if (unlikely(atomic_read(&jme->link_changing) != 1))
1108 goto out_inc;
1109
1110 if (unlikely(!netif_carrier_ok(jme->dev)))
1111 goto out_inc;
1112
1113 i = atomic_read(&rxring->next_to_clean);
1114 while (limit > 0) {
1115 rxdesc = rxring->desc;
1116 rxdesc += i;
1117
1118 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1119 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1120 goto out;
1121 --limit;
1122
1123 rmb();
1124 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1125
1126 if (unlikely(desccnt > 1 ||
1127 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1128
1129 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1130 ++(NET_STAT(jme).rx_crc_errors);
1131 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1132 ++(NET_STAT(jme).rx_fifo_errors);
1133 else
1134 ++(NET_STAT(jme).rx_errors);
1135
1136 if (desccnt > 1)
1137 limit -= desccnt - 1;
1138
1139 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1140 jme_set_clean_rxdesc(jme, j);
1141 j = (j + 1) & (mask);
1142 }
1143
1144 } else {
1145 jme_alloc_and_feed_skb(jme, i);
1146 }
1147
1148 i = (i + desccnt) & (mask);
1149 }
1150
1151out:
1152 atomic_set(&rxring->next_to_clean, i);
1153
1154out_inc:
1155 atomic_inc(&jme->rx_cleaning);
1156
1157 return limit > 0 ? limit : 0;
1158
1159}
1160
1161static void
1162jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1163{
1164 if (likely(atmp == dpi->cur)) {
1165 dpi->cnt = 0;
1166 return;
1167 }
1168
1169 if (dpi->attempt == atmp) {
1170 ++(dpi->cnt);
1171 } else {
1172 dpi->attempt = atmp;
1173 dpi->cnt = 0;
1174 }
1175
1176}
1177
1178static void
1179jme_dynamic_pcc(struct jme_adapter *jme)
1180{
1181 register struct dynpcc_info *dpi = &(jme->dpi);
1182
1183 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1184 jme_attempt_pcc(dpi, PCC_P3);
1185 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1186 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1187 jme_attempt_pcc(dpi, PCC_P2);
1188 else
1189 jme_attempt_pcc(dpi, PCC_P1);
1190
1191 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1192 if (dpi->attempt < dpi->cur)
1193 tasklet_schedule(&jme->rxclean_task);
1194 jme_set_rx_pcc(jme, dpi->attempt);
1195 dpi->cur = dpi->attempt;
1196 dpi->cnt = 0;
1197 }
1198}
1199
1200static void
1201jme_start_pcc_timer(struct jme_adapter *jme)
1202{
1203 struct dynpcc_info *dpi = &(jme->dpi);
1204 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1205 dpi->last_pkts = NET_STAT(jme).rx_packets;
1206 dpi->intr_cnt = 0;
1207 jwrite32(jme, JME_TMCSR,
1208 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1209}
1210
1211static inline void
1212jme_stop_pcc_timer(struct jme_adapter *jme)
1213{
1214 jwrite32(jme, JME_TMCSR, 0);
1215}
1216
1217static void
1218jme_shutdown_nic(struct jme_adapter *jme)
1219{
1220 u32 phylink;
1221
1222 phylink = jme_linkstat_from_phy(jme);
1223
1224 if (!(phylink & PHY_LINK_UP)) {
1225 /*
1226 * Disable all interrupt before issue timer
1227 */
1228 jme_stop_irq(jme);
1229 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1230 }
1231}
1232
1233static void
1234jme_pcc_tasklet(unsigned long arg)
1235{
1236 struct jme_adapter *jme = (struct jme_adapter *)arg;
1237 struct net_device *netdev = jme->dev;
1238
1239 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1240 jme_shutdown_nic(jme);
1241 return;
1242 }
1243
1244 if (unlikely(!netif_carrier_ok(netdev) ||
1245 (atomic_read(&jme->link_changing) != 1)
1246 )) {
1247 jme_stop_pcc_timer(jme);
1248 return;
1249 }
1250
1251 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1252 jme_dynamic_pcc(jme);
1253
1254 jme_start_pcc_timer(jme);
1255}
1256
1257static inline void
1258jme_polling_mode(struct jme_adapter *jme)
1259{
1260 jme_set_rx_pcc(jme, PCC_OFF);
1261}
1262
1263static inline void
1264jme_interrupt_mode(struct jme_adapter *jme)
1265{
1266 jme_set_rx_pcc(jme, PCC_P1);
1267}
1268
1269static inline int
1270jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1271{
1272 u32 apmc;
1273 apmc = jread32(jme, JME_APMC);
1274 return apmc & JME_APMC_PSEUDO_HP_EN;
1275}
1276
1277static void
1278jme_start_shutdown_timer(struct jme_adapter *jme)
1279{
1280 u32 apmc;
1281
1282 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1283 apmc &= ~JME_APMC_EPIEN_CTRL;
1284 if (!no_extplug) {
1285 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1286 wmb();
1287 }
1288 jwrite32f(jme, JME_APMC, apmc);
1289
1290 jwrite32f(jme, JME_TIMER2, 0);
1291 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1292 jwrite32(jme, JME_TMCSR,
1293 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1294}
1295
1296static void
1297jme_stop_shutdown_timer(struct jme_adapter *jme)
1298{
1299 u32 apmc;
1300
1301 jwrite32f(jme, JME_TMCSR, 0);
1302 jwrite32f(jme, JME_TIMER2, 0);
1303 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1304
1305 apmc = jread32(jme, JME_APMC);
1306 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1307 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1308 wmb();
1309 jwrite32f(jme, JME_APMC, apmc);
1310}
1311
1312static void
1313jme_link_change_tasklet(unsigned long arg)
1314{
1315 struct jme_adapter *jme = (struct jme_adapter *)arg;
1316 struct net_device *netdev = jme->dev;
1317 int rc;
1318
1319 while (!atomic_dec_and_test(&jme->link_changing)) {
1320 atomic_inc(&jme->link_changing);
1321 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1322 while (atomic_read(&jme->link_changing) != 1)
1323 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1324 }
1325
1326 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1327 goto out;
1328
1329 jme->old_mtu = netdev->mtu;
1330 netif_stop_queue(netdev);
1331 if (jme_pseudo_hotplug_enabled(jme))
1332 jme_stop_shutdown_timer(jme);
1333
1334 jme_stop_pcc_timer(jme);
1335 tasklet_disable(&jme->txclean_task);
1336 tasklet_disable(&jme->rxclean_task);
1337 tasklet_disable(&jme->rxempty_task);
1338
1339 if (netif_carrier_ok(netdev)) {
1340 jme_disable_rx_engine(jme);
1341 jme_disable_tx_engine(jme);
1342 jme_reset_mac_processor(jme);
1343 jme_free_rx_resources(jme);
1344 jme_free_tx_resources(jme);
1345
1346 if (test_bit(JME_FLAG_POLL, &jme->flags))
1347 jme_polling_mode(jme);
1348
1349 netif_carrier_off(netdev);
1350 }
1351
1352 jme_check_link(netdev, 0);
1353 if (netif_carrier_ok(netdev)) {
1354 rc = jme_setup_rx_resources(jme);
1355 if (rc) {
1356 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1357 goto out_enable_tasklet;
1358 }
1359
1360 rc = jme_setup_tx_resources(jme);
1361 if (rc) {
1362 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1363 goto err_out_free_rx_resources;
1364 }
1365
1366 jme_enable_rx_engine(jme);
1367 jme_enable_tx_engine(jme);
1368
1369 netif_start_queue(netdev);
1370
1371 if (test_bit(JME_FLAG_POLL, &jme->flags))
1372 jme_interrupt_mode(jme);
1373
1374 jme_start_pcc_timer(jme);
1375 } else if (jme_pseudo_hotplug_enabled(jme)) {
1376 jme_start_shutdown_timer(jme);
1377 }
1378
1379 goto out_enable_tasklet;
1380
1381err_out_free_rx_resources:
1382 jme_free_rx_resources(jme);
1383out_enable_tasklet:
1384 tasklet_enable(&jme->txclean_task);
1385 tasklet_hi_enable(&jme->rxclean_task);
1386 tasklet_hi_enable(&jme->rxempty_task);
1387out:
1388 atomic_inc(&jme->link_changing);
1389}
1390
1391static void
1392jme_rx_clean_tasklet(unsigned long arg)
1393{
1394 struct jme_adapter *jme = (struct jme_adapter *)arg;
1395 struct dynpcc_info *dpi = &(jme->dpi);
1396
1397 jme_process_receive(jme, jme->rx_ring_size);
1398 ++(dpi->intr_cnt);
1399
1400}
1401
1402static int
1403jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1404{
1405 struct jme_adapter *jme = jme_napi_priv(holder);
1406 DECLARE_NETDEV
1407 int rest;
1408
1409 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1410
1411 while (atomic_read(&jme->rx_empty) > 0) {
1412 atomic_dec(&jme->rx_empty);
1413 ++(NET_STAT(jme).rx_dropped);
1414 jme_restart_rx_engine(jme);
1415 }
1416 atomic_inc(&jme->rx_empty);
1417
1418 if (rest) {
1419 JME_RX_COMPLETE(netdev, holder);
1420 jme_interrupt_mode(jme);
1421 }
1422
1423 JME_NAPI_WEIGHT_SET(budget, rest);
1424 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1425}
1426
1427static void
1428jme_rx_empty_tasklet(unsigned long arg)
1429{
1430 struct jme_adapter *jme = (struct jme_adapter *)arg;
1431
1432 if (unlikely(atomic_read(&jme->link_changing) != 1))
1433 return;
1434
1435 if (unlikely(!netif_carrier_ok(jme->dev)))
1436 return;
1437
1438 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1439
1440 jme_rx_clean_tasklet(arg);
1441
1442 while (atomic_read(&jme->rx_empty) > 0) {
1443 atomic_dec(&jme->rx_empty);
1444 ++(NET_STAT(jme).rx_dropped);
1445 jme_restart_rx_engine(jme);
1446 }
1447 atomic_inc(&jme->rx_empty);
1448}
1449
1450static void
1451jme_wake_queue_if_stopped(struct jme_adapter *jme)
1452{
1453 struct jme_ring *txring = &(jme->txring[0]);
1454
1455 smp_wmb();
1456 if (unlikely(netif_queue_stopped(jme->dev) &&
1457 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1458 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1459 netif_wake_queue(jme->dev);
1460 }
1461
1462}
1463
1464static void
1465jme_tx_clean_tasklet(unsigned long arg)
1466{
1467 struct jme_adapter *jme = (struct jme_adapter *)arg;
1468 struct jme_ring *txring = &(jme->txring[0]);
1469 struct txdesc *txdesc = txring->desc;
1470 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1471 int i, j, cnt = 0, max, err, mask;
1472
1473 tx_dbg(jme, "Into txclean\n");
1474
1475 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1476 goto out;
1477
1478 if (unlikely(atomic_read(&jme->link_changing) != 1))
1479 goto out;
1480
1481 if (unlikely(!netif_carrier_ok(jme->dev)))
1482 goto out;
1483
1484 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1485 mask = jme->tx_ring_mask;
1486
1487 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1488
1489 ctxbi = txbi + i;
1490
1491 if (likely(ctxbi->skb &&
1492 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1493
1494 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1495 i, ctxbi->nr_desc, jiffies);
1496
1497 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1498
1499 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1500 ttxbi = txbi + ((i + j) & (mask));
1501 txdesc[(i + j) & (mask)].dw[0] = 0;
1502
1503 pci_unmap_page(jme->pdev,
1504 ttxbi->mapping,
1505 ttxbi->len,
1506 PCI_DMA_TODEVICE);
1507
1508 ttxbi->mapping = 0;
1509 ttxbi->len = 0;
1510 }
1511
1512 dev_kfree_skb(ctxbi->skb);
1513
1514 cnt += ctxbi->nr_desc;
1515
1516 if (unlikely(err)) {
1517 ++(NET_STAT(jme).tx_carrier_errors);
1518 } else {
1519 ++(NET_STAT(jme).tx_packets);
1520 NET_STAT(jme).tx_bytes += ctxbi->len;
1521 }
1522
1523 ctxbi->skb = NULL;
1524 ctxbi->len = 0;
1525 ctxbi->start_xmit = 0;
1526
1527 } else {
1528 break;
1529 }
1530
1531 i = (i + ctxbi->nr_desc) & mask;
1532
1533 ctxbi->nr_desc = 0;
1534 }
1535
1536 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1537 atomic_set(&txring->next_to_clean, i);
1538 atomic_add(cnt, &txring->nr_free);
1539
1540 jme_wake_queue_if_stopped(jme);
1541
1542out:
1543 atomic_inc(&jme->tx_cleaning);
1544}
1545
1546static void
1547jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1548{
1549 /*
1550 * Disable interrupt
1551 */
1552 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1553
1554 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1555 /*
1556 * Link change event is critical
1557 * all other events are ignored
1558 */
1559 jwrite32(jme, JME_IEVE, intrstat);
1560 tasklet_schedule(&jme->linkch_task);
1561 goto out_reenable;
1562 }
1563
1564 if (intrstat & INTR_TMINTR) {
1565 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1566 tasklet_schedule(&jme->pcc_task);
1567 }
1568
1569 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1570 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1571 tasklet_schedule(&jme->txclean_task);
1572 }
1573
1574 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1575 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1576 INTR_PCCRX0 |
1577 INTR_RX0EMP)) |
1578 INTR_RX0);
1579 }
1580
1581 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1582 if (intrstat & INTR_RX0EMP)
1583 atomic_inc(&jme->rx_empty);
1584
1585 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1586 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1587 jme_polling_mode(jme);
1588 JME_RX_SCHEDULE(jme);
1589 }
1590 }
1591 } else {
1592 if (intrstat & INTR_RX0EMP) {
1593 atomic_inc(&jme->rx_empty);
1594 tasklet_hi_schedule(&jme->rxempty_task);
1595 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1596 tasklet_hi_schedule(&jme->rxclean_task);
1597 }
1598 }
1599
1600out_reenable:
1601 /*
1602 * Re-enable interrupt
1603 */
1604 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1605}
1606
1607#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1608static irqreturn_t
1609jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1610#else
1611static irqreturn_t
1612jme_intr(int irq, void *dev_id)
1613#endif
1614{
1615 struct net_device *netdev = dev_id;
1616 struct jme_adapter *jme = netdev_priv(netdev);
1617 u32 intrstat;
1618
1619 intrstat = jread32(jme, JME_IEVE);
1620
1621 /*
1622 * Check if it's really an interrupt for us
1623 */
1624 if (unlikely((intrstat & INTR_ENABLE) == 0))
1625 return IRQ_NONE;
1626
1627 /*
1628 * Check if the device still exist
1629 */
1630 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1631 return IRQ_NONE;
1632
1633 jme_intr_msi(jme, intrstat);
1634
1635 return IRQ_HANDLED;
1636}
1637
1638#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1639static irqreturn_t
1640jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1641#else
1642static irqreturn_t
1643jme_msi(int irq, void *dev_id)
1644#endif
1645{
1646 struct net_device *netdev = dev_id;
1647 struct jme_adapter *jme = netdev_priv(netdev);
1648 u32 intrstat;
1649
1650 intrstat = jread32(jme, JME_IEVE);
1651
1652 jme_intr_msi(jme, intrstat);
1653
1654 return IRQ_HANDLED;
1655}
1656
1657static void
1658jme_reset_link(struct jme_adapter *jme)
1659{
1660 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1661}
1662
1663static void
1664jme_restart_an(struct jme_adapter *jme)
1665{
1666 u32 bmcr;
1667
1668 spin_lock_bh(&jme->phy_lock);
1669 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1670 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1671 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1672 spin_unlock_bh(&jme->phy_lock);
1673}
1674
1675static int
1676jme_request_irq(struct jme_adapter *jme)
1677{
1678 int rc;
1679 struct net_device *netdev = jme->dev;
1680#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1681 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1682 int irq_flags = SA_SHIRQ;
1683#else
1684 irq_handler_t handler = jme_intr;
1685 int irq_flags = IRQF_SHARED;
1686#endif
1687
1688 if (!pci_enable_msi(jme->pdev)) {
1689 set_bit(JME_FLAG_MSI, &jme->flags);
1690 handler = jme_msi;
1691 irq_flags = 0;
1692 }
1693
1694 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1695 netdev);
1696 if (rc) {
1697 netdev_err(netdev,
1698 "Unable to request %s interrupt (return: %d)\n",
1699 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1700 rc);
1701
1702 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1703 pci_disable_msi(jme->pdev);
1704 clear_bit(JME_FLAG_MSI, &jme->flags);
1705 }
1706 } else {
1707 netdev->irq = jme->pdev->irq;
1708 }
1709
1710 return rc;
1711}
1712
1713static void
1714jme_free_irq(struct jme_adapter *jme)
1715{
1716 free_irq(jme->pdev->irq, jme->dev);
1717 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1718 pci_disable_msi(jme->pdev);
1719 clear_bit(JME_FLAG_MSI, &jme->flags);
1720 jme->dev->irq = jme->pdev->irq;
1721 }
1722}
1723
1724static inline void
1725jme_new_phy_on(struct jme_adapter *jme)
1726{
1727 u32 reg;
1728
1729 reg = jread32(jme, JME_PHY_PWR);
1730 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1731 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1732 jwrite32(jme, JME_PHY_PWR, reg);
1733
1734 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1735 reg &= ~PE1_GPREG0_PBG;
1736 reg |= PE1_GPREG0_ENBG;
1737 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1738}
1739
1740static inline void
1741jme_new_phy_off(struct jme_adapter *jme)
1742{
1743 u32 reg;
1744
1745 reg = jread32(jme, JME_PHY_PWR);
1746 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1747 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1748 jwrite32(jme, JME_PHY_PWR, reg);
1749
1750 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1751 reg &= ~PE1_GPREG0_PBG;
1752 reg |= PE1_GPREG0_PDD3COLD;
1753 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1754}
1755
1756static inline void
1757jme_phy_on(struct jme_adapter *jme)
1758{
1759 u32 bmcr;
1760
1761 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1762 bmcr &= ~BMCR_PDOWN;
1763 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1764
1765 if (new_phy_power_ctrl(jme->chip_main_rev))
1766 jme_new_phy_on(jme);
1767}
1768
1769static inline void
1770jme_phy_off(struct jme_adapter *jme)
1771{
1772 u32 bmcr;
1773
1774 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1775 bmcr |= BMCR_PDOWN;
1776 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1777
1778 if (new_phy_power_ctrl(jme->chip_main_rev))
1779 jme_new_phy_off(jme);
1780}
1781
1782static int
1783jme_open(struct net_device *netdev)
1784{
1785 struct jme_adapter *jme = netdev_priv(netdev);
1786 int rc;
1787
1788 jme_clear_pm(jme);
1789 JME_NAPI_ENABLE(jme);
1790
1791 tasklet_enable(&jme->linkch_task);
1792 tasklet_enable(&jme->txclean_task);
1793 tasklet_hi_enable(&jme->rxclean_task);
1794 tasklet_hi_enable(&jme->rxempty_task);
1795
1796 rc = jme_request_irq(jme);
1797 if (rc)
1798 goto err_out;
1799
1800 jme_start_irq(jme);
1801
1802 jme_phy_on(jme);
1803 if (test_bit(JME_FLAG_SSET, &jme->flags))
1804 jme_set_settings(netdev, &jme->old_ecmd);
1805 else
1806 jme_reset_phy_processor(jme);
1807
1808 jme_reset_link(jme);
1809
1810 return 0;
1811
1812err_out:
1813 netif_stop_queue(netdev);
1814 netif_carrier_off(netdev);
1815 return rc;
1816}
1817
1818static void
1819jme_set_100m_half(struct jme_adapter *jme)
1820{
1821 u32 bmcr, tmp;
1822
1823 jme_phy_on(jme);
1824 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1825 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1826 BMCR_SPEED1000 | BMCR_FULLDPLX);
1827 tmp |= BMCR_SPEED100;
1828
1829 if (bmcr != tmp)
1830 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1831
1832 if (jme->fpgaver)
1833 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1834 else
1835 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1836}
1837
1838#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1839static void
1840jme_wait_link(struct jme_adapter *jme)
1841{
1842 u32 phylink, to = JME_WAIT_LINK_TIME;
1843
1844 mdelay(1000);
1845 phylink = jme_linkstat_from_phy(jme);
1846 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1847 mdelay(10);
1848 phylink = jme_linkstat_from_phy(jme);
1849 }
1850}
1851
1852static void
1853jme_powersave_phy(struct jme_adapter *jme)
1854{
1855 if (jme->reg_pmcs) {
1856 jme_set_100m_half(jme);
1857
1858 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1859 jme_wait_link(jme);
1860
1861 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1862 } else {
1863 jme_phy_off(jme);
1864 }
1865}
1866
1867static int
1868jme_close(struct net_device *netdev)
1869{
1870 struct jme_adapter *jme = netdev_priv(netdev);
1871
1872 netif_stop_queue(netdev);
1873 netif_carrier_off(netdev);
1874
1875 jme_stop_irq(jme);
1876 jme_free_irq(jme);
1877
1878 JME_NAPI_DISABLE(jme);
1879
1880 tasklet_disable(&jme->linkch_task);
1881 tasklet_disable(&jme->txclean_task);
1882 tasklet_disable(&jme->rxclean_task);
1883 tasklet_disable(&jme->rxempty_task);
1884
1885 jme_disable_rx_engine(jme);
1886 jme_disable_tx_engine(jme);
1887 jme_reset_mac_processor(jme);
1888 jme_free_rx_resources(jme);
1889 jme_free_tx_resources(jme);
1890 jme->phylink = 0;
1891 jme_phy_off(jme);
1892
1893 return 0;
1894}
1895
1896static int
1897jme_alloc_txdesc(struct jme_adapter *jme,
1898 struct sk_buff *skb)
1899{
1900 struct jme_ring *txring = &(jme->txring[0]);
1901 int idx, nr_alloc, mask = jme->tx_ring_mask;
1902
1903 idx = txring->next_to_use;
1904 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1905
1906 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1907 return -1;
1908
1909 atomic_sub(nr_alloc, &txring->nr_free);
1910
1911 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1912
1913 return idx;
1914}
1915
1916static void
1917jme_fill_tx_map(struct pci_dev *pdev,
1918 struct txdesc *txdesc,
1919 struct jme_buffer_info *txbi,
1920 struct page *page,
1921 u32 page_offset,
1922 u32 len,
1923 u8 hidma)
1924{
1925 dma_addr_t dmaaddr;
1926
1927 dmaaddr = pci_map_page(pdev,
1928 page,
1929 page_offset,
1930 len,
1931 PCI_DMA_TODEVICE);
1932
1933 pci_dma_sync_single_for_device(pdev,
1934 dmaaddr,
1935 len,
1936 PCI_DMA_TODEVICE);
1937
1938 txdesc->dw[0] = 0;
1939 txdesc->dw[1] = 0;
1940 txdesc->desc2.flags = TXFLAG_OWN;
1941 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1942 txdesc->desc2.datalen = cpu_to_le16(len);
1943 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1944 txdesc->desc2.bufaddrl = cpu_to_le32(
1945 (__u64)dmaaddr & 0xFFFFFFFFUL);
1946
1947 txbi->mapping = dmaaddr;
1948 txbi->len = len;
1949}
1950
1951static void
1952jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1953{
1954 struct jme_ring *txring = &(jme->txring[0]);
1955 struct txdesc *txdesc = txring->desc, *ctxdesc;
1956 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1957 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1958 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1959 int mask = jme->tx_ring_mask;
1960 struct skb_frag_struct *frag;
1961 u32 len;
1962
1963 for (i = 0 ; i < nr_frags ; ++i) {
1964 frag = &skb_shinfo(skb)->frags[i];
1965 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1966 ctxbi = txbi + ((idx + i + 2) & (mask));
1967
1968 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1969 frag->page_offset, frag->size, hidma);
1970 }
1971
1972 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1973 ctxdesc = txdesc + ((idx + 1) & (mask));
1974 ctxbi = txbi + ((idx + 1) & (mask));
1975 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1976 offset_in_page(skb->data), len, hidma);
1977
1978}
1979
1980static int
1981jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1982{
1983 if (unlikely(
1984#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1985 skb_shinfo(skb)->tso_size
1986#else
1987 skb_shinfo(skb)->gso_size
1988#endif
1989 && skb_header_cloned(skb) &&
1990 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1991 dev_kfree_skb(skb);
1992 return -1;
1993 }
1994
1995 return 0;
1996}
1997
1998static int
1999jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2000{
2001#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2002 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2003#else
2004 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2005#endif
2006 if (*mss) {
2007 *flags |= TXFLAG_LSEN;
2008
2009 if (skb->protocol == htons(ETH_P_IP)) {
2010 struct iphdr *iph = ip_hdr(skb);
2011
2012 iph->check = 0;
2013 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2014 iph->daddr, 0,
2015 IPPROTO_TCP,
2016 0);
2017 } else {
2018 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2019
2020 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2021 &ip6h->daddr, 0,
2022 IPPROTO_TCP,
2023 0);
2024 }
2025
2026 return 0;
2027 }
2028
2029 return 1;
2030}
2031
2032static void
2033jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2034{
2035#ifdef CHECKSUM_PARTIAL
2036 if (skb->ip_summed == CHECKSUM_PARTIAL)
2037#else
2038 if (skb->ip_summed == CHECKSUM_HW)
2039#endif
2040 {
2041 u8 ip_proto;
2042
2043#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2044 if (skb->protocol == htons(ETH_P_IP))
2045 ip_proto = ip_hdr(skb)->protocol;
2046 else if (skb->protocol == htons(ETH_P_IPV6))
2047 ip_proto = ipv6_hdr(skb)->nexthdr;
2048 else
2049 ip_proto = 0;
2050#else
2051 switch (skb->protocol) {
2052 case htons(ETH_P_IP):
2053 ip_proto = ip_hdr(skb)->protocol;
2054 break;
2055 case htons(ETH_P_IPV6):
2056 ip_proto = ipv6_hdr(skb)->nexthdr;
2057 break;
2058 default:
2059 ip_proto = 0;
2060 break;
2061 }
2062#endif
2063
2064 switch (ip_proto) {
2065 case IPPROTO_TCP:
2066 *flags |= TXFLAG_TCPCS;
2067 break;
2068 case IPPROTO_UDP:
2069 *flags |= TXFLAG_UDPCS;
2070 break;
2071 default:
2072 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2073 break;
2074 }
2075 }
2076}
2077
2078static inline void
2079jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2080{
2081 if (vlan_tx_tag_present(skb)) {
2082 *flags |= TXFLAG_TAGON;
2083 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2084 }
2085}
2086
2087static int
2088jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2089{
2090 struct jme_ring *txring = &(jme->txring[0]);
2091 struct txdesc *txdesc;
2092 struct jme_buffer_info *txbi;
2093 u8 flags;
2094
2095 txdesc = (struct txdesc *)txring->desc + idx;
2096 txbi = txring->bufinf + idx;
2097
2098 txdesc->dw[0] = 0;
2099 txdesc->dw[1] = 0;
2100 txdesc->dw[2] = 0;
2101 txdesc->dw[3] = 0;
2102 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2103 /*
2104 * Set OWN bit at final.
2105 * When kernel transmit faster than NIC.
2106 * And NIC trying to send this descriptor before we tell
2107 * it to start sending this TX queue.
2108 * Other fields are already filled correctly.
2109 */
2110 wmb();
2111 flags = TXFLAG_OWN | TXFLAG_INT;
2112 /*
2113 * Set checksum flags while not tso
2114 */
2115 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2116 jme_tx_csum(jme, skb, &flags);
2117 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2118 jme_map_tx_skb(jme, skb, idx);
2119 txdesc->desc1.flags = flags;
2120 /*
2121 * Set tx buffer info after telling NIC to send
2122 * For better tx_clean timing
2123 */
2124 wmb();
2125 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2126 txbi->skb = skb;
2127 txbi->len = skb->len;
2128 txbi->start_xmit = jiffies;
2129 if (!txbi->start_xmit)
2130 txbi->start_xmit = (0UL-1);
2131
2132 return 0;
2133}
2134
2135static void
2136jme_stop_queue_if_full(struct jme_adapter *jme)
2137{
2138 struct jme_ring *txring = &(jme->txring[0]);
2139 struct jme_buffer_info *txbi = txring->bufinf;
2140 int idx = atomic_read(&txring->next_to_clean);
2141
2142 txbi += idx;
2143
2144 smp_wmb();
2145 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2146 netif_stop_queue(jme->dev);
2147 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2148 smp_wmb();
2149 if (atomic_read(&txring->nr_free)
2150 >= (jme->tx_wake_threshold)) {
2151 netif_wake_queue(jme->dev);
2152 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2153 }
2154 }
2155
2156 if (unlikely(txbi->start_xmit &&
2157 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2158 txbi->skb)) {
2159 netif_stop_queue(jme->dev);
2160 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2161 }
2162}
2163
2164/*
2165 * This function is already protected by netif_tx_lock()
2166 */
2167
2168#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2169static int
2170#else
2171static netdev_tx_t
2172#endif
2173jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2174{
2175 struct jme_adapter *jme = netdev_priv(netdev);
2176 int idx;
2177
2178 if (unlikely(jme_expand_header(jme, skb))) {
2179 ++(NET_STAT(jme).tx_dropped);
2180 return NETDEV_TX_OK;
2181 }
2182
2183 idx = jme_alloc_txdesc(jme, skb);
2184
2185 if (unlikely(idx < 0)) {
2186 netif_stop_queue(netdev);
2187 netif_err(jme, tx_err, jme->dev,
2188 "BUG! Tx ring full when queue awake!\n");
2189
2190 return NETDEV_TX_BUSY;
2191 }
2192
2193 jme_fill_tx_desc(jme, skb, idx);
2194
2195 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2196 TXCS_SELECT_QUEUE0 |
2197 TXCS_QUEUE0S |
2198 TXCS_ENABLE);
2199#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2200 netdev->trans_start = jiffies;
2201#endif
2202
2203 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2204 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2205 jme_stop_queue_if_full(jme);
2206
2207 return NETDEV_TX_OK;
2208}
2209
2210static void
2211jme_set_unicastaddr(struct net_device *netdev)
2212{
2213 struct jme_adapter *jme = netdev_priv(netdev);
2214 u32 val;
2215
2216 val = (netdev->dev_addr[3] & 0xff) << 24 |
2217 (netdev->dev_addr[2] & 0xff) << 16 |
2218 (netdev->dev_addr[1] & 0xff) << 8 |
2219 (netdev->dev_addr[0] & 0xff);
2220 jwrite32(jme, JME_RXUMA_LO, val);
2221 val = (netdev->dev_addr[5] & 0xff) << 8 |
2222 (netdev->dev_addr[4] & 0xff);
2223 jwrite32(jme, JME_RXUMA_HI, val);
2224}
2225
2226static int
2227jme_set_macaddr(struct net_device *netdev, void *p)
2228{
2229 struct jme_adapter *jme = netdev_priv(netdev);
2230 struct sockaddr *addr = p;
2231
2232 if (netif_running(netdev))
2233 return -EBUSY;
2234
2235 spin_lock_bh(&jme->macaddr_lock);
2236 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2237 jme_set_unicastaddr(netdev);
2238 spin_unlock_bh(&jme->macaddr_lock);
2239
2240 return 0;
2241}
2242
2243static void
2244jme_set_multi(struct net_device *netdev)
2245{
2246 struct jme_adapter *jme = netdev_priv(netdev);
2247 u32 mc_hash[2] = {};
2248#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2249 int i;
2250#endif
2251
2252 spin_lock_bh(&jme->rxmcs_lock);
2253
2254 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2255
2256 if (netdev->flags & IFF_PROMISC) {
2257 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2258 } else if (netdev->flags & IFF_ALLMULTI) {
2259 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2260 } else if (netdev->flags & IFF_MULTICAST) {
2261#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2262 struct dev_mc_list *mclist;
2263#else
2264 struct netdev_hw_addr *ha;
2265#endif
2266 int bit_nr;
2267
2268 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2269#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2270 for (i = 0, mclist = netdev->mc_list;
2271 mclist && i < netdev->mc_count;
2272 ++i, mclist = mclist->next) {
2273#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2274 netdev_for_each_mc_addr(mclist, netdev) {
2275#else
2276 netdev_for_each_mc_addr(ha, netdev) {
2277#endif
2278#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2279 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2280#else
2281 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2282#endif
2283 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2284 }
2285
2286 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2287 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2288 }
2289
2290 wmb();
2291 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2292
2293 spin_unlock_bh(&jme->rxmcs_lock);
2294}
2295
2296static int
2297jme_change_mtu(struct net_device *netdev, int new_mtu)
2298{
2299 struct jme_adapter *jme = netdev_priv(netdev);
2300
2301 if (new_mtu == jme->old_mtu)
2302 return 0;
2303
2304 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2305 ((new_mtu) < IPV6_MIN_MTU))
2306 return -EINVAL;
2307
2308 if (new_mtu > 4000) {
2309 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2310 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2311 jme_restart_rx_engine(jme);
2312 } else {
2313 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2314 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2315 jme_restart_rx_engine(jme);
2316 }
2317
2318 if (new_mtu > 1900) {
2319 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2320 NETIF_F_TSO | NETIF_F_TSO6);
2321 } else {
2322 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2323 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2324 if (test_bit(JME_FLAG_TSO, &jme->flags))
2325 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2326 }
2327
2328 netdev->mtu = new_mtu;
2329 jme_reset_link(jme);
2330
2331 return 0;
2332}
2333
2334static void
2335jme_tx_timeout(struct net_device *netdev)
2336{
2337 struct jme_adapter *jme = netdev_priv(netdev);
2338
2339 jme->phylink = 0;
2340 jme_reset_phy_processor(jme);
2341 if (test_bit(JME_FLAG_SSET, &jme->flags))
2342 jme_set_settings(netdev, &jme->old_ecmd);
2343
2344 /*
2345 * Force to Reset the link again
2346 */
2347 jme_reset_link(jme);
2348}
2349
2350static inline void jme_pause_rx(struct jme_adapter *jme)
2351{
2352 atomic_dec(&jme->link_changing);
2353
2354 jme_set_rx_pcc(jme, PCC_OFF);
2355 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2356 JME_NAPI_DISABLE(jme);
2357 } else {
2358 tasklet_disable(&jme->rxclean_task);
2359 tasklet_disable(&jme->rxempty_task);
2360 }
2361}
2362
2363static inline void jme_resume_rx(struct jme_adapter *jme)
2364{
2365 struct dynpcc_info *dpi = &(jme->dpi);
2366
2367 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2368 JME_NAPI_ENABLE(jme);
2369 } else {
2370 tasklet_hi_enable(&jme->rxclean_task);
2371 tasklet_hi_enable(&jme->rxempty_task);
2372 }
2373 dpi->cur = PCC_P1;
2374 dpi->attempt = PCC_P1;
2375 dpi->cnt = 0;
2376 jme_set_rx_pcc(jme, PCC_P1);
2377
2378 atomic_inc(&jme->link_changing);
2379}
2380
2381static void
2382jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2383{
2384 struct jme_adapter *jme = netdev_priv(netdev);
2385
2386 jme_pause_rx(jme);
2387 jme->vlgrp = grp;
2388 jme_resume_rx(jme);
2389}
2390
2391#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2392static void
2393jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2394{
2395 struct jme_adapter *jme = netdev_priv(netdev);
2396
2397 if(jme->vlgrp) {
2398 jme_pause_rx(jme);
2399#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2400 jme->vlgrp->vlan_devices[vid] = NULL;
2401#else
2402 vlan_group_set_device(jme->vlgrp, vid, NULL);
2403#endif
2404 jme_resume_rx(jme);
2405 }
2406}
2407#endif
2408
2409static void
2410jme_get_drvinfo(struct net_device *netdev,
2411 struct ethtool_drvinfo *info)
2412{
2413 struct jme_adapter *jme = netdev_priv(netdev);
2414
2415 strcpy(info->driver, DRV_NAME);
2416 strcpy(info->version, DRV_VERSION);
2417 strcpy(info->bus_info, pci_name(jme->pdev));
2418}
2419
2420static int
2421jme_get_regs_len(struct net_device *netdev)
2422{
2423 return JME_REG_LEN;
2424}
2425
2426static void
2427mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2428{
2429 int i;
2430
2431 for (i = 0 ; i < len ; i += 4)
2432 p[i >> 2] = jread32(jme, reg + i);
2433}
2434
2435static void
2436mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2437{
2438 int i;
2439 u16 *p16 = (u16 *)p;
2440
2441 for (i = 0 ; i < reg_nr ; ++i)
2442 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2443}
2444
2445static void
2446jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2447{
2448 struct jme_adapter *jme = netdev_priv(netdev);
2449 u32 *p32 = (u32 *)p;
2450
2451 memset(p, 0xFF, JME_REG_LEN);
2452
2453 regs->version = 1;
2454 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2455
2456 p32 += 0x100 >> 2;
2457 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2458
2459 p32 += 0x100 >> 2;
2460 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2461
2462 printk("===jread32=%x===\n",jread32(jme, JME_EXGP2));
2463
2464 p32 += 0x100 >> 2;
2465 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2466
2467 p32 += 0x100 >> 2;
2468 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2469}
2470
2471static int
2472jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2473{
2474 struct jme_adapter *jme = netdev_priv(netdev);
2475
2476 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2477 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2478
2479 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2480 ecmd->use_adaptive_rx_coalesce = false;
2481 ecmd->rx_coalesce_usecs = 0;
2482 ecmd->rx_max_coalesced_frames = 0;
2483 return 0;
2484 }
2485
2486 ecmd->use_adaptive_rx_coalesce = true;
2487
2488 switch (jme->dpi.cur) {
2489 case PCC_P1:
2490 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2491 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2492 break;
2493 case PCC_P2:
2494 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2495 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2496 break;
2497 case PCC_P3:
2498 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2499 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2500 break;
2501 default:
2502 break;
2503 }
2504
2505 return 0;
2506}
2507
2508static int
2509jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2510{
2511 struct jme_adapter *jme = netdev_priv(netdev);
2512 struct dynpcc_info *dpi = &(jme->dpi);
2513
2514 if (netif_running(netdev))
2515 return -EBUSY;
2516
2517 if (ecmd->use_adaptive_rx_coalesce &&
2518 test_bit(JME_FLAG_POLL, &jme->flags)) {
2519 clear_bit(JME_FLAG_POLL, &jme->flags);
2520 jme->jme_rx = netif_rx;
2521 jme->jme_vlan_rx = vlan_hwaccel_rx;
2522 dpi->cur = PCC_P1;
2523 dpi->attempt = PCC_P1;
2524 dpi->cnt = 0;
2525 jme_set_rx_pcc(jme, PCC_P1);
2526 jme_interrupt_mode(jme);
2527 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2528 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2529 set_bit(JME_FLAG_POLL, &jme->flags);
2530 jme->jme_rx = netif_receive_skb;
2531 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2532 jme_interrupt_mode(jme);
2533 }
2534
2535 return 0;
2536}
2537
2538static void
2539jme_get_pauseparam(struct net_device *netdev,
2540 struct ethtool_pauseparam *ecmd)
2541{
2542 struct jme_adapter *jme = netdev_priv(netdev);
2543 u32 val;
2544
2545 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2546 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2547
2548 spin_lock_bh(&jme->phy_lock);
2549 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2550 spin_unlock_bh(&jme->phy_lock);
2551
2552 ecmd->autoneg =
2553 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2554}
2555
2556static int
2557jme_set_pauseparam(struct net_device *netdev,
2558 struct ethtool_pauseparam *ecmd)
2559{
2560 struct jme_adapter *jme = netdev_priv(netdev);
2561 u32 val;
2562
2563 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2564 (ecmd->tx_pause != 0)) {
2565
2566 if (ecmd->tx_pause)
2567 jme->reg_txpfc |= TXPFC_PF_EN;
2568 else
2569 jme->reg_txpfc &= ~TXPFC_PF_EN;
2570
2571 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2572 }
2573
2574 spin_lock_bh(&jme->rxmcs_lock);
2575 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2576 (ecmd->rx_pause != 0)) {
2577
2578 if (ecmd->rx_pause)
2579 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2580 else
2581 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2582
2583 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2584 }
2585 spin_unlock_bh(&jme->rxmcs_lock);
2586
2587 spin_lock_bh(&jme->phy_lock);
2588 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2589 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2590 (ecmd->autoneg != 0)) {
2591
2592 if (ecmd->autoneg)
2593 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2594 else
2595 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2596
2597 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2598 MII_ADVERTISE, val);
2599 }
2600 spin_unlock_bh(&jme->phy_lock);
2601
2602 return 0;
2603}
2604
2605static void
2606jme_get_wol(struct net_device *netdev,
2607 struct ethtool_wolinfo *wol)
2608{
2609 struct jme_adapter *jme = netdev_priv(netdev);
2610
2611 wol->supported = WAKE_MAGIC | WAKE_PHY;
2612
2613 wol->wolopts = 0;
2614
2615 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2616 wol->wolopts |= WAKE_PHY;
2617
2618 if (jme->reg_pmcs & PMCS_MFEN)
2619 wol->wolopts |= WAKE_MAGIC;
2620
2621}
2622
2623static int
2624jme_set_wol(struct net_device *netdev,
2625 struct ethtool_wolinfo *wol)
2626{
2627 struct jme_adapter *jme = netdev_priv(netdev);
2628
2629 if (wol->wolopts & (WAKE_MAGICSECURE |
2630 WAKE_UCAST |
2631 WAKE_MCAST |
2632 WAKE_BCAST |
2633 WAKE_ARP))
2634 return -EOPNOTSUPP;
2635
2636 jme->reg_pmcs = 0;
2637
2638 if (wol->wolopts & WAKE_PHY)
2639 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2640
2641 if (wol->wolopts & WAKE_MAGIC)
2642 jme->reg_pmcs |= PMCS_MFEN;
2643
2644 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2645
2646 return 0;
2647}
2648
2649static int
2650jme_get_settings(struct net_device *netdev,
2651 struct ethtool_cmd *ecmd)
2652{
2653 struct jme_adapter *jme = netdev_priv(netdev);
2654 int rc;
2655
2656 spin_lock_bh(&jme->phy_lock);
2657 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2658 spin_unlock_bh(&jme->phy_lock);
2659 return rc;
2660}
2661
2662static int
2663jme_set_settings(struct net_device *netdev,
2664 struct ethtool_cmd *ecmd)
2665{
2666 struct jme_adapter *jme = netdev_priv(netdev);
2667 int rc, fdc = 0;
2668
2669 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2670 return -EINVAL;
2671
2672 /*
2673 * Check If user changed duplex only while force_media.
2674 * Hardware would not generate link change interrupt.
2675 */
2676 if (jme->mii_if.force_media &&
2677 ecmd->autoneg != AUTONEG_ENABLE &&
2678 (jme->mii_if.full_duplex != ecmd->duplex))
2679 fdc = 1;
2680
2681 spin_lock_bh(&jme->phy_lock);
2682 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2683 spin_unlock_bh(&jme->phy_lock);
2684
2685 if (!rc) {
2686 if (fdc)
2687 jme_reset_link(jme);
2688 jme->old_ecmd = *ecmd;
2689 set_bit(JME_FLAG_SSET, &jme->flags);
2690 }
2691
2692 return rc;
2693}
2694
2695static int
2696jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2697{
2698 int rc;
2699 struct jme_adapter *jme = netdev_priv(netdev);
2700 struct mii_ioctl_data *mii_data = if_mii(rq);
2701 unsigned int duplex_chg;
2702
2703 if (cmd == SIOCSMIIREG) {
2704 u16 val = mii_data->val_in;
2705 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2706 (val & BMCR_SPEED1000))
2707 return -EINVAL;
2708 }
2709
2710 spin_lock_bh(&jme->phy_lock);
2711 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2712 spin_unlock_bh(&jme->phy_lock);
2713
2714 if (!rc && (cmd == SIOCSMIIREG)) {
2715 if (duplex_chg)
2716 jme_reset_link(jme);
2717 jme_get_settings(netdev, &jme->old_ecmd);
2718 set_bit(JME_FLAG_SSET, &jme->flags);
2719 }
2720
2721 return rc;
2722}
2723
2724static u32
2725jme_get_link(struct net_device *netdev)
2726{
2727 struct jme_adapter *jme = netdev_priv(netdev);
2728 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2729}
2730
2731static u32
2732jme_get_msglevel(struct net_device *netdev)
2733{
2734 struct jme_adapter *jme = netdev_priv(netdev);
2735 return jme->msg_enable;
2736}
2737
2738static void
2739jme_set_msglevel(struct net_device *netdev, u32 value)
2740{
2741 struct jme_adapter *jme = netdev_priv(netdev);
2742 jme->msg_enable = value;
2743}
2744
2745static u32
2746jme_get_rx_csum(struct net_device *netdev)
2747{
2748 struct jme_adapter *jme = netdev_priv(netdev);
2749 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2750}
2751
2752static int
2753jme_set_rx_csum(struct net_device *netdev, u32 on)
2754{
2755 struct jme_adapter *jme = netdev_priv(netdev);
2756
2757 spin_lock_bh(&jme->rxmcs_lock);
2758 if (on)
2759 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2760 else
2761 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2762 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2763 spin_unlock_bh(&jme->rxmcs_lock);
2764
2765 return 0;
2766}
2767
2768static int
2769jme_set_tx_csum(struct net_device *netdev, u32 on)
2770{
2771 struct jme_adapter *jme = netdev_priv(netdev);
2772
2773 if (on) {
2774 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2775 if (netdev->mtu <= 1900)
2776 netdev->features |=
2777 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2778 } else {
2779 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2780 netdev->features &=
2781 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2782 }
2783
2784 return 0;
2785}
2786
2787static int
2788jme_set_tso(struct net_device *netdev, u32 on)
2789{
2790 struct jme_adapter *jme = netdev_priv(netdev);
2791
2792 if (on) {
2793 set_bit(JME_FLAG_TSO, &jme->flags);
2794 if (netdev->mtu <= 1900)
2795 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2796 } else {
2797 clear_bit(JME_FLAG_TSO, &jme->flags);
2798 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2799 }
2800
2801 return 0;
2802}
2803
2804static int
2805jme_nway_reset(struct net_device *netdev)
2806{
2807 struct jme_adapter *jme = netdev_priv(netdev);
2808 jme_restart_an(jme);
2809 return 0;
2810}
2811
2812static u8
2813jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2814{
2815 u32 val;
2816 int to;
2817
2818 val = jread32(jme, JME_SMBCSR);
2819 to = JME_SMB_BUSY_TIMEOUT;
2820 while ((val & SMBCSR_BUSY) && --to) {
2821 msleep(1);
2822 val = jread32(jme, JME_SMBCSR);
2823 }
2824 if (!to) {
2825 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2826 return 0xFF;
2827 }
2828
2829 jwrite32(jme, JME_SMBINTF,
2830 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2831 SMBINTF_HWRWN_READ |
2832 SMBINTF_HWCMD);
2833
2834 val = jread32(jme, JME_SMBINTF);
2835 to = JME_SMB_BUSY_TIMEOUT;
2836 while ((val & SMBINTF_HWCMD) && --to) {
2837 msleep(1);
2838 val = jread32(jme, JME_SMBINTF);
2839 }
2840 if (!to) {
2841 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2842 return 0xFF;
2843 }
2844
2845 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2846}
2847
2848static void
2849jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2850{
2851 u32 val;
2852 int to;
2853
2854 val = jread32(jme, JME_SMBCSR);
2855 to = JME_SMB_BUSY_TIMEOUT;
2856 while ((val & SMBCSR_BUSY) && --to) {
2857 msleep(1);
2858 val = jread32(jme, JME_SMBCSR);
2859 }
2860 if (!to) {
2861 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2862 return;
2863 }
2864
2865 jwrite32(jme, JME_SMBINTF,
2866 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2867 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2868 SMBINTF_HWRWN_WRITE |
2869 SMBINTF_HWCMD);
2870
2871 val = jread32(jme, JME_SMBINTF);
2872 to = JME_SMB_BUSY_TIMEOUT;
2873 while ((val & SMBINTF_HWCMD) && --to) {
2874 msleep(1);
2875 val = jread32(jme, JME_SMBINTF);
2876 }
2877 if (!to) {
2878 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2879 return;
2880 }
2881
2882 mdelay(2);
2883}
2884
2885static int
2886jme_get_eeprom_len(struct net_device *netdev)
2887{
2888 struct jme_adapter *jme = netdev_priv(netdev);
2889 u32 val;
2890 val = jread32(jme, JME_SMBCSR);
2891 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2892}
2893
2894static int
2895jme_get_eeprom(struct net_device *netdev,
2896 struct ethtool_eeprom *eeprom, u8 *data)
2897{
2898 struct jme_adapter *jme = netdev_priv(netdev);
2899 int i, offset = eeprom->offset, len = eeprom->len;
2900
2901 /*
2902 * ethtool will check the boundary for us
2903 */
2904 eeprom->magic = JME_EEPROM_MAGIC;
2905 for (i = 0 ; i < len ; ++i)
2906 data[i] = jme_smb_read(jme, i + offset);
2907
2908 return 0;
2909}
2910
2911static int
2912jme_set_eeprom(struct net_device *netdev,
2913 struct ethtool_eeprom *eeprom, u8 *data)
2914{
2915 struct jme_adapter *jme = netdev_priv(netdev);
2916 int i, offset = eeprom->offset, len = eeprom->len;
2917
2918 if (eeprom->magic != JME_EEPROM_MAGIC)
2919 return -EINVAL;
2920
2921 /*
2922 * ethtool will check the boundary for us
2923 */
2924 for (i = 0 ; i < len ; ++i)
2925 jme_smb_write(jme, i + offset, data[i]);
2926
2927 return 0;
2928}
2929
2930#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2931static struct ethtool_ops jme_ethtool_ops = {
2932#else
2933static const struct ethtool_ops jme_ethtool_ops = {
2934#endif
2935 .get_drvinfo = jme_get_drvinfo,
2936 .get_regs_len = jme_get_regs_len,
2937 .get_regs = jme_get_regs,
2938 .get_coalesce = jme_get_coalesce,
2939 .set_coalesce = jme_set_coalesce,
2940 .get_pauseparam = jme_get_pauseparam,
2941 .set_pauseparam = jme_set_pauseparam,
2942 .get_wol = jme_get_wol,
2943 .set_wol = jme_set_wol,
2944 .get_settings = jme_get_settings,
2945 .set_settings = jme_set_settings,
2946 .get_link = jme_get_link,
2947 .get_msglevel = jme_get_msglevel,
2948 .set_msglevel = jme_set_msglevel,
2949 .get_rx_csum = jme_get_rx_csum,
2950 .set_rx_csum = jme_set_rx_csum,
2951 .set_tx_csum = jme_set_tx_csum,
2952 .set_tso = jme_set_tso,
2953 .set_sg = ethtool_op_set_sg,
2954 .nway_reset = jme_nway_reset,
2955 .get_eeprom_len = jme_get_eeprom_len,
2956 .get_eeprom = jme_get_eeprom,
2957 .set_eeprom = jme_set_eeprom,
2958};
2959
2960static int
2961jme_pci_dma64(struct pci_dev *pdev)
2962{
2963 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2964#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2965 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2966#else
2967 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2968#endif
2969 )
2970#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2971 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2972#else
2973 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2974#endif
2975 return 1;
2976
2977 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2978#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2979 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2980#else
2981 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2982#endif
2983 )
2984#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2985 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2986#else
2987 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2988#endif
2989 return 1;
2990
2991#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2992 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2993 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2994#else
2995 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2996 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2997#endif
2998 return 0;
2999
3000 return -1;
3001}
3002
3003static inline void
3004jme_phy_init(struct jme_adapter *jme)
3005{
3006 u16 reg26;
3007
3008 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3009 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3010}
3011
3012static inline void
3013jme_check_hw_ver(struct jme_adapter *jme)
3014{
3015 u32 chipmode;
3016
3017 chipmode = jread32(jme, JME_CHIPMODE);
3018
3019 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3020 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3021 jme->chip_main_rev = jme->chiprev & 0xF;
3022 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3023}
3024
3025#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3026static const struct net_device_ops jme_netdev_ops = {
3027 .ndo_open = jme_open,
3028 .ndo_stop = jme_close,
3029 .ndo_validate_addr = eth_validate_addr,
3030 .ndo_do_ioctl = jme_ioctl,
3031 .ndo_start_xmit = jme_start_xmit,
3032 .ndo_set_mac_address = jme_set_macaddr,
3033 .ndo_set_multicast_list = jme_set_multi,
3034 .ndo_change_mtu = jme_change_mtu,
3035 .ndo_tx_timeout = jme_tx_timeout,
3036 .ndo_vlan_rx_register = jme_vlan_rx_register,
3037};
3038#endif
3039
3040static int __devinit
3041jme_init_one(struct pci_dev *pdev,
3042 const struct pci_device_id *ent)
3043{
3044 int rc = 0, using_dac, i;
3045 struct net_device *netdev;
3046 struct jme_adapter *jme;
3047 u16 bmcr, bmsr;
3048 u32 apmc, phy_gp2;
3049
3050 /*
3051 * set up PCI device basics
3052 */
3053 rc = pci_enable_device(pdev);
3054 if (rc) {
3055 pr_err("Cannot enable PCI device\n");
3056 goto err_out;
3057 }
3058
3059 using_dac = jme_pci_dma64(pdev);
3060 if (using_dac < 0) {
3061 pr_err("Cannot set PCI DMA Mask\n");
3062 rc = -EIO;
3063 goto err_out_disable_pdev;
3064 }
3065
3066 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3067 pr_err("No PCI resource region found\n");
3068 rc = -ENOMEM;
3069 goto err_out_disable_pdev;
3070 }
3071
3072 rc = pci_request_regions(pdev, DRV_NAME);
3073 if (rc) {
3074 pr_err("Cannot obtain PCI resource region\n");
3075 goto err_out_disable_pdev;
3076 }
3077
3078 pci_set_master(pdev);
3079
3080 /*
3081 * alloc and init net device
3082 */
3083 netdev = alloc_etherdev(sizeof(*jme));
3084 if (!netdev) {
3085 pr_err("Cannot allocate netdev structure\n");
3086 rc = -ENOMEM;
3087 goto err_out_release_regions;
3088 }
3089#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3090 netdev->netdev_ops = &jme_netdev_ops;
3091#else
3092 netdev->open = jme_open;
3093 netdev->stop = jme_close;
3094 netdev->do_ioctl = jme_ioctl;
3095 netdev->hard_start_xmit = jme_start_xmit;
3096 netdev->set_mac_address = jme_set_macaddr;
3097 netdev->set_multicast_list = jme_set_multi;
3098 netdev->change_mtu = jme_change_mtu;
3099 netdev->tx_timeout = jme_tx_timeout;
3100 netdev->vlan_rx_register = jme_vlan_rx_register;
3101#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3102 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3103#endif
3104 NETDEV_GET_STATS(netdev, &jme_get_stats);
3105#endif
3106 netdev->ethtool_ops = &jme_ethtool_ops;
3107 netdev->watchdog_timeo = TX_TIMEOUT;
3108 netdev->features = NETIF_F_IP_CSUM |
3109 NETIF_F_IPV6_CSUM |
3110 NETIF_F_SG |
3111 NETIF_F_TSO |
3112 NETIF_F_TSO6 |
3113 NETIF_F_HW_VLAN_TX |
3114 NETIF_F_HW_VLAN_RX;
3115 if (using_dac)
3116 netdev->features |= NETIF_F_HIGHDMA;
3117
3118 SET_NETDEV_DEV(netdev, &pdev->dev);
3119 pci_set_drvdata(pdev, netdev);
3120
3121 /*
3122 * init adapter info
3123 */
3124 jme = netdev_priv(netdev);
3125 jme->pdev = pdev;
3126 jme->dev = netdev;
3127 jme->jme_rx = netif_rx;
3128 jme->jme_vlan_rx = vlan_hwaccel_rx;
3129 jme->old_mtu = netdev->mtu = 1500;
3130 jme->phylink = 0;
3131 jme->tx_ring_size = 1 << 10;
3132 jme->tx_ring_mask = jme->tx_ring_size - 1;
3133 jme->tx_wake_threshold = 1 << 9;
3134 jme->rx_ring_size = 1 << 9;
3135 jme->rx_ring_mask = jme->rx_ring_size - 1;
3136 jme->msg_enable = JME_DEF_MSG_ENABLE;
3137 jme->regs = ioremap(pci_resource_start(pdev, 0),
3138 pci_resource_len(pdev, 0));
3139 if (!(jme->regs)) {
3140 pr_err("Mapping PCI resource region error\n");
3141 rc = -ENOMEM;
3142 goto err_out_free_netdev;
3143 }
3144
3145 if (no_pseudohp) {
3146 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3147 jwrite32(jme, JME_APMC, apmc);
3148 } else if (force_pseudohp) {
3149 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3150 jwrite32(jme, JME_APMC, apmc);
3151 }
3152
3153 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3154
3155 spin_lock_init(&jme->phy_lock);
3156 spin_lock_init(&jme->macaddr_lock);
3157 spin_lock_init(&jme->rxmcs_lock);
3158
3159 atomic_set(&jme->link_changing, 1);
3160 atomic_set(&jme->rx_cleaning, 1);
3161 atomic_set(&jme->tx_cleaning, 1);
3162 atomic_set(&jme->rx_empty, 1);
3163
3164 tasklet_init(&jme->pcc_task,
3165 jme_pcc_tasklet,
3166 (unsigned long) jme);
3167 tasklet_init(&jme->linkch_task,
3168 jme_link_change_tasklet,
3169 (unsigned long) jme);
3170 tasklet_init(&jme->txclean_task,
3171 jme_tx_clean_tasklet,
3172 (unsigned long) jme);
3173 tasklet_init(&jme->rxclean_task,
3174 jme_rx_clean_tasklet,
3175 (unsigned long) jme);
3176 tasklet_init(&jme->rxempty_task,
3177 jme_rx_empty_tasklet,
3178 (unsigned long) jme);
3179 tasklet_disable_nosync(&jme->linkch_task);
3180 tasklet_disable_nosync(&jme->txclean_task);
3181 tasklet_disable_nosync(&jme->rxclean_task);
3182 tasklet_disable_nosync(&jme->rxempty_task);
3183 jme->dpi.cur = PCC_P1;
3184
3185 jme->reg_ghc = 0;
3186 jme->reg_rxcs = RXCS_DEFAULT;
3187 jme->reg_rxmcs = RXMCS_DEFAULT;
3188 jme->reg_txpfc = 0;
3189 jme->reg_pmcs = PMCS_MFEN;
3190 jme->reg_gpreg1 = GPREG1_DEFAULT;
3191 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3192 set_bit(JME_FLAG_TSO, &jme->flags);
3193
3194 /*
3195 * Get Max Read Req Size from PCI Config Space
3196 */
3197 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3198 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3199 switch (jme->mrrs) {
3200 case MRRS_128B:
3201 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3202 break;
3203 case MRRS_256B:
3204 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3205 break;
3206 default:
3207 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3208 break;
3209 }
3210
3211 /*
3212 * Must check before reset_mac_processor
3213 */
3214 jme_check_hw_ver(jme);
3215 jme->mii_if.dev = netdev;
3216 if (jme->fpgaver) {
3217 jme->mii_if.phy_id = 0;
3218 for (i = 1 ; i < 32 ; ++i) {
3219 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3220 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3221 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3222 jme->mii_if.phy_id = i;
3223 break;
3224 }
3225 }
3226
3227 if (!jme->mii_if.phy_id) {
3228 rc = -EIO;
3229 pr_err("Can not find phy_id\n");
3230 goto err_out_unmap;
3231 }
3232
3233 jme->reg_ghc |= GHC_LINK_POLL;
3234 } else {
3235 jme->mii_if.phy_id = 1;
3236 }
3237 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3238 jme->mii_if.supports_gmii = true;
3239 else
3240 jme->mii_if.supports_gmii = false;
3241 jme->mii_if.phy_id_mask = 0x1F;
3242 jme->mii_if.reg_num_mask = 0x1F;
3243 jme->mii_if.mdio_read = jme_mdio_read;
3244 jme->mii_if.mdio_write = jme_mdio_write;
3245
3246 jme_clear_pm(jme);
3247 jme_set_phyfifo_5level(jme);
3248 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3249 if (!jme->fpgaver)
3250 jme_phy_init(jme);
3251 jme_phy_off(jme);
3252
3253 /*
3254 * Reset MAC processor and reload EEPROM for MAC Address
3255 */
3256 jme_reset_mac_processor(jme);
3257 rc = jme_reload_eeprom(jme);
3258 if (rc) {
3259 pr_err("Reload eeprom for reading MAC Address error\n");
3260 goto err_out_unmap;
3261 }
3262 jme_load_macaddr(netdev);
3263
3264 phy_gp2 = jread32(jme, JME_EXGP2)|FIX_IPV6_CHECKSUM;
3265 jwrite32(jme, JME_EXGP2,phy_gp2);
3266 wmb();
3267 printk("==%x=====\n", jread32(jme, JME_EXGP2));
3268
3269 /*
3270 * Tell stack that we are not ready to work until open()
3271 */
3272 netif_carrier_off(netdev);
3273
3274 rc = register_netdev(netdev);
3275 if (rc) {
3276 pr_err("Cannot register net device\n");
3277 goto err_out_unmap;
3278 }
3279
3280 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3281 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3282 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3283 "JMC250 Gigabit Ethernet" :
3284 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3285 "JMC260 Fast Ethernet" : "Unknown",
3286 (jme->fpgaver != 0) ? " (FPGA)" : "",
3287 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3288 jme->pcirev,
3289 netdev->dev_addr[0],
3290 netdev->dev_addr[1],
3291 netdev->dev_addr[2],
3292 netdev->dev_addr[3],
3293 netdev->dev_addr[4],
3294 netdev->dev_addr[5]);
3295
3296 return 0;
3297
3298err_out_unmap:
3299 iounmap(jme->regs);
3300err_out_free_netdev:
3301 pci_set_drvdata(pdev, NULL);
3302 free_netdev(netdev);
3303err_out_release_regions:
3304 pci_release_regions(pdev);
3305err_out_disable_pdev:
3306 pci_disable_device(pdev);
3307err_out:
3308 return rc;
3309}
3310
3311static void __devexit
3312jme_remove_one(struct pci_dev *pdev)
3313{
3314 struct net_device *netdev = pci_get_drvdata(pdev);
3315 struct jme_adapter *jme = netdev_priv(netdev);
3316
3317 unregister_netdev(netdev);
3318 iounmap(jme->regs);
3319 pci_set_drvdata(pdev, NULL);
3320 free_netdev(netdev);
3321 pci_release_regions(pdev);
3322 pci_disable_device(pdev);
3323
3324}
3325
3326static void
3327jme_shutdown(struct pci_dev *pdev)
3328{
3329 struct net_device *netdev = pci_get_drvdata(pdev);
3330 struct jme_adapter *jme = netdev_priv(netdev);
3331
3332 jme_powersave_phy(jme);
3333#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3334 pci_enable_wake(pdev, PCI_D3hot, true);
3335#else
3336 pci_pme_active(pdev, true);
3337#endif
3338}
3339
3340#ifdef CONFIG_PM
3341static int
3342jme_suspend(struct pci_dev *pdev, pm_message_t state)
3343{
3344 struct net_device *netdev = pci_get_drvdata(pdev);
3345 struct jme_adapter *jme = netdev_priv(netdev);
3346
3347 atomic_dec(&jme->link_changing);
3348
3349 netif_device_detach(netdev);
3350 netif_stop_queue(netdev);
3351 jme_stop_irq(jme);
3352
3353 tasklet_disable(&jme->txclean_task);
3354 tasklet_disable(&jme->rxclean_task);
3355 tasklet_disable(&jme->rxempty_task);
3356
3357 if (netif_carrier_ok(netdev)) {
3358 if (test_bit(JME_FLAG_POLL, &jme->flags))
3359 jme_polling_mode(jme);
3360
3361 jme_stop_pcc_timer(jme);
3362 jme_disable_rx_engine(jme);
3363 jme_disable_tx_engine(jme);
3364 jme_reset_mac_processor(jme);
3365 jme_free_rx_resources(jme);
3366 jme_free_tx_resources(jme);
3367 netif_carrier_off(netdev);
3368 jme->phylink = 0;
3369 }
3370
3371 tasklet_enable(&jme->txclean_task);
3372 tasklet_hi_enable(&jme->rxclean_task);
3373 tasklet_hi_enable(&jme->rxempty_task);
3374
3375 pci_save_state(pdev);
3376 jme_powersave_phy(jme);
3377#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3378 pci_enable_wake(pdev, PCI_D3hot, true);
3379#else
3380 pci_pme_active(pdev, true);
3381#endif
3382 pci_set_power_state(pdev, PCI_D3hot);
3383
3384 return 0;
3385}
3386
3387static int
3388jme_resume(struct pci_dev *pdev)
3389{
3390 struct net_device *netdev = pci_get_drvdata(pdev);
3391 struct jme_adapter *jme = netdev_priv(netdev);
3392
3393 jme_clear_pm(jme);
3394 pci_restore_state(pdev);
3395
3396 jme_phy_on(jme);
3397 if (test_bit(JME_FLAG_SSET, &jme->flags))
3398 jme_set_settings(netdev, &jme->old_ecmd);
3399 else
3400 jme_reset_phy_processor(jme);
3401
3402 jme_start_irq(jme);
3403 netif_device_attach(netdev);
3404
3405 atomic_inc(&jme->link_changing);
3406
3407 jme_reset_link(jme);
3408
3409 return 0;
3410}
3411#endif
3412
3413#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3414static struct pci_device_id jme_pci_tbl[] = {
3415#else
3416static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3417#endif
3418 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3419 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3420 { }
3421};
3422
3423static struct pci_driver jme_driver = {
3424 .name = DRV_NAME,
3425 .id_table = jme_pci_tbl,
3426 .probe = jme_init_one,
3427 .remove = __devexit_p(jme_remove_one),
3428#ifdef CONFIG_PM
3429 .suspend = jme_suspend,
3430 .resume = jme_resume,
3431#endif /* CONFIG_PM */
3432 .shutdown = jme_shutdown,
3433};
3434
3435static int __init
3436jme_init_module(void)
3437{
3438 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3439 return pci_register_driver(&jme_driver);
3440}
3441
3442static void __exit
3443jme_cleanup_module(void)
3444{
3445 pci_unregister_driver(&jme_driver);
3446}
3447
3448module_init(jme_init_module);
3449module_exit(jme_cleanup_module);
3450
3451MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3452MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3453MODULE_LICENSE("GPL");
3454MODULE_VERSION(DRV_VERSION);
3455MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3456
JMicron Ethernet Linux driver