jme: Update CHANGELOG
[jme.git] / jme.h
CommitLineData
4330c2f2
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
4330c2f2 7 *
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8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
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10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
cd0ff491 25#ifndef __JME_H_INCLUDED__
3b70a6fa 26#define __JME_H_INCLUDED__
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27
28#define DRV_NAME "jme"
d3d584f5 29#define DRV_VERSION "1.0.7-jmmod"
cd0ff491 30#define PFX DRV_NAME ": "
d7699f87 31
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32#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
33#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
8d27293f 34
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35/*
36 * Message related definitions
37 */
38#define JME_DEF_MSG_ENABLE \
39 (NETIF_MSG_PROBE | \
40 NETIF_MSG_LINK | \
41 NETIF_MSG_RX_ERR | \
42 NETIF_MSG_TX_ERR | \
43 NETIF_MSG_HW)
44
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45#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
46#define pr_err(fmt, arg...) \
47 printk(KERN_ERR fmt, ##arg)
48#endif
49#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
50#define netdev_err(netdev, fmt, arg...) \
51 pr_err(fmt, ##arg)
52#endif
d7699f87 53
3bf61c55 54#ifdef TX_DEBUG
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55#define tx_dbg(priv, fmt, args...) \
56 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
3bf61c55 57#else
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58#define tx_dbg(priv, fmt, args...) \
59do { \
60 if (0) \
61 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
62} while (0)
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63#endif
64
7ca9ebee 65#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
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66#define jme_msg(msglvl, type, priv, fmt, args...) \
67 if (netif_msg_##type(priv)) \
68 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
3bf61c55 69
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70#define msg_probe(priv, fmt, args...) \
71 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
29bdd921 72
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73#define msg_link(priv, fmt, args...) \
74 jme_msg(KERN_INFO, link, priv, fmt, ## args)
79ce639c 75
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76#define msg_intr(priv, fmt, args...) \
77 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
78
79#define msg_rx_err(priv, fmt, args...) \
80 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
b3821cc5 81
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82#define msg_rx_status(priv, fmt, args...) \
83 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
4330c2f2 84
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85#define msg_tx_err(priv, fmt, args...) \
86 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
4330c2f2 87
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88#define msg_tx_done(priv, fmt, args...) \
89 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
d7699f87 90
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91#define msg_tx_queued(priv, fmt, args...) \
92 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
93
94#define msg_hw(priv, fmt, args...) \
95 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
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96
97#define netif_info(priv, type, dev, fmt, args...) \
98 msg_ ## type(priv, fmt, ## args)
99#define netif_err(priv, type, dev, fmt, args...) \
100 msg_ ## type(priv, fmt, ## args)
7ca9ebee 101#endif
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102
103/*
104 * Extra PCI Configuration space interface
105 */
106#define PCI_DCSR_MRRS 0x59
107#define PCI_DCSR_MRRS_MASK 0x70
108
109enum pci_dcsr_mrrs_vals {
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110 MRRS_128B = 0x00,
111 MRRS_256B = 0x10,
112 MRRS_512B = 0x20,
113 MRRS_1024B = 0x30,
114 MRRS_2048B = 0x40,
115 MRRS_4096B = 0x50,
116};
d7699f87 117
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118#define PCI_SPI 0xB0
119
120enum pci_spi_bits {
121 SPI_EN = 0x10,
122 SPI_MISO = 0x08,
123 SPI_MOSI = 0x04,
124 SPI_SCLK = 0x02,
125 SPI_CS = 0x01,
126};
127
128struct jme_spi_op {
129 void __user *uwbuf;
130 void __user *urbuf;
131 __u8 wn; /* Number of write actions */
132 __u8 rn; /* Number of read actions */
133 __u8 bitn; /* Number of bits per action */
134 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
135 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
136
137 /* Internal use only */
138 u8 *kwbuf;
139 u8 *krbuf;
140 u8 sr;
141 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
142};
79ce639c 143
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144enum jme_spi_op_bits {
145 SPI_MODE_CPHA = 0x01,
146 SPI_MODE_CPOL = 0x02,
147 SPI_MODE_DUP = 0x80,
148};
149
150#define HALF_US 500 /* 500 ns */
151#define JMESPIIOCTL SIOCDEVPRIVATE
152
153/*
154 * Dynamic(adaptive)/Static PCC values
155 */
3bf61c55 156enum dynamic_pcc_values {
192570e0 157 PCC_OFF = 0,
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158 PCC_P1 = 1,
159 PCC_P2 = 2,
160 PCC_P3 = 3,
161
192570e0 162 PCC_OFF_TO = 0,
3bf61c55 163 PCC_P1_TO = 1,
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164 PCC_P2_TO = 64,
165 PCC_P3_TO = 128,
3bf61c55 166
192570e0 167 PCC_OFF_CNT = 0,
3bf61c55 168 PCC_P1_CNT = 1,
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169 PCC_P2_CNT = 16,
170 PCC_P3_CNT = 32,
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171};
172struct dynpcc_info {
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173 unsigned long last_bytes;
174 unsigned long last_pkts;
79ce639c 175 unsigned long intr_cnt;
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176 unsigned char cur;
177 unsigned char attempt;
178 unsigned char cnt;
179};
79ce639c 180#define PCC_INTERVAL_US 100000
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181#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
182#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
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183#define PCC_P2_THRESHOLD 800
184#define PCC_INTR_THRESHOLD 800
47220951 185#define PCC_TX_TO 1000
b3821cc5 186#define PCC_TX_CNT 8
3bf61c55 187
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188/*
189 * TX/RX Descriptors
4330c2f2 190 *
cd0ff491 191 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
d7699f87 192 */
4330c2f2 193#define RING_DESC_ALIGN 16 /* Descriptor alignment */
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194#define TX_DESC_SIZE 16
195#define TX_RING_NR 8
cd0ff491 196#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 197
3bf61c55 198struct txdesc {
d7699f87 199 union {
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200 __u8 all[16];
201 __le32 dw[4];
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202 struct {
203 /* DW0 */
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204 __le16 vlan;
205 __u8 rsv1;
206 __u8 flags;
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207
208 /* DW1 */
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209 __le16 datalen;
210 __le16 mss;
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211
212 /* DW2 */
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213 __le16 pktsize;
214 __le16 rsv2;
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215
216 /* DW3 */
cd0ff491 217 __le32 bufaddr;
d7699f87 218 } desc1;
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219 struct {
220 /* DW0 */
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221 __le16 rsv1;
222 __u8 rsv2;
223 __u8 flags;
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224
225 /* DW1 */
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226 __le16 datalen;
227 __le16 rsv3;
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228
229 /* DW2 */
cd0ff491 230 __le32 bufaddrh;
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231
232 /* DW3 */
cd0ff491 233 __le32 bufaddrl;
3bf61c55 234 } desc2;
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235 struct {
236 /* DW0 */
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237 __u8 ehdrsz;
238 __u8 rsv1;
239 __u8 rsv2;
240 __u8 flags;
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241
242 /* DW1 */
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243 __le16 trycnt;
244 __le16 segcnt;
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245
246 /* DW2 */
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247 __le16 pktsz;
248 __le16 rsv3;
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249
250 /* DW3 */
cd0ff491 251 __le32 bufaddrl;
8c198884 252 } descwb;
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253 };
254};
cd0ff491 255
8c198884 256enum jme_txdesc_flags_bits {
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257 TXFLAG_OWN = 0x80,
258 TXFLAG_INT = 0x40,
3bf61c55 259 TXFLAG_64BIT = 0x20,
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260 TXFLAG_TCPCS = 0x10,
261 TXFLAG_UDPCS = 0x08,
262 TXFLAG_IPCS = 0x04,
263 TXFLAG_LSEN = 0x02,
264 TXFLAG_TAGON = 0x01,
265};
cd0ff491 266
b3821cc5 267#define TXDESC_MSS_SHIFT 2
0ede469c 268enum jme_txwbdesc_flags_bits {
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269 TXWBFLAG_OWN = 0x80,
270 TXWBFLAG_INT = 0x40,
271 TXWBFLAG_TMOUT = 0x20,
272 TXWBFLAG_TRYOUT = 0x10,
273 TXWBFLAG_COL = 0x08,
274
275 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
276 TXWBFLAG_TRYOUT |
277 TXWBFLAG_COL,
278};
d7699f87 279
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280#define RX_DESC_SIZE 16
281#define RX_RING_NR 4
cd0ff491 282#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 283#define RX_BUF_DMA_ALIGN 8
3bf61c55 284#define RX_PREPAD_SIZE 10
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285#define ETH_CRC_LEN 2
286#define RX_VLANHDR_LEN 2
287#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
288 ETH_HLEN + \
289 ETH_CRC_LEN + \
290 RX_VLANHDR_LEN + \
291 RX_BUF_DMA_ALIGN)
d7699f87 292
3bf61c55 293struct rxdesc {
d7699f87 294 union {
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295 __u8 all[16];
296 __le32 dw[4];
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297 struct {
298 /* DW0 */
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299 __le16 rsv2;
300 __u8 rsv1;
301 __u8 flags;
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302
303 /* DW1 */
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304 __le16 datalen;
305 __le16 wbcpl;
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306
307 /* DW2 */
cd0ff491 308 __le32 bufaddrh;
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309
310 /* DW3 */
cd0ff491 311 __le32 bufaddrl;
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312 } desc1;
313 struct {
314 /* DW0 */
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315 __le16 vlan;
316 __le16 flags;
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317
318 /* DW1 */
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319 __le16 framesize;
320 __u8 errstat;
321 __u8 desccnt;
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322
323 /* DW2 */
cd0ff491 324 __le32 rsshash;
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325
326 /* DW3 */
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327 __u8 hashfun;
328 __u8 hashtype;
329 __le16 resrv;
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330 } descwb;
331 };
332};
cd0ff491 333
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334enum jme_rxdesc_flags_bits {
335 RXFLAG_OWN = 0x80,
336 RXFLAG_INT = 0x40,
337 RXFLAG_64BIT = 0x20,
338};
cd0ff491 339
d7699f87 340enum jme_rxwbdesc_flags_bits {
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341 RXWBFLAG_OWN = 0x8000,
342 RXWBFLAG_INT = 0x4000,
343 RXWBFLAG_MF = 0x2000,
344 RXWBFLAG_64BIT = 0x2000,
345 RXWBFLAG_TCPON = 0x1000,
346 RXWBFLAG_UDPON = 0x0800,
347 RXWBFLAG_IPCS = 0x0400,
348 RXWBFLAG_TCPCS = 0x0200,
349 RXWBFLAG_UDPCS = 0x0100,
350 RXWBFLAG_TAGON = 0x0080,
351 RXWBFLAG_IPV4 = 0x0040,
352 RXWBFLAG_IPV6 = 0x0020,
353 RXWBFLAG_PAUSE = 0x0010,
354 RXWBFLAG_MAGIC = 0x0008,
355 RXWBFLAG_WAKEUP = 0x0004,
356 RXWBFLAG_DEST = 0x0003,
357 RXWBFLAG_DEST_UNI = 0x0001,
358 RXWBFLAG_DEST_MUL = 0x0002,
359 RXWBFLAG_DEST_BRO = 0x0003,
d7699f87 360};
cd0ff491 361
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362enum jme_rxwbdesc_desccnt_mask {
363 RXWBDCNT_WBCPL = 0x80,
364 RXWBDCNT_DCNT = 0x7F,
365};
cd0ff491 366
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367enum jme_rxwbdesc_errstat_bits {
368 RXWBERR_LIMIT = 0x80,
369 RXWBERR_MIIER = 0x40,
370 RXWBERR_NIBON = 0x20,
371 RXWBERR_COLON = 0x10,
372 RXWBERR_ABORT = 0x08,
373 RXWBERR_SHORT = 0x04,
374 RXWBERR_OVERUN = 0x02,
375 RXWBERR_CRCERR = 0x01,
376 RXWBERR_ALLERR = 0xFF,
377};
378
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379/*
380 * Buffer information corresponding to ring descriptors.
381 */
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382struct jme_buffer_info {
383 struct sk_buff *skb;
384 dma_addr_t mapping;
385 int len;
3bf61c55 386 int nr_desc;
cdcdc9eb 387 unsigned long start_xmit;
4330c2f2 388};
d7699f87 389
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390/*
391 * The structure holding buffer information and ring descriptors all together.
392 */
d7699f87 393struct jme_ring {
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394 void *alloc; /* pointer to allocated memory */
395 void *desc; /* pointer to ring memory */
396 dma_addr_t dmaalloc; /* phys address of ring alloc */
397 dma_addr_t dma; /* phys address for ring dma */
d7699f87 398
4330c2f2 399 /* Buffer information corresponding to each descriptor */
0ede469c 400 struct jme_buffer_info *bufinf;
d7699f87 401
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402 int next_to_use;
403 atomic_t next_to_clean;
79ce639c 404 atomic_t nr_free;
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405};
406
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407#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
408#define false 0
409#define true 0
410#define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
411#define PCI_VENDOR_ID_JMICRON 0x197B
412#endif
413
414#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
415#define PCI_VDEVICE(vendor, device) \
416 PCI_VENDOR_ID_##vendor, (device), \
417 PCI_ANY_ID, PCI_ANY_ID, 0, 0
418#endif
419
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420#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
421#define NET_STAT(priv) priv->stats
422#define NETDEV_GET_STATS(netdev, fun_ptr) \
423 netdev->get_stats = fun_ptr
424#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
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425/*
426 * CentOS 5.5 have *_hdr helpers back-ported
427 */
428#ifdef RHEL_RELEASE_CODE
429#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
430#define __DEFINE_IPHDR_HELPERS__
431#endif
432#else
433#define __DEFINE_IPHDR_HELPERS__
434#endif
435#else
436#define NET_STAT(priv) (priv->dev->stats)
437#define NETDEV_GET_STATS(netdev, fun_ptr)
438#define DECLARE_NET_DEVICE_STATS
439#endif
440
441#ifdef __DEFINE_IPHDR_HELPERS__
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442static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
443{
444 return skb->nh.iph;
445}
446
447static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
448{
449 return skb->nh.ipv6h;
450}
451
452static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
453{
454 return skb->h.th;
455}
85776f33 456#endif
3bf61c55 457
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458#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
459#define DECLARE_NAPI_STRUCT
460#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
461 dev->poll = pollfn; \
462 dev->weight = q;
463#define JME_NAPI_HOLDER(holder) struct net_device *holder
464#define JME_NAPI_WEIGHT(w) int *w
465#define JME_NAPI_WEIGHT_VAL(w) *w
466#define JME_NAPI_WEIGHT_SET(w, r) *w = r
3b70a6fa 467#define DECLARE_NETDEV struct net_device *netdev = jme->dev;
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468#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
469#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
470#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
471#define JME_RX_SCHEDULE_PREP(priv) \
472 netif_rx_schedule_prep(priv->dev)
473#define JME_RX_SCHEDULE(priv) \
474 __netif_rx_schedule(priv->dev);
0ede469c 475#else
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476#define DECLARE_NAPI_STRUCT struct napi_struct napi;
477#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
478 netif_napi_add(dev, napis, pollfn, q);
479#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
480#define JME_NAPI_WEIGHT(w) int w
481#define JME_NAPI_WEIGHT_VAL(w) w
482#define JME_NAPI_WEIGHT_SET(w, r)
483#define DECLARE_NETDEV
484#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
485#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
486#define JME_NAPI_DISABLE(priv) \
487 if (!napi_disable_pending(&priv->napi)) \
488 napi_disable(&priv->napi);
489#define JME_RX_SCHEDULE_PREP(priv) \
490 napi_schedule_prep(&priv->napi)
491#define JME_RX_SCHEDULE(priv) \
492 __napi_schedule(&priv->napi);
85776f33 493#endif
cdcdc9eb 494
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495/*
496 * Jmac Adapter Private data
497 */
498struct jme_adapter {
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499 struct pci_dev *pdev;
500 struct net_device *dev;
501 void __iomem *regs;
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502 struct mii_if_info mii_if;
503 struct jme_ring rxring[RX_RING_NR];
504 struct jme_ring txring[TX_RING_NR];
d7699f87 505 spinlock_t phy_lock;
fcf45b4c 506 spinlock_t macaddr_lock;
8c198884 507 spinlock_t rxmcs_lock;
fcf45b4c 508 struct tasklet_struct rxempty_task;
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509 struct tasklet_struct rxclean_task;
510 struct tasklet_struct txclean_task;
511 struct tasklet_struct linkch_task;
79ce639c 512 struct tasklet_struct pcc_task;
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513 unsigned long flags;
514 u32 reg_txcs;
515 u32 reg_txpfc;
516 u32 reg_rxcs;
517 u32 reg_rxmcs;
518 u32 reg_ghc;
519 u32 reg_pmcs;
520 u32 phylink;
521 u32 tx_ring_size;
522 u32 tx_ring_mask;
523 u32 tx_wake_threshold;
524 u32 rx_ring_size;
525 u32 rx_ring_mask;
526 u8 mrrs;
527 unsigned int fpgaver;
58c92f28 528 unsigned int chiprev;
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529 u8 rev;
530 u32 msg_enable;
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531 struct ethtool_cmd old_ecmd;
532 unsigned int old_mtu;
cd0ff491 533 struct vlan_group *vlgrp;
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534 struct dynpcc_info dpi;
535 atomic_t intr_sem;
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536 atomic_t link_changing;
537 atomic_t tx_cleaning;
538 atomic_t rx_cleaning;
192570e0 539 atomic_t rx_empty;
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540 int (*jme_rx)(struct sk_buff *skb);
541 int (*jme_vlan_rx)(struct sk_buff *skb,
542 struct vlan_group *grp,
543 unsigned short vlan_tag);
544 DECLARE_NAPI_STRUCT
3bf61c55 545 DECLARE_NET_DEVICE_STATS
d7699f87 546};
cd0ff491 547
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548#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
549static struct net_device_stats *
550jme_get_stats(struct net_device *netdev)
551{
552 struct jme_adapter *jme = netdev_priv(netdev);
553 return &jme->stats;
554}
555#endif
556
79ce639c 557enum jme_flags_bits {
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558 JME_FLAG_MSI = 1,
559 JME_FLAG_SSET = 2,
560 JME_FLAG_TXCSUM = 3,
561 JME_FLAG_TSO = 4,
562 JME_FLAG_POLL = 5,
563 JME_FLAG_SHUTDOWN = 6,
8c198884 564};
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565
566#define TX_TIMEOUT (5 * HZ)
186fc259 567#define JME_REG_LEN 0x500
cd0ff491 568#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
8c198884 569
85776f33 570#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
7ee473a3 571static inline struct jme_adapter*
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572jme_napi_priv(struct net_device *holder)
573{
7ee473a3 574 struct jme_adapter *jme;
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575 jme = netdev_priv(holder);
576 return jme;
577}
578#else
7ee473a3 579static inline struct jme_adapter*
cdcdc9eb
GFT
580jme_napi_priv(struct napi_struct *napi)
581{
7ee473a3 582 struct jme_adapter *jme;
cdcdc9eb
GFT
583 jme = container_of(napi, struct jme_adapter, napi);
584 return jme;
585}
85776f33 586#endif
d7699f87
GFT
587
588/*
589 * MMaped I/O Resters
590 */
591enum jme_iomap_offsets {
4330c2f2
GFT
592 JME_MAC = 0x0000,
593 JME_PHY = 0x0400,
d7699f87 594 JME_MISC = 0x0800,
4330c2f2 595 JME_RSS = 0x0C00,
d7699f87
GFT
596};
597
8c198884
GFT
598enum jme_iomap_lens {
599 JME_MAC_LEN = 0x80,
600 JME_PHY_LEN = 0x58,
601 JME_MISC_LEN = 0x98,
602 JME_RSS_LEN = 0xFF,
603};
604
d7699f87
GFT
605enum jme_iomap_regs {
606 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
3bf61c55
GFT
607 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
608 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
d7699f87
GFT
609 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
610 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
611 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
612 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
613 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
614
615 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
3bf61c55
GFT
616 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
617 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
d7699f87
GFT
618 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
619 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
620 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
4330c2f2
GFT
621 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
622 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
3bf61c55
GFT
623 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
624 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
d7699f87
GFT
625 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
626 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
627
628 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
629 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
630 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
631
632
3bf61c55 633 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
d7699f87
GFT
634 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
635 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
186fc259 636 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
d7699f87
GFT
637
638
cd0ff491
GFT
639 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
640 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
641 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
642 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
643 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
644 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
645 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
646 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
647 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
648 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
649 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
650 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
651 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
652 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
653 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
654 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
d7699f87
GFT
655};
656
657/*
658 * TX Control/Status Bits
659 */
660enum jme_txcs_bits {
661 TXCS_QUEUE7S = 0x00008000,
662 TXCS_QUEUE6S = 0x00004000,
663 TXCS_QUEUE5S = 0x00002000,
664 TXCS_QUEUE4S = 0x00001000,
665 TXCS_QUEUE3S = 0x00000800,
666 TXCS_QUEUE2S = 0x00000400,
667 TXCS_QUEUE1S = 0x00000200,
668 TXCS_QUEUE0S = 0x00000100,
669 TXCS_FIFOTH = 0x000000C0,
670 TXCS_DMASIZE = 0x00000030,
671 TXCS_BURST = 0x00000004,
672 TXCS_ENABLE = 0x00000001,
673};
cd0ff491 674
d7699f87
GFT
675enum jme_txcs_value {
676 TXCS_FIFOTH_16QW = 0x000000C0,
677 TXCS_FIFOTH_12QW = 0x00000080,
678 TXCS_FIFOTH_8QW = 0x00000040,
679 TXCS_FIFOTH_4QW = 0x00000000,
680
681 TXCS_DMASIZE_64B = 0x00000000,
682 TXCS_DMASIZE_128B = 0x00000010,
683 TXCS_DMASIZE_256B = 0x00000020,
684 TXCS_DMASIZE_512B = 0x00000030,
685
686 TXCS_SELECT_QUEUE0 = 0x00000000,
687 TXCS_SELECT_QUEUE1 = 0x00010000,
688 TXCS_SELECT_QUEUE2 = 0x00020000,
689 TXCS_SELECT_QUEUE3 = 0x00030000,
690 TXCS_SELECT_QUEUE4 = 0x00040000,
691 TXCS_SELECT_QUEUE5 = 0x00050000,
692 TXCS_SELECT_QUEUE6 = 0x00060000,
693 TXCS_SELECT_QUEUE7 = 0x00070000,
694
695 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
d7699f87
GFT
696 TXCS_BURST,
697};
cd0ff491 698
29bdd921 699#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
700
701/*
702 * TX MAC Control/Status Bits
703 */
704enum jme_txmcs_bit_masks {
705 TXMCS_IFG2 = 0xC0000000,
706 TXMCS_IFG1 = 0x30000000,
707 TXMCS_TTHOLD = 0x00000300,
708 TXMCS_FBURST = 0x00000080,
709 TXMCS_CARRIEREXT = 0x00000040,
710 TXMCS_DEFER = 0x00000020,
711 TXMCS_BACKOFF = 0x00000010,
712 TXMCS_CARRIERSENSE = 0x00000008,
713 TXMCS_COLLISION = 0x00000004,
714 TXMCS_CRC = 0x00000002,
715 TXMCS_PADDING = 0x00000001,
716};
cd0ff491 717
d7699f87
GFT
718enum jme_txmcs_values {
719 TXMCS_IFG2_6_4 = 0x00000000,
720 TXMCS_IFG2_8_5 = 0x40000000,
721 TXMCS_IFG2_10_6 = 0x80000000,
722 TXMCS_IFG2_12_7 = 0xC0000000,
723
724 TXMCS_IFG1_8_4 = 0x00000000,
725 TXMCS_IFG1_12_6 = 0x10000000,
726 TXMCS_IFG1_16_8 = 0x20000000,
727 TXMCS_IFG1_20_10 = 0x30000000,
728
729 TXMCS_TTHOLD_1_8 = 0x00000000,
730 TXMCS_TTHOLD_1_4 = 0x00000100,
731 TXMCS_TTHOLD_1_2 = 0x00000200,
732 TXMCS_TTHOLD_FULL = 0x00000300,
733
734 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
735 TXMCS_IFG1_16_8 |
736 TXMCS_TTHOLD_FULL |
737 TXMCS_DEFER |
738 TXMCS_CRC |
739 TXMCS_PADDING,
740};
741
8c198884
GFT
742enum jme_txpfc_bits_masks {
743 TXPFC_VLAN_TAG = 0xFFFF0000,
744 TXPFC_VLAN_EN = 0x00008000,
745 TXPFC_PF_EN = 0x00000001,
746};
747
748enum jme_txtrhd_bits_masks {
749 TXTRHD_TXPEN = 0x80000000,
750 TXTRHD_TXP = 0x7FFFFF00,
751 TXTRHD_TXREN = 0x00000080,
752 TXTRHD_TXRL = 0x0000007F,
753};
cd0ff491 754
8c198884
GFT
755enum jme_txtrhd_shifts {
756 TXTRHD_TXP_SHIFT = 8,
757 TXTRHD_TXRL_SHIFT = 0,
758};
759
d7699f87
GFT
760/*
761 * RX Control/Status Bits
762 */
4330c2f2 763enum jme_rxcs_bit_masks {
3bf61c55
GFT
764 /* FIFO full threshold for transmitting Tx Pause Packet */
765 RXCS_FIFOTHTP = 0x30000000,
766 /* FIFO threshold for processing next packet */
767 RXCS_FIFOTHNP = 0x0C000000,
4330c2f2
GFT
768 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
769 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
770 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
771 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
772 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
773 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
774 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
775 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
776 RXCS_QST = 0x00000004, /* Receive queue start */
777 RXCS_SUSPEND = 0x00000002,
d7699f87
GFT
778 RXCS_ENABLE = 0x00000001,
779};
cd0ff491 780
4330c2f2
GFT
781enum jme_rxcs_values {
782 RXCS_FIFOTHTP_16T = 0x00000000,
783 RXCS_FIFOTHTP_32T = 0x10000000,
784 RXCS_FIFOTHTP_64T = 0x20000000,
785 RXCS_FIFOTHTP_128T = 0x30000000,
786
787 RXCS_FIFOTHNP_16QW = 0x00000000,
788 RXCS_FIFOTHNP_32QW = 0x04000000,
789 RXCS_FIFOTHNP_64QW = 0x08000000,
790 RXCS_FIFOTHNP_128QW = 0x0C000000,
791
792 RXCS_DMAREQSZ_16B = 0x00000000,
793 RXCS_DMAREQSZ_32B = 0x01000000,
794 RXCS_DMAREQSZ_64B = 0x02000000,
795 RXCS_DMAREQSZ_128B = 0x03000000,
796
797 RXCS_QUEUESEL_Q0 = 0x00000000,
798 RXCS_QUEUESEL_Q1 = 0x00010000,
799 RXCS_QUEUESEL_Q2 = 0x00020000,
800 RXCS_QUEUESEL_Q3 = 0x00030000,
801
802 RXCS_RETRYGAP_256ns = 0x00000000,
803 RXCS_RETRYGAP_512ns = 0x00001000,
804 RXCS_RETRYGAP_1024ns = 0x00002000,
805 RXCS_RETRYGAP_2048ns = 0x00003000,
806 RXCS_RETRYGAP_4096ns = 0x00004000,
807 RXCS_RETRYGAP_8192ns = 0x00005000,
808 RXCS_RETRYGAP_16384ns = 0x00006000,
809 RXCS_RETRYGAP_32768ns = 0x00007000,
810
811 RXCS_RETRYCNT_0 = 0x00000000,
812 RXCS_RETRYCNT_4 = 0x00000100,
813 RXCS_RETRYCNT_8 = 0x00000200,
814 RXCS_RETRYCNT_12 = 0x00000300,
815 RXCS_RETRYCNT_16 = 0x00000400,
816 RXCS_RETRYCNT_20 = 0x00000500,
817 RXCS_RETRYCNT_24 = 0x00000600,
818 RXCS_RETRYCNT_28 = 0x00000700,
819 RXCS_RETRYCNT_32 = 0x00000800,
820 RXCS_RETRYCNT_36 = 0x00000900,
821 RXCS_RETRYCNT_40 = 0x00000A00,
822 RXCS_RETRYCNT_44 = 0x00000B00,
823 RXCS_RETRYCNT_48 = 0x00000C00,
824 RXCS_RETRYCNT_52 = 0x00000D00,
825 RXCS_RETRYCNT_56 = 0x00000E00,
826 RXCS_RETRYCNT_60 = 0x00000F00,
827
828 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
79ce639c 829 RXCS_FIFOTHNP_128QW |
4330c2f2
GFT
830 RXCS_DMAREQSZ_128B |
831 RXCS_RETRYGAP_256ns |
832 RXCS_RETRYCNT_32,
833};
cd0ff491 834
29bdd921 835#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
836
837/*
838 * RX MAC Control/Status Bits
839 */
840enum jme_rxmcs_bits {
841 RXMCS_ALLFRAME = 0x00000800,
842 RXMCS_BRDFRAME = 0x00000400,
843 RXMCS_MULFRAME = 0x00000200,
844 RXMCS_UNIFRAME = 0x00000100,
845 RXMCS_ALLMULFRAME = 0x00000080,
846 RXMCS_MULFILTERED = 0x00000040,
3bf61c55
GFT
847 RXMCS_RXCOLLDEC = 0x00000020,
848 RXMCS_FLOWCTRL = 0x00000008,
849 RXMCS_VTAGRM = 0x00000004,
850 RXMCS_PREPAD = 0x00000002,
851 RXMCS_CHECKSUM = 0x00000001,
b3821cc5 852
8c198884
GFT
853 RXMCS_DEFAULT = RXMCS_VTAGRM |
854 RXMCS_PREPAD |
855 RXMCS_FLOWCTRL |
856 RXMCS_CHECKSUM,
d7699f87
GFT
857};
858
859/*
b3821cc5
GFT
860 * Wakeup Frame setup interface registers
861 */
862#define WAKEUP_FRAME_NR 8
863#define WAKEUP_FRAME_MASK_DWNR 4
cd0ff491 864
b3821cc5
GFT
865enum jme_wfoi_bit_masks {
866 WFOI_MASK_SEL = 0x00000070,
867 WFOI_CRC_SEL = 0x00000008,
868 WFOI_FRAME_SEL = 0x00000007,
869};
cd0ff491 870
b3821cc5
GFT
871enum jme_wfoi_shifts {
872 WFOI_MASK_SHIFT = 4,
873};
874
875/*
d7699f87
GFT
876 * SMI Related definitions
877 */
cd0ff491 878enum jme_smi_bit_mask {
d7699f87
GFT
879 SMI_DATA_MASK = 0xFFFF0000,
880 SMI_REG_ADDR_MASK = 0x0000F800,
881 SMI_PHY_ADDR_MASK = 0x000007C0,
882 SMI_OP_WRITE = 0x00000020,
3bf61c55
GFT
883 /* Set to 1, after req done it'll be cleared to 0 */
884 SMI_OP_REQ = 0x00000010,
d7699f87
GFT
885 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
886 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
887 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
888 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
889};
cd0ff491
GFT
890
891enum jme_smi_bit_shift {
d7699f87
GFT
892 SMI_DATA_SHIFT = 16,
893 SMI_REG_ADDR_SHIFT = 11,
894 SMI_PHY_ADDR_SHIFT = 6,
895};
cd0ff491
GFT
896
897static inline u32 smi_reg_addr(int x)
d7699f87 898{
cd0ff491 899 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
d7699f87 900}
cd0ff491
GFT
901
902static inline u32 smi_phy_addr(int x)
d7699f87 903{
cd0ff491 904 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
d7699f87 905}
cd0ff491 906
8d27293f 907#define JME_PHY_TIMEOUT 100 /* 100 msec */
186fc259 908#define JME_PHY_REG_NR 32
d7699f87
GFT
909
910/*
911 * Global Host Control
912 */
913enum jme_ghc_bit_mask {
3b70a6fa
GFT
914 GHC_SWRST = 0x40000000,
915 GHC_DPX = 0x00000040,
916 GHC_SPEED = 0x00000030,
917 GHC_LINK_POLL = 0x00000001,
d7699f87 918};
cd0ff491 919
d7699f87 920enum jme_ghc_speed_val {
3b70a6fa
GFT
921 GHC_SPEED_10M = 0x00000010,
922 GHC_SPEED_100M = 0x00000020,
923 GHC_SPEED_1000M = 0x00000030,
924};
925
926enum jme_ghc_to_clk {
927 GHC_TO_CLK_OFF = 0x00000000,
928 GHC_TO_CLK_GPHY = 0x00400000,
929 GHC_TO_CLK_PCIE = 0x00800000,
930 GHC_TO_CLK_INVALID = 0x00C00000,
931};
932
933enum jme_ghc_txmac_clk {
934 GHC_TXMAC_CLK_OFF = 0x00000000,
935 GHC_TXMAC_CLK_GPHY = 0x00100000,
936 GHC_TXMAC_CLK_PCIE = 0x00200000,
937 GHC_TXMAC_CLK_INVALID = 0x00300000,
d7699f87
GFT
938};
939
940/*
29bdd921
GFT
941 * Power management control and status register
942 */
943enum jme_pmcs_bit_masks {
944 PMCS_WF7DET = 0x80000000,
945 PMCS_WF6DET = 0x40000000,
946 PMCS_WF5DET = 0x20000000,
947 PMCS_WF4DET = 0x10000000,
948 PMCS_WF3DET = 0x08000000,
949 PMCS_WF2DET = 0x04000000,
950 PMCS_WF1DET = 0x02000000,
951 PMCS_WF0DET = 0x01000000,
952 PMCS_LFDET = 0x00040000,
953 PMCS_LRDET = 0x00020000,
954 PMCS_MFDET = 0x00010000,
955 PMCS_WF7EN = 0x00008000,
956 PMCS_WF6EN = 0x00004000,
957 PMCS_WF5EN = 0x00002000,
958 PMCS_WF4EN = 0x00001000,
959 PMCS_WF3EN = 0x00000800,
960 PMCS_WF2EN = 0x00000400,
961 PMCS_WF1EN = 0x00000200,
962 PMCS_WF0EN = 0x00000100,
963 PMCS_LFEN = 0x00000004,
964 PMCS_LREN = 0x00000002,
965 PMCS_MFEN = 0x00000001,
966};
967
968/*
3bf61c55 969 * Giga PHY Status Registers
d7699f87
GFT
970 */
971enum jme_phy_link_bit_mask {
972 PHY_LINK_SPEED_MASK = 0x0000C000,
973 PHY_LINK_DUPLEX = 0x00002000,
974 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
975 PHY_LINK_UP = 0x00000400,
976 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
fcf45b4c 977 PHY_LINK_MDI_STAT = 0x00000040,
d7699f87 978};
cd0ff491 979
d7699f87
GFT
980enum jme_phy_link_speed_val {
981 PHY_LINK_SPEED_10M = 0x00000000,
982 PHY_LINK_SPEED_100M = 0x00004000,
983 PHY_LINK_SPEED_1000M = 0x00008000,
984};
cd0ff491 985
fcf45b4c 986#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
d7699f87
GFT
987
988/*
989 * SMB Control and Status
990 */
79ce639c 991enum jme_smbcsr_bit_mask {
d7699f87
GFT
992 SMBCSR_CNACK = 0x00020000,
993 SMBCSR_RELOAD = 0x00010000,
994 SMBCSR_EEPROMD = 0x00000020,
186fc259
GFT
995 SMBCSR_INITDONE = 0x00000010,
996 SMBCSR_BUSY = 0x0000000F,
997};
cd0ff491 998
186fc259
GFT
999enum jme_smbintf_bit_mask {
1000 SMBINTF_HWDATR = 0xFF000000,
1001 SMBINTF_HWDATW = 0x00FF0000,
1002 SMBINTF_HWADDR = 0x0000FF00,
1003 SMBINTF_HWRWN = 0x00000020,
1004 SMBINTF_HWCMD = 0x00000010,
1005 SMBINTF_FASTM = 0x00000008,
1006 SMBINTF_GPIOSCL = 0x00000004,
1007 SMBINTF_GPIOSDA = 0x00000002,
1008 SMBINTF_GPIOEN = 0x00000001,
1009};
cd0ff491 1010
186fc259
GFT
1011enum jme_smbintf_vals {
1012 SMBINTF_HWRWN_READ = 0x00000020,
1013 SMBINTF_HWRWN_WRITE = 0x00000000,
1014};
cd0ff491 1015
186fc259
GFT
1016enum jme_smbintf_shifts {
1017 SMBINTF_HWDATR_SHIFT = 24,
1018 SMBINTF_HWDATW_SHIFT = 16,
1019 SMBINTF_HWADDR_SHIFT = 8,
1020};
cd0ff491 1021
186fc259
GFT
1022#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1023#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1024#define JME_SMB_LEN 256
1025#define JME_EEPROM_MAGIC 0x250
d7699f87 1026
79ce639c
GFT
1027/*
1028 * Timer Control/Status Register
1029 */
1030enum jme_tmcsr_bit_masks {
1031 TMCSR_SWIT = 0x80000000,
1032 TMCSR_EN = 0x01000000,
1033 TMCSR_CNT = 0x00FFFFFF,
1034};
1035
d7699f87 1036/*
cd0ff491 1037 * General Purpose REG-0
4330c2f2
GFT
1038 */
1039enum jme_gpreg0_masks {
3bf61c55
GFT
1040 GPREG0_DISSH = 0xFF000000,
1041 GPREG0_PCIRLMT = 0x00300000,
1042 GPREG0_PCCNOMUTCLR = 0x00040000,
cdcdc9eb 1043 GPREG0_LNKINTPOLL = 0x00001000,
3bf61c55
GFT
1044 GPREG0_PCCTMR = 0x00000300,
1045 GPREG0_PHYADDR = 0x0000001F,
4330c2f2 1046};
cd0ff491 1047
4330c2f2
GFT
1048enum jme_gpreg0_vals {
1049 GPREG0_DISSH_DW7 = 0x80000000,
1050 GPREG0_DISSH_DW6 = 0x40000000,
1051 GPREG0_DISSH_DW5 = 0x20000000,
1052 GPREG0_DISSH_DW4 = 0x10000000,
1053 GPREG0_DISSH_DW3 = 0x08000000,
1054 GPREG0_DISSH_DW2 = 0x04000000,
1055 GPREG0_DISSH_DW1 = 0x02000000,
1056 GPREG0_DISSH_DW0 = 0x01000000,
1057 GPREG0_DISSH_ALL = 0xFF000000,
1058
1059 GPREG0_PCIRLMT_8 = 0x00000000,
1060 GPREG0_PCIRLMT_6 = 0x00100000,
1061 GPREG0_PCIRLMT_5 = 0x00200000,
1062 GPREG0_PCIRLMT_4 = 0x00300000,
1063
1064 GPREG0_PCCTMR_16ns = 0x00000000,
3bf61c55
GFT
1065 GPREG0_PCCTMR_256ns = 0x00000100,
1066 GPREG0_PCCTMR_1us = 0x00000200,
1067 GPREG0_PCCTMR_1ms = 0x00000300,
4330c2f2
GFT
1068
1069 GPREG0_PHYADDR_1 = 0x00000001,
1070
1071 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
3bf61c55
GFT
1072 GPREG0_PCCTMR_1us |
1073 GPREG0_PHYADDR_1,
4330c2f2
GFT
1074};
1075
1076/*
7ee473a3
GFT
1077 * General Purpose REG-1
1078 * Note: All theses bits defined here are for
1079 * Chip mode revision 0x11 only
1080 */
1081enum jme_gpreg1_masks {
1082 GPREG1_INTRDELAYUNIT = 0x00000018,
1083 GPREG1_INTRDELAYENABLE = 0x00000007,
1084};
1085
1086enum jme_gpreg1_vals {
1087 GPREG1_RSSPATCH = 0x00000040,
1088 GPREG1_HALFMODEPATCH = 0x00000020,
1089
1090 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1091 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1092 GPREG1_INTDLYUNIT_1US = 0x00000010,
1093 GPREG1_INTDLYUNIT_16US = 0x00000018,
1094
1095 GPREG1_INTDLYEN_1U = 0x00000001,
1096 GPREG1_INTDLYEN_2U = 0x00000002,
1097 GPREG1_INTDLYEN_3U = 0x00000003,
1098 GPREG1_INTDLYEN_4U = 0x00000004,
1099 GPREG1_INTDLYEN_5U = 0x00000005,
1100 GPREG1_INTDLYEN_6U = 0x00000006,
1101 GPREG1_INTDLYEN_7U = 0x00000007,
1102
1103 GPREG1_DEFAULT = 0x00000000,
1104};
1105
1106/*
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1107 * Interrupt Status Bits
1108 */
cd0ff491 1109enum jme_interrupt_bits {
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1110 INTR_SWINTR = 0x80000000,
1111 INTR_TMINTR = 0x40000000,
1112 INTR_LINKCH = 0x20000000,
1113 INTR_PAUSERCV = 0x10000000,
1114 INTR_MAGICRCV = 0x08000000,
1115 INTR_WAKERCV = 0x04000000,
1116 INTR_PCCRX0TO = 0x02000000,
1117 INTR_PCCRX1TO = 0x01000000,
1118 INTR_PCCRX2TO = 0x00800000,
1119 INTR_PCCRX3TO = 0x00400000,
1120 INTR_PCCTXTO = 0x00200000,
1121 INTR_PCCRX0 = 0x00100000,
1122 INTR_PCCRX1 = 0x00080000,
1123 INTR_PCCRX2 = 0x00040000,
1124 INTR_PCCRX3 = 0x00020000,
1125 INTR_PCCTX = 0x00010000,
1126 INTR_RX3EMP = 0x00008000,
1127 INTR_RX2EMP = 0x00004000,
1128 INTR_RX1EMP = 0x00002000,
1129 INTR_RX0EMP = 0x00001000,
1130 INTR_RX3 = 0x00000800,
1131 INTR_RX2 = 0x00000400,
1132 INTR_RX1 = 0x00000200,
1133 INTR_RX0 = 0x00000100,
1134 INTR_TX7 = 0x00000080,
1135 INTR_TX6 = 0x00000040,
1136 INTR_TX5 = 0x00000020,
1137 INTR_TX4 = 0x00000010,
1138 INTR_TX3 = 0x00000008,
1139 INTR_TX2 = 0x00000004,
1140 INTR_TX1 = 0x00000002,
1141 INTR_TX0 = 0x00000001,
1142};
cd0ff491
GFT
1143
1144static const u32 INTR_ENABLE = INTR_SWINTR |
79ce639c
GFT
1145 INTR_TMINTR |
1146 INTR_LINKCH |
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GFT
1147 INTR_PCCRX0TO |
1148 INTR_PCCRX0 |
1149 INTR_PCCTXTO |
cdcdc9eb
GFT
1150 INTR_PCCTX |
1151 INTR_RX0EMP;
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GFT
1152
1153/*
1154 * PCC Control Registers
1155 */
1156enum jme_pccrx_masks {
1157 PCCRXTO_MASK = 0xFFFF0000,
1158 PCCRX_MASK = 0x0000FF00,
1159};
cd0ff491 1160
3bf61c55
GFT
1161enum jme_pcctx_masks {
1162 PCCTXTO_MASK = 0xFFFF0000,
1163 PCCTX_MASK = 0x0000FF00,
1164 PCCTX_QS_MASK = 0x000000FF,
1165};
cd0ff491 1166
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GFT
1167enum jme_pccrx_shifts {
1168 PCCRXTO_SHIFT = 16,
1169 PCCRX_SHIFT = 8,
1170};
cd0ff491 1171
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GFT
1172enum jme_pcctx_shifts {
1173 PCCTXTO_SHIFT = 16,
1174 PCCTX_SHIFT = 8,
1175};
cd0ff491 1176
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GFT
1177enum jme_pcctx_bits {
1178 PCCTXQ0_EN = 0x00000001,
1179 PCCTXQ1_EN = 0x00000002,
1180 PCCTXQ2_EN = 0x00000004,
1181 PCCTXQ3_EN = 0x00000008,
1182 PCCTXQ4_EN = 0x00000010,
1183 PCCTXQ5_EN = 0x00000020,
1184 PCCTXQ6_EN = 0x00000040,
1185 PCCTXQ7_EN = 0x00000080,
1186};
1187
cdcdc9eb
GFT
1188/*
1189 * Chip Mode Register
1190 */
1191enum jme_chipmode_bit_masks {
1192 CM_FPGAVER_MASK = 0xFFFF0000,
58c92f28 1193 CM_CHIPREV_MASK = 0x0000FF00,
cdcdc9eb
GFT
1194 CM_CHIPMODE_MASK = 0x0000000F,
1195};
cd0ff491 1196
cdcdc9eb
GFT
1197enum jme_chipmode_shifts {
1198 CM_FPGAVER_SHIFT = 16,
58c92f28 1199 CM_CHIPREV_SHIFT = 8,
cdcdc9eb 1200};
d7699f87
GFT
1201
1202/*
cd0ff491
GFT
1203 * Aggressive Power Mode Control
1204 */
1205enum jme_apmc_bits {
1206 JME_APMC_PCIE_SD_EN = 0x40000000,
1207 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1208 JME_APMC_EPIEN = 0x04000000,
1209 JME_APMC_EPIEN_CTRL = 0x03000000,
1210};
1211
1212enum jme_apmc_values {
1213 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1214 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1215};
1216
1217#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1218
1219#ifdef REG_DEBUG
1220static char *MAC_REG_NAME[] = {
1221 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1222 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1223 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1224 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1225 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1226 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1227 "JME_PMCS"};
7ee473a3 1228
cd0ff491
GFT
1229static char *PE_REG_NAME[] = {
1230 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1231 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1232 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1233 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1234 "JME_SMBCSR", "JME_SMBINTF"};
7ee473a3 1235
cd0ff491
GFT
1236static char *MISC_REG_NAME[] = {
1237 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1238 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1239 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1240 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1241 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1242 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1243 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1244 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1245 "JME_PCCSRX0"};
7ee473a3 1246
cd0ff491
GFT
1247static inline void reg_dbg(const struct jme_adapter *jme,
1248 const char *msg, u32 val, u32 reg)
1249{
1250 const char *regname;
58c92f28 1251 switch (reg & 0xF00) {
cd0ff491
GFT
1252 case 0x000:
1253 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1254 break;
1255 case 0x400:
1256 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1257 break;
1258 case 0x800:
58c92f28 1259 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
cd0ff491
GFT
1260 break;
1261 default:
1262 regname = PE_REG_NAME[0];
1263 }
1264 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1265 msg, val, regname);
1266}
1267#else
1268static inline void reg_dbg(const struct jme_adapter *jme,
1269 const char *msg, u32 val, u32 reg) {}
1270#endif
1271
1272/*
d7699f87
GFT
1273 * Read/Write MMaped I/O Registers
1274 */
cd0ff491 1275static inline u32 jread32(struct jme_adapter *jme, u32 reg)
d7699f87 1276{
cd0ff491 1277 return readl(jme->regs + reg);
d7699f87 1278}
cd0ff491
GFT
1279
1280static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87 1281{
cd0ff491
GFT
1282 reg_dbg(jme, "REG WRITE", val, reg);
1283 writel(val, jme->regs + reg);
1284 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87 1285}
cd0ff491
GFT
1286
1287static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87
GFT
1288{
1289 /*
1290 * Read after write should cause flush
1291 */
cd0ff491
GFT
1292 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1293 writel(val, jme->regs + reg);
1294 readl(jme->regs + reg);
1295 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87
GFT
1296}
1297
1298/*
cdcdc9eb
GFT
1299 * PHY Regs
1300 */
1301enum jme_phy_reg17_bit_masks {
1302 PREG17_SPEED = 0xC000,
1303 PREG17_DUPLEX = 0x2000,
1304 PREG17_SPDRSV = 0x0800,
1305 PREG17_LNKUP = 0x0400,
1306 PREG17_MDI = 0x0040,
1307};
cd0ff491 1308
cdcdc9eb
GFT
1309enum jme_phy_reg17_vals {
1310 PREG17_SPEED_10M = 0x0000,
1311 PREG17_SPEED_100M = 0x4000,
1312 PREG17_SPEED_1000M = 0x8000,
1313};
cd0ff491 1314
8d27293f 1315#define BMSR_ANCOMP 0x0020
cdcdc9eb
GFT
1316
1317/*
58c92f28
GFT
1318 * Workaround
1319 */
1320static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1321{
1322 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1323}
1324
1325/*
cd0ff491 1326 * Function prototypes
d7699f87 1327 */
d7699f87 1328static int jme_set_settings(struct net_device *netdev,
cd0ff491 1329 struct ethtool_cmd *ecmd);
d7699f87
GFT
1330static void jme_set_multi(struct net_device *netdev);
1331
cd0ff491 1332#endif
e5169728 1333