jme: Cleanup PM operations after using new PM API
[jme.git] / jme.h
CommitLineData
4330c2f2
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
eee57828 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
4330c2f2 7 *
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8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
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10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
cd0ff491 25#ifndef __JME_H_INCLUDED__
94c5ea02 26#define __JME_H_INCLUDED__
aa9c0eb2 27#include <linux/interrupt.h>
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28
29#define DRV_NAME "jme"
d1ff1f9b 30#define DRV_VERSION "1.0.8"
cd0ff491 31#define PFX DRV_NAME ": "
d7699f87 32
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33#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
34#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
8d27293f 35
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36/*
37 * Message related definitions
38 */
39#define JME_DEF_MSG_ENABLE \
40 (NETIF_MSG_PROBE | \
41 NETIF_MSG_LINK | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR | \
44 NETIF_MSG_HW)
45
3bf61c55 46#ifdef TX_DEBUG
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47#define tx_dbg(priv, fmt, args...) \
48 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
3bf61c55 49#else
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50#define tx_dbg(priv, fmt, args...) \
51do { \
52 if (0) \
53 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
54} while (0)
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55#endif
56
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57/*
58 * Extra PCI Configuration space interface
59 */
60#define PCI_DCSR_MRRS 0x59
61#define PCI_DCSR_MRRS_MASK 0x70
62
63enum pci_dcsr_mrrs_vals {
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64 MRRS_128B = 0x00,
65 MRRS_256B = 0x10,
66 MRRS_512B = 0x20,
67 MRRS_1024B = 0x30,
68 MRRS_2048B = 0x40,
69 MRRS_4096B = 0x50,
70};
d7699f87 71
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72#define PCI_SPI 0xB0
73
74enum pci_spi_bits {
75 SPI_EN = 0x10,
76 SPI_MISO = 0x08,
77 SPI_MOSI = 0x04,
78 SPI_SCLK = 0x02,
79 SPI_CS = 0x01,
80};
81
82struct jme_spi_op {
83 void __user *uwbuf;
84 void __user *urbuf;
85 __u8 wn; /* Number of write actions */
86 __u8 rn; /* Number of read actions */
87 __u8 bitn; /* Number of bits per action */
88 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
89 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
90
91 /* Internal use only */
92 u8 *kwbuf;
93 u8 *krbuf;
94 u8 sr;
95 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
96};
79ce639c 97
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98enum jme_spi_op_bits {
99 SPI_MODE_CPHA = 0x01,
100 SPI_MODE_CPOL = 0x02,
101 SPI_MODE_DUP = 0x80,
102};
103
104#define HALF_US 500 /* 500 ns */
105#define JMESPIIOCTL SIOCDEVPRIVATE
106
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107#define PCI_PRIV_PE1 0xE4
108
109enum pci_priv_pe1_bit_masks {
110 PE1_ASPMSUPRT = 0x00000003, /*
111 * RW:
112 * Aspm_support[1:0]
113 * (R/W Port of 5C[11:10])
114 */
115 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
116 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
117 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
118 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
119 PE1_GPREG0 = 0x0000FF00, /*
120 * SRW:
121 * Cfg_gp_reg0
122 * [7:6] phy_giga BG control
123 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
124 * [4:0] Reserved
125 */
126 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
127 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
128 PE1_REVID = 0xFF000000, /* RO: Rev ID */
129};
130
131enum pci_priv_pe1_values {
132 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
133 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
134 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
135 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
136};
137
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138/*
139 * Dynamic(adaptive)/Static PCC values
140 */
3bf61c55 141enum dynamic_pcc_values {
192570e0 142 PCC_OFF = 0,
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143 PCC_P1 = 1,
144 PCC_P2 = 2,
145 PCC_P3 = 3,
146
192570e0 147 PCC_OFF_TO = 0,
3bf61c55 148 PCC_P1_TO = 1,
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149 PCC_P2_TO = 64,
150 PCC_P3_TO = 128,
3bf61c55 151
192570e0 152 PCC_OFF_CNT = 0,
3bf61c55 153 PCC_P1_CNT = 1,
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154 PCC_P2_CNT = 16,
155 PCC_P3_CNT = 32,
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156};
157struct dynpcc_info {
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158 unsigned long last_bytes;
159 unsigned long last_pkts;
79ce639c 160 unsigned long intr_cnt;
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161 unsigned char cur;
162 unsigned char attempt;
163 unsigned char cnt;
164};
79ce639c 165#define PCC_INTERVAL_US 100000
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166#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
167#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
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168#define PCC_P2_THRESHOLD 800
169#define PCC_INTR_THRESHOLD 800
47220951 170#define PCC_TX_TO 1000
b3821cc5 171#define PCC_TX_CNT 8
3bf61c55 172
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173/*
174 * TX/RX Descriptors
4330c2f2 175 *
cd0ff491 176 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
d7699f87 177 */
4330c2f2 178#define RING_DESC_ALIGN 16 /* Descriptor alignment */
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179#define TX_DESC_SIZE 16
180#define TX_RING_NR 8
cd0ff491 181#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 182
3bf61c55 183struct txdesc {
d7699f87 184 union {
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185 __u8 all[16];
186 __le32 dw[4];
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187 struct {
188 /* DW0 */
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189 __le16 vlan;
190 __u8 rsv1;
191 __u8 flags;
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192
193 /* DW1 */
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194 __le16 datalen;
195 __le16 mss;
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196
197 /* DW2 */
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198 __le16 pktsize;
199 __le16 rsv2;
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200
201 /* DW3 */
cd0ff491 202 __le32 bufaddr;
d7699f87 203 } desc1;
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204 struct {
205 /* DW0 */
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206 __le16 rsv1;
207 __u8 rsv2;
208 __u8 flags;
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209
210 /* DW1 */
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211 __le16 datalen;
212 __le16 rsv3;
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213
214 /* DW2 */
cd0ff491 215 __le32 bufaddrh;
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216
217 /* DW3 */
cd0ff491 218 __le32 bufaddrl;
3bf61c55 219 } desc2;
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220 struct {
221 /* DW0 */
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222 __u8 ehdrsz;
223 __u8 rsv1;
224 __u8 rsv2;
225 __u8 flags;
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226
227 /* DW1 */
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228 __le16 trycnt;
229 __le16 segcnt;
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230
231 /* DW2 */
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232 __le16 pktsz;
233 __le16 rsv3;
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234
235 /* DW3 */
cd0ff491 236 __le32 bufaddrl;
8c198884 237 } descwb;
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238 };
239};
cd0ff491 240
8c198884 241enum jme_txdesc_flags_bits {
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242 TXFLAG_OWN = 0x80,
243 TXFLAG_INT = 0x40,
3bf61c55 244 TXFLAG_64BIT = 0x20,
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245 TXFLAG_TCPCS = 0x10,
246 TXFLAG_UDPCS = 0x08,
247 TXFLAG_IPCS = 0x04,
248 TXFLAG_LSEN = 0x02,
249 TXFLAG_TAGON = 0x01,
250};
cd0ff491 251
b3821cc5 252#define TXDESC_MSS_SHIFT 2
fa97b924 253enum jme_txwbdesc_flags_bits {
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254 TXWBFLAG_OWN = 0x80,
255 TXWBFLAG_INT = 0x40,
256 TXWBFLAG_TMOUT = 0x20,
257 TXWBFLAG_TRYOUT = 0x10,
258 TXWBFLAG_COL = 0x08,
259
260 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
261 TXWBFLAG_TRYOUT |
262 TXWBFLAG_COL,
263};
d7699f87 264
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265#define RX_DESC_SIZE 16
266#define RX_RING_NR 4
cd0ff491 267#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 268#define RX_BUF_DMA_ALIGN 8
3bf61c55 269#define RX_PREPAD_SIZE 10
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270#define ETH_CRC_LEN 2
271#define RX_VLANHDR_LEN 2
272#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
273 ETH_HLEN + \
274 ETH_CRC_LEN + \
275 RX_VLANHDR_LEN + \
276 RX_BUF_DMA_ALIGN)
d7699f87 277
3bf61c55 278struct rxdesc {
d7699f87 279 union {
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280 __u8 all[16];
281 __le32 dw[4];
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282 struct {
283 /* DW0 */
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284 __le16 rsv2;
285 __u8 rsv1;
286 __u8 flags;
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287
288 /* DW1 */
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289 __le16 datalen;
290 __le16 wbcpl;
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291
292 /* DW2 */
cd0ff491 293 __le32 bufaddrh;
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294
295 /* DW3 */
cd0ff491 296 __le32 bufaddrl;
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297 } desc1;
298 struct {
299 /* DW0 */
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300 __le16 vlan;
301 __le16 flags;
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302
303 /* DW1 */
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304 __le16 framesize;
305 __u8 errstat;
306 __u8 desccnt;
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307
308 /* DW2 */
cd0ff491 309 __le32 rsshash;
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310
311 /* DW3 */
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312 __u8 hashfun;
313 __u8 hashtype;
314 __le16 resrv;
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315 } descwb;
316 };
317};
cd0ff491 318
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319enum jme_rxdesc_flags_bits {
320 RXFLAG_OWN = 0x80,
321 RXFLAG_INT = 0x40,
322 RXFLAG_64BIT = 0x20,
323};
cd0ff491 324
d7699f87 325enum jme_rxwbdesc_flags_bits {
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326 RXWBFLAG_OWN = 0x8000,
327 RXWBFLAG_INT = 0x4000,
328 RXWBFLAG_MF = 0x2000,
329 RXWBFLAG_64BIT = 0x2000,
330 RXWBFLAG_TCPON = 0x1000,
331 RXWBFLAG_UDPON = 0x0800,
332 RXWBFLAG_IPCS = 0x0400,
333 RXWBFLAG_TCPCS = 0x0200,
334 RXWBFLAG_UDPCS = 0x0100,
335 RXWBFLAG_TAGON = 0x0080,
336 RXWBFLAG_IPV4 = 0x0040,
337 RXWBFLAG_IPV6 = 0x0020,
338 RXWBFLAG_PAUSE = 0x0010,
339 RXWBFLAG_MAGIC = 0x0008,
340 RXWBFLAG_WAKEUP = 0x0004,
341 RXWBFLAG_DEST = 0x0003,
342 RXWBFLAG_DEST_UNI = 0x0001,
343 RXWBFLAG_DEST_MUL = 0x0002,
344 RXWBFLAG_DEST_BRO = 0x0003,
d7699f87 345};
cd0ff491 346
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347enum jme_rxwbdesc_desccnt_mask {
348 RXWBDCNT_WBCPL = 0x80,
349 RXWBDCNT_DCNT = 0x7F,
350};
cd0ff491 351
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352enum jme_rxwbdesc_errstat_bits {
353 RXWBERR_LIMIT = 0x80,
354 RXWBERR_MIIER = 0x40,
355 RXWBERR_NIBON = 0x20,
356 RXWBERR_COLON = 0x10,
357 RXWBERR_ABORT = 0x08,
358 RXWBERR_SHORT = 0x04,
359 RXWBERR_OVERUN = 0x02,
360 RXWBERR_CRCERR = 0x01,
361 RXWBERR_ALLERR = 0xFF,
362};
363
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364/*
365 * Buffer information corresponding to ring descriptors.
366 */
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367struct jme_buffer_info {
368 struct sk_buff *skb;
369 dma_addr_t mapping;
370 int len;
3bf61c55 371 int nr_desc;
cdcdc9eb 372 unsigned long start_xmit;
4330c2f2 373};
d7699f87 374
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375/*
376 * The structure holding buffer information and ring descriptors all together.
377 */
d7699f87 378struct jme_ring {
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379 void *alloc; /* pointer to allocated memory */
380 void *desc; /* pointer to ring memory */
381 dma_addr_t dmaalloc; /* phys address of ring alloc */
382 dma_addr_t dma; /* phys address for ring dma */
d7699f87 383
4330c2f2 384 /* Buffer information corresponding to each descriptor */
fa97b924 385 struct jme_buffer_info *bufinf;
d7699f87 386
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387 int next_to_use;
388 atomic_t next_to_clean;
79ce639c 389 atomic_t nr_free;
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390};
391
cd0ff491 392#define NET_STAT(priv) (priv->dev->stats)
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393#define NETDEV_GET_STATS(netdev, fun_ptr)
394#define DECLARE_NET_DEVICE_STATS
3bf61c55 395
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396#define DECLARE_NAPI_STRUCT struct napi_struct napi;
397#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
398 netif_napi_add(dev, napis, pollfn, q);
399#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
400#define JME_NAPI_WEIGHT(w) int w
401#define JME_NAPI_WEIGHT_VAL(w) w
402#define JME_NAPI_WEIGHT_SET(w, r)
94c5ea02 403#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
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404#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
405#define JME_NAPI_DISABLE(priv) \
cd0ff491 406 if (!napi_disable_pending(&priv->napi)) \
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407 napi_disable(&priv->napi);
408#define JME_RX_SCHEDULE_PREP(priv) \
94c5ea02 409 napi_schedule_prep(&priv->napi)
cdcdc9eb 410#define JME_RX_SCHEDULE(priv) \
94c5ea02 411 __napi_schedule(&priv->napi);
cdcdc9eb 412
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413/*
414 * Jmac Adapter Private data
415 */
416struct jme_adapter {
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417 struct pci_dev *pdev;
418 struct net_device *dev;
419 void __iomem *regs;
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420 struct mii_if_info mii_if;
421 struct jme_ring rxring[RX_RING_NR];
422 struct jme_ring txring[TX_RING_NR];
d7699f87 423 spinlock_t phy_lock;
fcf45b4c 424 spinlock_t macaddr_lock;
8c198884 425 spinlock_t rxmcs_lock;
fcf45b4c 426 struct tasklet_struct rxempty_task;
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427 struct tasklet_struct rxclean_task;
428 struct tasklet_struct txclean_task;
429 struct tasklet_struct linkch_task;
79ce639c 430 struct tasklet_struct pcc_task;
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431 unsigned long flags;
432 u32 reg_txcs;
433 u32 reg_txpfc;
434 u32 reg_rxcs;
435 u32 reg_rxmcs;
436 u32 reg_ghc;
437 u32 reg_pmcs;
ed830419 438 u32 reg_gpreg1;
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439 u32 phylink;
440 u32 tx_ring_size;
441 u32 tx_ring_mask;
442 u32 tx_wake_threshold;
443 u32 rx_ring_size;
444 u32 rx_ring_mask;
445 u8 mrrs;
446 unsigned int fpgaver;
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447 u8 chiprev;
448 u8 chip_main_rev;
449 u8 chip_sub_rev;
450 u8 pcirev;
cd0ff491 451 u32 msg_enable;
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452 struct ethtool_cmd old_ecmd;
453 unsigned int old_mtu;
cd0ff491 454 struct vlan_group *vlgrp;
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455 struct dynpcc_info dpi;
456 atomic_t intr_sem;
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457 atomic_t link_changing;
458 atomic_t tx_cleaning;
459 atomic_t rx_cleaning;
192570e0 460 atomic_t rx_empty;
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461 int (*jme_rx)(struct sk_buff *skb);
462 int (*jme_vlan_rx)(struct sk_buff *skb,
463 struct vlan_group *grp,
464 unsigned short vlan_tag);
465 DECLARE_NAPI_STRUCT
3bf61c55 466 DECLARE_NET_DEVICE_STATS
d7699f87 467};
cd0ff491 468
79ce639c 469enum jme_flags_bits {
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470 JME_FLAG_MSI = 1,
471 JME_FLAG_SSET = 2,
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472 JME_FLAG_POLL = 5,
473 JME_FLAG_SHUTDOWN = 6,
8c198884 474};
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475
476#define TX_TIMEOUT (5 * HZ)
186fc259 477#define JME_REG_LEN 0x500
cd0ff491 478#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
8c198884 479
cd0ff491 480static inline struct jme_adapter*
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481jme_napi_priv(struct napi_struct *napi)
482{
cd0ff491 483 struct jme_adapter *jme;
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484 jme = container_of(napi, struct jme_adapter, napi);
485 return jme;
486}
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487
488/*
489 * MMaped I/O Resters
490 */
491enum jme_iomap_offsets {
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492 JME_MAC = 0x0000,
493 JME_PHY = 0x0400,
d7699f87 494 JME_MISC = 0x0800,
4330c2f2 495 JME_RSS = 0x0C00,
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496};
497
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498enum jme_iomap_lens {
499 JME_MAC_LEN = 0x80,
500 JME_PHY_LEN = 0x58,
501 JME_MISC_LEN = 0x98,
502 JME_RSS_LEN = 0xFF,
503};
504
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505enum jme_iomap_regs {
506 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
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507 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
508 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
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509 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
510 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
511 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
512 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
513 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
514
515 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
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516 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
517 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
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518 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
519 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
520 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
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521 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
522 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
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523 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
524 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
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525 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
526 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
527
528 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
529 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
530 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
531
532
e4610a83 533 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
3bf61c55 534 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
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535 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
536 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
186fc259 537 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
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538
539
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540 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
541 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
542 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
543 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
544 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
545 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
546 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
547 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
548 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
549 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
550 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
551 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
552 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
553 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
554 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
555 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
d7699f87
GFT
556};
557
558/*
559 * TX Control/Status Bits
560 */
561enum jme_txcs_bits {
562 TXCS_QUEUE7S = 0x00008000,
563 TXCS_QUEUE6S = 0x00004000,
564 TXCS_QUEUE5S = 0x00002000,
565 TXCS_QUEUE4S = 0x00001000,
566 TXCS_QUEUE3S = 0x00000800,
567 TXCS_QUEUE2S = 0x00000400,
568 TXCS_QUEUE1S = 0x00000200,
569 TXCS_QUEUE0S = 0x00000100,
570 TXCS_FIFOTH = 0x000000C0,
571 TXCS_DMASIZE = 0x00000030,
572 TXCS_BURST = 0x00000004,
573 TXCS_ENABLE = 0x00000001,
574};
cd0ff491 575
d7699f87
GFT
576enum jme_txcs_value {
577 TXCS_FIFOTH_16QW = 0x000000C0,
578 TXCS_FIFOTH_12QW = 0x00000080,
579 TXCS_FIFOTH_8QW = 0x00000040,
580 TXCS_FIFOTH_4QW = 0x00000000,
581
582 TXCS_DMASIZE_64B = 0x00000000,
583 TXCS_DMASIZE_128B = 0x00000010,
584 TXCS_DMASIZE_256B = 0x00000020,
585 TXCS_DMASIZE_512B = 0x00000030,
586
587 TXCS_SELECT_QUEUE0 = 0x00000000,
588 TXCS_SELECT_QUEUE1 = 0x00010000,
589 TXCS_SELECT_QUEUE2 = 0x00020000,
590 TXCS_SELECT_QUEUE3 = 0x00030000,
591 TXCS_SELECT_QUEUE4 = 0x00040000,
592 TXCS_SELECT_QUEUE5 = 0x00050000,
593 TXCS_SELECT_QUEUE6 = 0x00060000,
594 TXCS_SELECT_QUEUE7 = 0x00070000,
595
596 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
d7699f87
GFT
597 TXCS_BURST,
598};
cd0ff491 599
29bdd921 600#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
601
602/*
603 * TX MAC Control/Status Bits
604 */
605enum jme_txmcs_bit_masks {
606 TXMCS_IFG2 = 0xC0000000,
607 TXMCS_IFG1 = 0x30000000,
608 TXMCS_TTHOLD = 0x00000300,
609 TXMCS_FBURST = 0x00000080,
610 TXMCS_CARRIEREXT = 0x00000040,
611 TXMCS_DEFER = 0x00000020,
612 TXMCS_BACKOFF = 0x00000010,
613 TXMCS_CARRIERSENSE = 0x00000008,
614 TXMCS_COLLISION = 0x00000004,
615 TXMCS_CRC = 0x00000002,
616 TXMCS_PADDING = 0x00000001,
617};
cd0ff491 618
d7699f87
GFT
619enum jme_txmcs_values {
620 TXMCS_IFG2_6_4 = 0x00000000,
621 TXMCS_IFG2_8_5 = 0x40000000,
622 TXMCS_IFG2_10_6 = 0x80000000,
623 TXMCS_IFG2_12_7 = 0xC0000000,
624
625 TXMCS_IFG1_8_4 = 0x00000000,
626 TXMCS_IFG1_12_6 = 0x10000000,
627 TXMCS_IFG1_16_8 = 0x20000000,
628 TXMCS_IFG1_20_10 = 0x30000000,
629
630 TXMCS_TTHOLD_1_8 = 0x00000000,
631 TXMCS_TTHOLD_1_4 = 0x00000100,
632 TXMCS_TTHOLD_1_2 = 0x00000200,
633 TXMCS_TTHOLD_FULL = 0x00000300,
634
635 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
636 TXMCS_IFG1_16_8 |
637 TXMCS_TTHOLD_FULL |
638 TXMCS_DEFER |
639 TXMCS_CRC |
640 TXMCS_PADDING,
641};
642
8c198884
GFT
643enum jme_txpfc_bits_masks {
644 TXPFC_VLAN_TAG = 0xFFFF0000,
645 TXPFC_VLAN_EN = 0x00008000,
646 TXPFC_PF_EN = 0x00000001,
647};
648
649enum jme_txtrhd_bits_masks {
650 TXTRHD_TXPEN = 0x80000000,
651 TXTRHD_TXP = 0x7FFFFF00,
652 TXTRHD_TXREN = 0x00000080,
653 TXTRHD_TXRL = 0x0000007F,
654};
cd0ff491 655
8c198884
GFT
656enum jme_txtrhd_shifts {
657 TXTRHD_TXP_SHIFT = 8,
658 TXTRHD_TXRL_SHIFT = 0,
659};
660
19bbc546
GFT
661enum jme_txtrhd_values {
662 TXTRHD_FULLDUPLEX = 0x00000000,
663 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
664 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
665 TXTRHD_TXREN |
666 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
667};
668
d7699f87
GFT
669/*
670 * RX Control/Status Bits
671 */
4330c2f2 672enum jme_rxcs_bit_masks {
3bf61c55
GFT
673 /* FIFO full threshold for transmitting Tx Pause Packet */
674 RXCS_FIFOTHTP = 0x30000000,
675 /* FIFO threshold for processing next packet */
676 RXCS_FIFOTHNP = 0x0C000000,
4330c2f2
GFT
677 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
678 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
679 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
680 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
681 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
682 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
683 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
684 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
685 RXCS_QST = 0x00000004, /* Receive queue start */
686 RXCS_SUSPEND = 0x00000002,
d7699f87
GFT
687 RXCS_ENABLE = 0x00000001,
688};
cd0ff491 689
4330c2f2
GFT
690enum jme_rxcs_values {
691 RXCS_FIFOTHTP_16T = 0x00000000,
692 RXCS_FIFOTHTP_32T = 0x10000000,
693 RXCS_FIFOTHTP_64T = 0x20000000,
694 RXCS_FIFOTHTP_128T = 0x30000000,
695
696 RXCS_FIFOTHNP_16QW = 0x00000000,
697 RXCS_FIFOTHNP_32QW = 0x04000000,
698 RXCS_FIFOTHNP_64QW = 0x08000000,
699 RXCS_FIFOTHNP_128QW = 0x0C000000,
700
701 RXCS_DMAREQSZ_16B = 0x00000000,
702 RXCS_DMAREQSZ_32B = 0x01000000,
703 RXCS_DMAREQSZ_64B = 0x02000000,
704 RXCS_DMAREQSZ_128B = 0x03000000,
705
706 RXCS_QUEUESEL_Q0 = 0x00000000,
707 RXCS_QUEUESEL_Q1 = 0x00010000,
708 RXCS_QUEUESEL_Q2 = 0x00020000,
709 RXCS_QUEUESEL_Q3 = 0x00030000,
710
711 RXCS_RETRYGAP_256ns = 0x00000000,
712 RXCS_RETRYGAP_512ns = 0x00001000,
713 RXCS_RETRYGAP_1024ns = 0x00002000,
714 RXCS_RETRYGAP_2048ns = 0x00003000,
715 RXCS_RETRYGAP_4096ns = 0x00004000,
716 RXCS_RETRYGAP_8192ns = 0x00005000,
717 RXCS_RETRYGAP_16384ns = 0x00006000,
718 RXCS_RETRYGAP_32768ns = 0x00007000,
719
720 RXCS_RETRYCNT_0 = 0x00000000,
721 RXCS_RETRYCNT_4 = 0x00000100,
722 RXCS_RETRYCNT_8 = 0x00000200,
723 RXCS_RETRYCNT_12 = 0x00000300,
724 RXCS_RETRYCNT_16 = 0x00000400,
725 RXCS_RETRYCNT_20 = 0x00000500,
726 RXCS_RETRYCNT_24 = 0x00000600,
727 RXCS_RETRYCNT_28 = 0x00000700,
728 RXCS_RETRYCNT_32 = 0x00000800,
729 RXCS_RETRYCNT_36 = 0x00000900,
730 RXCS_RETRYCNT_40 = 0x00000A00,
731 RXCS_RETRYCNT_44 = 0x00000B00,
732 RXCS_RETRYCNT_48 = 0x00000C00,
733 RXCS_RETRYCNT_52 = 0x00000D00,
734 RXCS_RETRYCNT_56 = 0x00000E00,
735 RXCS_RETRYCNT_60 = 0x00000F00,
736
737 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
79ce639c 738 RXCS_FIFOTHNP_128QW |
4330c2f2
GFT
739 RXCS_DMAREQSZ_128B |
740 RXCS_RETRYGAP_256ns |
741 RXCS_RETRYCNT_32,
742};
cd0ff491 743
29bdd921 744#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
745
746/*
747 * RX MAC Control/Status Bits
748 */
749enum jme_rxmcs_bits {
750 RXMCS_ALLFRAME = 0x00000800,
751 RXMCS_BRDFRAME = 0x00000400,
752 RXMCS_MULFRAME = 0x00000200,
753 RXMCS_UNIFRAME = 0x00000100,
754 RXMCS_ALLMULFRAME = 0x00000080,
755 RXMCS_MULFILTERED = 0x00000040,
3bf61c55
GFT
756 RXMCS_RXCOLLDEC = 0x00000020,
757 RXMCS_FLOWCTRL = 0x00000008,
758 RXMCS_VTAGRM = 0x00000004,
759 RXMCS_PREPAD = 0x00000002,
760 RXMCS_CHECKSUM = 0x00000001,
b3821cc5 761
8c198884
GFT
762 RXMCS_DEFAULT = RXMCS_VTAGRM |
763 RXMCS_PREPAD |
764 RXMCS_FLOWCTRL |
765 RXMCS_CHECKSUM,
d7699f87
GFT
766};
767
768/*
b3821cc5
GFT
769 * Wakeup Frame setup interface registers
770 */
771#define WAKEUP_FRAME_NR 8
772#define WAKEUP_FRAME_MASK_DWNR 4
cd0ff491 773
b3821cc5
GFT
774enum jme_wfoi_bit_masks {
775 WFOI_MASK_SEL = 0x00000070,
776 WFOI_CRC_SEL = 0x00000008,
777 WFOI_FRAME_SEL = 0x00000007,
778};
cd0ff491 779
b3821cc5
GFT
780enum jme_wfoi_shifts {
781 WFOI_MASK_SHIFT = 4,
782};
783
784/*
d7699f87
GFT
785 * SMI Related definitions
786 */
cd0ff491 787enum jme_smi_bit_mask {
d7699f87
GFT
788 SMI_DATA_MASK = 0xFFFF0000,
789 SMI_REG_ADDR_MASK = 0x0000F800,
790 SMI_PHY_ADDR_MASK = 0x000007C0,
791 SMI_OP_WRITE = 0x00000020,
3bf61c55
GFT
792 /* Set to 1, after req done it'll be cleared to 0 */
793 SMI_OP_REQ = 0x00000010,
d7699f87
GFT
794 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
795 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
796 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
797 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
798};
cd0ff491
GFT
799
800enum jme_smi_bit_shift {
d7699f87
GFT
801 SMI_DATA_SHIFT = 16,
802 SMI_REG_ADDR_SHIFT = 11,
803 SMI_PHY_ADDR_SHIFT = 6,
804};
cd0ff491
GFT
805
806static inline u32 smi_reg_addr(int x)
d7699f87 807{
cd0ff491 808 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
d7699f87 809}
cd0ff491
GFT
810
811static inline u32 smi_phy_addr(int x)
d7699f87 812{
cd0ff491 813 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
d7699f87 814}
cd0ff491 815
8d27293f 816#define JME_PHY_TIMEOUT 100 /* 100 msec */
186fc259 817#define JME_PHY_REG_NR 32
d7699f87
GFT
818
819/*
820 * Global Host Control
821 */
822enum jme_ghc_bit_mask {
94c5ea02 823 GHC_SWRST = 0x40000000,
ed830419
GFT
824 GHC_TO_CLK_SRC = 0x00C00000,
825 GHC_TXMAC_CLK_SRC = 0x00300000,
94c5ea02
GFT
826 GHC_DPX = 0x00000040,
827 GHC_SPEED = 0x00000030,
828 GHC_LINK_POLL = 0x00000001,
d7699f87 829};
cd0ff491 830
d7699f87 831enum jme_ghc_speed_val {
94c5ea02
GFT
832 GHC_SPEED_10M = 0x00000010,
833 GHC_SPEED_100M = 0x00000020,
834 GHC_SPEED_1000M = 0x00000030,
835};
836
837enum jme_ghc_to_clk {
838 GHC_TO_CLK_OFF = 0x00000000,
839 GHC_TO_CLK_GPHY = 0x00400000,
840 GHC_TO_CLK_PCIE = 0x00800000,
841 GHC_TO_CLK_INVALID = 0x00C00000,
842};
843
844enum jme_ghc_txmac_clk {
845 GHC_TXMAC_CLK_OFF = 0x00000000,
846 GHC_TXMAC_CLK_GPHY = 0x00100000,
847 GHC_TXMAC_CLK_PCIE = 0x00200000,
848 GHC_TXMAC_CLK_INVALID = 0x00300000,
d7699f87
GFT
849};
850
851/*
29bdd921
GFT
852 * Power management control and status register
853 */
854enum jme_pmcs_bit_masks {
18783c49 855 PMCS_STMASK = 0xFFFF0000,
29bdd921
GFT
856 PMCS_WF7DET = 0x80000000,
857 PMCS_WF6DET = 0x40000000,
858 PMCS_WF5DET = 0x20000000,
859 PMCS_WF4DET = 0x10000000,
860 PMCS_WF3DET = 0x08000000,
861 PMCS_WF2DET = 0x04000000,
862 PMCS_WF1DET = 0x02000000,
863 PMCS_WF0DET = 0x01000000,
864 PMCS_LFDET = 0x00040000,
865 PMCS_LRDET = 0x00020000,
866 PMCS_MFDET = 0x00010000,
18783c49 867 PMCS_ENMASK = 0x0000FFFF,
29bdd921
GFT
868 PMCS_WF7EN = 0x00008000,
869 PMCS_WF6EN = 0x00004000,
870 PMCS_WF5EN = 0x00002000,
871 PMCS_WF4EN = 0x00001000,
872 PMCS_WF3EN = 0x00000800,
873 PMCS_WF2EN = 0x00000400,
874 PMCS_WF1EN = 0x00000200,
875 PMCS_WF0EN = 0x00000100,
876 PMCS_LFEN = 0x00000004,
877 PMCS_LREN = 0x00000002,
878 PMCS_MFEN = 0x00000001,
879};
880
881/*
e4610a83
GFT
882 * New PHY Power Control Register
883 */
884enum jme_phy_pwr_bit_masks {
885 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
886 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
887 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
888 PHY_PWR_CLKSEL = 0x08000000, /*
889 * XTL_OUT Clock select
890 * (an internal free-running clock)
891 * 0: xtl_out = phy_giga.A_XTL25_O
892 * 1: xtl_out = phy_giga.PD_OSC
893 */
894};
895
896/*
3bf61c55 897 * Giga PHY Status Registers
d7699f87
GFT
898 */
899enum jme_phy_link_bit_mask {
900 PHY_LINK_SPEED_MASK = 0x0000C000,
901 PHY_LINK_DUPLEX = 0x00002000,
902 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
903 PHY_LINK_UP = 0x00000400,
904 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
fcf45b4c 905 PHY_LINK_MDI_STAT = 0x00000040,
d7699f87 906};
cd0ff491 907
d7699f87
GFT
908enum jme_phy_link_speed_val {
909 PHY_LINK_SPEED_10M = 0x00000000,
910 PHY_LINK_SPEED_100M = 0x00004000,
911 PHY_LINK_SPEED_1000M = 0x00008000,
912};
cd0ff491 913
fcf45b4c 914#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
d7699f87
GFT
915
916/*
917 * SMB Control and Status
918 */
79ce639c 919enum jme_smbcsr_bit_mask {
d7699f87
GFT
920 SMBCSR_CNACK = 0x00020000,
921 SMBCSR_RELOAD = 0x00010000,
922 SMBCSR_EEPROMD = 0x00000020,
186fc259
GFT
923 SMBCSR_INITDONE = 0x00000010,
924 SMBCSR_BUSY = 0x0000000F,
925};
cd0ff491 926
186fc259
GFT
927enum jme_smbintf_bit_mask {
928 SMBINTF_HWDATR = 0xFF000000,
929 SMBINTF_HWDATW = 0x00FF0000,
930 SMBINTF_HWADDR = 0x0000FF00,
931 SMBINTF_HWRWN = 0x00000020,
932 SMBINTF_HWCMD = 0x00000010,
933 SMBINTF_FASTM = 0x00000008,
934 SMBINTF_GPIOSCL = 0x00000004,
935 SMBINTF_GPIOSDA = 0x00000002,
936 SMBINTF_GPIOEN = 0x00000001,
937};
cd0ff491 938
186fc259
GFT
939enum jme_smbintf_vals {
940 SMBINTF_HWRWN_READ = 0x00000020,
941 SMBINTF_HWRWN_WRITE = 0x00000000,
942};
cd0ff491 943
186fc259
GFT
944enum jme_smbintf_shifts {
945 SMBINTF_HWDATR_SHIFT = 24,
946 SMBINTF_HWDATW_SHIFT = 16,
947 SMBINTF_HWADDR_SHIFT = 8,
948};
cd0ff491 949
186fc259
GFT
950#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
951#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
952#define JME_SMB_LEN 256
953#define JME_EEPROM_MAGIC 0x250
d7699f87 954
79ce639c
GFT
955/*
956 * Timer Control/Status Register
957 */
958enum jme_tmcsr_bit_masks {
959 TMCSR_SWIT = 0x80000000,
960 TMCSR_EN = 0x01000000,
961 TMCSR_CNT = 0x00FFFFFF,
962};
963
d7699f87 964/*
cd0ff491 965 * General Purpose REG-0
4330c2f2
GFT
966 */
967enum jme_gpreg0_masks {
3bf61c55
GFT
968 GPREG0_DISSH = 0xFF000000,
969 GPREG0_PCIRLMT = 0x00300000,
970 GPREG0_PCCNOMUTCLR = 0x00040000,
cdcdc9eb 971 GPREG0_LNKINTPOLL = 0x00001000,
3bf61c55
GFT
972 GPREG0_PCCTMR = 0x00000300,
973 GPREG0_PHYADDR = 0x0000001F,
4330c2f2 974};
cd0ff491 975
4330c2f2
GFT
976enum jme_gpreg0_vals {
977 GPREG0_DISSH_DW7 = 0x80000000,
978 GPREG0_DISSH_DW6 = 0x40000000,
979 GPREG0_DISSH_DW5 = 0x20000000,
980 GPREG0_DISSH_DW4 = 0x10000000,
981 GPREG0_DISSH_DW3 = 0x08000000,
982 GPREG0_DISSH_DW2 = 0x04000000,
983 GPREG0_DISSH_DW1 = 0x02000000,
984 GPREG0_DISSH_DW0 = 0x01000000,
985 GPREG0_DISSH_ALL = 0xFF000000,
986
987 GPREG0_PCIRLMT_8 = 0x00000000,
988 GPREG0_PCIRLMT_6 = 0x00100000,
989 GPREG0_PCIRLMT_5 = 0x00200000,
990 GPREG0_PCIRLMT_4 = 0x00300000,
991
992 GPREG0_PCCTMR_16ns = 0x00000000,
3bf61c55
GFT
993 GPREG0_PCCTMR_256ns = 0x00000100,
994 GPREG0_PCCTMR_1us = 0x00000200,
995 GPREG0_PCCTMR_1ms = 0x00000300,
4330c2f2
GFT
996
997 GPREG0_PHYADDR_1 = 0x00000001,
998
999 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
3bf61c55
GFT
1000 GPREG0_PCCTMR_1us |
1001 GPREG0_PHYADDR_1,
4330c2f2
GFT
1002};
1003
1004/*
9b9d55de 1005 * General Purpose REG-1
9b9d55de 1006 */
ed830419
GFT
1007enum jme_gpreg1_bit_masks {
1008 GPREG1_RXCLKOFF = 0x04000000,
1009 GPREG1_PCREQN = 0x00020000,
1010 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1011 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
9b9d55de
GFT
1012 GPREG1_INTRDELAYUNIT = 0x00000018,
1013 GPREG1_INTRDELAYENABLE = 0x00000007,
1014};
1015
1016enum jme_gpreg1_vals {
9b9d55de
GFT
1017 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1018 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1019 GPREG1_INTDLYUNIT_1US = 0x00000010,
1020 GPREG1_INTDLYUNIT_16US = 0x00000018,
1021
1022 GPREG1_INTDLYEN_1U = 0x00000001,
1023 GPREG1_INTDLYEN_2U = 0x00000002,
1024 GPREG1_INTDLYEN_3U = 0x00000003,
1025 GPREG1_INTDLYEN_4U = 0x00000004,
1026 GPREG1_INTDLYEN_5U = 0x00000005,
1027 GPREG1_INTDLYEN_6U = 0x00000006,
1028 GPREG1_INTDLYEN_7U = 0x00000007,
1029
ed830419 1030 GPREG1_DEFAULT = GPREG1_PCREQN,
9b9d55de
GFT
1031};
1032
1033/*
d7699f87
GFT
1034 * Interrupt Status Bits
1035 */
cd0ff491 1036enum jme_interrupt_bits {
d7699f87
GFT
1037 INTR_SWINTR = 0x80000000,
1038 INTR_TMINTR = 0x40000000,
1039 INTR_LINKCH = 0x20000000,
1040 INTR_PAUSERCV = 0x10000000,
1041 INTR_MAGICRCV = 0x08000000,
1042 INTR_WAKERCV = 0x04000000,
1043 INTR_PCCRX0TO = 0x02000000,
1044 INTR_PCCRX1TO = 0x01000000,
1045 INTR_PCCRX2TO = 0x00800000,
1046 INTR_PCCRX3TO = 0x00400000,
1047 INTR_PCCTXTO = 0x00200000,
1048 INTR_PCCRX0 = 0x00100000,
1049 INTR_PCCRX1 = 0x00080000,
1050 INTR_PCCRX2 = 0x00040000,
1051 INTR_PCCRX3 = 0x00020000,
1052 INTR_PCCTX = 0x00010000,
1053 INTR_RX3EMP = 0x00008000,
1054 INTR_RX2EMP = 0x00004000,
1055 INTR_RX1EMP = 0x00002000,
1056 INTR_RX0EMP = 0x00001000,
1057 INTR_RX3 = 0x00000800,
1058 INTR_RX2 = 0x00000400,
1059 INTR_RX1 = 0x00000200,
1060 INTR_RX0 = 0x00000100,
1061 INTR_TX7 = 0x00000080,
1062 INTR_TX6 = 0x00000040,
1063 INTR_TX5 = 0x00000020,
1064 INTR_TX4 = 0x00000010,
1065 INTR_TX3 = 0x00000008,
1066 INTR_TX2 = 0x00000004,
1067 INTR_TX1 = 0x00000002,
1068 INTR_TX0 = 0x00000001,
1069};
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1070
1071static const u32 INTR_ENABLE = INTR_SWINTR |
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1072 INTR_TMINTR |
1073 INTR_LINKCH |
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1074 INTR_PCCRX0TO |
1075 INTR_PCCRX0 |
1076 INTR_PCCTXTO |
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1077 INTR_PCCTX |
1078 INTR_RX0EMP;
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1079
1080/*
1081 * PCC Control Registers
1082 */
1083enum jme_pccrx_masks {
1084 PCCRXTO_MASK = 0xFFFF0000,
1085 PCCRX_MASK = 0x0000FF00,
1086};
cd0ff491 1087
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1088enum jme_pcctx_masks {
1089 PCCTXTO_MASK = 0xFFFF0000,
1090 PCCTX_MASK = 0x0000FF00,
1091 PCCTX_QS_MASK = 0x000000FF,
1092};
cd0ff491 1093
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1094enum jme_pccrx_shifts {
1095 PCCRXTO_SHIFT = 16,
1096 PCCRX_SHIFT = 8,
1097};
cd0ff491 1098
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1099enum jme_pcctx_shifts {
1100 PCCTXTO_SHIFT = 16,
1101 PCCTX_SHIFT = 8,
1102};
cd0ff491 1103
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1104enum jme_pcctx_bits {
1105 PCCTXQ0_EN = 0x00000001,
1106 PCCTXQ1_EN = 0x00000002,
1107 PCCTXQ2_EN = 0x00000004,
1108 PCCTXQ3_EN = 0x00000008,
1109 PCCTXQ4_EN = 0x00000010,
1110 PCCTXQ5_EN = 0x00000020,
1111 PCCTXQ6_EN = 0x00000040,
1112 PCCTXQ7_EN = 0x00000080,
1113};
1114
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1115/*
1116 * Chip Mode Register
1117 */
1118enum jme_chipmode_bit_masks {
1119 CM_FPGAVER_MASK = 0xFFFF0000,
e882564f 1120 CM_CHIPREV_MASK = 0x0000FF00,
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1121 CM_CHIPMODE_MASK = 0x0000000F,
1122};
cd0ff491 1123
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1124enum jme_chipmode_shifts {
1125 CM_FPGAVER_SHIFT = 16,
e882564f 1126 CM_CHIPREV_SHIFT = 8,
cdcdc9eb 1127};
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1128
1129/*
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1130 * Aggressive Power Mode Control
1131 */
1132enum jme_apmc_bits {
1133 JME_APMC_PCIE_SD_EN = 0x40000000,
1134 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1135 JME_APMC_EPIEN = 0x04000000,
1136 JME_APMC_EPIEN_CTRL = 0x03000000,
1137};
1138
1139enum jme_apmc_values {
1140 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1141 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1142};
1143
1144#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1145
1146#ifdef REG_DEBUG
1147static char *MAC_REG_NAME[] = {
1148 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1149 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1150 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1151 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1152 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1153 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1154 "JME_PMCS"};
9b9d55de 1155
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1156static char *PE_REG_NAME[] = {
1157 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1158 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1159 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1160 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1161 "JME_SMBCSR", "JME_SMBINTF"};
9b9d55de 1162
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GFT
1163static char *MISC_REG_NAME[] = {
1164 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1165 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1166 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1167 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1168 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1169 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1170 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1171 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1172 "JME_PCCSRX0"};
9b9d55de 1173
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1174static inline void reg_dbg(const struct jme_adapter *jme,
1175 const char *msg, u32 val, u32 reg)
1176{
1177 const char *regname;
e882564f 1178 switch (reg & 0xF00) {
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GFT
1179 case 0x000:
1180 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1181 break;
1182 case 0x400:
1183 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1184 break;
1185 case 0x800:
e882564f 1186 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
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GFT
1187 break;
1188 default:
1189 regname = PE_REG_NAME[0];
1190 }
1191 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1192 msg, val, regname);
1193}
1194#else
1195static inline void reg_dbg(const struct jme_adapter *jme,
1196 const char *msg, u32 val, u32 reg) {}
1197#endif
1198
1199/*
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1200 * Read/Write MMaped I/O Registers
1201 */
cd0ff491 1202static inline u32 jread32(struct jme_adapter *jme, u32 reg)
d7699f87 1203{
cd0ff491 1204 return readl(jme->regs + reg);
d7699f87 1205}
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1206
1207static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87 1208{
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1209 reg_dbg(jme, "REG WRITE", val, reg);
1210 writel(val, jme->regs + reg);
1211 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87 1212}
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GFT
1213
1214static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
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GFT
1215{
1216 /*
1217 * Read after write should cause flush
1218 */
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GFT
1219 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1220 writel(val, jme->regs + reg);
1221 readl(jme->regs + reg);
1222 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
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GFT
1223}
1224
1225/*
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1226 * PHY Regs
1227 */
1228enum jme_phy_reg17_bit_masks {
1229 PREG17_SPEED = 0xC000,
1230 PREG17_DUPLEX = 0x2000,
1231 PREG17_SPDRSV = 0x0800,
1232 PREG17_LNKUP = 0x0400,
1233 PREG17_MDI = 0x0040,
1234};
cd0ff491 1235
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GFT
1236enum jme_phy_reg17_vals {
1237 PREG17_SPEED_10M = 0x0000,
1238 PREG17_SPEED_100M = 0x4000,
1239 PREG17_SPEED_1000M = 0x8000,
1240};
cd0ff491 1241
8d27293f 1242#define BMSR_ANCOMP 0x0020
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1243
1244/*
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GFT
1245 * Workaround
1246 */
4400ae98 1247static inline int is_buggy250(unsigned short device, u8 chiprev)
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GFT
1248{
1249 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1250}
1251
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GFT
1252static inline int new_phy_power_ctrl(u8 chip_main_rev)
1253{
1254 return chip_main_rev >= 5;
1255}
1256
e882564f 1257/*
cd0ff491 1258 * Function prototypes
d7699f87 1259 */
d7699f87 1260static int jme_set_settings(struct net_device *netdev,
cd0ff491 1261 struct ethtool_cmd *ecmd);
bb4c5c8c 1262static void jme_set_unicastaddr(struct net_device *netdev);
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GFT
1263static void jme_set_multi(struct net_device *netdev);
1264
cd0ff491 1265#endif