jme: Safer MAC processor reset sequence
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT
40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT
48#include "jme.h"
49
cd0ff491
GFT
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
3bf61c55
GFT
62static int
63jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
64{
65 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 67
186fc259 68read_again:
cd0ff491 69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
70 smi_phy_addr(phy) |
71 smi_reg_addr(reg));
d7699f87
GFT
72
73 wmb();
cd0ff491 74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 75 udelay(20);
b3821cc5
GFT
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
3bf61c55 78 break;
cd0ff491 79 }
d7699f87 80
cd0ff491 81 if (i == 0) {
937ef75a 82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 83 return 0;
cd0ff491 84 }
d7699f87 85
cd0ff491 86 if (again--)
186fc259
GFT
87 goto read_again;
88
cd0ff491 89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
90}
91
3bf61c55
GFT
92static void
93jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
d7699f87
GFT
95{
96 struct jme_adapter *jme = netdev_priv(netdev);
97 int i;
98
3bf61c55
GFT
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT
102
103 wmb();
cdcdc9eb
GFT
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 udelay(20);
8d27293f 106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
107 break;
108 }
d7699f87 109
3bf61c55 110 if (i == 0)
937ef75a 111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT
112}
113
cd0ff491 114static inline void
3bf61c55 115jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 116{
cd0ff491 117 u32 val;
3bf61c55
GFT
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
8c198884
GFT
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 123
cd0ff491 124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
125 jme_mdio_write(jme->dev,
126 jme->mii_if.phy_id,
127 MII_CTRL1000,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 129
fcf45b4c
GFT
130 val = jme_mdio_read(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR);
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT
137}
138
b3821cc5
GFT
139static void
140jme_setup_wakeup_frame(struct jme_adapter *jme,
a4181cd4 141 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
142{
143 int i;
144
145 /*
146 * Setup CRC pattern
147 */
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 wmb();
150 jwrite32(jme, JME_WFODP, crc);
151 wmb();
152
153 /*
154 * Setup Mask
155 */
cd0ff491 156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
160 wmb();
161 jwrite32(jme, JME_WFODP, mask[i]);
162 wmb();
163 }
164}
3bf61c55 165
cd0ff491 166static inline void
dc4185bd
GFT
167jme_mac_rxclk_off(struct jme_adapter *jme)
168{
169 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
170 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
171}
172
173static inline void
174jme_mac_rxclk_on(struct jme_adapter *jme)
175{
176 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
177 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
178}
179
180static inline void
181jme_mac_txclk_off(struct jme_adapter *jme)
182{
183 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
184 jwrite32f(jme, JME_GHC, jme->reg_ghc);
185}
186
187static inline void
188jme_mac_txclk_on(struct jme_adapter *jme)
189{
190 u32 speed = jme->reg_ghc & GHC_SPEED;
191 if (speed == GHC_SPEED_1000M)
192 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
193 else
194 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
195 jwrite32f(jme, JME_GHC, jme->reg_ghc);
196}
197
198static inline void
199jme_reset_ghc_speed(struct jme_adapter *jme)
200{
201 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
202 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203}
204
205static inline void
206jme_reset_250A2_workaround(struct jme_adapter *jme)
207{
208 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
209 GPREG1_RSSPATCH);
210 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
211}
212
213static inline void
214jme_assert_ghc_reset(struct jme_adapter *jme)
215{
216 jme->reg_ghc |= GHC_SWRST;
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_clear_ghc_reset(struct jme_adapter *jme)
222{
223 jme->reg_ghc &= ~GHC_SWRST;
224 jwrite32f(jme, JME_GHC, jme->reg_ghc);
225}
226
227static inline void
3bf61c55
GFT
228jme_reset_mac_processor(struct jme_adapter *jme)
229{
a4181cd4 230 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT
231 u32 crc = 0xCDCDCDCD;
232 u32 gpreg0;
b3821cc5
GFT
233 int i;
234
dc4185bd
GFT
235 jme_reset_ghc_speed(jme);
236 jme_reset_250A2_workaround(jme);
237
238 jme_mac_rxclk_on(jme);
239 jme_mac_txclk_on(jme);
240 udelay(1);
241 jme_assert_ghc_reset(jme);
242 udelay(1);
243 jme_mac_rxclk_off(jme);
244 jme_mac_txclk_off(jme);
245 udelay(1);
246 jme_clear_ghc_reset(jme);
247 udelay(1);
248 jme_mac_rxclk_on(jme);
249 jme_mac_txclk_on(jme);
250 udelay(1);
251 jme_mac_rxclk_off(jme);
252 jme_mac_txclk_off(jme);
cd0ff491
GFT
253
254 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
255 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
256 jwrite32(jme, JME_RXQDC, 0x00000000);
257 jwrite32(jme, JME_RXNDA, 0x00000000);
258 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
259 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
260 jwrite32(jme, JME_TXQDC, 0x00000000);
261 jwrite32(jme, JME_TXNDA, 0x00000000);
262
4330c2f2
GFT
263 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
264 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 265 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 266 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 267 if (jme->fpgaver)
cdcdc9eb
GFT
268 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
269 else
270 gpreg0 = GPREG0_DEFAULT;
271 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT
272}
273
274static inline void
3bf61c55 275jme_clear_pm(struct jme_adapter *jme)
d7699f87 276{
29bdd921 277 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 278 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 279 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT
280}
281
3bf61c55
GFT
282static int
283jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 284{
cd0ff491 285 u32 val;
d7699f87
GFT
286 int i;
287
288 val = jread32(jme, JME_SMBCSR);
289
cd0ff491 290 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
291 val |= SMBCSR_CNACK;
292 jwrite32(jme, JME_SMBCSR, val);
293 val |= SMBCSR_RELOAD;
294 jwrite32(jme, JME_SMBCSR, val);
295 mdelay(12);
296
cd0ff491 297 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
298 mdelay(1);
299 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
300 break;
301 }
302
cd0ff491 303 if (i == 0) {
937ef75a 304 pr_err("eeprom reload timeout\n");
d7699f87
GFT
305 return -EIO;
306 }
307 }
3bf61c55 308
d7699f87
GFT
309 return 0;
310}
311
3bf61c55
GFT
312static void
313jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
314{
315 struct jme_adapter *jme = netdev_priv(netdev);
316 unsigned char macaddr[6];
cd0ff491 317 u32 val;
d7699f87 318
cd0ff491 319 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 320 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
321 macaddr[0] = (val >> 0) & 0xFF;
322 macaddr[1] = (val >> 8) & 0xFF;
323 macaddr[2] = (val >> 16) & 0xFF;
324 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 325 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
326 macaddr[4] = (val >> 0) & 0xFF;
327 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
328 memcpy(netdev->dev_addr, macaddr, 6);
329 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
330}
331
cd0ff491 332static inline void
3bf61c55
GFT
333jme_set_rx_pcc(struct jme_adapter *jme, int p)
334{
cd0ff491 335 switch (p) {
192570e0
GFT
336 case PCC_OFF:
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340 break;
3bf61c55
GFT
341 case PCC_P1:
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345 break;
346 case PCC_P2:
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350 break;
351 case PCC_P3:
352 jwrite32(jme, JME_PCCRX0,
353 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
354 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
355 break;
356 default:
357 break;
358 }
192570e0 359 wmb();
3bf61c55 360
cd0ff491 361 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 362 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT
363}
364
fcf45b4c 365static void
3bf61c55 366jme_start_irq(struct jme_adapter *jme)
d7699f87 367{
3bf61c55
GFT
368 register struct dynpcc_info *dpi = &(jme->dpi);
369
370 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
371 dpi->cur = PCC_P1;
372 dpi->attempt = PCC_P1;
373 dpi->cnt = 0;
374
375 jwrite32(jme, JME_PCCTX,
8c198884
GFT
376 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
377 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
378 PCCTXQ0_EN
379 );
380
d7699f87
GFT
381 /*
382 * Enable Interrupts
383 */
384 jwrite32(jme, JME_IENS, INTR_ENABLE);
385}
386
cd0ff491 387static inline void
3bf61c55 388jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
389{
390 /*
391 * Disable Interrupts
392 */
cd0ff491 393 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
394}
395
cd0ff491 396static u32
cdcdc9eb
GFT
397jme_linkstat_from_phy(struct jme_adapter *jme)
398{
cd0ff491 399 u32 phylink, bmsr;
cdcdc9eb
GFT
400
401 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
402 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 403 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
404 phylink |= PHY_LINK_AUTONEG_COMPLETE;
405
406 return phylink;
407}
408
cd0ff491 409static inline void
55d19799 410jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT
411{
412 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
413}
414
415static inline void
55d19799 416jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT
417{
418 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
419}
420
fcf45b4c
GFT
421static int
422jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
423{
424 struct jme_adapter *jme = netdev_priv(netdev);
dc4185bd 425 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 426 char linkmsg[64];
fcf45b4c 427 int rc = 0;
d7699f87 428
b3821cc5 429 linkmsg[0] = '\0';
cdcdc9eb 430
cd0ff491 431 if (jme->fpgaver)
cdcdc9eb
GFT
432 phylink = jme_linkstat_from_phy(jme);
433 else
434 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 435
cd0ff491
GFT
436 if (phylink & PHY_LINK_UP) {
437 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
438 /*
439 * If we did not enable AN
440 * Speed/Duplex Info should be obtained from SMI
441 */
442 phylink = PHY_LINK_UP;
443
444 bmcr = jme_mdio_read(jme->dev,
445 jme->mii_if.phy_id,
446 MII_BMCR);
447
448 phylink |= ((bmcr & BMCR_SPEED1000) &&
449 (bmcr & BMCR_SPEED100) == 0) ?
450 PHY_LINK_SPEED_1000M :
451 (bmcr & BMCR_SPEED100) ?
452 PHY_LINK_SPEED_100M :
453 PHY_LINK_SPEED_10M;
454
455 phylink |= (bmcr & BMCR_FULLDPLX) ?
456 PHY_LINK_DUPLEX : 0;
79ce639c 457
b3821cc5 458 strcat(linkmsg, "Forced: ");
cd0ff491 459 } else {
8c198884
GFT
460 /*
461 * Keep polling for speed/duplex resolve complete
462 */
cd0ff491 463 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
464 --cnt) {
465
466 udelay(1);
8c198884 467
cd0ff491 468 if (jme->fpgaver)
cdcdc9eb
GFT
469 phylink = jme_linkstat_from_phy(jme);
470 else
471 phylink = jread32(jme, JME_PHY_LINK);
8c198884 472 }
cd0ff491 473 if (!cnt)
937ef75a 474 pr_err("Waiting speed resolve timeout\n");
79ce639c 475
b3821cc5 476 strcat(linkmsg, "ANed: ");
d7699f87
GFT
477 }
478
cd0ff491 479 if (jme->phylink == phylink) {
fcf45b4c
GFT
480 rc = 1;
481 goto out;
482 }
cd0ff491 483 if (testonly)
fcf45b4c
GFT
484 goto out;
485
486 jme->phylink = phylink;
487
dc4185bd
GFT
488 /*
489 * The speed/duplex setting of jme->reg_ghc already cleared
490 * by jme_reset_mac_processor()
491 */
cd0ff491
GFT
492 switch (phylink & PHY_LINK_SPEED_MASK) {
493 case PHY_LINK_SPEED_10M:
dc4185bd 494 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 495 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
496 break;
497 case PHY_LINK_SPEED_100M:
dc4185bd 498 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 499 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
500 break;
501 case PHY_LINK_SPEED_1000M:
dc4185bd 502 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 503 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
504 break;
505 default:
506 break;
d7699f87 507 }
d7699f87 508
cd0ff491 509 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 510 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
809b2798 511 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
dc4185bd 512 jme->reg_ghc |= GHC_DPX;
cd0ff491 513 } else {
d7699f87 514 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
515 TXMCS_BACKOFF |
516 TXMCS_CARRIERSENSE |
517 TXMCS_COLLISION);
809b2798 518 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 519 }
7ee473a3 520
dc4185bd
GFT
521 jwrite32(jme, JME_GHC, jme->reg_ghc);
522
7ee473a3 523 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
dc4185bd
GFT
524 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
525 GPREG1_RSSPATCH);
7ee473a3 526 if (!(phylink & PHY_LINK_DUPLEX))
dc4185bd 527 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
7ee473a3
GFT
528 switch (phylink & PHY_LINK_SPEED_MASK) {
529 case PHY_LINK_SPEED_10M:
55d19799 530 jme_set_phyfifo_8level(jme);
dc4185bd 531 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT
532 break;
533 case PHY_LINK_SPEED_100M:
55d19799 534 jme_set_phyfifo_5level(jme);
dc4185bd 535 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT
536 break;
537 case PHY_LINK_SPEED_1000M:
55d19799 538 jme_set_phyfifo_8level(jme);
7ee473a3
GFT
539 break;
540 default:
541 break;
542 }
543 }
dc4185bd 544 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 545
3b70a6fa
GFT
546 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
547 "Full-Duplex, " :
548 "Half-Duplex, ");
549 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
550 "MDI-X" :
551 "MDI");
937ef75a 552 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT
553 netif_carrier_on(netdev);
554 } else {
555 if (testonly)
fcf45b4c
GFT
556 goto out;
557
937ef75a 558 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 559 jme->phylink = 0;
cd0ff491 560 netif_carrier_off(netdev);
d7699f87 561 }
fcf45b4c
GFT
562
563out:
564 return rc;
d7699f87
GFT
565}
566
3bf61c55
GFT
567static int
568jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 569{
d7699f87
GFT
570 struct jme_ring *txring = &(jme->txring[0]);
571
572 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
574 &(txring->dmaalloc),
575 GFP_ATOMIC);
fcf45b4c 576
0ede469c
GFT
577 if (!txring->alloc)
578 goto err_set_null;
d7699f87
GFT
579
580 /*
581 * 16 Bytes align
582 */
cd0ff491 583 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 584 RING_DESC_ALIGN);
4330c2f2 585 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 586 txring->next_to_use = 0;
cdcdc9eb 587 atomic_set(&txring->next_to_clean, 0);
b3821cc5 588 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 589
0ede469c
GFT
590 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
591 jme->tx_ring_size, GFP_ATOMIC);
592 if (unlikely(!(txring->bufinf)))
593 goto err_free_txring;
594
d7699f87 595 /*
b3821cc5 596 * Initialize Transmit Descriptors
d7699f87 597 */
b3821cc5 598 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 599 memset(txring->bufinf, 0,
b3821cc5 600 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
601
602 return 0;
0ede469c
GFT
603
604err_free_txring:
605 dma_free_coherent(&(jme->pdev->dev),
606 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
607 txring->alloc,
608 txring->dmaalloc);
609
610err_set_null:
611 txring->desc = NULL;
612 txring->dmaalloc = 0;
613 txring->dma = 0;
614 txring->bufinf = NULL;
615
616 return -ENOMEM;
d7699f87
GFT
617}
618
3bf61c55
GFT
619static void
620jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
621{
622 int i;
623 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 624 struct jme_buffer_info *txbi;
d7699f87 625
cd0ff491 626 if (txring->alloc) {
0ede469c
GFT
627 if (txring->bufinf) {
628 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
629 txbi = txring->bufinf + i;
630 if (txbi->skb) {
631 dev_kfree_skb(txbi->skb);
632 txbi->skb = NULL;
633 }
634 txbi->mapping = 0;
635 txbi->len = 0;
636 txbi->nr_desc = 0;
637 txbi->start_xmit = 0;
d7699f87 638 }
0ede469c 639 kfree(txring->bufinf);
d7699f87
GFT
640 }
641
642 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 643 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
644 txring->alloc,
645 txring->dmaalloc);
3bf61c55
GFT
646
647 txring->alloc = NULL;
648 txring->desc = NULL;
649 txring->dmaalloc = 0;
650 txring->dma = 0;
0ede469c 651 txring->bufinf = NULL;
d7699f87 652 }
3bf61c55 653 txring->next_to_use = 0;
cdcdc9eb 654 atomic_set(&txring->next_to_clean, 0);
79ce639c 655 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
656}
657
cd0ff491 658static inline void
3bf61c55 659jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
660{
661 /*
662 * Select Queue 0
663 */
664 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 665 wmb();
d7699f87
GFT
666
667 /*
668 * Setup TX Queue 0 DMA Bass Address
669 */
fcf45b4c 670 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 671 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 672 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
673
674 /*
675 * Setup TX Descptor Count
676 */
b3821cc5 677 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
678
679 /*
680 * Enable TX Engine
681 */
682 wmb();
dc4185bd 683 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT
684 TXCS_SELECT_QUEUE0 |
685 TXCS_ENABLE);
d7699f87 686
dc4185bd
GFT
687 /*
688 * Start clock for TX MAC Processor
689 */
690 jme_mac_txclk_on(jme);
d7699f87
GFT
691}
692
cd0ff491 693static inline void
29bdd921
GFT
694jme_restart_tx_engine(struct jme_adapter *jme)
695{
696 /*
697 * Restart TX Engine
698 */
699 jwrite32(jme, JME_TXCS, jme->reg_txcs |
700 TXCS_SELECT_QUEUE0 |
701 TXCS_ENABLE);
702}
703
cd0ff491 704static inline void
3bf61c55 705jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
706{
707 int i;
cd0ff491 708 u32 val;
d7699f87
GFT
709
710 /*
711 * Disable TX Engine
712 */
fcf45b4c 713 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 714 wmb();
d7699f87
GFT
715
716 val = jread32(jme, JME_TXCS);
cd0ff491 717 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 718 mdelay(1);
d7699f87 719 val = jread32(jme, JME_TXCS);
cd0ff491 720 rmb();
d7699f87
GFT
721 }
722
cd0ff491 723 if (!i)
937ef75a 724 pr_err("Disable TX engine timeout\n");
dc4185bd
GFT
725
726 /*
727 * Stop clock for TX MAC Processor
728 */
729 jme_mac_txclk_off(jme);
d7699f87
GFT
730}
731
3bf61c55
GFT
732static void
733jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 734{
0ede469c 735 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 736 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
737 struct jme_buffer_info *rxbi = rxring->bufinf;
738 rxdesc += i;
739 rxbi += i;
740
741 rxdesc->dw[0] = 0;
742 rxdesc->dw[1] = 0;
3bf61c55 743 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
744 rxdesc->desc1.bufaddrl = cpu_to_le32(
745 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 746 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 747 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 748 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 749 wmb();
3bf61c55 750 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
751}
752
3bf61c55
GFT
753static int
754jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
755{
756 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 757 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 758 struct sk_buff *skb;
4330c2f2 759
79ce639c
GFT
760 skb = netdev_alloc_skb(jme->dev,
761 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 762 if (unlikely(!skb))
4330c2f2 763 return -ENOMEM;
3b70a6fa
GFT
764#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
765 skb->dev = jme->dev;
766#endif
3bf61c55 767
4330c2f2 768 rxbi->skb = skb;
3bf61c55 769 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
770 rxbi->mapping = pci_map_page(jme->pdev,
771 virt_to_page(skb->data),
772 offset_in_page(skb->data),
773 rxbi->len,
774 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
775
776 return 0;
777}
778
3bf61c55
GFT
779static void
780jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
781{
782 struct jme_ring *rxring = &(jme->rxring[0]);
783 struct jme_buffer_info *rxbi = rxring->bufinf;
784 rxbi += i;
785
cd0ff491 786 if (rxbi->skb) {
b3821cc5 787 pci_unmap_page(jme->pdev,
4330c2f2 788 rxbi->mapping,
3bf61c55 789 rxbi->len,
4330c2f2
GFT
790 PCI_DMA_FROMDEVICE);
791 dev_kfree_skb(rxbi->skb);
792 rxbi->skb = NULL;
793 rxbi->mapping = 0;
3bf61c55 794 rxbi->len = 0;
4330c2f2
GFT
795 }
796}
797
3bf61c55
GFT
798static void
799jme_free_rx_resources(struct jme_adapter *jme)
800{
801 int i;
802 struct jme_ring *rxring = &(jme->rxring[0]);
803
cd0ff491 804 if (rxring->alloc) {
0ede469c
GFT
805 if (rxring->bufinf) {
806 for (i = 0 ; i < jme->rx_ring_size ; ++i)
807 jme_free_rx_buf(jme, i);
808 kfree(rxring->bufinf);
809 }
3bf61c55
GFT
810
811 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 812 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
813 rxring->alloc,
814 rxring->dmaalloc);
815 rxring->alloc = NULL;
816 rxring->desc = NULL;
817 rxring->dmaalloc = 0;
818 rxring->dma = 0;
0ede469c 819 rxring->bufinf = NULL;
3bf61c55
GFT
820 }
821 rxring->next_to_use = 0;
cdcdc9eb 822 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
823}
824
825static int
826jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
827{
828 int i;
829 struct jme_ring *rxring = &(jme->rxring[0]);
830
831 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
832 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
833 &(rxring->dmaalloc),
834 GFP_ATOMIC);
0ede469c
GFT
835 if (!rxring->alloc)
836 goto err_set_null;
d7699f87
GFT
837
838 /*
839 * 16 Bytes align
840 */
cd0ff491 841 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 842 RING_DESC_ALIGN);
4330c2f2 843 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 844 rxring->next_to_use = 0;
cdcdc9eb 845 atomic_set(&rxring->next_to_clean, 0);
d7699f87 846
0ede469c
GFT
847 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
848 jme->rx_ring_size, GFP_ATOMIC);
849 if (unlikely(!(rxring->bufinf)))
850 goto err_free_rxring;
851
d7699f87
GFT
852 /*
853 * Initiallize Receive Descriptors
854 */
0ede469c
GFT
855 memset(rxring->bufinf, 0,
856 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT
857 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
858 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
859 jme_free_rx_resources(jme);
860 return -ENOMEM;
861 }
d7699f87
GFT
862
863 jme_set_clean_rxdesc(jme, i);
864 }
865
d7699f87 866 return 0;
0ede469c
GFT
867
868err_free_rxring:
869 dma_free_coherent(&(jme->pdev->dev),
870 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
871 rxring->alloc,
872 rxring->dmaalloc);
873err_set_null:
874 rxring->desc = NULL;
875 rxring->dmaalloc = 0;
876 rxring->dma = 0;
877 rxring->bufinf = NULL;
878
879 return -ENOMEM;
d7699f87
GFT
880}
881
cd0ff491 882static inline void
3bf61c55 883jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 884{
d7699f87 885 /*
cd0ff491
GFT
886 * Select Queue 0
887 */
888 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
889 RXCS_QUEUESEL_Q0);
890 wmb();
891
892 /*
d7699f87
GFT
893 * Setup RX DMA Bass Address
894 */
0ede469c 895 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 896 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 897 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT
898
899 /*
b3821cc5 900 * Setup RX Descriptor Count
d7699f87 901 */
b3821cc5 902 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 903
3bf61c55 904 /*
d7699f87
GFT
905 * Setup Unicast Filter
906 */
907 jme_set_multi(jme->dev);
908
909 /*
910 * Enable RX Engine
911 */
912 wmb();
dc4185bd 913 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
914 RXCS_QUEUESEL_Q0 |
915 RXCS_ENABLE |
916 RXCS_QST);
dc4185bd
GFT
917
918 /*
919 * Start clock for RX MAC Processor
920 */
921 jme_mac_rxclk_on(jme);
d7699f87
GFT
922}
923
cd0ff491 924static inline void
3bf61c55 925jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
926{
927 /*
3bf61c55 928 * Start RX Engine
4330c2f2 929 */
79ce639c 930 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
931 RXCS_QUEUESEL_Q0 |
932 RXCS_ENABLE |
933 RXCS_QST);
934}
935
cd0ff491 936static inline void
3bf61c55 937jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
938{
939 int i;
cd0ff491 940 u32 val;
d7699f87
GFT
941
942 /*
943 * Disable RX Engine
944 */
29bdd921 945 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 946 wmb();
d7699f87
GFT
947
948 val = jread32(jme, JME_RXCS);
cd0ff491 949 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 950 mdelay(1);
d7699f87 951 val = jread32(jme, JME_RXCS);
cd0ff491 952 rmb();
d7699f87
GFT
953 }
954
cd0ff491 955 if (!i)
937ef75a 956 pr_err("Disable RX engine timeout\n");
d7699f87 957
dc4185bd
GFT
958 /*
959 * Stop clock for RX MAC Processor
960 */
961 jme_mac_rxclk_off(jme);
d7699f87
GFT
962}
963
192570e0 964static int
cd0ff491 965jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 966{
cd0ff491 967 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
968 return false;
969
0ede469c
GFT
970 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
971 == RXWBFLAG_TCPON)) {
972 if (flags & RXWBFLAG_IPV4)
7ca9ebee 973 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 974 return false;
192570e0
GFT
975 }
976
0ede469c
GFT
977 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
978 == RXWBFLAG_UDPON)) {
979 if (flags & RXWBFLAG_IPV4)
937ef75a 980 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 981 return false;
192570e0
GFT
982 }
983
0ede469c
GFT
984 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
985 == RXWBFLAG_IPV4)) {
937ef75a 986 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 987 return false;
192570e0
GFT
988 }
989
990 return true;
991}
992
3bf61c55 993static void
42b1055e 994jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 995{
d7699f87 996 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 997 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 998 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 999 struct sk_buff *skb;
3bf61c55 1000 int framesize;
d7699f87 1001
3bf61c55
GFT
1002 rxdesc += idx;
1003 rxbi += idx;
d7699f87 1004
3bf61c55
GFT
1005 skb = rxbi->skb;
1006 pci_dma_sync_single_for_cpu(jme->pdev,
1007 rxbi->mapping,
1008 rxbi->len,
1009 PCI_DMA_FROMDEVICE);
1010
cd0ff491 1011 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
1012 pci_dma_sync_single_for_device(jme->pdev,
1013 rxbi->mapping,
1014 rxbi->len,
1015 PCI_DMA_FROMDEVICE);
1016
1017 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1018 } else {
3bf61c55
GFT
1019 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1020 - RX_PREPAD_SIZE;
1021
1022 skb_reserve(skb, RX_PREPAD_SIZE);
1023 skb_put(skb, framesize);
1024 skb->protocol = eth_type_trans(skb, jme->dev);
1025
3b70a6fa 1026 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 1027 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1028 else
08f5fcfa 1029#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
29bdd921 1030 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED
1031#else
1032 skb_checksum_none_assert(skb);
1033#endif
8c198884 1034
3b70a6fa 1035 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1036 if (jme->vlgrp) {
cdcdc9eb 1037 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 1038 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1039 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 1040 } else {
7ca9ebee 1041 dev_kfree_skb(skb);
b3821cc5 1042 }
cd0ff491 1043 } else {
cdcdc9eb 1044 jme->jme_rx(skb);
b3821cc5 1045 }
3bf61c55 1046
3b70a6fa
GFT
1047 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1048 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT
1049 ++(NET_STAT(jme).multicast);
1050
3bf61c55
GFT
1051 NET_STAT(jme).rx_bytes += framesize;
1052 ++(NET_STAT(jme).rx_packets);
1053 }
1054
1055 jme_set_clean_rxdesc(jme, idx);
1056
1057}
1058
8c198884 1059static int
3bf61c55
GFT
1060jme_process_receive(struct jme_adapter *jme, int limit)
1061{
1062 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1063 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1064 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1065
cd0ff491 1066 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
1067 goto out_inc;
1068
cd0ff491 1069 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
1070 goto out_inc;
1071
cd0ff491 1072 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
1073 goto out_inc;
1074
cdcdc9eb 1075 i = atomic_read(&rxring->next_to_clean);
0ede469c 1076 while (limit > 0) {
3bf61c55
GFT
1077 rxdesc = rxring->desc;
1078 rxdesc += i;
1079
3b70a6fa 1080 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT
1081 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1082 goto out;
0ede469c 1083 --limit;
d7699f87 1084
9134abda 1085 rmb();
4330c2f2
GFT
1086 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1087
cd0ff491 1088 if (unlikely(desccnt > 1 ||
192570e0 1089 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1090
cd0ff491 1091 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1092 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1093 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
1094 ++(NET_STAT(jme).rx_fifo_errors);
1095 else
1096 ++(NET_STAT(jme).rx_errors);
4330c2f2 1097
cd0ff491 1098 if (desccnt > 1)
3bf61c55 1099 limit -= desccnt - 1;
4330c2f2 1100
cd0ff491 1101 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1102 jme_set_clean_rxdesc(jme, j);
b3821cc5 1103 j = (j + 1) & (mask);
4330c2f2 1104 }
3bf61c55 1105
cd0ff491 1106 } else {
42b1055e 1107 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1108 }
4330c2f2 1109
b3821cc5 1110 i = (i + desccnt) & (mask);
3bf61c55 1111 }
4330c2f2 1112
3bf61c55 1113out:
cdcdc9eb 1114 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1115
192570e0
GFT
1116out_inc:
1117 atomic_inc(&jme->rx_cleaning);
1118
3bf61c55 1119 return limit > 0 ? limit : 0;
4330c2f2 1120
3bf61c55 1121}
d7699f87 1122
3bf61c55 1123static void
79ce639c
GFT
1124jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1125{
cd0ff491 1126 if (likely(atmp == dpi->cur)) {
192570e0 1127 dpi->cnt = 0;
79ce639c 1128 return;
192570e0 1129 }
79ce639c 1130
cd0ff491 1131 if (dpi->attempt == atmp) {
79ce639c 1132 ++(dpi->cnt);
cd0ff491 1133 } else {
79ce639c
GFT
1134 dpi->attempt = atmp;
1135 dpi->cnt = 0;
1136 }
1137
1138}
1139
1140static void
1141jme_dynamic_pcc(struct jme_adapter *jme)
1142{
1143 register struct dynpcc_info *dpi = &(jme->dpi);
1144
cd0ff491 1145 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1146 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT
1147 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1148 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT
1149 jme_attempt_pcc(dpi, PCC_P2);
1150 else
1151 jme_attempt_pcc(dpi, PCC_P1);
1152
cd0ff491
GFT
1153 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1154 if (dpi->attempt < dpi->cur)
1155 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1156 jme_set_rx_pcc(jme, dpi->attempt);
1157 dpi->cur = dpi->attempt;
1158 dpi->cnt = 0;
1159 }
1160}
1161
1162static void
1163jme_start_pcc_timer(struct jme_adapter *jme)
1164{
1165 struct dynpcc_info *dpi = &(jme->dpi);
1166 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1167 dpi->last_pkts = NET_STAT(jme).rx_packets;
1168 dpi->intr_cnt = 0;
1169 jwrite32(jme, JME_TMCSR,
1170 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1171}
1172
cd0ff491 1173static inline void
29bdd921
GFT
1174jme_stop_pcc_timer(struct jme_adapter *jme)
1175{
1176 jwrite32(jme, JME_TMCSR, 0);
1177}
1178
1179static void
cd0ff491
GFT
1180jme_shutdown_nic(struct jme_adapter *jme)
1181{
1182 u32 phylink;
1183
1184 phylink = jme_linkstat_from_phy(jme);
1185
1186 if (!(phylink & PHY_LINK_UP)) {
1187 /*
1188 * Disable all interrupt before issue timer
1189 */
1190 jme_stop_irq(jme);
1191 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1192 }
1193}
1194
1195static void
79ce639c
GFT
1196jme_pcc_tasklet(unsigned long arg)
1197{
cd0ff491 1198 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1199 struct net_device *netdev = jme->dev;
1200
cd0ff491
GFT
1201 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1202 jme_shutdown_nic(jme);
1203 return;
1204 }
29bdd921 1205
cd0ff491 1206 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1207 (atomic_read(&jme->link_changing) != 1)
1208 )) {
1209 jme_stop_pcc_timer(jme);
79ce639c
GFT
1210 return;
1211 }
29bdd921 1212
cd0ff491 1213 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1214 jme_dynamic_pcc(jme);
1215
79ce639c
GFT
1216 jme_start_pcc_timer(jme);
1217}
1218
cd0ff491 1219static inline void
192570e0
GFT
1220jme_polling_mode(struct jme_adapter *jme)
1221{
1222 jme_set_rx_pcc(jme, PCC_OFF);
1223}
1224
cd0ff491 1225static inline void
192570e0
GFT
1226jme_interrupt_mode(struct jme_adapter *jme)
1227{
1228 jme_set_rx_pcc(jme, PCC_P1);
1229}
1230
cd0ff491
GFT
1231static inline int
1232jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1233{
1234 u32 apmc;
1235 apmc = jread32(jme, JME_APMC);
1236 return apmc & JME_APMC_PSEUDO_HP_EN;
1237}
1238
1239static void
1240jme_start_shutdown_timer(struct jme_adapter *jme)
1241{
1242 u32 apmc;
1243
1244 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1245 apmc &= ~JME_APMC_EPIEN_CTRL;
1246 if (!no_extplug) {
1247 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1248 wmb();
1249 }
1250 jwrite32f(jme, JME_APMC, apmc);
1251
1252 jwrite32f(jme, JME_TIMER2, 0);
1253 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1254 jwrite32(jme, JME_TMCSR,
1255 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1256}
1257
1258static void
1259jme_stop_shutdown_timer(struct jme_adapter *jme)
1260{
1261 u32 apmc;
1262
1263 jwrite32f(jme, JME_TMCSR, 0);
1264 jwrite32f(jme, JME_TIMER2, 0);
1265 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1266
1267 apmc = jread32(jme, JME_APMC);
1268 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1269 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1270 wmb();
1271 jwrite32f(jme, JME_APMC, apmc);
1272}
1273
79ce639c 1274static void
3bf61c55
GFT
1275jme_link_change_tasklet(unsigned long arg)
1276{
cd0ff491 1277 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1278 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1279 int rc;
1280
cd0ff491
GFT
1281 while (!atomic_dec_and_test(&jme->link_changing)) {
1282 atomic_inc(&jme->link_changing);
937ef75a 1283 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1284 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1285 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1286 }
fcf45b4c 1287
cd0ff491 1288 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1289 goto out;
1290
29bdd921 1291 jme->old_mtu = netdev->mtu;
fcf45b4c 1292 netif_stop_queue(netdev);
cd0ff491
GFT
1293 if (jme_pseudo_hotplug_enabled(jme))
1294 jme_stop_shutdown_timer(jme);
1295
1296 jme_stop_pcc_timer(jme);
1297 tasklet_disable(&jme->txclean_task);
1298 tasklet_disable(&jme->rxclean_task);
1299 tasklet_disable(&jme->rxempty_task);
1300
1301 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT
1302 jme_disable_rx_engine(jme);
1303 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1304 jme_reset_mac_processor(jme);
1305 jme_free_rx_resources(jme);
1306 jme_free_tx_resources(jme);
192570e0 1307
cd0ff491 1308 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1309 jme_polling_mode(jme);
cd0ff491
GFT
1310
1311 netif_carrier_off(netdev);
fcf45b4c
GFT
1312 }
1313
1314 jme_check_link(netdev, 0);
cd0ff491 1315 if (netif_carrier_ok(netdev)) {
fcf45b4c 1316 rc = jme_setup_rx_resources(jme);
cd0ff491 1317 if (rc) {
937ef75a 1318 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1319 goto out_enable_tasklet;
fcf45b4c
GFT
1320 }
1321
fcf45b4c 1322 rc = jme_setup_tx_resources(jme);
cd0ff491 1323 if (rc) {
937ef75a 1324 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT
1325 goto err_out_free_rx_resources;
1326 }
1327
1328 jme_enable_rx_engine(jme);
1329 jme_enable_tx_engine(jme);
1330
1331 netif_start_queue(netdev);
192570e0 1332
cd0ff491 1333 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1334 jme_interrupt_mode(jme);
192570e0 1335
79ce639c 1336 jme_start_pcc_timer(jme);
cd0ff491
GFT
1337 } else if (jme_pseudo_hotplug_enabled(jme)) {
1338 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1339 }
1340
cd0ff491 1341 goto out_enable_tasklet;
fcf45b4c
GFT
1342
1343err_out_free_rx_resources:
1344 jme_free_rx_resources(jme);
cd0ff491
GFT
1345out_enable_tasklet:
1346 tasklet_enable(&jme->txclean_task);
1347 tasklet_hi_enable(&jme->rxclean_task);
1348 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1349out:
1350 atomic_inc(&jme->link_changing);
3bf61c55 1351}
d7699f87 1352
3bf61c55
GFT
1353static void
1354jme_rx_clean_tasklet(unsigned long arg)
1355{
cd0ff491 1356 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1357 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1358
192570e0
GFT
1359 jme_process_receive(jme, jme->rx_ring_size);
1360 ++(dpi->intr_cnt);
42b1055e 1361
192570e0 1362}
fcf45b4c 1363
192570e0 1364static int
cdcdc9eb 1365jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1366{
cdcdc9eb 1367 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1368 DECLARE_NETDEV
192570e0 1369 int rest;
fcf45b4c 1370
cdcdc9eb 1371 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1372
cd0ff491 1373 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1374 atomic_dec(&jme->rx_empty);
192570e0
GFT
1375 ++(NET_STAT(jme).rx_dropped);
1376 jme_restart_rx_engine(jme);
1377 }
1378 atomic_inc(&jme->rx_empty);
1379
cd0ff491 1380 if (rest) {
cdcdc9eb 1381 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1382 jme_interrupt_mode(jme);
1383 }
1384
cdcdc9eb
GFT
1385 JME_NAPI_WEIGHT_SET(budget, rest);
1386 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1387}
1388
1389static void
1390jme_rx_empty_tasklet(unsigned long arg)
1391{
cd0ff491 1392 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1393
cd0ff491 1394 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1395 return;
1396
cd0ff491 1397 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1398 return;
1399
7ca9ebee 1400 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1401
fcf45b4c 1402 jme_rx_clean_tasklet(arg);
cdcdc9eb 1403
cd0ff491 1404 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1405 atomic_dec(&jme->rx_empty);
1406 ++(NET_STAT(jme).rx_dropped);
1407 jme_restart_rx_engine(jme);
1408 }
1409 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1410}
1411
3bf61c55 1412static void
b3821cc5
GFT
1413jme_wake_queue_if_stopped(struct jme_adapter *jme)
1414{
0ede469c 1415 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1416
1417 smp_wmb();
cd0ff491 1418 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1419 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1420 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1421 netif_wake_queue(jme->dev);
b3821cc5
GFT
1422 }
1423
1424}
1425
1426static void
3bf61c55 1427jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1428{
cd0ff491 1429 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1430 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1431 struct txdesc *txdesc = txring->desc;
3bf61c55 1432 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1433 int i, j, cnt = 0, max, err, mask;
3bf61c55 1434
937ef75a 1435 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT
1436
1437 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1438 goto out;
1439
cd0ff491 1440 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1441 goto out;
1442
cd0ff491 1443 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1444 goto out;
1445
b3821cc5
GFT
1446 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1447 mask = jme->tx_ring_mask;
3bf61c55 1448
cd0ff491 1449 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1450
1451 ctxbi = txbi + i;
1452
cd0ff491 1453 if (likely(ctxbi->skb &&
b3821cc5 1454 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1455
cd0ff491 1456 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1457 i, ctxbi->nr_desc, jiffies);
3bf61c55 1458
cd0ff491 1459 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1460
cd0ff491 1461 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1462 ttxbi = txbi + ((i + j) & (mask));
1463 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1464
b3821cc5 1465 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1466 ttxbi->mapping,
1467 ttxbi->len,
1468 PCI_DMA_TODEVICE);
1469
3bf61c55
GFT
1470 ttxbi->mapping = 0;
1471 ttxbi->len = 0;
1472 }
1473
1474 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1475
1476 cnt += ctxbi->nr_desc;
1477
cd0ff491 1478 if (unlikely(err)) {
8c198884 1479 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1480 } else {
8c198884 1481 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1482 NET_STAT(jme).tx_bytes += ctxbi->len;
1483 }
1484
1485 ctxbi->skb = NULL;
1486 ctxbi->len = 0;
cdcdc9eb 1487 ctxbi->start_xmit = 0;
cd0ff491
GFT
1488
1489 } else {
3bf61c55
GFT
1490 break;
1491 }
1492
b3821cc5 1493 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1494
1495 ctxbi->nr_desc = 0;
d7699f87
GFT
1496 }
1497
937ef75a 1498 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1499 atomic_set(&txring->next_to_clean, i);
79ce639c 1500 atomic_add(cnt, &txring->nr_free);
3bf61c55 1501
b3821cc5
GFT
1502 jme_wake_queue_if_stopped(jme);
1503
fcf45b4c
GFT
1504out:
1505 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1506}
1507
79ce639c 1508static void
cd0ff491 1509jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1510{
3bf61c55
GFT
1511 /*
1512 * Disable interrupt
1513 */
1514 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1515
cd0ff491 1516 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1517 /*
1518 * Link change event is critical
1519 * all other events are ignored
1520 */
1521 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1522 tasklet_schedule(&jme->linkch_task);
29bdd921 1523 goto out_reenable;
fcf45b4c 1524 }
d7699f87 1525
cd0ff491 1526 if (intrstat & INTR_TMINTR) {
47220951 1527 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1528 tasklet_schedule(&jme->pcc_task);
47220951 1529 }
79ce639c 1530
cd0ff491 1531 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1532 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1533 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1534 }
1535
cd0ff491 1536 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1537 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1538 INTR_PCCRX0 |
1539 INTR_RX0EMP)) |
1540 INTR_RX0);
1541 }
d7699f87 1542
cd0ff491
GFT
1543 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1544 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1545 atomic_inc(&jme->rx_empty);
1546
cd0ff491
GFT
1547 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1548 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1549 jme_polling_mode(jme);
cdcdc9eb 1550 JME_RX_SCHEDULE(jme);
192570e0
GFT
1551 }
1552 }
cd0ff491
GFT
1553 } else {
1554 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1555 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1556 tasklet_hi_schedule(&jme->rxempty_task);
1557 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1558 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1559 }
4330c2f2 1560 }
d7699f87 1561
29bdd921 1562out_reenable:
3bf61c55 1563 /*
fcf45b4c 1564 * Re-enable interrupt
3bf61c55 1565 */
fcf45b4c 1566 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1567}
1568
3b70a6fa
GFT
1569#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1570static irqreturn_t
1571jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1572#else
79ce639c
GFT
1573static irqreturn_t
1574jme_intr(int irq, void *dev_id)
3b70a6fa 1575#endif
79ce639c 1576{
cd0ff491
GFT
1577 struct net_device *netdev = dev_id;
1578 struct jme_adapter *jme = netdev_priv(netdev);
1579 u32 intrstat;
79ce639c
GFT
1580
1581 intrstat = jread32(jme, JME_IEVE);
1582
1583 /*
1584 * Check if it's really an interrupt for us
1585 */
7ee473a3 1586 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1587 return IRQ_NONE;
79ce639c
GFT
1588
1589 /*
1590 * Check if the device still exist
1591 */
cd0ff491
GFT
1592 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1593 return IRQ_NONE;
79ce639c
GFT
1594
1595 jme_intr_msi(jme, intrstat);
1596
cd0ff491 1597 return IRQ_HANDLED;
d7699f87
GFT
1598}
1599
3b70a6fa
GFT
1600#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1601static irqreturn_t
1602jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1603#else
79ce639c
GFT
1604static irqreturn_t
1605jme_msi(int irq, void *dev_id)
3b70a6fa 1606#endif
79ce639c 1607{
cd0ff491
GFT
1608 struct net_device *netdev = dev_id;
1609 struct jme_adapter *jme = netdev_priv(netdev);
1610 u32 intrstat;
79ce639c 1611
0ede469c 1612 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT
1613
1614 jme_intr_msi(jme, intrstat);
1615
cd0ff491 1616 return IRQ_HANDLED;
79ce639c
GFT
1617}
1618
79ce639c
GFT
1619static void
1620jme_reset_link(struct jme_adapter *jme)
1621{
1622 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1623}
1624
fcf45b4c
GFT
1625static void
1626jme_restart_an(struct jme_adapter *jme)
1627{
cd0ff491 1628 u32 bmcr;
fcf45b4c 1629
cd0ff491 1630 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1631 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1632 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1633 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1634 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1635}
1636
1637static int
1638jme_request_irq(struct jme_adapter *jme)
1639{
1640 int rc;
cd0ff491 1641 struct net_device *netdev = jme->dev;
3b70a6fa
GFT
1642#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1643 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1644 int irq_flags = SA_SHIRQ;
1645#else
cd0ff491
GFT
1646 irq_handler_t handler = jme_intr;
1647 int irq_flags = IRQF_SHARED;
3b70a6fa 1648#endif
cd0ff491
GFT
1649
1650 if (!pci_enable_msi(jme->pdev)) {
1651 set_bit(JME_FLAG_MSI, &jme->flags);
1652 handler = jme_msi;
1653 irq_flags = 0;
1654 }
1655
1656 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1657 netdev);
1658 if (rc) {
937ef75a
JP
1659 netdev_err(netdev,
1660 "Unable to request %s interrupt (return: %d)\n",
1661 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1662 rc);
79ce639c 1663
cd0ff491
GFT
1664 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1665 pci_disable_msi(jme->pdev);
1666 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1667 }
cd0ff491 1668 } else {
79ce639c
GFT
1669 netdev->irq = jme->pdev->irq;
1670 }
1671
cd0ff491 1672 return rc;
79ce639c
GFT
1673}
1674
1675static void
1676jme_free_irq(struct jme_adapter *jme)
1677{
cd0ff491
GFT
1678 free_irq(jme->pdev->irq, jme->dev);
1679 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1680 pci_disable_msi(jme->pdev);
1681 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1682 jme->dev->irq = jme->pdev->irq;
cd0ff491 1683 }
fcf45b4c
GFT
1684}
1685
e58b908e 1686static inline void
ed457bcc
GFT
1687jme_new_phy_on(struct jme_adapter *jme)
1688{
1689 u32 reg;
1690
1691 reg = jread32(jme, JME_PHY_PWR);
1692 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1693 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1694 jwrite32(jme, JME_PHY_PWR, reg);
1695
1696 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1697 reg &= ~PE1_GPREG0_PBG;
1698 reg |= PE1_GPREG0_ENBG;
1699 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1700}
1701
1702static inline void
1703jme_new_phy_off(struct jme_adapter *jme)
1704{
1705 u32 reg;
1706
1707 reg = jread32(jme, JME_PHY_PWR);
1708 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1709 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1710 jwrite32(jme, JME_PHY_PWR, reg);
1711
1712 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1713 reg &= ~PE1_GPREG0_PBG;
1714 reg |= PE1_GPREG0_PDD3COLD;
1715 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1716}
1717
1718static inline void
e58b908e
GFT
1719jme_phy_on(struct jme_adapter *jme)
1720{
1721 u32 bmcr;
1722
1723 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1724 bmcr &= ~BMCR_PDOWN;
1725 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
ed457bcc
GFT
1726
1727 if (new_phy_power_ctrl(jme->chip_main_rev))
1728 jme_new_phy_on(jme);
1729}
1730
1731static inline void
1732jme_phy_off(struct jme_adapter *jme)
1733{
1734 u32 bmcr;
1735
1736 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1737 bmcr |= BMCR_PDOWN;
1738 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1739
1740 if (new_phy_power_ctrl(jme->chip_main_rev))
1741 jme_new_phy_off(jme);
e58b908e
GFT
1742}
1743
3bf61c55
GFT
1744static int
1745jme_open(struct net_device *netdev)
d7699f87
GFT
1746{
1747 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1748 int rc;
79ce639c 1749
42b1055e 1750 jme_clear_pm(jme);
cdcdc9eb 1751 JME_NAPI_ENABLE(jme);
d7699f87 1752
0ede469c 1753 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT
1754 tasklet_enable(&jme->txclean_task);
1755 tasklet_hi_enable(&jme->rxclean_task);
1756 tasklet_hi_enable(&jme->rxempty_task);
1757
79ce639c 1758 rc = jme_request_irq(jme);
cd0ff491 1759 if (rc)
4330c2f2 1760 goto err_out;
79ce639c 1761
d7699f87 1762 jme_start_irq(jme);
42b1055e 1763
ed457bcc
GFT
1764 jme_phy_on(jme);
1765 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1766 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 1767 else
42b1055e
GFT
1768 jme_reset_phy_processor(jme);
1769
29bdd921 1770 jme_reset_link(jme);
d7699f87
GFT
1771
1772 return 0;
1773
d7699f87
GFT
1774err_out:
1775 netif_stop_queue(netdev);
1776 netif_carrier_off(netdev);
4330c2f2 1777 return rc;
d7699f87
GFT
1778}
1779
42b1055e
GFT
1780static void
1781jme_set_100m_half(struct jme_adapter *jme)
1782{
cd0ff491 1783 u32 bmcr, tmp;
42b1055e 1784
a82e368c 1785 jme_phy_on(jme);
42b1055e
GFT
1786 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1787 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1788 BMCR_SPEED1000 | BMCR_FULLDPLX);
1789 tmp |= BMCR_SPEED100;
1790
1791 if (bmcr != tmp)
1792 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1793
cd0ff491 1794 if (jme->fpgaver)
cdcdc9eb
GFT
1795 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1796 else
1797 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1798}
1799
47220951
GFT
1800#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1801static void
1802jme_wait_link(struct jme_adapter *jme)
1803{
cd0ff491 1804 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1805
1806 mdelay(1000);
1807 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1808 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1809 mdelay(10);
1810 phylink = jme_linkstat_from_phy(jme);
1811 }
1812}
1813
a82e368c
GFT
1814static void
1815jme_powersave_phy(struct jme_adapter *jme)
1816{
1817 if (jme->reg_pmcs) {
1818 jme_set_100m_half(jme);
1819
1820 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1821 jme_wait_link(jme);
1822
1823 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1824 } else {
1825 jme_phy_off(jme);
1826 }
1827}
1828
3bf61c55
GFT
1829static int
1830jme_close(struct net_device *netdev)
d7699f87
GFT
1831{
1832 struct jme_adapter *jme = netdev_priv(netdev);
1833
1834 netif_stop_queue(netdev);
1835 netif_carrier_off(netdev);
1836
1837 jme_stop_irq(jme);
79ce639c 1838 jme_free_irq(jme);
d7699f87 1839
cdcdc9eb 1840 JME_NAPI_DISABLE(jme);
192570e0 1841
0ede469c
GFT
1842 tasklet_disable(&jme->linkch_task);
1843 tasklet_disable(&jme->txclean_task);
1844 tasklet_disable(&jme->rxclean_task);
1845 tasklet_disable(&jme->rxempty_task);
8c198884 1846
cd0ff491
GFT
1847 jme_disable_rx_engine(jme);
1848 jme_disable_tx_engine(jme);
8c198884 1849 jme_reset_mac_processor(jme);
d7699f87
GFT
1850 jme_free_rx_resources(jme);
1851 jme_free_tx_resources(jme);
42b1055e 1852 jme->phylink = 0;
b3821cc5
GFT
1853 jme_phy_off(jme);
1854
1855 return 0;
1856}
1857
1858static int
1859jme_alloc_txdesc(struct jme_adapter *jme,
1860 struct sk_buff *skb)
1861{
0ede469c 1862 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1863 int idx, nr_alloc, mask = jme->tx_ring_mask;
1864
1865 idx = txring->next_to_use;
1866 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1867
cd0ff491 1868 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1869 return -1;
1870
1871 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1872
b3821cc5
GFT
1873 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1874
1875 return idx;
1876}
1877
1878static void
1879jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1880 struct txdesc *txdesc,
b3821cc5
GFT
1881 struct jme_buffer_info *txbi,
1882 struct page *page,
cd0ff491
GFT
1883 u32 page_offset,
1884 u32 len,
1885 u8 hidma)
b3821cc5
GFT
1886{
1887 dma_addr_t dmaaddr;
1888
1889 dmaaddr = pci_map_page(pdev,
1890 page,
1891 page_offset,
1892 len,
1893 PCI_DMA_TODEVICE);
1894
1895 pci_dma_sync_single_for_device(pdev,
1896 dmaaddr,
1897 len,
1898 PCI_DMA_TODEVICE);
1899
1900 txdesc->dw[0] = 0;
1901 txdesc->dw[1] = 0;
1902 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1903 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1904 txdesc->desc2.datalen = cpu_to_le16(len);
1905 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1906 txdesc->desc2.bufaddrl = cpu_to_le32(
1907 (__u64)dmaaddr & 0xFFFFFFFFUL);
1908
1909 txbi->mapping = dmaaddr;
1910 txbi->len = len;
1911}
1912
1913static void
1914jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1915{
0ede469c 1916 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1917 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1918 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1919 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1920 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1921 int mask = jme->tx_ring_mask;
1922 struct skb_frag_struct *frag;
cd0ff491 1923 u32 len;
b3821cc5 1924
cd0ff491
GFT
1925 for (i = 0 ; i < nr_frags ; ++i) {
1926 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1927 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1928 ctxbi = txbi + ((idx + i + 2) & (mask));
1929
1930 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1931 frag->page_offset, frag->size, hidma);
42b1055e 1932 }
b3821cc5 1933
cd0ff491 1934 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1935 ctxdesc = txdesc + ((idx + 1) & (mask));
1936 ctxbi = txbi + ((idx + 1) & (mask));
1937 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1938 offset_in_page(skb->data), len, hidma);
1939
1940}
1941
1942static int
1943jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1944{
3b70a6fa 1945 if (unlikely(
0ede469c 1946#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT
1947 skb_shinfo(skb)->tso_size
1948#else
1949 skb_shinfo(skb)->gso_size
1950#endif
1951 && skb_header_cloned(skb) &&
b3821cc5
GFT
1952 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1953 dev_kfree_skb(skb);
1954 return -1;
1955 }
1956
1957 return 0;
1958}
1959
1960static int
3b70a6fa 1961jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1962{
0ede469c 1963#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT
1964 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1965#else
1966 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1967#endif
cd0ff491 1968 if (*mss) {
b3821cc5
GFT
1969 *flags |= TXFLAG_LSEN;
1970
cd0ff491 1971 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1972 struct iphdr *iph = ip_hdr(skb);
1973
1974 iph->check = 0;
cd0ff491 1975 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1976 iph->daddr, 0,
1977 IPPROTO_TCP,
1978 0);
cd0ff491 1979 } else {
b3821cc5
GFT
1980 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1981
cd0ff491 1982 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1983 &ip6h->daddr, 0,
1984 IPPROTO_TCP,
1985 0);
1986 }
1987
1988 return 0;
1989 }
1990
1991 return 1;
1992}
1993
1994static void
cd0ff491 1995jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1996{
3b70a6fa
GFT
1997#ifdef CHECKSUM_PARTIAL
1998 if (skb->ip_summed == CHECKSUM_PARTIAL)
1999#else
2000 if (skb->ip_summed == CHECKSUM_HW)
2001#endif
2002 {
cd0ff491 2003 u8 ip_proto;
b3821cc5 2004
3b70a6fa
GFT
2005#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2006 if (skb->protocol == htons(ETH_P_IP))
2007 ip_proto = ip_hdr(skb)->protocol;
2008 else if (skb->protocol == htons(ETH_P_IPV6))
2009 ip_proto = ipv6_hdr(skb)->nexthdr;
2010 else
2011 ip_proto = 0;
2012#else
b3821cc5 2013 switch (skb->protocol) {
cd0ff491 2014 case htons(ETH_P_IP):
b3821cc5
GFT
2015 ip_proto = ip_hdr(skb)->protocol;
2016 break;
cd0ff491 2017 case htons(ETH_P_IPV6):
b3821cc5
GFT
2018 ip_proto = ipv6_hdr(skb)->nexthdr;
2019 break;
2020 default:
2021 ip_proto = 0;
2022 break;
2023 }
3b70a6fa 2024#endif
b3821cc5 2025
cd0ff491 2026 switch (ip_proto) {
b3821cc5
GFT
2027 case IPPROTO_TCP:
2028 *flags |= TXFLAG_TCPCS;
2029 break;
2030 case IPPROTO_UDP:
2031 *flags |= TXFLAG_UDPCS;
2032 break;
2033 default:
937ef75a 2034 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT
2035 break;
2036 }
2037 }
2038}
2039
cd0ff491 2040static inline void
3b70a6fa 2041jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2042{
cd0ff491 2043 if (vlan_tx_tag_present(skb)) {
b3821cc5 2044 *flags |= TXFLAG_TAGON;
3b70a6fa 2045 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2046 }
b3821cc5
GFT
2047}
2048
2049static int
3b70a6fa 2050jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2051{
0ede469c 2052 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2053 struct txdesc *txdesc;
b3821cc5 2054 struct jme_buffer_info *txbi;
cd0ff491 2055 u8 flags;
b3821cc5 2056
cd0ff491 2057 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
2058 txbi = txring->bufinf + idx;
2059
2060 txdesc->dw[0] = 0;
2061 txdesc->dw[1] = 0;
2062 txdesc->dw[2] = 0;
2063 txdesc->dw[3] = 0;
2064 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2065 /*
2066 * Set OWN bit at final.
2067 * When kernel transmit faster than NIC.
2068 * And NIC trying to send this descriptor before we tell
2069 * it to start sending this TX queue.
2070 * Other fields are already filled correctly.
2071 */
2072 wmb();
2073 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
2074 /*
2075 * Set checksum flags while not tso
2076 */
2077 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2078 jme_tx_csum(jme, skb, &flags);
b3821cc5 2079 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 2080 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT
2081 txdesc->desc1.flags = flags;
2082 /*
2083 * Set tx buffer info after telling NIC to send
2084 * For better tx_clean timing
2085 */
2086 wmb();
2087 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2088 txbi->skb = skb;
2089 txbi->len = skb->len;
cd0ff491
GFT
2090 txbi->start_xmit = jiffies;
2091 if (!txbi->start_xmit)
8d27293f 2092 txbi->start_xmit = (0UL-1);
d7699f87
GFT
2093
2094 return 0;
2095}
2096
b3821cc5
GFT
2097static void
2098jme_stop_queue_if_full(struct jme_adapter *jme)
2099{
0ede469c 2100 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT
2101 struct jme_buffer_info *txbi = txring->bufinf;
2102 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2103
cd0ff491 2104 txbi += idx;
b3821cc5
GFT
2105
2106 smp_wmb();
cd0ff491 2107 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2108 netif_stop_queue(jme->dev);
937ef75a 2109 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2110 smp_wmb();
cd0ff491
GFT
2111 if (atomic_read(&txring->nr_free)
2112 >= (jme->tx_wake_threshold)) {
b3821cc5 2113 netif_wake_queue(jme->dev);
937ef75a 2114 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT
2115 }
2116 }
2117
cd0ff491 2118 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
2119 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2120 txbi->skb)) {
2121 netif_stop_queue(jme->dev);
937ef75a 2122 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2123 }
b3821cc5
GFT
2124}
2125
3bf61c55
GFT
2126/*
2127 * This function is already protected by netif_tx_lock()
2128 */
cd0ff491 2129
7ca9ebee 2130#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 2131static int
7ca9ebee
GFT
2132#else
2133static netdev_tx_t
2134#endif
3bf61c55 2135jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2136{
cd0ff491 2137 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2138 int idx;
d7699f87 2139
cd0ff491 2140 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
2141 ++(NET_STAT(jme).tx_dropped);
2142 return NETDEV_TX_OK;
2143 }
2144
2145 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2146
cd0ff491 2147 if (unlikely(idx < 0)) {
b3821cc5 2148 netif_stop_queue(netdev);
937ef75a
JP
2149 netif_err(jme, tx_err, jme->dev,
2150 "BUG! Tx ring full when queue awake!\n");
d7699f87 2151
cd0ff491 2152 return NETDEV_TX_BUSY;
b3821cc5
GFT
2153 }
2154
3b70a6fa 2155 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2156
4330c2f2
GFT
2157 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2158 TXCS_SELECT_QUEUE0 |
2159 TXCS_QUEUE0S |
2160 TXCS_ENABLE);
0ede469c 2161#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2162 netdev->trans_start = jiffies;
0ede469c 2163#endif
d7699f87 2164
937ef75a
JP
2165 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2166 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT
2167 jme_stop_queue_if_full(jme);
2168
cd0ff491 2169 return NETDEV_TX_OK;
d7699f87
GFT
2170}
2171
3bf61c55
GFT
2172static int
2173jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2174{
cd0ff491 2175 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2176 struct sockaddr *addr = p;
cd0ff491 2177 u32 val;
d7699f87 2178
cd0ff491 2179 if (netif_running(netdev))
d7699f87
GFT
2180 return -EBUSY;
2181
cd0ff491 2182 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT
2183 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2184
186fc259
GFT
2185 val = (addr->sa_data[3] & 0xff) << 24 |
2186 (addr->sa_data[2] & 0xff) << 16 |
2187 (addr->sa_data[1] & 0xff) << 8 |
2188 (addr->sa_data[0] & 0xff);
4330c2f2 2189 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
2190 val = (addr->sa_data[5] & 0xff) << 8 |
2191 (addr->sa_data[4] & 0xff);
4330c2f2 2192 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 2193 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
2194
2195 return 0;
2196}
2197
3bf61c55
GFT
2198static void
2199jme_set_multi(struct net_device *netdev)
d7699f87 2200{
3bf61c55 2201 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2202 u32 mc_hash[2] = {};
7ca9ebee 2203#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2204 int i;
7ca9ebee 2205#endif
d7699f87 2206
cd0ff491 2207 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
2208
2209 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2210
cd0ff491 2211 if (netdev->flags & IFF_PROMISC) {
8c198884 2212 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2213 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2214 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2215 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2216#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2217 struct dev_mc_list *mclist;
8e14c278
JP
2218#else
2219 struct netdev_hw_addr *ha;
2220#endif
3bf61c55 2221 int bit_nr;
d7699f87 2222
8c198884 2223 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2224#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT
2225 for (i = 0, mclist = netdev->mc_list;
2226 mclist && i < netdev->mc_count;
2227 ++i, mclist = mclist->next) {
8e14c278 2228#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2229 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP
2230#else
2231 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2232#endif
8e14c278 2233#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2234 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP
2235#else
2236 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2237#endif
cd0ff491
GFT
2238 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2239 }
d7699f87 2240
4330c2f2
GFT
2241 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2242 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2243 }
2244
d7699f87 2245 wmb();
8c198884
GFT
2246 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2247
cd0ff491 2248 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2249}
2250
3bf61c55 2251static int
8c198884 2252jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2253{
cd0ff491 2254 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2255
cd0ff491 2256 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2257 return 0;
2258
cd0ff491
GFT
2259 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2260 ((new_mtu) < IPV6_MIN_MTU))
2261 return -EINVAL;
79ce639c 2262
cd0ff491 2263 if (new_mtu > 4000) {
79ce639c
GFT
2264 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2265 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2266 jme_restart_rx_engine(jme);
cd0ff491 2267 } else {
79ce639c
GFT
2268 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2269 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2270 jme_restart_rx_engine(jme);
2271 }
2272
cd0ff491 2273 if (new_mtu > 1900) {
1a0b42f4
MM
2274 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2275 NETIF_F_TSO | NETIF_F_TSO6);
cd0ff491
GFT
2276 } else {
2277 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
1a0b42f4 2278 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491 2279 if (test_bit(JME_FLAG_TSO, &jme->flags))
1a0b42f4 2280 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT
2281 }
2282
cd0ff491
GFT
2283 netdev->mtu = new_mtu;
2284 jme_reset_link(jme);
79ce639c
GFT
2285
2286 return 0;
d7699f87
GFT
2287}
2288
3bf61c55 2289static void
8c198884
GFT
2290jme_tx_timeout(struct net_device *netdev)
2291{
cd0ff491 2292 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2293
cdcdc9eb
GFT
2294 jme->phylink = 0;
2295 jme_reset_phy_processor(jme);
cd0ff491 2296 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2297 jme_set_settings(netdev, &jme->old_ecmd);
2298
8c198884 2299 /*
cdcdc9eb 2300 * Force to Reset the link again
8c198884 2301 */
29bdd921 2302 jme_reset_link(jme);
8c198884
GFT
2303}
2304
1e5ebebc
GFT
2305static inline void jme_pause_rx(struct jme_adapter *jme)
2306{
2307 atomic_dec(&jme->link_changing);
2308
2309 jme_set_rx_pcc(jme, PCC_OFF);
2310 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2311 JME_NAPI_DISABLE(jme);
2312 } else {
2313 tasklet_disable(&jme->rxclean_task);
2314 tasklet_disable(&jme->rxempty_task);
2315 }
2316}
2317
2318static inline void jme_resume_rx(struct jme_adapter *jme)
2319{
2320 struct dynpcc_info *dpi = &(jme->dpi);
2321
2322 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2323 JME_NAPI_ENABLE(jme);
2324 } else {
2325 tasklet_hi_enable(&jme->rxclean_task);
2326 tasklet_hi_enable(&jme->rxempty_task);
2327 }
2328 dpi->cur = PCC_P1;
2329 dpi->attempt = PCC_P1;
2330 dpi->cnt = 0;
2331 jme_set_rx_pcc(jme, PCC_P1);
2332
2333 atomic_inc(&jme->link_changing);
2334}
2335
8c198884 2336static void
42b1055e
GFT
2337jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2338{
2339 struct jme_adapter *jme = netdev_priv(netdev);
2340
1e5ebebc 2341 jme_pause_rx(jme);
42b1055e 2342 jme->vlgrp = grp;
1e5ebebc 2343 jme_resume_rx(jme);
42b1055e
GFT
2344}
2345
7ca9ebee
GFT
2346#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2347static void
2348jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2349{
2350 struct jme_adapter *jme = netdev_priv(netdev);
2351
7ca9ebee 2352 if(jme->vlgrp) {
1e5ebebc 2353 jme_pause_rx(jme);
7ca9ebee
GFT
2354#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2355 jme->vlgrp->vlan_devices[vid] = NULL;
2356#else
2357 vlan_group_set_device(jme->vlgrp, vid, NULL);
2358#endif
1e5ebebc 2359 jme_resume_rx(jme);
7ca9ebee 2360 }
7ca9ebee
GFT
2361}
2362#endif
2363
42b1055e 2364static void
3bf61c55
GFT
2365jme_get_drvinfo(struct net_device *netdev,
2366 struct ethtool_drvinfo *info)
d7699f87 2367{
cd0ff491 2368 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2369
cd0ff491
GFT
2370 strcpy(info->driver, DRV_NAME);
2371 strcpy(info->version, DRV_VERSION);
2372 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2373}
2374
3bf61c55 2375static int
8c198884
GFT
2376jme_get_regs_len(struct net_device *netdev)
2377{
cd0ff491 2378 return JME_REG_LEN;
8c198884
GFT
2379}
2380
2381static void
cd0ff491 2382mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2383{
2384 int i;
2385
cd0ff491 2386 for (i = 0 ; i < len ; i += 4)
79ce639c 2387 p[i >> 2] = jread32(jme, reg + i);
186fc259 2388}
8c198884 2389
186fc259 2390static void
cd0ff491 2391mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2392{
2393 int i;
cd0ff491 2394 u16 *p16 = (u16 *)p;
186fc259 2395
cd0ff491 2396 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2397 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2398}
2399
2400static void
2401jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2402{
cd0ff491
GFT
2403 struct jme_adapter *jme = netdev_priv(netdev);
2404 u32 *p32 = (u32 *)p;
8c198884 2405
186fc259 2406 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2407
2408 regs->version = 1;
2409 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2410
2411 p32 += 0x100 >> 2;
2412 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2413
2414 p32 += 0x100 >> 2;
2415 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2416
2417 p32 += 0x100 >> 2;
2418 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2419
186fc259
GFT
2420 p32 += 0x100 >> 2;
2421 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2422}
2423
2424static int
2425jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2426{
2427 struct jme_adapter *jme = netdev_priv(netdev);
2428
8c198884
GFT
2429 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2430 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2431
cd0ff491 2432 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2433 ecmd->use_adaptive_rx_coalesce = false;
2434 ecmd->rx_coalesce_usecs = 0;
2435 ecmd->rx_max_coalesced_frames = 0;
2436 return 0;
2437 }
2438
2439 ecmd->use_adaptive_rx_coalesce = true;
2440
cd0ff491 2441 switch (jme->dpi.cur) {
8c198884
GFT
2442 case PCC_P1:
2443 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2444 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2445 break;
2446 case PCC_P2:
2447 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2448 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2449 break;
2450 case PCC_P3:
2451 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2452 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2453 break;
2454 default:
2455 break;
2456 }
2457
2458 return 0;
2459}
2460
192570e0
GFT
2461static int
2462jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2463{
2464 struct jme_adapter *jme = netdev_priv(netdev);
2465 struct dynpcc_info *dpi = &(jme->dpi);
2466
cd0ff491 2467 if (netif_running(netdev))
cdcdc9eb
GFT
2468 return -EBUSY;
2469
7ca9ebee
GFT
2470 if (ecmd->use_adaptive_rx_coalesce &&
2471 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2472 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2473 jme->jme_rx = netif_rx;
2474 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2475 dpi->cur = PCC_P1;
2476 dpi->attempt = PCC_P1;
2477 dpi->cnt = 0;
2478 jme_set_rx_pcc(jme, PCC_P1);
2479 jme_interrupt_mode(jme);
7ca9ebee
GFT
2480 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2481 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2482 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2483 jme->jme_rx = netif_receive_skb;
2484 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2485 jme_interrupt_mode(jme);
2486 }
2487
2488 return 0;
2489}
2490
8c198884
GFT
2491static void
2492jme_get_pauseparam(struct net_device *netdev,
2493 struct ethtool_pauseparam *ecmd)
2494{
2495 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2496 u32 val;
8c198884
GFT
2497
2498 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2499 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2500
cd0ff491
GFT
2501 spin_lock_bh(&jme->phy_lock);
2502 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2503 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2504
2505 ecmd->autoneg =
2506 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2507}
2508
2509static int
2510jme_set_pauseparam(struct net_device *netdev,
2511 struct ethtool_pauseparam *ecmd)
2512{
2513 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2514 u32 val;
8c198884 2515
cd0ff491 2516 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2517 (ecmd->tx_pause != 0)) {
2518
cd0ff491 2519 if (ecmd->tx_pause)
8c198884
GFT
2520 jme->reg_txpfc |= TXPFC_PF_EN;
2521 else
2522 jme->reg_txpfc &= ~TXPFC_PF_EN;
2523
2524 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2525 }
2526
cd0ff491
GFT
2527 spin_lock_bh(&jme->rxmcs_lock);
2528 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2529 (ecmd->rx_pause != 0)) {
2530
cd0ff491 2531 if (ecmd->rx_pause)
8c198884
GFT
2532 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2533 else
2534 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2535
2536 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2537 }
cd0ff491 2538 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2539
cd0ff491
GFT
2540 spin_lock_bh(&jme->phy_lock);
2541 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2542 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2543 (ecmd->autoneg != 0)) {
2544
cd0ff491 2545 if (ecmd->autoneg)
8c198884
GFT
2546 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2547 else
2548 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2549
b3821cc5
GFT
2550 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2551 MII_ADVERTISE, val);
8c198884 2552 }
cd0ff491 2553 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2554
2555 return 0;
2556}
2557
29bdd921
GFT
2558static void
2559jme_get_wol(struct net_device *netdev,
2560 struct ethtool_wolinfo *wol)
2561{
2562 struct jme_adapter *jme = netdev_priv(netdev);
2563
2564 wol->supported = WAKE_MAGIC | WAKE_PHY;
2565
2566 wol->wolopts = 0;
2567
cd0ff491 2568 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2569 wol->wolopts |= WAKE_PHY;
2570
cd0ff491 2571 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2572 wol->wolopts |= WAKE_MAGIC;
2573
2574}
2575
2576static int
2577jme_set_wol(struct net_device *netdev,
2578 struct ethtool_wolinfo *wol)
2579{
2580 struct jme_adapter *jme = netdev_priv(netdev);
2581
cd0ff491 2582 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2583 WAKE_UCAST |
2584 WAKE_MCAST |
2585 WAKE_BCAST |
2586 WAKE_ARP))
2587 return -EOPNOTSUPP;
2588
2589 jme->reg_pmcs = 0;
2590
cd0ff491 2591 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2592 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2593
cd0ff491 2594 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2595 jme->reg_pmcs |= PMCS_MFEN;
2596
cd0ff491 2597 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2598
29bdd921
GFT
2599 return 0;
2600}
b3821cc5 2601
8c198884 2602static int
3bf61c55
GFT
2603jme_get_settings(struct net_device *netdev,
2604 struct ethtool_cmd *ecmd)
d7699f87
GFT
2605{
2606 struct jme_adapter *jme = netdev_priv(netdev);
2607 int rc;
8c198884 2608
cd0ff491 2609 spin_lock_bh(&jme->phy_lock);
d7699f87 2610 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2611 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2612 return rc;
2613}
2614
3bf61c55
GFT
2615static int
2616jme_set_settings(struct net_device *netdev,
2617 struct ethtool_cmd *ecmd)
d7699f87
GFT
2618{
2619 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2620 int rc, fdc = 0;
fcf45b4c 2621
cd0ff491 2622 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2623 return -EINVAL;
2624
e6b41b51
GFT
2625 /*
2626 * Check If user changed duplex only while force_media.
2627 * Hardware would not generate link change interrupt.
2628 */
cd0ff491 2629 if (jme->mii_if.force_media &&
79ce639c
GFT
2630 ecmd->autoneg != AUTONEG_ENABLE &&
2631 (jme->mii_if.full_duplex != ecmd->duplex))
2632 fdc = 1;
2633
cd0ff491 2634 spin_lock_bh(&jme->phy_lock);
d7699f87 2635 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2636 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2637
cd0ff491 2638 if (!rc) {
e6b41b51
GFT
2639 if (fdc)
2640 jme_reset_link(jme);
29bdd921 2641 jme->old_ecmd = *ecmd;
aa1e7189
GFT
2642 set_bit(JME_FLAG_SSET, &jme->flags);
2643 }
2644
2645 return rc;
2646}
2647
2648static int
2649jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2650{
2651 int rc;
2652 struct jme_adapter *jme = netdev_priv(netdev);
2653 struct mii_ioctl_data *mii_data = if_mii(rq);
2654 unsigned int duplex_chg;
2655
2656 if (cmd == SIOCSMIIREG) {
2657 u16 val = mii_data->val_in;
2658 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2659 (val & BMCR_SPEED1000))
2660 return -EINVAL;
2661 }
2662
2663 spin_lock_bh(&jme->phy_lock);
2664 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2665 spin_unlock_bh(&jme->phy_lock);
2666
2667 if (!rc && (cmd == SIOCSMIIREG)) {
2668 if (duplex_chg)
2669 jme_reset_link(jme);
2670 jme_get_settings(netdev, &jme->old_ecmd);
2671 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2672 }
2673
d7699f87
GFT
2674 return rc;
2675}
2676
cd0ff491 2677static u32
3bf61c55
GFT
2678jme_get_link(struct net_device *netdev)
2679{
d7699f87
GFT
2680 struct jme_adapter *jme = netdev_priv(netdev);
2681 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2682}
2683
8c198884 2684static u32
cd0ff491
GFT
2685jme_get_msglevel(struct net_device *netdev)
2686{
2687 struct jme_adapter *jme = netdev_priv(netdev);
2688 return jme->msg_enable;
2689}
2690
2691static void
2692jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2693{
cd0ff491
GFT
2694 struct jme_adapter *jme = netdev_priv(netdev);
2695 jme->msg_enable = value;
2696}
8c198884 2697
cd0ff491
GFT
2698static u32
2699jme_get_rx_csum(struct net_device *netdev)
2700{
2701 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2702 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2703}
2704
2705static int
2706jme_set_rx_csum(struct net_device *netdev, u32 on)
2707{
cd0ff491 2708 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2709
cd0ff491
GFT
2710 spin_lock_bh(&jme->rxmcs_lock);
2711 if (on)
8c198884
GFT
2712 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2713 else
2714 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2715 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2716 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2717
2718 return 0;
2719}
2720
2721static int
2722jme_set_tx_csum(struct net_device *netdev, u32 on)
2723{
cd0ff491 2724 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2725
cd0ff491
GFT
2726 if (on) {
2727 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2728 if (netdev->mtu <= 1900)
1a0b42f4
MM
2729 netdev->features |=
2730 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491
GFT
2731 } else {
2732 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
1a0b42f4
MM
2733 netdev->features &=
2734 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b3821cc5 2735 }
8c198884
GFT
2736
2737 return 0;
2738}
2739
2740static int
b3821cc5
GFT
2741jme_set_tso(struct net_device *netdev, u32 on)
2742{
cd0ff491 2743 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2744
cd0ff491
GFT
2745 if (on) {
2746 set_bit(JME_FLAG_TSO, &jme->flags);
2747 if (netdev->mtu <= 1900)
1a0b42f4 2748 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT
2749 } else {
2750 clear_bit(JME_FLAG_TSO, &jme->flags);
1a0b42f4 2751 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT
2752 }
2753
cd0ff491 2754 return 0;
b3821cc5
GFT
2755}
2756
2757static int
8c198884
GFT
2758jme_nway_reset(struct net_device *netdev)
2759{
cd0ff491 2760 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2761 jme_restart_an(jme);
2762 return 0;
2763}
2764
cd0ff491 2765static u8
186fc259
GFT
2766jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2767{
cd0ff491 2768 u32 val;
186fc259
GFT
2769 int to;
2770
2771 val = jread32(jme, JME_SMBCSR);
2772 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2773 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2774 msleep(1);
2775 val = jread32(jme, JME_SMBCSR);
2776 }
cd0ff491 2777 if (!to) {
937ef75a 2778 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2779 return 0xFF;
2780 }
2781
2782 jwrite32(jme, JME_SMBINTF,
2783 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2784 SMBINTF_HWRWN_READ |
2785 SMBINTF_HWCMD);
2786
2787 val = jread32(jme, JME_SMBINTF);
2788 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2789 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2790 msleep(1);
2791 val = jread32(jme, JME_SMBINTF);
2792 }
cd0ff491 2793 if (!to) {
937ef75a 2794 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2795 return 0xFF;
2796 }
2797
2798 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2799}
2800
2801static void
cd0ff491 2802jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2803{
cd0ff491 2804 u32 val;
186fc259
GFT
2805 int to;
2806
2807 val = jread32(jme, JME_SMBCSR);
2808 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2809 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2810 msleep(1);
2811 val = jread32(jme, JME_SMBCSR);
2812 }
cd0ff491 2813 if (!to) {
937ef75a 2814 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2815 return;
2816 }
2817
2818 jwrite32(jme, JME_SMBINTF,
2819 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2820 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2821 SMBINTF_HWRWN_WRITE |
2822 SMBINTF_HWCMD);
2823
2824 val = jread32(jme, JME_SMBINTF);
2825 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2826 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2827 msleep(1);
2828 val = jread32(jme, JME_SMBINTF);
2829 }
cd0ff491 2830 if (!to) {
937ef75a 2831 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2832 return;
2833 }
2834
2835 mdelay(2);
2836}
2837
2838static int
2839jme_get_eeprom_len(struct net_device *netdev)
2840{
cd0ff491
GFT
2841 struct jme_adapter *jme = netdev_priv(netdev);
2842 u32 val;
186fc259 2843 val = jread32(jme, JME_SMBCSR);
cd0ff491 2844 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2845}
2846
2847static int
2848jme_get_eeprom(struct net_device *netdev,
2849 struct ethtool_eeprom *eeprom, u8 *data)
2850{
cd0ff491 2851 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2852 int i, offset = eeprom->offset, len = eeprom->len;
2853
2854 /*
8d27293f 2855 * ethtool will check the boundary for us
186fc259
GFT
2856 */
2857 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2858 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2859 data[i] = jme_smb_read(jme, i + offset);
2860
2861 return 0;
2862}
2863
2864static int
2865jme_set_eeprom(struct net_device *netdev,
2866 struct ethtool_eeprom *eeprom, u8 *data)
2867{
cd0ff491 2868 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2869 int i, offset = eeprom->offset, len = eeprom->len;
2870
2871 if (eeprom->magic != JME_EEPROM_MAGIC)
2872 return -EINVAL;
2873
2874 /*
8d27293f 2875 * ethtool will check the boundary for us
186fc259 2876 */
cd0ff491 2877 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2878 jme_smb_write(jme, i + offset, data[i]);
2879
2880 return 0;
2881}
2882
3b70a6fa
GFT
2883#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2884static struct ethtool_ops jme_ethtool_ops = {
2885#else
d7699f87 2886static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 2887#endif
cd0ff491 2888 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2889 .get_regs_len = jme_get_regs_len,
2890 .get_regs = jme_get_regs,
2891 .get_coalesce = jme_get_coalesce,
192570e0 2892 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2893 .get_pauseparam = jme_get_pauseparam,
2894 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2895 .get_wol = jme_get_wol,
2896 .set_wol = jme_set_wol,
d7699f87
GFT
2897 .get_settings = jme_get_settings,
2898 .set_settings = jme_set_settings,
2899 .get_link = jme_get_link,
cd0ff491
GFT
2900 .get_msglevel = jme_get_msglevel,
2901 .set_msglevel = jme_set_msglevel,
8c198884
GFT
2902 .get_rx_csum = jme_get_rx_csum,
2903 .set_rx_csum = jme_set_rx_csum,
2904 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2905 .set_tso = jme_set_tso,
2906 .set_sg = ethtool_op_set_sg,
8c198884 2907 .nway_reset = jme_nway_reset,
186fc259
GFT
2908 .get_eeprom_len = jme_get_eeprom_len,
2909 .get_eeprom = jme_get_eeprom,
2910 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2911};
2912
3bf61c55
GFT
2913static int
2914jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2915{
3b70a6fa 2916 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT
2917#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2918 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2919#else
2920 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2921#endif
2922 )
2923#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2924 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2925#else
cd0ff491 2926 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 2927#endif
3bf61c55
GFT
2928 return 1;
2929
3b70a6fa 2930 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT
2931#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2932 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2933#else
2934 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2935#endif
2936 )
2937#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2938 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2939#else
cd0ff491 2940 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 2941#endif
8c198884
GFT
2942 return 1;
2943
0ede469c
GFT
2944#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2945 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2946 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2947#else
cd0ff491
GFT
2948 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2949 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 2950#endif
3bf61c55
GFT
2951 return 0;
2952
2953 return -1;
2954}
2955
cd0ff491 2956static inline void
cdcdc9eb
GFT
2957jme_phy_init(struct jme_adapter *jme)
2958{
cd0ff491 2959 u16 reg26;
cdcdc9eb
GFT
2960
2961 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2962 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2963}
2964
cd0ff491 2965static inline void
cdcdc9eb 2966jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2967{
cd0ff491 2968 u32 chipmode;
cdcdc9eb
GFT
2969
2970 chipmode = jread32(jme, JME_CHIPMODE);
2971
2972 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 2973 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
98ef18f1
GFT
2974 jme->chip_main_rev = jme->chiprev & 0xF;
2975 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT
2976}
2977
3b70a6fa
GFT
2978#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2979static const struct net_device_ops jme_netdev_ops = {
2980 .ndo_open = jme_open,
2981 .ndo_stop = jme_close,
2982 .ndo_validate_addr = eth_validate_addr,
aa1e7189 2983 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT
2984 .ndo_start_xmit = jme_start_xmit,
2985 .ndo_set_mac_address = jme_set_macaddr,
2986 .ndo_set_multicast_list = jme_set_multi,
2987 .ndo_change_mtu = jme_change_mtu,
2988 .ndo_tx_timeout = jme_tx_timeout,
2989 .ndo_vlan_rx_register = jme_vlan_rx_register,
2990};
2991#endif
2992
3bf61c55
GFT
2993static int __devinit
2994jme_init_one(struct pci_dev *pdev,
2995 const struct pci_device_id *ent)
2996{
cdcdc9eb 2997 int rc = 0, using_dac, i;
d7699f87
GFT
2998 struct net_device *netdev;
2999 struct jme_adapter *jme;
cd0ff491
GFT
3000 u16 bmcr, bmsr;
3001 u32 apmc;
d7699f87
GFT
3002
3003 /*
3004 * set up PCI device basics
3005 */
4330c2f2 3006 rc = pci_enable_device(pdev);
cd0ff491 3007 if (rc) {
937ef75a 3008 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT
3009 goto err_out;
3010 }
d7699f87 3011
3bf61c55 3012 using_dac = jme_pci_dma64(pdev);
cd0ff491 3013 if (using_dac < 0) {
937ef75a 3014 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT
3015 rc = -EIO;
3016 goto err_out_disable_pdev;
3017 }
3018
cd0ff491 3019 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 3020 pr_err("No PCI resource region found\n");
4330c2f2
GFT
3021 rc = -ENOMEM;
3022 goto err_out_disable_pdev;
3023 }
d7699f87 3024
4330c2f2 3025 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 3026 if (rc) {
937ef75a 3027 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT
3028 goto err_out_disable_pdev;
3029 }
d7699f87
GFT
3030
3031 pci_set_master(pdev);
3032
3033 /*
3034 * alloc and init net device
3035 */
3bf61c55 3036 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 3037 if (!netdev) {
937ef75a 3038 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT
3039 rc = -ENOMEM;
3040 goto err_out_release_regions;
d7699f87 3041 }
3b70a6fa
GFT
3042#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3043 netdev->netdev_ops = &jme_netdev_ops;
3044#else
d7699f87
GFT
3045 netdev->open = jme_open;
3046 netdev->stop = jme_close;
aa1e7189 3047 netdev->do_ioctl = jme_ioctl;
d7699f87 3048 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT
3049 netdev->set_mac_address = jme_set_macaddr;
3050 netdev->set_multicast_list = jme_set_multi;
3051 netdev->change_mtu = jme_change_mtu;
8c198884 3052 netdev->tx_timeout = jme_tx_timeout;
42b1055e 3053 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT
3054#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3055 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3056#endif
3bf61c55 3057 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT
3058#endif
3059 netdev->ethtool_ops = &jme_ethtool_ops;
3060 netdev->watchdog_timeo = TX_TIMEOUT;
1a0b42f4
MM
3061 netdev->features = NETIF_F_IP_CSUM |
3062 NETIF_F_IPV6_CSUM |
b3821cc5
GFT
3063 NETIF_F_SG |
3064 NETIF_F_TSO |
3065 NETIF_F_TSO6 |
42b1055e
GFT
3066 NETIF_F_HW_VLAN_TX |
3067 NETIF_F_HW_VLAN_RX;
cd0ff491 3068 if (using_dac)
8c198884 3069 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
3070
3071 SET_NETDEV_DEV(netdev, &pdev->dev);
3072 pci_set_drvdata(pdev, netdev);
3073
3074 /*
3075 * init adapter info
3076 */
3077 jme = netdev_priv(netdev);
3078 jme->pdev = pdev;
3079 jme->dev = netdev;
cdcdc9eb
GFT
3080 jme->jme_rx = netif_rx;
3081 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 3082 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 3083 jme->phylink = 0;
b3821cc5 3084 jme->tx_ring_size = 1 << 10;
0ede469c 3085 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT
3086 jme->tx_wake_threshold = 1 << 9;
3087 jme->rx_ring_size = 1 << 9;
3088 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 3089 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
3090 jme->regs = ioremap(pci_resource_start(pdev, 0),
3091 pci_resource_len(pdev, 0));
4330c2f2 3092 if (!(jme->regs)) {
937ef75a 3093 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT
3094 rc = -ENOMEM;
3095 goto err_out_free_netdev;
3096 }
4330c2f2 3097
cd0ff491
GFT
3098 if (no_pseudohp) {
3099 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3100 jwrite32(jme, JME_APMC, apmc);
3101 } else if (force_pseudohp) {
3102 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3103 jwrite32(jme, JME_APMC, apmc);
3104 }
3105
cdcdc9eb 3106 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 3107
d7699f87 3108 spin_lock_init(&jme->phy_lock);
fcf45b4c 3109 spin_lock_init(&jme->macaddr_lock);
8c198884 3110 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 3111
fcf45b4c
GFT
3112 atomic_set(&jme->link_changing, 1);
3113 atomic_set(&jme->rx_cleaning, 1);
3114 atomic_set(&jme->tx_cleaning, 1);
192570e0 3115 atomic_set(&jme->rx_empty, 1);
fcf45b4c 3116
79ce639c 3117 tasklet_init(&jme->pcc_task,
7ca9ebee 3118 jme_pcc_tasklet,
79ce639c 3119 (unsigned long) jme);
4330c2f2 3120 tasklet_init(&jme->linkch_task,
7ca9ebee 3121 jme_link_change_tasklet,
4330c2f2
GFT
3122 (unsigned long) jme);
3123 tasklet_init(&jme->txclean_task,
7ca9ebee 3124 jme_tx_clean_tasklet,
4330c2f2
GFT
3125 (unsigned long) jme);
3126 tasklet_init(&jme->rxclean_task,
7ca9ebee 3127 jme_rx_clean_tasklet,
4330c2f2 3128 (unsigned long) jme);
fcf45b4c 3129 tasklet_init(&jme->rxempty_task,
7ca9ebee 3130 jme_rx_empty_tasklet,
fcf45b4c 3131 (unsigned long) jme);
0ede469c 3132 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT
3133 tasklet_disable_nosync(&jme->txclean_task);
3134 tasklet_disable_nosync(&jme->rxclean_task);
3135 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
3136 jme->dpi.cur = PCC_P1;
3137
cd0ff491 3138 jme->reg_ghc = 0;
79ce639c 3139 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
3140 jme->reg_rxmcs = RXMCS_DEFAULT;
3141 jme->reg_txpfc = 0;
47220951 3142 jme->reg_pmcs = PMCS_MFEN;
dc4185bd 3143 jme->reg_gpreg1 = GPREG1_DEFAULT;
cd0ff491
GFT
3144 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3145 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 3146
d7699f87 3147 /*
fcf45b4c
GFT
3148 * Get Max Read Req Size from PCI Config Space
3149 */
cd0ff491
GFT
3150 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3151 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3152 switch (jme->mrrs) {
3153 case MRRS_128B:
3154 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3155 break;
3156 case MRRS_256B:
3157 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3158 break;
3159 default:
3160 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3161 break;
cd54cf32 3162 }
fcf45b4c 3163
fcf45b4c 3164 /*
cdcdc9eb 3165 * Must check before reset_mac_processor
d7699f87 3166 */
cdcdc9eb
GFT
3167 jme_check_hw_ver(jme);
3168 jme->mii_if.dev = netdev;
cd0ff491 3169 if (jme->fpgaver) {
cdcdc9eb 3170 jme->mii_if.phy_id = 0;
cd0ff491 3171 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
3172 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3173 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3174 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
3175 jme->mii_if.phy_id = i;
3176 break;
3177 }
3178 }
3179
cd0ff491 3180 if (!jme->mii_if.phy_id) {
cdcdc9eb 3181 rc = -EIO;
937ef75a
JP
3182 pr_err("Can not find phy_id\n");
3183 goto err_out_unmap;
cdcdc9eb
GFT
3184 }
3185
3186 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3187 } else {
cdcdc9eb
GFT
3188 jme->mii_if.phy_id = 1;
3189 }
cd0ff491 3190 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
3191 jme->mii_if.supports_gmii = true;
3192 else
3193 jme->mii_if.supports_gmii = false;
aa1e7189
GFT
3194 jme->mii_if.phy_id_mask = 0x1F;
3195 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT
3196 jme->mii_if.mdio_read = jme_mdio_read;
3197 jme->mii_if.mdio_write = jme_mdio_write;
3198
d7699f87 3199 jme_clear_pm(jme);
55d19799 3200 jme_set_phyfifo_5level(jme);
98ef18f1 3201 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
cd0ff491 3202 if (!jme->fpgaver)
cdcdc9eb 3203 jme_phy_init(jme);
42b1055e 3204 jme_phy_off(jme);
cdcdc9eb
GFT
3205
3206 /*
3207 * Reset MAC processor and reload EEPROM for MAC Address
3208 */
d7699f87 3209 jme_reset_mac_processor(jme);
4330c2f2 3210 rc = jme_reload_eeprom(jme);
cd0ff491 3211 if (rc) {
937ef75a 3212 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3213 goto err_out_unmap;
4330c2f2 3214 }
d7699f87
GFT
3215 jme_load_macaddr(netdev);
3216
d7699f87
GFT
3217 /*
3218 * Tell stack that we are not ready to work until open()
3219 */
3220 netif_carrier_off(netdev);
d7699f87 3221
4330c2f2 3222 rc = register_netdev(netdev);
cd0ff491 3223 if (rc) {
937ef75a 3224 pr_err("Cannot register net device\n");
0ede469c 3225 goto err_out_unmap;
4330c2f2 3226 }
d7699f87 3227
98ef18f1 3228 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
937ef75a 3229 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT
3230 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3231 "JMC250 Gigabit Ethernet" :
3232 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3233 "JMC260 Fast Ethernet" : "Unknown",
3234 (jme->fpgaver != 0) ? " (FPGA)" : "",
3235 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
98ef18f1 3236 jme->pcirev,
937ef75a
JP
3237 netdev->dev_addr[0],
3238 netdev->dev_addr[1],
3239 netdev->dev_addr[2],
3240 netdev->dev_addr[3],
3241 netdev->dev_addr[4],
3242 netdev->dev_addr[5]);
d7699f87
GFT
3243
3244 return 0;
3245
3246err_out_unmap:
3247 iounmap(jme->regs);
3248err_out_free_netdev:
3249 pci_set_drvdata(pdev, NULL);
3250 free_netdev(netdev);
4330c2f2
GFT
3251err_out_release_regions:
3252 pci_release_regions(pdev);
d7699f87 3253err_out_disable_pdev:
cd0ff491 3254 pci_disable_device(pdev);
d7699f87 3255err_out:
4330c2f2 3256 return rc;
d7699f87
GFT
3257}
3258
3bf61c55
GFT
3259static void __devexit
3260jme_remove_one(struct pci_dev *pdev)
3261{
d7699f87
GFT
3262 struct net_device *netdev = pci_get_drvdata(pdev);
3263 struct jme_adapter *jme = netdev_priv(netdev);
3264
3265 unregister_netdev(netdev);
3266 iounmap(jme->regs);
3267 pci_set_drvdata(pdev, NULL);
3268 free_netdev(netdev);
3269 pci_release_regions(pdev);
3270 pci_disable_device(pdev);
3271
3272}
3273
a82e368c
GFT
3274static void
3275jme_shutdown(struct pci_dev *pdev)
3276{
3277 struct net_device *netdev = pci_get_drvdata(pdev);
3278 struct jme_adapter *jme = netdev_priv(netdev);
3279
3280 jme_powersave_phy(jme);
3281#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3282 pci_enable_wake(pdev, PCI_D3hot, true);
3283#else
3284 pci_pme_active(pdev, true);
3285#endif
3286}
3287
7ee473a3 3288#ifdef CONFIG_PM
29bdd921
GFT
3289static int
3290jme_suspend(struct pci_dev *pdev, pm_message_t state)
3291{
3292 struct net_device *netdev = pci_get_drvdata(pdev);
3293 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
3294
3295 atomic_dec(&jme->link_changing);
3296
3297 netif_device_detach(netdev);
3298 netif_stop_queue(netdev);
3299 jme_stop_irq(jme);
29bdd921 3300
cd0ff491
GFT
3301 tasklet_disable(&jme->txclean_task);
3302 tasklet_disable(&jme->rxclean_task);
3303 tasklet_disable(&jme->rxempty_task);
3304
cd0ff491
GFT
3305 if (netif_carrier_ok(netdev)) {
3306 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
3307 jme_polling_mode(jme);
3308
29bdd921 3309 jme_stop_pcc_timer(jme);
cd0ff491
GFT
3310 jme_disable_rx_engine(jme);
3311 jme_disable_tx_engine(jme);
29bdd921
GFT
3312 jme_reset_mac_processor(jme);
3313 jme_free_rx_resources(jme);
3314 jme_free_tx_resources(jme);
3315 netif_carrier_off(netdev);
3316 jme->phylink = 0;
3317 }
3318
cd0ff491
GFT
3319 tasklet_enable(&jme->txclean_task);
3320 tasklet_hi_enable(&jme->rxclean_task);
3321 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT
3322
3323 pci_save_state(pdev);
a82e368c
GFT
3324 jme_powersave_phy(jme);
3325 pci_enable_wake(pdev, PCI_D3hot, true);
3326 pci_set_power_state(pdev, PCI_D3hot);
29bdd921
GFT
3327
3328 return 0;
3329}
3330
3331static int
3332jme_resume(struct pci_dev *pdev)
3333{
3334 struct net_device *netdev = pci_get_drvdata(pdev);
3335 struct jme_adapter *jme = netdev_priv(netdev);
3336
3337 jme_clear_pm(jme);
3338 pci_restore_state(pdev);
3339
ed457bcc
GFT
3340 jme_phy_on(jme);
3341 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3342 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 3343 else
29bdd921
GFT
3344 jme_reset_phy_processor(jme);
3345
29bdd921
GFT
3346 jme_start_irq(jme);
3347 netif_device_attach(netdev);
3348
3349 atomic_inc(&jme->link_changing);
3350
3351 jme_reset_link(jme);
3352
3353 return 0;
3354}
7ee473a3 3355#endif
29bdd921 3356
7ca9ebee 3357#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3358static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT
3359#else
3360static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3361#endif
cd0ff491
GFT
3362 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3363 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3364 { }
3365};
3366
3367static struct pci_driver jme_driver = {
cd0ff491
GFT
3368 .name = DRV_NAME,
3369 .id_table = jme_pci_tbl,
3370 .probe = jme_init_one,
3371 .remove = __devexit_p(jme_remove_one),
d7699f87 3372#ifdef CONFIG_PM
cd0ff491
GFT
3373 .suspend = jme_suspend,
3374 .resume = jme_resume,
d7699f87 3375#endif /* CONFIG_PM */
a82e368c 3376 .shutdown = jme_shutdown,
d7699f87
GFT
3377};
3378
3bf61c55
GFT
3379static int __init
3380jme_init_module(void)
d7699f87 3381{
937ef75a 3382 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT
3383 return pci_register_driver(&jme_driver);
3384}
3385
3bf61c55
GFT
3386static void __exit
3387jme_cleanup_module(void)
d7699f87
GFT
3388{
3389 pci_unregister_driver(&jme_driver);
3390}
3391
3392module_init(jme_init_module);
3393module_exit(jme_cleanup_module);
3394
3bf61c55 3395MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3396MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3397MODULE_LICENSE("GPL");
3398MODULE_VERSION(DRV_VERSION);
3399MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3400