drivers/net: avoid some skb->ip_summed initializations
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
3bf61c55
GFT
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
d7699f87
GFT
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
d7699f87
GFT
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/mii.h>
31#include <linux/crc32.h>
4330c2f2 32#include <linux/delay.h>
29bdd921 33#include <linux/spinlock.h>
8c198884
GFT
34#include <linux/in.h>
35#include <linux/ip.h>
79ce639c
GFT
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
38#include <linux/udp.h>
42b1055e 39#include <linux/if_vlan.h>
6d641c63 40#include <linux/slab.h>
94c5ea02 41#include <net/ip6_checksum.h>
d7699f87
GFT
42#include "jme.h"
43
cd0ff491
GFT
44static int force_pseudohp = -1;
45static int no_pseudohp = -1;
46static int no_extplug = -1;
47module_param(force_pseudohp, int, 0);
48MODULE_PARM_DESC(force_pseudohp,
49 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
50module_param(no_pseudohp, int, 0);
51MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
52module_param(no_extplug, int, 0);
53MODULE_PARM_DESC(no_extplug,
54 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 55
3bf61c55
GFT
56static int
57jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
58{
59 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 60 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 61
186fc259 62read_again:
cd0ff491 63 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
64 smi_phy_addr(phy) |
65 smi_reg_addr(reg));
d7699f87
GFT
66
67 wmb();
cd0ff491 68 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 69 udelay(20);
b3821cc5
GFT
70 val = jread32(jme, JME_SMI);
71 if ((val & SMI_OP_REQ) == 0)
3bf61c55 72 break;
cd0ff491 73 }
d7699f87 74
cd0ff491
GFT
75 if (i == 0) {
76 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 77 return 0;
cd0ff491 78 }
d7699f87 79
cd0ff491 80 if (again--)
186fc259
GFT
81 goto read_again;
82
cd0ff491 83 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
84}
85
3bf61c55
GFT
86static void
87jme_mdio_write(struct net_device *netdev,
88 int phy, int reg, int val)
d7699f87
GFT
89{
90 struct jme_adapter *jme = netdev_priv(netdev);
91 int i;
92
3bf61c55
GFT
93 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
94 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
95 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT
96
97 wmb();
cdcdc9eb
GFT
98 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 udelay(20);
8d27293f 100 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
101 break;
102 }
d7699f87 103
3bf61c55 104 if (i == 0)
cd0ff491 105 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT
106}
107
cd0ff491 108static inline void
3bf61c55 109jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 110{
cd0ff491 111 u32 val;
3bf61c55
GFT
112
113 jme_mdio_write(jme->dev,
114 jme->mii_if.phy_id,
8c198884
GFT
115 MII_ADVERTISE, ADVERTISE_ALL |
116 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 117
cd0ff491 118 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_CTRL1000,
122 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 123
fcf45b4c
GFT
124 val = jme_mdio_read(jme->dev,
125 jme->mii_if.phy_id,
126 MII_BMCR);
127
128 jme_mdio_write(jme->dev,
129 jme->mii_if.phy_id,
130 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT
131}
132
b3821cc5
GFT
133static void
134jme_setup_wakeup_frame(struct jme_adapter *jme,
cd0ff491 135 u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
136{
137 int i;
138
139 /*
140 * Setup CRC pattern
141 */
142 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
143 wmb();
144 jwrite32(jme, JME_WFODP, crc);
145 wmb();
146
147 /*
148 * Setup Mask
149 */
cd0ff491 150 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
151 jwrite32(jme, JME_WFOI,
152 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
153 (fnr & WFOI_FRAME_SEL));
154 wmb();
155 jwrite32(jme, JME_WFODP, mask[i]);
156 wmb();
157 }
158}
3bf61c55 159
cd0ff491 160static inline void
3bf61c55
GFT
161jme_reset_mac_processor(struct jme_adapter *jme)
162{
cd0ff491
GFT
163 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
164 u32 crc = 0xCDCDCDCD;
165 u32 gpreg0;
b3821cc5
GFT
166 int i;
167
3bf61c55 168 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 169 udelay(2);
3bf61c55 170 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT
171
172 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
173 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
174 jwrite32(jme, JME_RXQDC, 0x00000000);
175 jwrite32(jme, JME_RXNDA, 0x00000000);
176 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
177 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
178 jwrite32(jme, JME_TXQDC, 0x00000000);
179 jwrite32(jme, JME_TXNDA, 0x00000000);
180
4330c2f2
GFT
181 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
182 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 183 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 184 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 185 if (jme->fpgaver)
cdcdc9eb
GFT
186 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
187 else
188 gpreg0 = GPREG0_DEFAULT;
189 jwrite32(jme, JME_GPREG0, gpreg0);
9b9d55de 190 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT
191}
192
cd0ff491
GFT
193static inline void
194jme_reset_ghc_speed(struct jme_adapter *jme)
195{
196 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
197 jwrite32(jme, JME_GHC, jme->reg_ghc);
198}
199
200static inline void
3bf61c55 201jme_clear_pm(struct jme_adapter *jme)
d7699f87 202{
29bdd921 203 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 204 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 205 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT
206}
207
3bf61c55
GFT
208static int
209jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 210{
cd0ff491 211 u32 val;
d7699f87
GFT
212 int i;
213
214 val = jread32(jme, JME_SMBCSR);
215
cd0ff491 216 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
217 val |= SMBCSR_CNACK;
218 jwrite32(jme, JME_SMBCSR, val);
219 val |= SMBCSR_RELOAD;
220 jwrite32(jme, JME_SMBCSR, val);
221 mdelay(12);
222
cd0ff491 223 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
224 mdelay(1);
225 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
226 break;
227 }
228
cd0ff491
GFT
229 if (i == 0) {
230 jeprintk(jme->pdev, "eeprom reload timeout\n");
d7699f87
GFT
231 return -EIO;
232 }
233 }
3bf61c55 234
d7699f87
GFT
235 return 0;
236}
237
3bf61c55
GFT
238static void
239jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
240{
241 struct jme_adapter *jme = netdev_priv(netdev);
242 unsigned char macaddr[6];
cd0ff491 243 u32 val;
d7699f87 244
cd0ff491 245 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 246 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
247 macaddr[0] = (val >> 0) & 0xFF;
248 macaddr[1] = (val >> 8) & 0xFF;
249 macaddr[2] = (val >> 16) & 0xFF;
250 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 251 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
252 macaddr[4] = (val >> 0) & 0xFF;
253 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
254 memcpy(netdev->dev_addr, macaddr, 6);
255 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
256}
257
cd0ff491 258static inline void
3bf61c55
GFT
259jme_set_rx_pcc(struct jme_adapter *jme, int p)
260{
cd0ff491 261 switch (p) {
192570e0
GFT
262 case PCC_OFF:
263 jwrite32(jme, JME_PCCRX0,
264 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
265 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
266 break;
3bf61c55
GFT
267 case PCC_P1:
268 jwrite32(jme, JME_PCCRX0,
269 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
270 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 break;
272 case PCC_P2:
273 jwrite32(jme, JME_PCCRX0,
274 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
275 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 break;
277 case PCC_P3:
278 jwrite32(jme, JME_PCCRX0,
279 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
280 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 break;
282 default:
283 break;
284 }
192570e0 285 wmb();
3bf61c55 286
cd0ff491 287 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
c97b5740 288 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT
289}
290
fcf45b4c 291static void
3bf61c55 292jme_start_irq(struct jme_adapter *jme)
d7699f87 293{
3bf61c55
GFT
294 register struct dynpcc_info *dpi = &(jme->dpi);
295
296 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
297 dpi->cur = PCC_P1;
298 dpi->attempt = PCC_P1;
299 dpi->cnt = 0;
300
301 jwrite32(jme, JME_PCCTX,
8c198884
GFT
302 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
303 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
304 PCCTXQ0_EN
305 );
306
d7699f87
GFT
307 /*
308 * Enable Interrupts
309 */
310 jwrite32(jme, JME_IENS, INTR_ENABLE);
311}
312
cd0ff491 313static inline void
3bf61c55 314jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
315{
316 /*
317 * Disable Interrupts
318 */
cd0ff491 319 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
320}
321
cd0ff491 322static u32
cdcdc9eb
GFT
323jme_linkstat_from_phy(struct jme_adapter *jme)
324{
cd0ff491 325 u32 phylink, bmsr;
cdcdc9eb
GFT
326
327 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
328 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 329 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
330 phylink |= PHY_LINK_AUTONEG_COMPLETE;
331
332 return phylink;
333}
334
cd0ff491 335static inline void
e882564f 336jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT
337{
338 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
339}
340
341static inline void
e882564f 342jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT
343{
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
345}
346
fcf45b4c
GFT
347static int
348jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
349{
350 struct jme_adapter *jme = netdev_priv(netdev);
9b9d55de 351 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 352 char linkmsg[64];
fcf45b4c 353 int rc = 0;
d7699f87 354
b3821cc5 355 linkmsg[0] = '\0';
cdcdc9eb 356
cd0ff491 357 if (jme->fpgaver)
cdcdc9eb
GFT
358 phylink = jme_linkstat_from_phy(jme);
359 else
360 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 361
cd0ff491
GFT
362 if (phylink & PHY_LINK_UP) {
363 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
364 /*
365 * If we did not enable AN
366 * Speed/Duplex Info should be obtained from SMI
367 */
368 phylink = PHY_LINK_UP;
369
370 bmcr = jme_mdio_read(jme->dev,
371 jme->mii_if.phy_id,
372 MII_BMCR);
373
374 phylink |= ((bmcr & BMCR_SPEED1000) &&
375 (bmcr & BMCR_SPEED100) == 0) ?
376 PHY_LINK_SPEED_1000M :
377 (bmcr & BMCR_SPEED100) ?
378 PHY_LINK_SPEED_100M :
379 PHY_LINK_SPEED_10M;
380
381 phylink |= (bmcr & BMCR_FULLDPLX) ?
382 PHY_LINK_DUPLEX : 0;
79ce639c 383
b3821cc5 384 strcat(linkmsg, "Forced: ");
cd0ff491 385 } else {
8c198884
GFT
386 /*
387 * Keep polling for speed/duplex resolve complete
388 */
cd0ff491 389 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
390 --cnt) {
391
392 udelay(1);
8c198884 393
cd0ff491 394 if (jme->fpgaver)
cdcdc9eb
GFT
395 phylink = jme_linkstat_from_phy(jme);
396 else
397 phylink = jread32(jme, JME_PHY_LINK);
8c198884 398 }
cd0ff491
GFT
399 if (!cnt)
400 jeprintk(jme->pdev,
8c198884 401 "Waiting speed resolve timeout.\n");
79ce639c 402
b3821cc5 403 strcat(linkmsg, "ANed: ");
d7699f87
GFT
404 }
405
cd0ff491 406 if (jme->phylink == phylink) {
fcf45b4c
GFT
407 rc = 1;
408 goto out;
409 }
cd0ff491 410 if (testonly)
fcf45b4c
GFT
411 goto out;
412
413 jme->phylink = phylink;
414
94c5ea02
GFT
415 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
416 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
417 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
cd0ff491
GFT
418 switch (phylink & PHY_LINK_SPEED_MASK) {
419 case PHY_LINK_SPEED_10M:
94c5ea02
GFT
420 ghc |= GHC_SPEED_10M |
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 422 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
423 break;
424 case PHY_LINK_SPEED_100M:
94c5ea02
GFT
425 ghc |= GHC_SPEED_100M |
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 427 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
428 break;
429 case PHY_LINK_SPEED_1000M:
94c5ea02
GFT
430 ghc |= GHC_SPEED_1000M |
431 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
cd0ff491 432 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
433 break;
434 default:
435 break;
d7699f87 436 }
d7699f87 437
cd0ff491 438 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 439 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
9b9d55de 440 ghc |= GHC_DPX;
cd0ff491 441 } else {
d7699f87 442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
443 TXMCS_BACKOFF |
444 TXMCS_CARRIERSENSE |
445 TXMCS_COLLISION);
8c198884
GFT
446 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
447 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
448 TXTRHD_TXREN |
449 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
450 }
9b9d55de
GFT
451
452 gpreg1 = GPREG1_DEFAULT;
453 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
454 if (!(phylink & PHY_LINK_DUPLEX))
455 gpreg1 |= GPREG1_HALFMODEPATCH;
456 switch (phylink & PHY_LINK_SPEED_MASK) {
457 case PHY_LINK_SPEED_10M:
458 jme_set_phyfifoa(jme);
459 gpreg1 |= GPREG1_RSSPATCH;
460 break;
461 case PHY_LINK_SPEED_100M:
462 jme_set_phyfifob(jme);
463 gpreg1 |= GPREG1_RSSPATCH;
464 break;
465 case PHY_LINK_SPEED_1000M:
466 jme_set_phyfifoa(jme);
467 break;
468 default:
469 break;
470 }
471 }
d7699f87 472
94c5ea02 473 jwrite32(jme, JME_GPREG1, gpreg1);
fcf45b4c 474 jwrite32(jme, JME_GHC, ghc);
94c5ea02 475 jme->reg_ghc = ghc;
fcf45b4c 476
94c5ea02
GFT
477 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
478 "Full-Duplex, " :
479 "Half-Duplex, ");
480 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
481 "MDI-X" :
482 "MDI");
c97b5740 483 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
cd0ff491
GFT
484 netif_carrier_on(netdev);
485 } else {
486 if (testonly)
fcf45b4c
GFT
487 goto out;
488
c97b5740 489 netif_info(jme, link, jme->dev, "Link is down.\n");
fcf45b4c 490 jme->phylink = 0;
cd0ff491 491 netif_carrier_off(netdev);
d7699f87 492 }
fcf45b4c
GFT
493
494out:
495 return rc;
d7699f87
GFT
496}
497
3bf61c55
GFT
498static int
499jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 500{
d7699f87
GFT
501 struct jme_ring *txring = &(jme->txring[0]);
502
503 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
504 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
505 &(txring->dmaalloc),
506 GFP_ATOMIC);
fcf45b4c 507
fa97b924
GFT
508 if (!txring->alloc)
509 goto err_set_null;
d7699f87
GFT
510
511 /*
512 * 16 Bytes align
513 */
cd0ff491 514 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 515 RING_DESC_ALIGN);
4330c2f2 516 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 517 txring->next_to_use = 0;
cdcdc9eb 518 atomic_set(&txring->next_to_clean, 0);
b3821cc5 519 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 520
fa97b924
GFT
521 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
522 jme->tx_ring_size, GFP_ATOMIC);
523 if (unlikely(!(txring->bufinf)))
524 goto err_free_txring;
525
d7699f87 526 /*
b3821cc5 527 * Initialize Transmit Descriptors
d7699f87 528 */
b3821cc5 529 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 530 memset(txring->bufinf, 0,
b3821cc5 531 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
532
533 return 0;
fa97b924
GFT
534
535err_free_txring:
536 dma_free_coherent(&(jme->pdev->dev),
537 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
538 txring->alloc,
539 txring->dmaalloc);
540
541err_set_null:
542 txring->desc = NULL;
543 txring->dmaalloc = 0;
544 txring->dma = 0;
545 txring->bufinf = NULL;
546
547 return -ENOMEM;
d7699f87
GFT
548}
549
3bf61c55
GFT
550static void
551jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
552{
553 int i;
554 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 555 struct jme_buffer_info *txbi;
d7699f87 556
cd0ff491 557 if (txring->alloc) {
fa97b924
GFT
558 if (txring->bufinf) {
559 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
560 txbi = txring->bufinf + i;
561 if (txbi->skb) {
562 dev_kfree_skb(txbi->skb);
563 txbi->skb = NULL;
564 }
565 txbi->mapping = 0;
566 txbi->len = 0;
567 txbi->nr_desc = 0;
568 txbi->start_xmit = 0;
d7699f87 569 }
fa97b924 570 kfree(txring->bufinf);
d7699f87
GFT
571 }
572
573 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 574 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
575 txring->alloc,
576 txring->dmaalloc);
3bf61c55
GFT
577
578 txring->alloc = NULL;
579 txring->desc = NULL;
580 txring->dmaalloc = 0;
581 txring->dma = 0;
fa97b924 582 txring->bufinf = NULL;
d7699f87 583 }
3bf61c55 584 txring->next_to_use = 0;
cdcdc9eb 585 atomic_set(&txring->next_to_clean, 0);
79ce639c 586 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
587}
588
cd0ff491 589static inline void
3bf61c55 590jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
591{
592 /*
593 * Select Queue 0
594 */
595 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 596 wmb();
d7699f87
GFT
597
598 /*
599 * Setup TX Queue 0 DMA Bass Address
600 */
fcf45b4c 601 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 602 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 603 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
604
605 /*
606 * Setup TX Descptor Count
607 */
b3821cc5 608 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
609
610 /*
611 * Enable TX Engine
612 */
613 wmb();
4330c2f2
GFT
614 jwrite32(jme, JME_TXCS, jme->reg_txcs |
615 TXCS_SELECT_QUEUE0 |
616 TXCS_ENABLE);
d7699f87
GFT
617
618}
619
cd0ff491 620static inline void
29bdd921
GFT
621jme_restart_tx_engine(struct jme_adapter *jme)
622{
623 /*
624 * Restart TX Engine
625 */
626 jwrite32(jme, JME_TXCS, jme->reg_txcs |
627 TXCS_SELECT_QUEUE0 |
628 TXCS_ENABLE);
629}
630
cd0ff491 631static inline void
3bf61c55 632jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
633{
634 int i;
cd0ff491 635 u32 val;
d7699f87
GFT
636
637 /*
638 * Disable TX Engine
639 */
fcf45b4c 640 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 641 wmb();
d7699f87
GFT
642
643 val = jread32(jme, JME_TXCS);
cd0ff491 644 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 645 mdelay(1);
d7699f87 646 val = jread32(jme, JME_TXCS);
cd0ff491 647 rmb();
d7699f87
GFT
648 }
649
cd0ff491
GFT
650 if (!i)
651 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
d7699f87
GFT
652}
653
3bf61c55
GFT
654static void
655jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 656{
fa97b924 657 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 658 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
659 struct jme_buffer_info *rxbi = rxring->bufinf;
660 rxdesc += i;
661 rxbi += i;
662
663 rxdesc->dw[0] = 0;
664 rxdesc->dw[1] = 0;
3bf61c55 665 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
666 rxdesc->desc1.bufaddrl = cpu_to_le32(
667 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 668 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 669 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 670 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 671 wmb();
3bf61c55 672 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
673}
674
3bf61c55
GFT
675static int
676jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
677{
678 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 679 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 680 struct sk_buff *skb;
4330c2f2 681
79ce639c
GFT
682 skb = netdev_alloc_skb(jme->dev,
683 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 684 if (unlikely(!skb))
4330c2f2 685 return -ENOMEM;
3bf61c55 686
4330c2f2 687 rxbi->skb = skb;
3bf61c55 688 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
689 rxbi->mapping = pci_map_page(jme->pdev,
690 virt_to_page(skb->data),
691 offset_in_page(skb->data),
692 rxbi->len,
693 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
694
695 return 0;
696}
697
3bf61c55
GFT
698static void
699jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
700{
701 struct jme_ring *rxring = &(jme->rxring[0]);
702 struct jme_buffer_info *rxbi = rxring->bufinf;
703 rxbi += i;
704
cd0ff491 705 if (rxbi->skb) {
b3821cc5 706 pci_unmap_page(jme->pdev,
4330c2f2 707 rxbi->mapping,
3bf61c55 708 rxbi->len,
4330c2f2
GFT
709 PCI_DMA_FROMDEVICE);
710 dev_kfree_skb(rxbi->skb);
711 rxbi->skb = NULL;
712 rxbi->mapping = 0;
3bf61c55 713 rxbi->len = 0;
4330c2f2
GFT
714 }
715}
716
3bf61c55
GFT
717static void
718jme_free_rx_resources(struct jme_adapter *jme)
719{
720 int i;
721 struct jme_ring *rxring = &(jme->rxring[0]);
722
cd0ff491 723 if (rxring->alloc) {
fa97b924
GFT
724 if (rxring->bufinf) {
725 for (i = 0 ; i < jme->rx_ring_size ; ++i)
726 jme_free_rx_buf(jme, i);
727 kfree(rxring->bufinf);
728 }
3bf61c55
GFT
729
730 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 731 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
732 rxring->alloc,
733 rxring->dmaalloc);
734 rxring->alloc = NULL;
735 rxring->desc = NULL;
736 rxring->dmaalloc = 0;
737 rxring->dma = 0;
fa97b924 738 rxring->bufinf = NULL;
3bf61c55
GFT
739 }
740 rxring->next_to_use = 0;
cdcdc9eb 741 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
742}
743
744static int
745jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
746{
747 int i;
748 struct jme_ring *rxring = &(jme->rxring[0]);
749
750 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
751 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
752 &(rxring->dmaalloc),
753 GFP_ATOMIC);
fa97b924
GFT
754 if (!rxring->alloc)
755 goto err_set_null;
d7699f87
GFT
756
757 /*
758 * 16 Bytes align
759 */
cd0ff491 760 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 761 RING_DESC_ALIGN);
4330c2f2 762 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 763 rxring->next_to_use = 0;
cdcdc9eb 764 atomic_set(&rxring->next_to_clean, 0);
d7699f87 765
fa97b924
GFT
766 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
767 jme->rx_ring_size, GFP_ATOMIC);
768 if (unlikely(!(rxring->bufinf)))
769 goto err_free_rxring;
770
d7699f87
GFT
771 /*
772 * Initiallize Receive Descriptors
773 */
fa97b924
GFT
774 memset(rxring->bufinf, 0,
775 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT
776 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
777 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
778 jme_free_rx_resources(jme);
779 return -ENOMEM;
780 }
d7699f87
GFT
781
782 jme_set_clean_rxdesc(jme, i);
783 }
784
d7699f87 785 return 0;
fa97b924
GFT
786
787err_free_rxring:
788 dma_free_coherent(&(jme->pdev->dev),
789 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
790 rxring->alloc,
791 rxring->dmaalloc);
792err_set_null:
793 rxring->desc = NULL;
794 rxring->dmaalloc = 0;
795 rxring->dma = 0;
796 rxring->bufinf = NULL;
797
798 return -ENOMEM;
d7699f87
GFT
799}
800
cd0ff491 801static inline void
3bf61c55 802jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 803{
d7699f87 804 /*
cd0ff491
GFT
805 * Select Queue 0
806 */
807 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
808 RXCS_QUEUESEL_Q0);
809 wmb();
810
811 /*
d7699f87
GFT
812 * Setup RX DMA Bass Address
813 */
fa97b924 814 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 815 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 816 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT
817
818 /*
b3821cc5 819 * Setup RX Descriptor Count
d7699f87 820 */
b3821cc5 821 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 822
3bf61c55 823 /*
d7699f87
GFT
824 * Setup Unicast Filter
825 */
826 jme_set_multi(jme->dev);
827
828 /*
829 * Enable RX Engine
830 */
831 wmb();
79ce639c 832 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
833 RXCS_QUEUESEL_Q0 |
834 RXCS_ENABLE |
835 RXCS_QST);
d7699f87
GFT
836}
837
cd0ff491 838static inline void
3bf61c55 839jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
840{
841 /*
3bf61c55 842 * Start RX Engine
4330c2f2 843 */
79ce639c 844 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
845 RXCS_QUEUESEL_Q0 |
846 RXCS_ENABLE |
847 RXCS_QST);
848}
849
cd0ff491 850static inline void
3bf61c55 851jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
852{
853 int i;
cd0ff491 854 u32 val;
d7699f87
GFT
855
856 /*
857 * Disable RX Engine
858 */
29bdd921 859 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 860 wmb();
d7699f87
GFT
861
862 val = jread32(jme, JME_RXCS);
cd0ff491 863 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 864 mdelay(1);
d7699f87 865 val = jread32(jme, JME_RXCS);
cd0ff491 866 rmb();
d7699f87
GFT
867 }
868
cd0ff491
GFT
869 if (!i)
870 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
d7699f87
GFT
871
872}
873
192570e0 874static int
cd0ff491 875jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 876{
cd0ff491 877 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
878 return false;
879
fa97b924
GFT
880 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
881 == RXWBFLAG_TCPON)) {
882 if (flags & RXWBFLAG_IPV4)
c97b5740 883 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
fa97b924 884 return false;
192570e0
GFT
885 }
886
fa97b924
GFT
887 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
888 == RXWBFLAG_UDPON)) {
889 if (flags & RXWBFLAG_IPV4)
c97b5740 890 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
fa97b924 891 return false;
192570e0
GFT
892 }
893
fa97b924
GFT
894 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
895 == RXWBFLAG_IPV4)) {
c97b5740 896 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
fa97b924 897 return false;
192570e0
GFT
898 }
899
900 return true;
901}
902
3bf61c55 903static void
42b1055e 904jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 905{
d7699f87 906 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 907 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 908 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 909 struct sk_buff *skb;
3bf61c55 910 int framesize;
d7699f87 911
3bf61c55
GFT
912 rxdesc += idx;
913 rxbi += idx;
d7699f87 914
3bf61c55
GFT
915 skb = rxbi->skb;
916 pci_dma_sync_single_for_cpu(jme->pdev,
917 rxbi->mapping,
918 rxbi->len,
919 PCI_DMA_FROMDEVICE);
920
cd0ff491 921 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
922 pci_dma_sync_single_for_device(jme->pdev,
923 rxbi->mapping,
924 rxbi->len,
925 PCI_DMA_FROMDEVICE);
926
927 ++(NET_STAT(jme).rx_dropped);
cd0ff491 928 } else {
3bf61c55
GFT
929 framesize = le16_to_cpu(rxdesc->descwb.framesize)
930 - RX_PREPAD_SIZE;
931
932 skb_reserve(skb, RX_PREPAD_SIZE);
933 skb_put(skb, framesize);
934 skb->protocol = eth_type_trans(skb, jme->dev);
935
94c5ea02 936 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 937 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 938 else
97984ab7 939 skb_checksum_none_assert(skb);
8c198884 940
94c5ea02 941 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 942 if (jme->vlgrp) {
cdcdc9eb 943 jme->jme_vlan_rx(skb, jme->vlgrp,
94c5ea02 944 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 945 NET_STAT(jme).rx_bytes += 4;
c97b5740 946 } else {
c97b5740 947 dev_kfree_skb(skb);
b3821cc5 948 }
cd0ff491 949 } else {
cdcdc9eb 950 jme->jme_rx(skb);
b3821cc5 951 }
3bf61c55 952
94c5ea02
GFT
953 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
954 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT
955 ++(NET_STAT(jme).multicast);
956
3bf61c55
GFT
957 NET_STAT(jme).rx_bytes += framesize;
958 ++(NET_STAT(jme).rx_packets);
959 }
960
961 jme_set_clean_rxdesc(jme, idx);
962
963}
964
8c198884 965static int
3bf61c55
GFT
966jme_process_receive(struct jme_adapter *jme, int limit)
967{
968 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 969 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 970 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 971
cd0ff491 972 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
973 goto out_inc;
974
cd0ff491 975 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
976 goto out_inc;
977
cd0ff491 978 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
979 goto out_inc;
980
cdcdc9eb 981 i = atomic_read(&rxring->next_to_clean);
fa97b924 982 while (limit > 0) {
3bf61c55
GFT
983 rxdesc = rxring->desc;
984 rxdesc += i;
985
94c5ea02 986 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT
987 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
988 goto out;
fa97b924 989 --limit;
d7699f87 990
4330c2f2
GFT
991 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
992
cd0ff491 993 if (unlikely(desccnt > 1 ||
192570e0 994 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 995
cd0ff491 996 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 997 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 998 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
999 ++(NET_STAT(jme).rx_fifo_errors);
1000 else
1001 ++(NET_STAT(jme).rx_errors);
4330c2f2 1002
cd0ff491 1003 if (desccnt > 1)
3bf61c55 1004 limit -= desccnt - 1;
4330c2f2 1005
cd0ff491 1006 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1007 jme_set_clean_rxdesc(jme, j);
b3821cc5 1008 j = (j + 1) & (mask);
4330c2f2 1009 }
3bf61c55 1010
cd0ff491 1011 } else {
42b1055e 1012 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1013 }
4330c2f2 1014
b3821cc5 1015 i = (i + desccnt) & (mask);
3bf61c55 1016 }
4330c2f2 1017
3bf61c55 1018out:
cdcdc9eb 1019 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1020
192570e0
GFT
1021out_inc:
1022 atomic_inc(&jme->rx_cleaning);
1023
3bf61c55 1024 return limit > 0 ? limit : 0;
4330c2f2 1025
3bf61c55 1026}
d7699f87 1027
3bf61c55 1028static void
79ce639c
GFT
1029jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1030{
cd0ff491 1031 if (likely(atmp == dpi->cur)) {
192570e0 1032 dpi->cnt = 0;
79ce639c 1033 return;
192570e0 1034 }
79ce639c 1035
cd0ff491 1036 if (dpi->attempt == atmp) {
79ce639c 1037 ++(dpi->cnt);
cd0ff491 1038 } else {
79ce639c
GFT
1039 dpi->attempt = atmp;
1040 dpi->cnt = 0;
1041 }
1042
1043}
1044
1045static void
1046jme_dynamic_pcc(struct jme_adapter *jme)
1047{
1048 register struct dynpcc_info *dpi = &(jme->dpi);
1049
cd0ff491 1050 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1051 jme_attempt_pcc(dpi, PCC_P3);
c97b5740
GFT
1052 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1053 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT
1054 jme_attempt_pcc(dpi, PCC_P2);
1055 else
1056 jme_attempt_pcc(dpi, PCC_P1);
1057
cd0ff491
GFT
1058 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1059 if (dpi->attempt < dpi->cur)
1060 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1061 jme_set_rx_pcc(jme, dpi->attempt);
1062 dpi->cur = dpi->attempt;
1063 dpi->cnt = 0;
1064 }
1065}
1066
1067static void
1068jme_start_pcc_timer(struct jme_adapter *jme)
1069{
1070 struct dynpcc_info *dpi = &(jme->dpi);
1071 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1072 dpi->last_pkts = NET_STAT(jme).rx_packets;
1073 dpi->intr_cnt = 0;
1074 jwrite32(jme, JME_TMCSR,
1075 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1076}
1077
cd0ff491 1078static inline void
29bdd921
GFT
1079jme_stop_pcc_timer(struct jme_adapter *jme)
1080{
1081 jwrite32(jme, JME_TMCSR, 0);
1082}
1083
1084static void
cd0ff491
GFT
1085jme_shutdown_nic(struct jme_adapter *jme)
1086{
1087 u32 phylink;
1088
1089 phylink = jme_linkstat_from_phy(jme);
1090
1091 if (!(phylink & PHY_LINK_UP)) {
1092 /*
1093 * Disable all interrupt before issue timer
1094 */
1095 jme_stop_irq(jme);
1096 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1097 }
1098}
1099
1100static void
79ce639c
GFT
1101jme_pcc_tasklet(unsigned long arg)
1102{
cd0ff491 1103 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1104 struct net_device *netdev = jme->dev;
1105
cd0ff491
GFT
1106 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1107 jme_shutdown_nic(jme);
1108 return;
1109 }
29bdd921 1110
cd0ff491 1111 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1112 (atomic_read(&jme->link_changing) != 1)
1113 )) {
1114 jme_stop_pcc_timer(jme);
79ce639c
GFT
1115 return;
1116 }
29bdd921 1117
cd0ff491 1118 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1119 jme_dynamic_pcc(jme);
1120
79ce639c
GFT
1121 jme_start_pcc_timer(jme);
1122}
1123
cd0ff491 1124static inline void
192570e0
GFT
1125jme_polling_mode(struct jme_adapter *jme)
1126{
1127 jme_set_rx_pcc(jme, PCC_OFF);
1128}
1129
cd0ff491 1130static inline void
192570e0
GFT
1131jme_interrupt_mode(struct jme_adapter *jme)
1132{
1133 jme_set_rx_pcc(jme, PCC_P1);
1134}
1135
cd0ff491
GFT
1136static inline int
1137jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1138{
1139 u32 apmc;
1140 apmc = jread32(jme, JME_APMC);
1141 return apmc & JME_APMC_PSEUDO_HP_EN;
1142}
1143
1144static void
1145jme_start_shutdown_timer(struct jme_adapter *jme)
1146{
1147 u32 apmc;
1148
1149 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1150 apmc &= ~JME_APMC_EPIEN_CTRL;
1151 if (!no_extplug) {
1152 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1153 wmb();
1154 }
1155 jwrite32f(jme, JME_APMC, apmc);
1156
1157 jwrite32f(jme, JME_TIMER2, 0);
1158 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1159 jwrite32(jme, JME_TMCSR,
1160 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1161}
1162
1163static void
1164jme_stop_shutdown_timer(struct jme_adapter *jme)
1165{
1166 u32 apmc;
1167
1168 jwrite32f(jme, JME_TMCSR, 0);
1169 jwrite32f(jme, JME_TIMER2, 0);
1170 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1171
1172 apmc = jread32(jme, JME_APMC);
1173 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1174 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1175 wmb();
1176 jwrite32f(jme, JME_APMC, apmc);
1177}
1178
79ce639c 1179static void
3bf61c55
GFT
1180jme_link_change_tasklet(unsigned long arg)
1181{
cd0ff491 1182 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1183 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1184 int rc;
1185
cd0ff491
GFT
1186 while (!atomic_dec_and_test(&jme->link_changing)) {
1187 atomic_inc(&jme->link_changing);
c97b5740 1188 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
e882564f 1189 while (atomic_read(&jme->link_changing) != 1)
c97b5740 1190 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
cd0ff491 1191 }
fcf45b4c 1192
cd0ff491 1193 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1194 goto out;
1195
29bdd921 1196 jme->old_mtu = netdev->mtu;
fcf45b4c 1197 netif_stop_queue(netdev);
cd0ff491
GFT
1198 if (jme_pseudo_hotplug_enabled(jme))
1199 jme_stop_shutdown_timer(jme);
1200
1201 jme_stop_pcc_timer(jme);
1202 tasklet_disable(&jme->txclean_task);
1203 tasklet_disable(&jme->rxclean_task);
1204 tasklet_disable(&jme->rxempty_task);
1205
1206 if (netif_carrier_ok(netdev)) {
1207 jme_reset_ghc_speed(jme);
1208 jme_disable_rx_engine(jme);
1209 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1210 jme_reset_mac_processor(jme);
1211 jme_free_rx_resources(jme);
1212 jme_free_tx_resources(jme);
192570e0 1213
cd0ff491 1214 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1215 jme_polling_mode(jme);
cd0ff491
GFT
1216
1217 netif_carrier_off(netdev);
fcf45b4c
GFT
1218 }
1219
1220 jme_check_link(netdev, 0);
cd0ff491 1221 if (netif_carrier_ok(netdev)) {
fcf45b4c 1222 rc = jme_setup_rx_resources(jme);
cd0ff491
GFT
1223 if (rc) {
1224 jeprintk(jme->pdev, "Allocating resources for RX error"
fcf45b4c 1225 ", Device STOPPED!\n");
cd0ff491 1226 goto out_enable_tasklet;
fcf45b4c
GFT
1227 }
1228
fcf45b4c 1229 rc = jme_setup_tx_resources(jme);
cd0ff491
GFT
1230 if (rc) {
1231 jeprintk(jme->pdev, "Allocating resources for TX error"
fcf45b4c
GFT
1232 ", Device STOPPED!\n");
1233 goto err_out_free_rx_resources;
1234 }
1235
1236 jme_enable_rx_engine(jme);
1237 jme_enable_tx_engine(jme);
1238
1239 netif_start_queue(netdev);
192570e0 1240
cd0ff491 1241 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1242 jme_interrupt_mode(jme);
192570e0 1243
79ce639c 1244 jme_start_pcc_timer(jme);
cd0ff491
GFT
1245 } else if (jme_pseudo_hotplug_enabled(jme)) {
1246 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1247 }
1248
cd0ff491 1249 goto out_enable_tasklet;
fcf45b4c
GFT
1250
1251err_out_free_rx_resources:
1252 jme_free_rx_resources(jme);
cd0ff491
GFT
1253out_enable_tasklet:
1254 tasklet_enable(&jme->txclean_task);
1255 tasklet_hi_enable(&jme->rxclean_task);
1256 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1257out:
1258 atomic_inc(&jme->link_changing);
3bf61c55 1259}
d7699f87 1260
3bf61c55
GFT
1261static void
1262jme_rx_clean_tasklet(unsigned long arg)
1263{
cd0ff491 1264 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1265 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1266
192570e0
GFT
1267 jme_process_receive(jme, jme->rx_ring_size);
1268 ++(dpi->intr_cnt);
42b1055e 1269
192570e0 1270}
fcf45b4c 1271
192570e0 1272static int
cdcdc9eb 1273jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1274{
cdcdc9eb 1275 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1276 int rest;
fcf45b4c 1277
cdcdc9eb 1278 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1279
cd0ff491 1280 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1281 atomic_dec(&jme->rx_empty);
192570e0
GFT
1282 ++(NET_STAT(jme).rx_dropped);
1283 jme_restart_rx_engine(jme);
1284 }
1285 atomic_inc(&jme->rx_empty);
1286
cd0ff491 1287 if (rest) {
cdcdc9eb 1288 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1289 jme_interrupt_mode(jme);
1290 }
1291
cdcdc9eb
GFT
1292 JME_NAPI_WEIGHT_SET(budget, rest);
1293 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1294}
1295
1296static void
1297jme_rx_empty_tasklet(unsigned long arg)
1298{
cd0ff491 1299 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1300
cd0ff491 1301 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1302 return;
1303
cd0ff491 1304 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1305 return;
1306
c97b5740 1307 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1308
fcf45b4c 1309 jme_rx_clean_tasklet(arg);
cdcdc9eb 1310
cd0ff491 1311 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1312 atomic_dec(&jme->rx_empty);
1313 ++(NET_STAT(jme).rx_dropped);
1314 jme_restart_rx_engine(jme);
1315 }
1316 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1317}
1318
3bf61c55 1319static void
b3821cc5
GFT
1320jme_wake_queue_if_stopped(struct jme_adapter *jme)
1321{
fa97b924 1322 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1323
1324 smp_wmb();
cd0ff491 1325 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1326 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
c97b5740 1327 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
b3821cc5 1328 netif_wake_queue(jme->dev);
b3821cc5
GFT
1329 }
1330
1331}
1332
1333static void
3bf61c55 1334jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1335{
cd0ff491 1336 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1337 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1338 struct txdesc *txdesc = txring->desc;
3bf61c55 1339 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1340 int i, j, cnt = 0, max, err, mask;
3bf61c55 1341
cd0ff491
GFT
1342 tx_dbg(jme, "Into txclean.\n");
1343
1344 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1345 goto out;
1346
cd0ff491 1347 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1348 goto out;
1349
cd0ff491 1350 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1351 goto out;
1352
b3821cc5
GFT
1353 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1354 mask = jme->tx_ring_mask;
3bf61c55 1355
cd0ff491 1356 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1357
1358 ctxbi = txbi + i;
1359
cd0ff491 1360 if (likely(ctxbi->skb &&
b3821cc5 1361 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1362
cd0ff491
GFT
1363 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1364 i, ctxbi->nr_desc, jiffies);
3bf61c55 1365
cd0ff491 1366 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1367
cd0ff491 1368 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1369 ttxbi = txbi + ((i + j) & (mask));
1370 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1371
b3821cc5 1372 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1373 ttxbi->mapping,
1374 ttxbi->len,
1375 PCI_DMA_TODEVICE);
1376
3bf61c55
GFT
1377 ttxbi->mapping = 0;
1378 ttxbi->len = 0;
1379 }
1380
1381 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1382
1383 cnt += ctxbi->nr_desc;
1384
cd0ff491 1385 if (unlikely(err)) {
8c198884 1386 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1387 } else {
8c198884 1388 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1389 NET_STAT(jme).tx_bytes += ctxbi->len;
1390 }
1391
1392 ctxbi->skb = NULL;
1393 ctxbi->len = 0;
cdcdc9eb 1394 ctxbi->start_xmit = 0;
cd0ff491
GFT
1395
1396 } else {
3bf61c55
GFT
1397 break;
1398 }
1399
b3821cc5 1400 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1401
1402 ctxbi->nr_desc = 0;
d7699f87
GFT
1403 }
1404
cd0ff491 1405 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
cdcdc9eb 1406 atomic_set(&txring->next_to_clean, i);
79ce639c 1407 atomic_add(cnt, &txring->nr_free);
3bf61c55 1408
b3821cc5
GFT
1409 jme_wake_queue_if_stopped(jme);
1410
fcf45b4c
GFT
1411out:
1412 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1413}
1414
79ce639c 1415static void
cd0ff491 1416jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1417{
3bf61c55
GFT
1418 /*
1419 * Disable interrupt
1420 */
1421 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1422
cd0ff491 1423 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1424 /*
1425 * Link change event is critical
1426 * all other events are ignored
1427 */
1428 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1429 tasklet_schedule(&jme->linkch_task);
29bdd921 1430 goto out_reenable;
fcf45b4c 1431 }
d7699f87 1432
cd0ff491 1433 if (intrstat & INTR_TMINTR) {
47220951 1434 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1435 tasklet_schedule(&jme->pcc_task);
47220951 1436 }
79ce639c 1437
cd0ff491 1438 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1439 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1440 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1441 }
1442
cd0ff491 1443 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1444 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1445 INTR_PCCRX0 |
1446 INTR_RX0EMP)) |
1447 INTR_RX0);
1448 }
d7699f87 1449
cd0ff491
GFT
1450 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1451 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1452 atomic_inc(&jme->rx_empty);
1453
cd0ff491
GFT
1454 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1455 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1456 jme_polling_mode(jme);
cdcdc9eb 1457 JME_RX_SCHEDULE(jme);
192570e0
GFT
1458 }
1459 }
cd0ff491
GFT
1460 } else {
1461 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1462 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1463 tasklet_hi_schedule(&jme->rxempty_task);
1464 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1465 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1466 }
4330c2f2 1467 }
d7699f87 1468
29bdd921 1469out_reenable:
3bf61c55 1470 /*
fcf45b4c 1471 * Re-enable interrupt
3bf61c55 1472 */
fcf45b4c 1473 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1474}
1475
1476static irqreturn_t
1477jme_intr(int irq, void *dev_id)
1478{
cd0ff491
GFT
1479 struct net_device *netdev = dev_id;
1480 struct jme_adapter *jme = netdev_priv(netdev);
1481 u32 intrstat;
79ce639c
GFT
1482
1483 intrstat = jread32(jme, JME_IEVE);
1484
1485 /*
1486 * Check if it's really an interrupt for us
1487 */
9b9d55de 1488 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1489 return IRQ_NONE;
79ce639c
GFT
1490
1491 /*
1492 * Check if the device still exist
1493 */
cd0ff491
GFT
1494 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1495 return IRQ_NONE;
79ce639c
GFT
1496
1497 jme_intr_msi(jme, intrstat);
1498
cd0ff491 1499 return IRQ_HANDLED;
d7699f87
GFT
1500}
1501
79ce639c
GFT
1502static irqreturn_t
1503jme_msi(int irq, void *dev_id)
1504{
cd0ff491
GFT
1505 struct net_device *netdev = dev_id;
1506 struct jme_adapter *jme = netdev_priv(netdev);
1507 u32 intrstat;
79ce639c 1508
fa97b924 1509 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT
1510
1511 jme_intr_msi(jme, intrstat);
1512
cd0ff491 1513 return IRQ_HANDLED;
79ce639c
GFT
1514}
1515
79ce639c
GFT
1516static void
1517jme_reset_link(struct jme_adapter *jme)
1518{
1519 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1520}
1521
fcf45b4c
GFT
1522static void
1523jme_restart_an(struct jme_adapter *jme)
1524{
cd0ff491 1525 u32 bmcr;
fcf45b4c 1526
cd0ff491 1527 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1528 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1529 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1530 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1531 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1532}
1533
1534static int
1535jme_request_irq(struct jme_adapter *jme)
1536{
1537 int rc;
cd0ff491
GFT
1538 struct net_device *netdev = jme->dev;
1539 irq_handler_t handler = jme_intr;
1540 int irq_flags = IRQF_SHARED;
1541
1542 if (!pci_enable_msi(jme->pdev)) {
1543 set_bit(JME_FLAG_MSI, &jme->flags);
1544 handler = jme_msi;
1545 irq_flags = 0;
1546 }
1547
1548 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1549 netdev);
1550 if (rc) {
1551 jeprintk(jme->pdev,
b3821cc5 1552 "Unable to request %s interrupt (return: %d)\n",
cd0ff491
GFT
1553 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1554 rc);
79ce639c 1555
cd0ff491
GFT
1556 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1557 pci_disable_msi(jme->pdev);
1558 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1559 }
cd0ff491 1560 } else {
79ce639c
GFT
1561 netdev->irq = jme->pdev->irq;
1562 }
1563
cd0ff491 1564 return rc;
79ce639c
GFT
1565}
1566
1567static void
1568jme_free_irq(struct jme_adapter *jme)
1569{
cd0ff491
GFT
1570 free_irq(jme->pdev->irq, jme->dev);
1571 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1572 pci_disable_msi(jme->pdev);
1573 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1574 jme->dev->irq = jme->pdev->irq;
cd0ff491 1575 }
fcf45b4c
GFT
1576}
1577
3bf61c55
GFT
1578static int
1579jme_open(struct net_device *netdev)
d7699f87
GFT
1580{
1581 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1582 int rc;
79ce639c 1583
42b1055e 1584 jme_clear_pm(jme);
cdcdc9eb 1585 JME_NAPI_ENABLE(jme);
d7699f87 1586
fa97b924 1587 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT
1588 tasklet_enable(&jme->txclean_task);
1589 tasklet_hi_enable(&jme->rxclean_task);
1590 tasklet_hi_enable(&jme->rxempty_task);
1591
79ce639c 1592 rc = jme_request_irq(jme);
cd0ff491 1593 if (rc)
4330c2f2 1594 goto err_out;
79ce639c 1595
d7699f87 1596 jme_start_irq(jme);
42b1055e 1597
cd0ff491 1598 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e
GFT
1599 jme_set_settings(netdev, &jme->old_ecmd);
1600 else
1601 jme_reset_phy_processor(jme);
1602
29bdd921 1603 jme_reset_link(jme);
d7699f87
GFT
1604
1605 return 0;
1606
d7699f87
GFT
1607err_out:
1608 netif_stop_queue(netdev);
1609 netif_carrier_off(netdev);
4330c2f2 1610 return rc;
d7699f87
GFT
1611}
1612
9b9d55de 1613#ifdef CONFIG_PM
42b1055e
GFT
1614static void
1615jme_set_100m_half(struct jme_adapter *jme)
1616{
cd0ff491 1617 u32 bmcr, tmp;
42b1055e
GFT
1618
1619 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1620 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1621 BMCR_SPEED1000 | BMCR_FULLDPLX);
1622 tmp |= BMCR_SPEED100;
1623
1624 if (bmcr != tmp)
1625 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1626
cd0ff491 1627 if (jme->fpgaver)
cdcdc9eb
GFT
1628 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1629 else
1630 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1631}
1632
47220951
GFT
1633#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1634static void
1635jme_wait_link(struct jme_adapter *jme)
1636{
cd0ff491 1637 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1638
1639 mdelay(1000);
1640 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1641 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1642 mdelay(10);
1643 phylink = jme_linkstat_from_phy(jme);
1644 }
1645}
9b9d55de 1646#endif
47220951 1647
cd0ff491 1648static inline void
42b1055e
GFT
1649jme_phy_off(struct jme_adapter *jme)
1650{
1651 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1652}
1653
3bf61c55
GFT
1654static int
1655jme_close(struct net_device *netdev)
d7699f87
GFT
1656{
1657 struct jme_adapter *jme = netdev_priv(netdev);
1658
1659 netif_stop_queue(netdev);
1660 netif_carrier_off(netdev);
1661
1662 jme_stop_irq(jme);
79ce639c 1663 jme_free_irq(jme);
d7699f87 1664
cdcdc9eb 1665 JME_NAPI_DISABLE(jme);
192570e0 1666
fa97b924
GFT
1667 tasklet_disable(&jme->linkch_task);
1668 tasklet_disable(&jme->txclean_task);
1669 tasklet_disable(&jme->rxclean_task);
1670 tasklet_disable(&jme->rxempty_task);
8c198884 1671
cd0ff491
GFT
1672 jme_reset_ghc_speed(jme);
1673 jme_disable_rx_engine(jme);
1674 jme_disable_tx_engine(jme);
8c198884 1675 jme_reset_mac_processor(jme);
d7699f87
GFT
1676 jme_free_rx_resources(jme);
1677 jme_free_tx_resources(jme);
42b1055e 1678 jme->phylink = 0;
b3821cc5
GFT
1679 jme_phy_off(jme);
1680
1681 return 0;
1682}
1683
1684static int
1685jme_alloc_txdesc(struct jme_adapter *jme,
1686 struct sk_buff *skb)
1687{
fa97b924 1688 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1689 int idx, nr_alloc, mask = jme->tx_ring_mask;
1690
1691 idx = txring->next_to_use;
1692 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1693
cd0ff491 1694 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1695 return -1;
1696
1697 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1698
b3821cc5
GFT
1699 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1700
1701 return idx;
1702}
1703
1704static void
1705jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1706 struct txdesc *txdesc,
b3821cc5
GFT
1707 struct jme_buffer_info *txbi,
1708 struct page *page,
cd0ff491
GFT
1709 u32 page_offset,
1710 u32 len,
1711 u8 hidma)
b3821cc5
GFT
1712{
1713 dma_addr_t dmaaddr;
1714
1715 dmaaddr = pci_map_page(pdev,
1716 page,
1717 page_offset,
1718 len,
1719 PCI_DMA_TODEVICE);
1720
1721 pci_dma_sync_single_for_device(pdev,
1722 dmaaddr,
1723 len,
1724 PCI_DMA_TODEVICE);
1725
1726 txdesc->dw[0] = 0;
1727 txdesc->dw[1] = 0;
1728 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1729 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1730 txdesc->desc2.datalen = cpu_to_le16(len);
1731 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1732 txdesc->desc2.bufaddrl = cpu_to_le32(
1733 (__u64)dmaaddr & 0xFFFFFFFFUL);
1734
1735 txbi->mapping = dmaaddr;
1736 txbi->len = len;
1737}
1738
1739static void
1740jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1741{
fa97b924 1742 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1743 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1744 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1745 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1746 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1747 int mask = jme->tx_ring_mask;
1748 struct skb_frag_struct *frag;
cd0ff491 1749 u32 len;
b3821cc5 1750
cd0ff491
GFT
1751 for (i = 0 ; i < nr_frags ; ++i) {
1752 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1753 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1754 ctxbi = txbi + ((idx + i + 2) & (mask));
1755
1756 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1757 frag->page_offset, frag->size, hidma);
42b1055e 1758 }
b3821cc5 1759
cd0ff491 1760 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1761 ctxdesc = txdesc + ((idx + 1) & (mask));
1762 ctxbi = txbi + ((idx + 1) & (mask));
1763 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1764 offset_in_page(skb->data), len, hidma);
1765
1766}
1767
1768static int
1769jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1770{
cd0ff491 1771 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT
1772 skb_header_cloned(skb) &&
1773 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1774 dev_kfree_skb(skb);
1775 return -1;
1776 }
1777
1778 return 0;
1779}
1780
1781static int
94c5ea02 1782jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1783{
94c5ea02 1784 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1785 if (*mss) {
b3821cc5
GFT
1786 *flags |= TXFLAG_LSEN;
1787
cd0ff491 1788 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1789 struct iphdr *iph = ip_hdr(skb);
1790
1791 iph->check = 0;
cd0ff491 1792 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1793 iph->daddr, 0,
1794 IPPROTO_TCP,
1795 0);
cd0ff491 1796 } else {
b3821cc5
GFT
1797 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1798
cd0ff491 1799 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1800 &ip6h->daddr, 0,
1801 IPPROTO_TCP,
1802 0);
1803 }
1804
1805 return 0;
1806 }
1807
1808 return 1;
1809}
1810
1811static void
cd0ff491 1812jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1813{
cd0ff491
GFT
1814 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1815 u8 ip_proto;
b3821cc5
GFT
1816
1817 switch (skb->protocol) {
cd0ff491 1818 case htons(ETH_P_IP):
b3821cc5
GFT
1819 ip_proto = ip_hdr(skb)->protocol;
1820 break;
cd0ff491 1821 case htons(ETH_P_IPV6):
b3821cc5
GFT
1822 ip_proto = ipv6_hdr(skb)->nexthdr;
1823 break;
1824 default:
1825 ip_proto = 0;
1826 break;
1827 }
1828
cd0ff491 1829 switch (ip_proto) {
b3821cc5
GFT
1830 case IPPROTO_TCP:
1831 *flags |= TXFLAG_TCPCS;
1832 break;
1833 case IPPROTO_UDP:
1834 *flags |= TXFLAG_UDPCS;
1835 break;
1836 default:
c97b5740 1837 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
b3821cc5
GFT
1838 break;
1839 }
1840 }
1841}
1842
cd0ff491 1843static inline void
94c5ea02 1844jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 1845{
cd0ff491 1846 if (vlan_tx_tag_present(skb)) {
b3821cc5 1847 *flags |= TXFLAG_TAGON;
94c5ea02 1848 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 1849 }
b3821cc5
GFT
1850}
1851
1852static int
94c5ea02 1853jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 1854{
fa97b924 1855 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1856 struct txdesc *txdesc;
b3821cc5 1857 struct jme_buffer_info *txbi;
cd0ff491 1858 u8 flags;
b3821cc5 1859
cd0ff491 1860 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
1861 txbi = txring->bufinf + idx;
1862
1863 txdesc->dw[0] = 0;
1864 txdesc->dw[1] = 0;
1865 txdesc->dw[2] = 0;
1866 txdesc->dw[3] = 0;
1867 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1868 /*
1869 * Set OWN bit at final.
1870 * When kernel transmit faster than NIC.
1871 * And NIC trying to send this descriptor before we tell
1872 * it to start sending this TX queue.
1873 * Other fields are already filled correctly.
1874 */
1875 wmb();
1876 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
1877 /*
1878 * Set checksum flags while not tso
1879 */
1880 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1881 jme_tx_csum(jme, skb, &flags);
b3821cc5 1882 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 1883 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT
1884 txdesc->desc1.flags = flags;
1885 /*
1886 * Set tx buffer info after telling NIC to send
1887 * For better tx_clean timing
1888 */
1889 wmb();
1890 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1891 txbi->skb = skb;
1892 txbi->len = skb->len;
cd0ff491
GFT
1893 txbi->start_xmit = jiffies;
1894 if (!txbi->start_xmit)
8d27293f 1895 txbi->start_xmit = (0UL-1);
d7699f87
GFT
1896
1897 return 0;
1898}
1899
b3821cc5
GFT
1900static void
1901jme_stop_queue_if_full(struct jme_adapter *jme)
1902{
fa97b924 1903 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT
1904 struct jme_buffer_info *txbi = txring->bufinf;
1905 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 1906
cd0ff491 1907 txbi += idx;
b3821cc5
GFT
1908
1909 smp_wmb();
cd0ff491 1910 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 1911 netif_stop_queue(jme->dev);
c97b5740 1912 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
b3821cc5 1913 smp_wmb();
cd0ff491
GFT
1914 if (atomic_read(&txring->nr_free)
1915 >= (jme->tx_wake_threshold)) {
b3821cc5 1916 netif_wake_queue(jme->dev);
c97b5740 1917 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
b3821cc5
GFT
1918 }
1919 }
1920
cd0ff491 1921 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
1922 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1923 txbi->skb)) {
1924 netif_stop_queue(jme->dev);
c97b5740 1925 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
cdcdc9eb 1926 }
b3821cc5
GFT
1927}
1928
3bf61c55
GFT
1929/*
1930 * This function is already protected by netif_tx_lock()
1931 */
cd0ff491 1932
c97b5740 1933static netdev_tx_t
3bf61c55 1934jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 1935{
cd0ff491 1936 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 1937 int idx;
d7699f87 1938
cd0ff491 1939 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
1940 ++(NET_STAT(jme).tx_dropped);
1941 return NETDEV_TX_OK;
1942 }
1943
1944 idx = jme_alloc_txdesc(jme, skb);
79ce639c 1945
cd0ff491 1946 if (unlikely(idx < 0)) {
b3821cc5 1947 netif_stop_queue(netdev);
c97b5740 1948 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
d7699f87 1949
cd0ff491 1950 return NETDEV_TX_BUSY;
b3821cc5
GFT
1951 }
1952
94c5ea02 1953 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 1954
4330c2f2
GFT
1955 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1956 TXCS_SELECT_QUEUE0 |
1957 TXCS_QUEUE0S |
1958 TXCS_ENABLE);
d7699f87 1959
cd0ff491
GFT
1960 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1961 skb_shinfo(skb)->nr_frags + 2,
1962 jiffies);
b3821cc5
GFT
1963 jme_stop_queue_if_full(jme);
1964
cd0ff491 1965 return NETDEV_TX_OK;
d7699f87
GFT
1966}
1967
3bf61c55
GFT
1968static int
1969jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 1970{
cd0ff491 1971 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1972 struct sockaddr *addr = p;
cd0ff491 1973 u32 val;
d7699f87 1974
cd0ff491 1975 if (netif_running(netdev))
d7699f87
GFT
1976 return -EBUSY;
1977
cd0ff491 1978 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT
1979 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1980
186fc259
GFT
1981 val = (addr->sa_data[3] & 0xff) << 24 |
1982 (addr->sa_data[2] & 0xff) << 16 |
1983 (addr->sa_data[1] & 0xff) << 8 |
1984 (addr->sa_data[0] & 0xff);
4330c2f2 1985 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
1986 val = (addr->sa_data[5] & 0xff) << 8 |
1987 (addr->sa_data[4] & 0xff);
4330c2f2 1988 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 1989 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
1990
1991 return 0;
1992}
1993
3bf61c55
GFT
1994static void
1995jme_set_multi(struct net_device *netdev)
d7699f87 1996{
3bf61c55 1997 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1998 u32 mc_hash[2] = {};
d7699f87 1999
cd0ff491 2000 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
2001
2002 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2003
cd0ff491 2004 if (netdev->flags & IFF_PROMISC) {
8c198884 2005 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2006 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2007 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2008 } else if (netdev->flags & IFF_MULTICAST) {
d401cb9a 2009 struct netdev_hw_addr *ha;
3bf61c55 2010 int bit_nr;
d7699f87 2011
8c198884 2012 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
d401cb9a
JP
2013 netdev_for_each_mc_addr(ha, netdev) {
2014 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
cd0ff491
GFT
2015 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2016 }
d7699f87 2017
4330c2f2
GFT
2018 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2019 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2020 }
2021
d7699f87 2022 wmb();
8c198884
GFT
2023 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2024
cd0ff491 2025 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2026}
2027
3bf61c55 2028static int
8c198884 2029jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2030{
cd0ff491 2031 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2032
cd0ff491 2033 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2034 return 0;
2035
cd0ff491
GFT
2036 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2037 ((new_mtu) < IPV6_MIN_MTU))
2038 return -EINVAL;
79ce639c 2039
cd0ff491 2040 if (new_mtu > 4000) {
79ce639c
GFT
2041 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2042 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2043 jme_restart_rx_engine(jme);
cd0ff491 2044 } else {
79ce639c
GFT
2045 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2046 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2047 jme_restart_rx_engine(jme);
2048 }
2049
cd0ff491 2050 if (new_mtu > 1900) {
b3821cc5
GFT
2051 netdev->features &= ~(NETIF_F_HW_CSUM |
2052 NETIF_F_TSO |
2053 NETIF_F_TSO6);
cd0ff491
GFT
2054 } else {
2055 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
b3821cc5 2056 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491 2057 if (test_bit(JME_FLAG_TSO, &jme->flags))
b3821cc5 2058 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT
2059 }
2060
cd0ff491
GFT
2061 netdev->mtu = new_mtu;
2062 jme_reset_link(jme);
79ce639c
GFT
2063
2064 return 0;
d7699f87
GFT
2065}
2066
3bf61c55 2067static void
8c198884
GFT
2068jme_tx_timeout(struct net_device *netdev)
2069{
cd0ff491 2070 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2071
cdcdc9eb
GFT
2072 jme->phylink = 0;
2073 jme_reset_phy_processor(jme);
cd0ff491 2074 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2075 jme_set_settings(netdev, &jme->old_ecmd);
2076
8c198884 2077 /*
cdcdc9eb 2078 * Force to Reset the link again
8c198884 2079 */
29bdd921 2080 jme_reset_link(jme);
8c198884
GFT
2081}
2082
f7f428e4
GFT
2083static inline void jme_pause_rx(struct jme_adapter *jme)
2084{
2085 atomic_dec(&jme->link_changing);
2086
2087 jme_set_rx_pcc(jme, PCC_OFF);
2088 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2089 JME_NAPI_DISABLE(jme);
2090 } else {
2091 tasklet_disable(&jme->rxclean_task);
2092 tasklet_disable(&jme->rxempty_task);
2093 }
2094}
2095
2096static inline void jme_resume_rx(struct jme_adapter *jme)
2097{
2098 struct dynpcc_info *dpi = &(jme->dpi);
2099
2100 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2101 JME_NAPI_ENABLE(jme);
2102 } else {
2103 tasklet_hi_enable(&jme->rxclean_task);
2104 tasklet_hi_enable(&jme->rxempty_task);
2105 }
2106 dpi->cur = PCC_P1;
2107 dpi->attempt = PCC_P1;
2108 dpi->cnt = 0;
2109 jme_set_rx_pcc(jme, PCC_P1);
2110
2111 atomic_inc(&jme->link_changing);
2112}
2113
8c198884 2114static void
42b1055e
GFT
2115jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2116{
2117 struct jme_adapter *jme = netdev_priv(netdev);
2118
f7f428e4 2119 jme_pause_rx(jme);
42b1055e 2120 jme->vlgrp = grp;
f7f428e4 2121 jme_resume_rx(jme);
42b1055e
GFT
2122}
2123
2124static void
3bf61c55
GFT
2125jme_get_drvinfo(struct net_device *netdev,
2126 struct ethtool_drvinfo *info)
d7699f87 2127{
cd0ff491 2128 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2129
cd0ff491
GFT
2130 strcpy(info->driver, DRV_NAME);
2131 strcpy(info->version, DRV_VERSION);
2132 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2133}
2134
3bf61c55 2135static int
8c198884
GFT
2136jme_get_regs_len(struct net_device *netdev)
2137{
cd0ff491 2138 return JME_REG_LEN;
8c198884
GFT
2139}
2140
2141static void
cd0ff491 2142mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2143{
2144 int i;
2145
cd0ff491 2146 for (i = 0 ; i < len ; i += 4)
79ce639c 2147 p[i >> 2] = jread32(jme, reg + i);
186fc259 2148}
8c198884 2149
186fc259 2150static void
cd0ff491 2151mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2152{
2153 int i;
cd0ff491 2154 u16 *p16 = (u16 *)p;
186fc259 2155
cd0ff491 2156 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2157 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2158}
2159
2160static void
2161jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2162{
cd0ff491
GFT
2163 struct jme_adapter *jme = netdev_priv(netdev);
2164 u32 *p32 = (u32 *)p;
8c198884 2165
186fc259 2166 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2167
2168 regs->version = 1;
2169 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2170
2171 p32 += 0x100 >> 2;
2172 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2173
2174 p32 += 0x100 >> 2;
2175 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2176
2177 p32 += 0x100 >> 2;
2178 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2179
186fc259
GFT
2180 p32 += 0x100 >> 2;
2181 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2182}
2183
2184static int
2185jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2186{
2187 struct jme_adapter *jme = netdev_priv(netdev);
2188
8c198884
GFT
2189 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2190 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2191
cd0ff491 2192 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2193 ecmd->use_adaptive_rx_coalesce = false;
2194 ecmd->rx_coalesce_usecs = 0;
2195 ecmd->rx_max_coalesced_frames = 0;
2196 return 0;
2197 }
2198
2199 ecmd->use_adaptive_rx_coalesce = true;
2200
cd0ff491 2201 switch (jme->dpi.cur) {
8c198884
GFT
2202 case PCC_P1:
2203 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2204 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2205 break;
2206 case PCC_P2:
2207 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2208 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2209 break;
2210 case PCC_P3:
2211 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2212 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2213 break;
2214 default:
2215 break;
2216 }
2217
2218 return 0;
2219}
2220
192570e0
GFT
2221static int
2222jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2223{
2224 struct jme_adapter *jme = netdev_priv(netdev);
2225 struct dynpcc_info *dpi = &(jme->dpi);
2226
cd0ff491 2227 if (netif_running(netdev))
cdcdc9eb
GFT
2228 return -EBUSY;
2229
c97b5740
GFT
2230 if (ecmd->use_adaptive_rx_coalesce &&
2231 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2232 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2233 jme->jme_rx = netif_rx;
2234 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2235 dpi->cur = PCC_P1;
2236 dpi->attempt = PCC_P1;
2237 dpi->cnt = 0;
2238 jme_set_rx_pcc(jme, PCC_P1);
2239 jme_interrupt_mode(jme);
c97b5740
GFT
2240 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2241 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2242 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2243 jme->jme_rx = netif_receive_skb;
2244 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2245 jme_interrupt_mode(jme);
2246 }
2247
2248 return 0;
2249}
2250
8c198884
GFT
2251static void
2252jme_get_pauseparam(struct net_device *netdev,
2253 struct ethtool_pauseparam *ecmd)
2254{
2255 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2256 u32 val;
8c198884
GFT
2257
2258 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2259 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2260
cd0ff491
GFT
2261 spin_lock_bh(&jme->phy_lock);
2262 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2263 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2264
2265 ecmd->autoneg =
2266 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2267}
2268
2269static int
2270jme_set_pauseparam(struct net_device *netdev,
2271 struct ethtool_pauseparam *ecmd)
2272{
2273 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2274 u32 val;
8c198884 2275
cd0ff491 2276 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2277 (ecmd->tx_pause != 0)) {
2278
cd0ff491 2279 if (ecmd->tx_pause)
8c198884
GFT
2280 jme->reg_txpfc |= TXPFC_PF_EN;
2281 else
2282 jme->reg_txpfc &= ~TXPFC_PF_EN;
2283
2284 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2285 }
2286
cd0ff491
GFT
2287 spin_lock_bh(&jme->rxmcs_lock);
2288 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2289 (ecmd->rx_pause != 0)) {
2290
cd0ff491 2291 if (ecmd->rx_pause)
8c198884
GFT
2292 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2293 else
2294 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2295
2296 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2297 }
cd0ff491 2298 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2299
cd0ff491
GFT
2300 spin_lock_bh(&jme->phy_lock);
2301 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2302 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2303 (ecmd->autoneg != 0)) {
2304
cd0ff491 2305 if (ecmd->autoneg)
8c198884
GFT
2306 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2307 else
2308 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2309
b3821cc5
GFT
2310 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2311 MII_ADVERTISE, val);
8c198884 2312 }
cd0ff491 2313 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2314
2315 return 0;
2316}
2317
29bdd921
GFT
2318static void
2319jme_get_wol(struct net_device *netdev,
2320 struct ethtool_wolinfo *wol)
2321{
2322 struct jme_adapter *jme = netdev_priv(netdev);
2323
2324 wol->supported = WAKE_MAGIC | WAKE_PHY;
2325
2326 wol->wolopts = 0;
2327
cd0ff491 2328 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2329 wol->wolopts |= WAKE_PHY;
2330
cd0ff491 2331 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2332 wol->wolopts |= WAKE_MAGIC;
2333
2334}
2335
2336static int
2337jme_set_wol(struct net_device *netdev,
2338 struct ethtool_wolinfo *wol)
2339{
2340 struct jme_adapter *jme = netdev_priv(netdev);
2341
cd0ff491 2342 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2343 WAKE_UCAST |
2344 WAKE_MCAST |
2345 WAKE_BCAST |
2346 WAKE_ARP))
2347 return -EOPNOTSUPP;
2348
2349 jme->reg_pmcs = 0;
2350
cd0ff491 2351 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2352 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2353
cd0ff491 2354 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2355 jme->reg_pmcs |= PMCS_MFEN;
2356
cd0ff491 2357 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2358
29bdd921
GFT
2359 return 0;
2360}
b3821cc5 2361
8c198884 2362static int
3bf61c55
GFT
2363jme_get_settings(struct net_device *netdev,
2364 struct ethtool_cmd *ecmd)
d7699f87
GFT
2365{
2366 struct jme_adapter *jme = netdev_priv(netdev);
2367 int rc;
8c198884 2368
cd0ff491 2369 spin_lock_bh(&jme->phy_lock);
d7699f87 2370 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2371 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2372 return rc;
2373}
2374
3bf61c55
GFT
2375static int
2376jme_set_settings(struct net_device *netdev,
2377 struct ethtool_cmd *ecmd)
d7699f87
GFT
2378{
2379 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2380 int rc, fdc = 0;
fcf45b4c 2381
cd0ff491 2382 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2383 return -EINVAL;
2384
cd0ff491 2385 if (jme->mii_if.force_media &&
79ce639c
GFT
2386 ecmd->autoneg != AUTONEG_ENABLE &&
2387 (jme->mii_if.full_duplex != ecmd->duplex))
2388 fdc = 1;
2389
cd0ff491 2390 spin_lock_bh(&jme->phy_lock);
d7699f87 2391 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2392 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2393
cd0ff491 2394 if (!rc && fdc)
79ce639c
GFT
2395 jme_reset_link(jme);
2396
cd0ff491
GFT
2397 if (!rc) {
2398 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2399 jme->old_ecmd = *ecmd;
2400 }
2401
d7699f87
GFT
2402 return rc;
2403}
2404
cd0ff491 2405static u32
3bf61c55
GFT
2406jme_get_link(struct net_device *netdev)
2407{
d7699f87
GFT
2408 struct jme_adapter *jme = netdev_priv(netdev);
2409 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2410}
2411
8c198884 2412static u32
cd0ff491
GFT
2413jme_get_msglevel(struct net_device *netdev)
2414{
2415 struct jme_adapter *jme = netdev_priv(netdev);
2416 return jme->msg_enable;
2417}
2418
2419static void
2420jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2421{
cd0ff491
GFT
2422 struct jme_adapter *jme = netdev_priv(netdev);
2423 jme->msg_enable = value;
2424}
8c198884 2425
cd0ff491
GFT
2426static u32
2427jme_get_rx_csum(struct net_device *netdev)
2428{
2429 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2430 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2431}
2432
2433static int
2434jme_set_rx_csum(struct net_device *netdev, u32 on)
2435{
cd0ff491 2436 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2437
cd0ff491
GFT
2438 spin_lock_bh(&jme->rxmcs_lock);
2439 if (on)
8c198884
GFT
2440 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2441 else
2442 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2443 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2444 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2445
2446 return 0;
2447}
2448
2449static int
2450jme_set_tx_csum(struct net_device *netdev, u32 on)
2451{
cd0ff491 2452 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2453
cd0ff491
GFT
2454 if (on) {
2455 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2456 if (netdev->mtu <= 1900)
b3821cc5 2457 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491
GFT
2458 } else {
2459 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
8c198884 2460 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2461 }
8c198884
GFT
2462
2463 return 0;
2464}
2465
2466static int
b3821cc5
GFT
2467jme_set_tso(struct net_device *netdev, u32 on)
2468{
cd0ff491 2469 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2470
cd0ff491
GFT
2471 if (on) {
2472 set_bit(JME_FLAG_TSO, &jme->flags);
2473 if (netdev->mtu <= 1900)
b3821cc5 2474 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT
2475 } else {
2476 clear_bit(JME_FLAG_TSO, &jme->flags);
2477 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT
2478 }
2479
cd0ff491 2480 return 0;
b3821cc5
GFT
2481}
2482
2483static int
8c198884
GFT
2484jme_nway_reset(struct net_device *netdev)
2485{
cd0ff491 2486 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2487 jme_restart_an(jme);
2488 return 0;
2489}
2490
cd0ff491 2491static u8
186fc259
GFT
2492jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2493{
cd0ff491 2494 u32 val;
186fc259
GFT
2495 int to;
2496
2497 val = jread32(jme, JME_SMBCSR);
2498 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2499 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2500 msleep(1);
2501 val = jread32(jme, JME_SMBCSR);
2502 }
cd0ff491 2503 if (!to) {
c97b5740 2504 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
186fc259
GFT
2505 return 0xFF;
2506 }
2507
2508 jwrite32(jme, JME_SMBINTF,
2509 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2510 SMBINTF_HWRWN_READ |
2511 SMBINTF_HWCMD);
2512
2513 val = jread32(jme, JME_SMBINTF);
2514 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2515 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2516 msleep(1);
2517 val = jread32(jme, JME_SMBINTF);
2518 }
cd0ff491 2519 if (!to) {
c97b5740 2520 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
186fc259
GFT
2521 return 0xFF;
2522 }
2523
2524 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2525}
2526
2527static void
cd0ff491 2528jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2529{
cd0ff491 2530 u32 val;
186fc259
GFT
2531 int to;
2532
2533 val = jread32(jme, JME_SMBCSR);
2534 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2535 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2536 msleep(1);
2537 val = jread32(jme, JME_SMBCSR);
2538 }
cd0ff491 2539 if (!to) {
c97b5740 2540 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
186fc259
GFT
2541 return;
2542 }
2543
2544 jwrite32(jme, JME_SMBINTF,
2545 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2546 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2547 SMBINTF_HWRWN_WRITE |
2548 SMBINTF_HWCMD);
2549
2550 val = jread32(jme, JME_SMBINTF);
2551 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2552 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2553 msleep(1);
2554 val = jread32(jme, JME_SMBINTF);
2555 }
cd0ff491 2556 if (!to) {
c97b5740 2557 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
186fc259
GFT
2558 return;
2559 }
2560
2561 mdelay(2);
2562}
2563
2564static int
2565jme_get_eeprom_len(struct net_device *netdev)
2566{
cd0ff491
GFT
2567 struct jme_adapter *jme = netdev_priv(netdev);
2568 u32 val;
186fc259 2569 val = jread32(jme, JME_SMBCSR);
cd0ff491 2570 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2571}
2572
2573static int
2574jme_get_eeprom(struct net_device *netdev,
2575 struct ethtool_eeprom *eeprom, u8 *data)
2576{
cd0ff491 2577 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2578 int i, offset = eeprom->offset, len = eeprom->len;
2579
2580 /*
8d27293f 2581 * ethtool will check the boundary for us
186fc259
GFT
2582 */
2583 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2584 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2585 data[i] = jme_smb_read(jme, i + offset);
2586
2587 return 0;
2588}
2589
2590static int
2591jme_set_eeprom(struct net_device *netdev,
2592 struct ethtool_eeprom *eeprom, u8 *data)
2593{
cd0ff491 2594 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2595 int i, offset = eeprom->offset, len = eeprom->len;
2596
2597 if (eeprom->magic != JME_EEPROM_MAGIC)
2598 return -EINVAL;
2599
2600 /*
8d27293f 2601 * ethtool will check the boundary for us
186fc259 2602 */
cd0ff491 2603 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2604 jme_smb_write(jme, i + offset, data[i]);
2605
2606 return 0;
2607}
2608
d7699f87 2609static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2610 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2611 .get_regs_len = jme_get_regs_len,
2612 .get_regs = jme_get_regs,
2613 .get_coalesce = jme_get_coalesce,
192570e0 2614 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2615 .get_pauseparam = jme_get_pauseparam,
2616 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2617 .get_wol = jme_get_wol,
2618 .set_wol = jme_set_wol,
d7699f87
GFT
2619 .get_settings = jme_get_settings,
2620 .set_settings = jme_set_settings,
2621 .get_link = jme_get_link,
cd0ff491
GFT
2622 .get_msglevel = jme_get_msglevel,
2623 .set_msglevel = jme_set_msglevel,
8c198884
GFT
2624 .get_rx_csum = jme_get_rx_csum,
2625 .set_rx_csum = jme_set_rx_csum,
2626 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2627 .set_tso = jme_set_tso,
2628 .set_sg = ethtool_op_set_sg,
8c198884 2629 .nway_reset = jme_nway_reset,
186fc259
GFT
2630 .get_eeprom_len = jme_get_eeprom_len,
2631 .get_eeprom = jme_get_eeprom,
2632 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2633};
2634
3bf61c55
GFT
2635static int
2636jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2637{
94c5ea02 2638 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT
2639 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2640 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT
2641 return 1;
2642
94c5ea02 2643 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT
2644 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2645 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT
2646 return 1;
2647
fa97b924
GFT
2648 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2649 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT
2650 return 0;
2651
2652 return -1;
2653}
2654
cd0ff491 2655static inline void
cdcdc9eb
GFT
2656jme_phy_init(struct jme_adapter *jme)
2657{
cd0ff491 2658 u16 reg26;
cdcdc9eb
GFT
2659
2660 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2661 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2662}
2663
cd0ff491 2664static inline void
cdcdc9eb 2665jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2666{
cd0ff491 2667 u32 chipmode;
cdcdc9eb
GFT
2668
2669 chipmode = jread32(jme, JME_CHIPMODE);
2670
2671 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2672 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
42b1055e
GFT
2673}
2674
94c5ea02
GFT
2675static const struct net_device_ops jme_netdev_ops = {
2676 .ndo_open = jme_open,
2677 .ndo_stop = jme_close,
2678 .ndo_validate_addr = eth_validate_addr,
2679 .ndo_start_xmit = jme_start_xmit,
2680 .ndo_set_mac_address = jme_set_macaddr,
2681 .ndo_set_multicast_list = jme_set_multi,
2682 .ndo_change_mtu = jme_change_mtu,
2683 .ndo_tx_timeout = jme_tx_timeout,
2684 .ndo_vlan_rx_register = jme_vlan_rx_register,
2685};
2686
3bf61c55
GFT
2687static int __devinit
2688jme_init_one(struct pci_dev *pdev,
2689 const struct pci_device_id *ent)
2690{
cdcdc9eb 2691 int rc = 0, using_dac, i;
d7699f87
GFT
2692 struct net_device *netdev;
2693 struct jme_adapter *jme;
cd0ff491
GFT
2694 u16 bmcr, bmsr;
2695 u32 apmc;
d7699f87
GFT
2696
2697 /*
2698 * set up PCI device basics
2699 */
4330c2f2 2700 rc = pci_enable_device(pdev);
cd0ff491
GFT
2701 if (rc) {
2702 jeprintk(pdev, "Cannot enable PCI device.\n");
4330c2f2
GFT
2703 goto err_out;
2704 }
d7699f87 2705
3bf61c55 2706 using_dac = jme_pci_dma64(pdev);
cd0ff491
GFT
2707 if (using_dac < 0) {
2708 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
3bf61c55
GFT
2709 rc = -EIO;
2710 goto err_out_disable_pdev;
2711 }
2712
cd0ff491
GFT
2713 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2714 jeprintk(pdev, "No PCI resource region found.\n");
4330c2f2
GFT
2715 rc = -ENOMEM;
2716 goto err_out_disable_pdev;
2717 }
d7699f87 2718
4330c2f2 2719 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491
GFT
2720 if (rc) {
2721 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
4330c2f2
GFT
2722 goto err_out_disable_pdev;
2723 }
d7699f87
GFT
2724
2725 pci_set_master(pdev);
2726
2727 /*
2728 * alloc and init net device
2729 */
3bf61c55 2730 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491
GFT
2731 if (!netdev) {
2732 jeprintk(pdev, "Cannot allocate netdev structure.\n");
4330c2f2
GFT
2733 rc = -ENOMEM;
2734 goto err_out_release_regions;
d7699f87 2735 }
94c5ea02 2736 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2737 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2738 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2739 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT
2740 NETIF_F_SG |
2741 NETIF_F_TSO |
2742 NETIF_F_TSO6 |
42b1055e
GFT
2743 NETIF_F_HW_VLAN_TX |
2744 NETIF_F_HW_VLAN_RX;
cd0ff491 2745 if (using_dac)
8c198884 2746 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2747
2748 SET_NETDEV_DEV(netdev, &pdev->dev);
2749 pci_set_drvdata(pdev, netdev);
2750
2751 /*
2752 * init adapter info
2753 */
2754 jme = netdev_priv(netdev);
2755 jme->pdev = pdev;
2756 jme->dev = netdev;
cdcdc9eb
GFT
2757 jme->jme_rx = netif_rx;
2758 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2759 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2760 jme->phylink = 0;
b3821cc5
GFT
2761 jme->tx_ring_size = 1 << 10;
2762 jme->tx_ring_mask = jme->tx_ring_size - 1;
2763 jme->tx_wake_threshold = 1 << 9;
2764 jme->rx_ring_size = 1 << 9;
2765 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2766 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
2767 jme->regs = ioremap(pci_resource_start(pdev, 0),
2768 pci_resource_len(pdev, 0));
4330c2f2 2769 if (!(jme->regs)) {
cd0ff491 2770 jeprintk(pdev, "Mapping PCI resource region error.\n");
d7699f87
GFT
2771 rc = -ENOMEM;
2772 goto err_out_free_netdev;
2773 }
4330c2f2 2774
cd0ff491
GFT
2775 if (no_pseudohp) {
2776 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2777 jwrite32(jme, JME_APMC, apmc);
2778 } else if (force_pseudohp) {
2779 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2780 jwrite32(jme, JME_APMC, apmc);
2781 }
2782
cdcdc9eb 2783 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2784
d7699f87 2785 spin_lock_init(&jme->phy_lock);
fcf45b4c 2786 spin_lock_init(&jme->macaddr_lock);
8c198884 2787 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2788
fcf45b4c
GFT
2789 atomic_set(&jme->link_changing, 1);
2790 atomic_set(&jme->rx_cleaning, 1);
2791 atomic_set(&jme->tx_cleaning, 1);
192570e0 2792 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2793
79ce639c 2794 tasklet_init(&jme->pcc_task,
c97b5740 2795 jme_pcc_tasklet,
79ce639c 2796 (unsigned long) jme);
4330c2f2 2797 tasklet_init(&jme->linkch_task,
c97b5740 2798 jme_link_change_tasklet,
4330c2f2
GFT
2799 (unsigned long) jme);
2800 tasklet_init(&jme->txclean_task,
c97b5740 2801 jme_tx_clean_tasklet,
4330c2f2
GFT
2802 (unsigned long) jme);
2803 tasklet_init(&jme->rxclean_task,
c97b5740 2804 jme_rx_clean_tasklet,
4330c2f2 2805 (unsigned long) jme);
fcf45b4c 2806 tasklet_init(&jme->rxempty_task,
c97b5740 2807 jme_rx_empty_tasklet,
fcf45b4c 2808 (unsigned long) jme);
fa97b924 2809 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT
2810 tasklet_disable_nosync(&jme->txclean_task);
2811 tasklet_disable_nosync(&jme->rxclean_task);
2812 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
2813 jme->dpi.cur = PCC_P1;
2814
cd0ff491 2815 jme->reg_ghc = 0;
79ce639c 2816 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
2817 jme->reg_rxmcs = RXMCS_DEFAULT;
2818 jme->reg_txpfc = 0;
47220951 2819 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT
2820 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2821 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 2822
d7699f87 2823 /*
fcf45b4c
GFT
2824 * Get Max Read Req Size from PCI Config Space
2825 */
cd0ff491
GFT
2826 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2827 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2828 switch (jme->mrrs) {
2829 case MRRS_128B:
2830 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2831 break;
2832 case MRRS_256B:
2833 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2834 break;
2835 default:
2836 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2837 break;
06527f9b 2838 }
fcf45b4c 2839
fcf45b4c 2840 /*
cdcdc9eb 2841 * Must check before reset_mac_processor
d7699f87 2842 */
cdcdc9eb
GFT
2843 jme_check_hw_ver(jme);
2844 jme->mii_if.dev = netdev;
cd0ff491 2845 if (jme->fpgaver) {
cdcdc9eb 2846 jme->mii_if.phy_id = 0;
cd0ff491 2847 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
2848 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2849 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 2850 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
2851 jme->mii_if.phy_id = i;
2852 break;
2853 }
2854 }
2855
cd0ff491 2856 if (!jme->mii_if.phy_id) {
cdcdc9eb 2857 rc = -EIO;
cd0ff491 2858 jeprintk(pdev, "Can not find phy_id.\n");
fa97b924 2859 goto err_out_unmap;
cdcdc9eb
GFT
2860 }
2861
2862 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 2863 } else {
cdcdc9eb
GFT
2864 jme->mii_if.phy_id = 1;
2865 }
cd0ff491 2866 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
2867 jme->mii_if.supports_gmii = true;
2868 else
2869 jme->mii_if.supports_gmii = false;
cdcdc9eb
GFT
2870 jme->mii_if.mdio_read = jme_mdio_read;
2871 jme->mii_if.mdio_write = jme_mdio_write;
2872
d7699f87 2873 jme_clear_pm(jme);
e882564f 2874 jme_set_phyfifoa(jme);
cd0ff491
GFT
2875 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2876 if (!jme->fpgaver)
cdcdc9eb 2877 jme_phy_init(jme);
42b1055e 2878 jme_phy_off(jme);
cdcdc9eb
GFT
2879
2880 /*
2881 * Reset MAC processor and reload EEPROM for MAC Address
2882 */
d7699f87 2883 jme_reset_mac_processor(jme);
4330c2f2 2884 rc = jme_reload_eeprom(jme);
cd0ff491
GFT
2885 if (rc) {
2886 jeprintk(pdev,
b3821cc5 2887 "Reload eeprom for reading MAC Address error.\n");
fa97b924 2888 goto err_out_unmap;
4330c2f2 2889 }
d7699f87
GFT
2890 jme_load_macaddr(netdev);
2891
d7699f87
GFT
2892 /*
2893 * Tell stack that we are not ready to work until open()
2894 */
2895 netif_carrier_off(netdev);
2896 netif_stop_queue(netdev);
2897
2898 /*
2899 * Register netdev
2900 */
4330c2f2 2901 rc = register_netdev(netdev);
cd0ff491
GFT
2902 if (rc) {
2903 jeprintk(pdev, "Cannot register net device.\n");
fa97b924 2904 goto err_out_unmap;
4330c2f2 2905 }
d7699f87 2906
c97b5740
GFT
2907 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2908 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2909 "JMC250 Gigabit Ethernet" :
2910 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2911 "JMC260 Fast Ethernet" : "Unknown",
2912 (jme->fpgaver != 0) ? " (FPGA)" : "",
2913 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2914 jme->rev, netdev->dev_addr);
d7699f87
GFT
2915
2916 return 0;
2917
2918err_out_unmap:
2919 iounmap(jme->regs);
2920err_out_free_netdev:
2921 pci_set_drvdata(pdev, NULL);
2922 free_netdev(netdev);
4330c2f2
GFT
2923err_out_release_regions:
2924 pci_release_regions(pdev);
d7699f87 2925err_out_disable_pdev:
cd0ff491 2926 pci_disable_device(pdev);
d7699f87 2927err_out:
4330c2f2 2928 return rc;
d7699f87
GFT
2929}
2930
3bf61c55
GFT
2931static void __devexit
2932jme_remove_one(struct pci_dev *pdev)
2933{
d7699f87
GFT
2934 struct net_device *netdev = pci_get_drvdata(pdev);
2935 struct jme_adapter *jme = netdev_priv(netdev);
2936
2937 unregister_netdev(netdev);
2938 iounmap(jme->regs);
2939 pci_set_drvdata(pdev, NULL);
2940 free_netdev(netdev);
2941 pci_release_regions(pdev);
2942 pci_disable_device(pdev);
2943
2944}
2945
9b9d55de 2946#ifdef CONFIG_PM
29bdd921
GFT
2947static int
2948jme_suspend(struct pci_dev *pdev, pm_message_t state)
2949{
2950 struct net_device *netdev = pci_get_drvdata(pdev);
2951 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
2952
2953 atomic_dec(&jme->link_changing);
2954
2955 netif_device_detach(netdev);
2956 netif_stop_queue(netdev);
2957 jme_stop_irq(jme);
29bdd921 2958
cd0ff491
GFT
2959 tasklet_disable(&jme->txclean_task);
2960 tasklet_disable(&jme->rxclean_task);
2961 tasklet_disable(&jme->rxempty_task);
2962
cd0ff491
GFT
2963 if (netif_carrier_ok(netdev)) {
2964 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
2965 jme_polling_mode(jme);
2966
29bdd921 2967 jme_stop_pcc_timer(jme);
cd0ff491
GFT
2968 jme_reset_ghc_speed(jme);
2969 jme_disable_rx_engine(jme);
2970 jme_disable_tx_engine(jme);
29bdd921
GFT
2971 jme_reset_mac_processor(jme);
2972 jme_free_rx_resources(jme);
2973 jme_free_tx_resources(jme);
2974 netif_carrier_off(netdev);
2975 jme->phylink = 0;
2976 }
2977
cd0ff491
GFT
2978 tasklet_enable(&jme->txclean_task);
2979 tasklet_hi_enable(&jme->rxclean_task);
2980 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT
2981
2982 pci_save_state(pdev);
cd0ff491 2983 if (jme->reg_pmcs) {
42b1055e 2984 jme_set_100m_half(jme);
47220951 2985
cd0ff491 2986 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
47220951
GFT
2987 jme_wait_link(jme);
2988
29bdd921 2989 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
cd0ff491 2990
42b1055e 2991 pci_enable_wake(pdev, PCI_D3cold, true);
cd0ff491 2992 } else {
42b1055e 2993 jme_phy_off(jme);
29bdd921 2994 }
cd0ff491 2995 pci_set_power_state(pdev, PCI_D3cold);
29bdd921
GFT
2996
2997 return 0;
2998}
2999
3000static int
3001jme_resume(struct pci_dev *pdev)
3002{
3003 struct net_device *netdev = pci_get_drvdata(pdev);
3004 struct jme_adapter *jme = netdev_priv(netdev);
3005
3006 jme_clear_pm(jme);
3007 pci_restore_state(pdev);
3008
cd0ff491 3009 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921
GFT
3010 jme_set_settings(netdev, &jme->old_ecmd);
3011 else
3012 jme_reset_phy_processor(jme);
3013
29bdd921
GFT
3014 jme_start_irq(jme);
3015 netif_device_attach(netdev);
3016
3017 atomic_inc(&jme->link_changing);
3018
3019 jme_reset_link(jme);
3020
3021 return 0;
3022}
9b9d55de 3023#endif
29bdd921 3024
c97b5740 3025static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
cd0ff491
GFT
3026 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3027 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3028 { }
3029};
3030
3031static struct pci_driver jme_driver = {
cd0ff491
GFT
3032 .name = DRV_NAME,
3033 .id_table = jme_pci_tbl,
3034 .probe = jme_init_one,
3035 .remove = __devexit_p(jme_remove_one),
d7699f87 3036#ifdef CONFIG_PM
cd0ff491
GFT
3037 .suspend = jme_suspend,
3038 .resume = jme_resume,
d7699f87 3039#endif /* CONFIG_PM */
d7699f87
GFT
3040};
3041
3bf61c55
GFT
3042static int __init
3043jme_init_module(void)
d7699f87 3044{
94c5ea02 3045 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
4330c2f2 3046 "driver version %s\n", DRV_VERSION);
d7699f87
GFT
3047 return pci_register_driver(&jme_driver);
3048}
3049
3bf61c55
GFT
3050static void __exit
3051jme_cleanup_module(void)
d7699f87
GFT
3052{
3053 pci_unregister_driver(&jme_driver);
3054}
3055
3056module_init(jme_init_module);
3057module_exit(jme_cleanup_module);
3058
3bf61c55 3059MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3060MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3061MODULE_LICENSE("GPL");
3062MODULE_VERSION(DRV_VERSION);
3063MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3064