jme: Prevent possible read re-order error
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
3bf61c55
GFT
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
d7699f87
GFT
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
52a46ba8
JP
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
d7699f87
GFT
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/mii.h>
33#include <linux/crc32.h>
4330c2f2 34#include <linux/delay.h>
29bdd921 35#include <linux/spinlock.h>
8c198884
GFT
36#include <linux/in.h>
37#include <linux/ip.h>
79ce639c
GFT
38#include <linux/ipv6.h>
39#include <linux/tcp.h>
40#include <linux/udp.h>
42b1055e 41#include <linux/if_vlan.h>
6d641c63 42#include <linux/slab.h>
94c5ea02 43#include <net/ip6_checksum.h>
d7699f87
GFT
44#include "jme.h"
45
cd0ff491
GFT
46static int force_pseudohp = -1;
47static int no_pseudohp = -1;
48static int no_extplug = -1;
49module_param(force_pseudohp, int, 0);
50MODULE_PARM_DESC(force_pseudohp,
51 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
52module_param(no_pseudohp, int, 0);
53MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
54module_param(no_extplug, int, 0);
55MODULE_PARM_DESC(no_extplug,
56 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 57
3bf61c55
GFT
58static int
59jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
60{
61 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 62 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 63
186fc259 64read_again:
cd0ff491 65 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
66 smi_phy_addr(phy) |
67 smi_reg_addr(reg));
d7699f87
GFT
68
69 wmb();
cd0ff491 70 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 71 udelay(20);
b3821cc5
GFT
72 val = jread32(jme, JME_SMI);
73 if ((val & SMI_OP_REQ) == 0)
3bf61c55 74 break;
cd0ff491 75 }
d7699f87 76
cd0ff491 77 if (i == 0) {
52a46ba8 78 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 79 return 0;
cd0ff491 80 }
d7699f87 81
cd0ff491 82 if (again--)
186fc259
GFT
83 goto read_again;
84
cd0ff491 85 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
86}
87
3bf61c55
GFT
88static void
89jme_mdio_write(struct net_device *netdev,
90 int phy, int reg, int val)
d7699f87
GFT
91{
92 struct jme_adapter *jme = netdev_priv(netdev);
93 int i;
94
3bf61c55
GFT
95 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
96 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
97 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT
98
99 wmb();
cdcdc9eb
GFT
100 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
101 udelay(20);
8d27293f 102 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
103 break;
104 }
d7699f87 105
3bf61c55 106 if (i == 0)
52a46ba8 107 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT
108}
109
cd0ff491 110static inline void
3bf61c55 111jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 112{
cd0ff491 113 u32 val;
3bf61c55
GFT
114
115 jme_mdio_write(jme->dev,
116 jme->mii_if.phy_id,
8c198884
GFT
117 MII_ADVERTISE, ADVERTISE_ALL |
118 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 119
cd0ff491 120 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
121 jme_mdio_write(jme->dev,
122 jme->mii_if.phy_id,
123 MII_CTRL1000,
124 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 125
fcf45b4c
GFT
126 val = jme_mdio_read(jme->dev,
127 jme->mii_if.phy_id,
128 MII_BMCR);
129
130 jme_mdio_write(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT
133}
134
b3821cc5
GFT
135static void
136jme_setup_wakeup_frame(struct jme_adapter *jme,
cd0ff491 137 u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
138{
139 int i;
140
141 /*
142 * Setup CRC pattern
143 */
144 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
145 wmb();
146 jwrite32(jme, JME_WFODP, crc);
147 wmb();
148
149 /*
150 * Setup Mask
151 */
cd0ff491 152 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
153 jwrite32(jme, JME_WFOI,
154 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
155 (fnr & WFOI_FRAME_SEL));
156 wmb();
157 jwrite32(jme, JME_WFODP, mask[i]);
158 wmb();
159 }
160}
3bf61c55 161
cd0ff491 162static inline void
3bf61c55
GFT
163jme_reset_mac_processor(struct jme_adapter *jme)
164{
cd0ff491
GFT
165 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
166 u32 crc = 0xCDCDCDCD;
167 u32 gpreg0;
b3821cc5
GFT
168 int i;
169
3bf61c55 170 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 171 udelay(2);
3bf61c55 172 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT
173
174 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
175 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
176 jwrite32(jme, JME_RXQDC, 0x00000000);
177 jwrite32(jme, JME_RXNDA, 0x00000000);
178 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_TXQDC, 0x00000000);
181 jwrite32(jme, JME_TXNDA, 0x00000000);
182
4330c2f2
GFT
183 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 185 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 186 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 187 if (jme->fpgaver)
cdcdc9eb
GFT
188 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
189 else
190 gpreg0 = GPREG0_DEFAULT;
191 jwrite32(jme, JME_GPREG0, gpreg0);
9b9d55de 192 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT
193}
194
cd0ff491
GFT
195static inline void
196jme_reset_ghc_speed(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
199 jwrite32(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
3bf61c55 203jme_clear_pm(struct jme_adapter *jme)
d7699f87 204{
29bdd921 205 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 206 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 207 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT
208}
209
3bf61c55
GFT
210static int
211jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 212{
cd0ff491 213 u32 val;
d7699f87
GFT
214 int i;
215
216 val = jread32(jme, JME_SMBCSR);
217
cd0ff491 218 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
219 val |= SMBCSR_CNACK;
220 jwrite32(jme, JME_SMBCSR, val);
221 val |= SMBCSR_RELOAD;
222 jwrite32(jme, JME_SMBCSR, val);
223 mdelay(12);
224
cd0ff491 225 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
226 mdelay(1);
227 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
228 break;
229 }
230
cd0ff491 231 if (i == 0) {
52a46ba8 232 pr_err("eeprom reload timeout\n");
d7699f87
GFT
233 return -EIO;
234 }
235 }
3bf61c55 236
d7699f87
GFT
237 return 0;
238}
239
3bf61c55
GFT
240static void
241jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
242{
243 struct jme_adapter *jme = netdev_priv(netdev);
244 unsigned char macaddr[6];
cd0ff491 245 u32 val;
d7699f87 246
cd0ff491 247 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 248 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
249 macaddr[0] = (val >> 0) & 0xFF;
250 macaddr[1] = (val >> 8) & 0xFF;
251 macaddr[2] = (val >> 16) & 0xFF;
252 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 253 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
254 macaddr[4] = (val >> 0) & 0xFF;
255 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
256 memcpy(netdev->dev_addr, macaddr, 6);
257 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
258}
259
cd0ff491 260static inline void
3bf61c55
GFT
261jme_set_rx_pcc(struct jme_adapter *jme, int p)
262{
cd0ff491 263 switch (p) {
192570e0
GFT
264 case PCC_OFF:
265 jwrite32(jme, JME_PCCRX0,
266 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
267 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
268 break;
3bf61c55
GFT
269 case PCC_P1:
270 jwrite32(jme, JME_PCCRX0,
271 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
272 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
273 break;
274 case PCC_P2:
275 jwrite32(jme, JME_PCCRX0,
276 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
277 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
278 break;
279 case PCC_P3:
280 jwrite32(jme, JME_PCCRX0,
281 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
282 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
283 break;
284 default:
285 break;
286 }
192570e0 287 wmb();
3bf61c55 288
cd0ff491 289 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
c97b5740 290 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT
291}
292
fcf45b4c 293static void
3bf61c55 294jme_start_irq(struct jme_adapter *jme)
d7699f87 295{
3bf61c55
GFT
296 register struct dynpcc_info *dpi = &(jme->dpi);
297
298 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
299 dpi->cur = PCC_P1;
300 dpi->attempt = PCC_P1;
301 dpi->cnt = 0;
302
303 jwrite32(jme, JME_PCCTX,
8c198884
GFT
304 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
305 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
306 PCCTXQ0_EN
307 );
308
d7699f87
GFT
309 /*
310 * Enable Interrupts
311 */
312 jwrite32(jme, JME_IENS, INTR_ENABLE);
313}
314
cd0ff491 315static inline void
3bf61c55 316jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
317{
318 /*
319 * Disable Interrupts
320 */
cd0ff491 321 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
322}
323
cd0ff491 324static u32
cdcdc9eb
GFT
325jme_linkstat_from_phy(struct jme_adapter *jme)
326{
cd0ff491 327 u32 phylink, bmsr;
cdcdc9eb
GFT
328
329 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
330 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 331 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
332 phylink |= PHY_LINK_AUTONEG_COMPLETE;
333
334 return phylink;
335}
336
cd0ff491 337static inline void
e882564f 338jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT
339{
340 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
341}
342
343static inline void
e882564f 344jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT
345{
346 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
347}
348
fcf45b4c
GFT
349static int
350jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
351{
352 struct jme_adapter *jme = netdev_priv(netdev);
9b9d55de 353 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 354 char linkmsg[64];
fcf45b4c 355 int rc = 0;
d7699f87 356
b3821cc5 357 linkmsg[0] = '\0';
cdcdc9eb 358
cd0ff491 359 if (jme->fpgaver)
cdcdc9eb
GFT
360 phylink = jme_linkstat_from_phy(jme);
361 else
362 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 363
cd0ff491
GFT
364 if (phylink & PHY_LINK_UP) {
365 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
366 /*
367 * If we did not enable AN
368 * Speed/Duplex Info should be obtained from SMI
369 */
370 phylink = PHY_LINK_UP;
371
372 bmcr = jme_mdio_read(jme->dev,
373 jme->mii_if.phy_id,
374 MII_BMCR);
375
376 phylink |= ((bmcr & BMCR_SPEED1000) &&
377 (bmcr & BMCR_SPEED100) == 0) ?
378 PHY_LINK_SPEED_1000M :
379 (bmcr & BMCR_SPEED100) ?
380 PHY_LINK_SPEED_100M :
381 PHY_LINK_SPEED_10M;
382
383 phylink |= (bmcr & BMCR_FULLDPLX) ?
384 PHY_LINK_DUPLEX : 0;
79ce639c 385
b3821cc5 386 strcat(linkmsg, "Forced: ");
cd0ff491 387 } else {
8c198884
GFT
388 /*
389 * Keep polling for speed/duplex resolve complete
390 */
cd0ff491 391 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
392 --cnt) {
393
394 udelay(1);
8c198884 395
cd0ff491 396 if (jme->fpgaver)
cdcdc9eb
GFT
397 phylink = jme_linkstat_from_phy(jme);
398 else
399 phylink = jread32(jme, JME_PHY_LINK);
8c198884 400 }
cd0ff491 401 if (!cnt)
52a46ba8 402 pr_err("Waiting speed resolve timeout\n");
79ce639c 403
b3821cc5 404 strcat(linkmsg, "ANed: ");
d7699f87
GFT
405 }
406
cd0ff491 407 if (jme->phylink == phylink) {
fcf45b4c
GFT
408 rc = 1;
409 goto out;
410 }
cd0ff491 411 if (testonly)
fcf45b4c
GFT
412 goto out;
413
414 jme->phylink = phylink;
415
94c5ea02
GFT
416 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
417 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
418 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
cd0ff491
GFT
419 switch (phylink & PHY_LINK_SPEED_MASK) {
420 case PHY_LINK_SPEED_10M:
94c5ea02
GFT
421 ghc |= GHC_SPEED_10M |
422 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 423 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
424 break;
425 case PHY_LINK_SPEED_100M:
94c5ea02
GFT
426 ghc |= GHC_SPEED_100M |
427 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 428 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
429 break;
430 case PHY_LINK_SPEED_1000M:
94c5ea02
GFT
431 ghc |= GHC_SPEED_1000M |
432 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
cd0ff491 433 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
434 break;
435 default:
436 break;
d7699f87 437 }
d7699f87 438
cd0ff491 439 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 440 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
9b9d55de 441 ghc |= GHC_DPX;
cd0ff491 442 } else {
d7699f87 443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
444 TXMCS_BACKOFF |
445 TXMCS_CARRIERSENSE |
446 TXMCS_COLLISION);
8c198884
GFT
447 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
448 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
449 TXTRHD_TXREN |
450 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
451 }
9b9d55de
GFT
452
453 gpreg1 = GPREG1_DEFAULT;
454 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
455 if (!(phylink & PHY_LINK_DUPLEX))
456 gpreg1 |= GPREG1_HALFMODEPATCH;
457 switch (phylink & PHY_LINK_SPEED_MASK) {
458 case PHY_LINK_SPEED_10M:
459 jme_set_phyfifoa(jme);
460 gpreg1 |= GPREG1_RSSPATCH;
461 break;
462 case PHY_LINK_SPEED_100M:
463 jme_set_phyfifob(jme);
464 gpreg1 |= GPREG1_RSSPATCH;
465 break;
466 case PHY_LINK_SPEED_1000M:
467 jme_set_phyfifoa(jme);
468 break;
469 default:
470 break;
471 }
472 }
d7699f87 473
94c5ea02 474 jwrite32(jme, JME_GPREG1, gpreg1);
fcf45b4c 475 jwrite32(jme, JME_GHC, ghc);
94c5ea02 476 jme->reg_ghc = ghc;
fcf45b4c 477
94c5ea02
GFT
478 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
479 "Full-Duplex, " :
480 "Half-Duplex, ");
481 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
482 "MDI-X" :
483 "MDI");
52a46ba8 484 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT
485 netif_carrier_on(netdev);
486 } else {
487 if (testonly)
fcf45b4c
GFT
488 goto out;
489
52a46ba8 490 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 491 jme->phylink = 0;
cd0ff491 492 netif_carrier_off(netdev);
d7699f87 493 }
fcf45b4c
GFT
494
495out:
496 return rc;
d7699f87
GFT
497}
498
3bf61c55
GFT
499static int
500jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 501{
d7699f87
GFT
502 struct jme_ring *txring = &(jme->txring[0]);
503
504 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
505 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
506 &(txring->dmaalloc),
507 GFP_ATOMIC);
fcf45b4c 508
fa97b924
GFT
509 if (!txring->alloc)
510 goto err_set_null;
d7699f87
GFT
511
512 /*
513 * 16 Bytes align
514 */
cd0ff491 515 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 516 RING_DESC_ALIGN);
4330c2f2 517 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 518 txring->next_to_use = 0;
cdcdc9eb 519 atomic_set(&txring->next_to_clean, 0);
b3821cc5 520 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 521
fa97b924
GFT
522 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
523 jme->tx_ring_size, GFP_ATOMIC);
524 if (unlikely(!(txring->bufinf)))
525 goto err_free_txring;
526
d7699f87 527 /*
b3821cc5 528 * Initialize Transmit Descriptors
d7699f87 529 */
b3821cc5 530 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 531 memset(txring->bufinf, 0,
b3821cc5 532 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
533
534 return 0;
fa97b924
GFT
535
536err_free_txring:
537 dma_free_coherent(&(jme->pdev->dev),
538 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
539 txring->alloc,
540 txring->dmaalloc);
541
542err_set_null:
543 txring->desc = NULL;
544 txring->dmaalloc = 0;
545 txring->dma = 0;
546 txring->bufinf = NULL;
547
548 return -ENOMEM;
d7699f87
GFT
549}
550
3bf61c55
GFT
551static void
552jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
553{
554 int i;
555 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 556 struct jme_buffer_info *txbi;
d7699f87 557
cd0ff491 558 if (txring->alloc) {
fa97b924
GFT
559 if (txring->bufinf) {
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
562 if (txbi->skb) {
563 dev_kfree_skb(txbi->skb);
564 txbi->skb = NULL;
565 }
566 txbi->mapping = 0;
567 txbi->len = 0;
568 txbi->nr_desc = 0;
569 txbi->start_xmit = 0;
d7699f87 570 }
fa97b924 571 kfree(txring->bufinf);
d7699f87
GFT
572 }
573
574 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 575 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
576 txring->alloc,
577 txring->dmaalloc);
3bf61c55
GFT
578
579 txring->alloc = NULL;
580 txring->desc = NULL;
581 txring->dmaalloc = 0;
582 txring->dma = 0;
fa97b924 583 txring->bufinf = NULL;
d7699f87 584 }
3bf61c55 585 txring->next_to_use = 0;
cdcdc9eb 586 atomic_set(&txring->next_to_clean, 0);
79ce639c 587 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
588}
589
cd0ff491 590static inline void
3bf61c55 591jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
592{
593 /*
594 * Select Queue 0
595 */
596 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 597 wmb();
d7699f87
GFT
598
599 /*
600 * Setup TX Queue 0 DMA Bass Address
601 */
fcf45b4c 602 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 603 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 604 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
605
606 /*
607 * Setup TX Descptor Count
608 */
b3821cc5 609 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
610
611 /*
612 * Enable TX Engine
613 */
614 wmb();
4330c2f2
GFT
615 jwrite32(jme, JME_TXCS, jme->reg_txcs |
616 TXCS_SELECT_QUEUE0 |
617 TXCS_ENABLE);
d7699f87
GFT
618
619}
620
cd0ff491 621static inline void
29bdd921
GFT
622jme_restart_tx_engine(struct jme_adapter *jme)
623{
624 /*
625 * Restart TX Engine
626 */
627 jwrite32(jme, JME_TXCS, jme->reg_txcs |
628 TXCS_SELECT_QUEUE0 |
629 TXCS_ENABLE);
630}
631
cd0ff491 632static inline void
3bf61c55 633jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
634{
635 int i;
cd0ff491 636 u32 val;
d7699f87
GFT
637
638 /*
639 * Disable TX Engine
640 */
fcf45b4c 641 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 642 wmb();
d7699f87
GFT
643
644 val = jread32(jme, JME_TXCS);
cd0ff491 645 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 646 mdelay(1);
d7699f87 647 val = jread32(jme, JME_TXCS);
cd0ff491 648 rmb();
d7699f87
GFT
649 }
650
cd0ff491 651 if (!i)
52a46ba8 652 pr_err("Disable TX engine timeout\n");
d7699f87
GFT
653}
654
3bf61c55
GFT
655static void
656jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 657{
fa97b924 658 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 659 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
660 struct jme_buffer_info *rxbi = rxring->bufinf;
661 rxdesc += i;
662 rxbi += i;
663
664 rxdesc->dw[0] = 0;
665 rxdesc->dw[1] = 0;
3bf61c55 666 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
667 rxdesc->desc1.bufaddrl = cpu_to_le32(
668 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 669 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 670 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 671 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 672 wmb();
3bf61c55 673 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
674}
675
3bf61c55
GFT
676static int
677jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
678{
679 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 680 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 681 struct sk_buff *skb;
4330c2f2 682
79ce639c
GFT
683 skb = netdev_alloc_skb(jme->dev,
684 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 685 if (unlikely(!skb))
4330c2f2 686 return -ENOMEM;
3bf61c55 687
4330c2f2 688 rxbi->skb = skb;
3bf61c55 689 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
690 rxbi->mapping = pci_map_page(jme->pdev,
691 virt_to_page(skb->data),
692 offset_in_page(skb->data),
693 rxbi->len,
694 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
695
696 return 0;
697}
698
3bf61c55
GFT
699static void
700jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
701{
702 struct jme_ring *rxring = &(jme->rxring[0]);
703 struct jme_buffer_info *rxbi = rxring->bufinf;
704 rxbi += i;
705
cd0ff491 706 if (rxbi->skb) {
b3821cc5 707 pci_unmap_page(jme->pdev,
4330c2f2 708 rxbi->mapping,
3bf61c55 709 rxbi->len,
4330c2f2
GFT
710 PCI_DMA_FROMDEVICE);
711 dev_kfree_skb(rxbi->skb);
712 rxbi->skb = NULL;
713 rxbi->mapping = 0;
3bf61c55 714 rxbi->len = 0;
4330c2f2
GFT
715 }
716}
717
3bf61c55
GFT
718static void
719jme_free_rx_resources(struct jme_adapter *jme)
720{
721 int i;
722 struct jme_ring *rxring = &(jme->rxring[0]);
723
cd0ff491 724 if (rxring->alloc) {
fa97b924
GFT
725 if (rxring->bufinf) {
726 for (i = 0 ; i < jme->rx_ring_size ; ++i)
727 jme_free_rx_buf(jme, i);
728 kfree(rxring->bufinf);
729 }
3bf61c55
GFT
730
731 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 732 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
733 rxring->alloc,
734 rxring->dmaalloc);
735 rxring->alloc = NULL;
736 rxring->desc = NULL;
737 rxring->dmaalloc = 0;
738 rxring->dma = 0;
fa97b924 739 rxring->bufinf = NULL;
3bf61c55
GFT
740 }
741 rxring->next_to_use = 0;
cdcdc9eb 742 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
743}
744
745static int
746jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
747{
748 int i;
749 struct jme_ring *rxring = &(jme->rxring[0]);
750
751 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
752 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
753 &(rxring->dmaalloc),
754 GFP_ATOMIC);
fa97b924
GFT
755 if (!rxring->alloc)
756 goto err_set_null;
d7699f87
GFT
757
758 /*
759 * 16 Bytes align
760 */
cd0ff491 761 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 762 RING_DESC_ALIGN);
4330c2f2 763 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 764 rxring->next_to_use = 0;
cdcdc9eb 765 atomic_set(&rxring->next_to_clean, 0);
d7699f87 766
fa97b924
GFT
767 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
768 jme->rx_ring_size, GFP_ATOMIC);
769 if (unlikely(!(rxring->bufinf)))
770 goto err_free_rxring;
771
d7699f87
GFT
772 /*
773 * Initiallize Receive Descriptors
774 */
fa97b924
GFT
775 memset(rxring->bufinf, 0,
776 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT
777 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
778 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
779 jme_free_rx_resources(jme);
780 return -ENOMEM;
781 }
d7699f87
GFT
782
783 jme_set_clean_rxdesc(jme, i);
784 }
785
d7699f87 786 return 0;
fa97b924
GFT
787
788err_free_rxring:
789 dma_free_coherent(&(jme->pdev->dev),
790 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
791 rxring->alloc,
792 rxring->dmaalloc);
793err_set_null:
794 rxring->desc = NULL;
795 rxring->dmaalloc = 0;
796 rxring->dma = 0;
797 rxring->bufinf = NULL;
798
799 return -ENOMEM;
d7699f87
GFT
800}
801
cd0ff491 802static inline void
3bf61c55 803jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 804{
d7699f87 805 /*
cd0ff491
GFT
806 * Select Queue 0
807 */
808 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
809 RXCS_QUEUESEL_Q0);
810 wmb();
811
812 /*
d7699f87
GFT
813 * Setup RX DMA Bass Address
814 */
fa97b924 815 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 816 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 817 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT
818
819 /*
b3821cc5 820 * Setup RX Descriptor Count
d7699f87 821 */
b3821cc5 822 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 823
3bf61c55 824 /*
d7699f87
GFT
825 * Setup Unicast Filter
826 */
827 jme_set_multi(jme->dev);
828
829 /*
830 * Enable RX Engine
831 */
832 wmb();
79ce639c 833 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
834 RXCS_QUEUESEL_Q0 |
835 RXCS_ENABLE |
836 RXCS_QST);
d7699f87
GFT
837}
838
cd0ff491 839static inline void
3bf61c55 840jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
841{
842 /*
3bf61c55 843 * Start RX Engine
4330c2f2 844 */
79ce639c 845 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
846 RXCS_QUEUESEL_Q0 |
847 RXCS_ENABLE |
848 RXCS_QST);
849}
850
cd0ff491 851static inline void
3bf61c55 852jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
853{
854 int i;
cd0ff491 855 u32 val;
d7699f87
GFT
856
857 /*
858 * Disable RX Engine
859 */
29bdd921 860 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 861 wmb();
d7699f87
GFT
862
863 val = jread32(jme, JME_RXCS);
cd0ff491 864 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 865 mdelay(1);
d7699f87 866 val = jread32(jme, JME_RXCS);
cd0ff491 867 rmb();
d7699f87
GFT
868 }
869
cd0ff491 870 if (!i)
52a46ba8 871 pr_err("Disable RX engine timeout\n");
d7699f87
GFT
872
873}
874
192570e0 875static int
cd0ff491 876jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 877{
cd0ff491 878 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
879 return false;
880
fa97b924
GFT
881 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
882 == RXWBFLAG_TCPON)) {
883 if (flags & RXWBFLAG_IPV4)
c97b5740 884 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
fa97b924 885 return false;
192570e0
GFT
886 }
887
fa97b924
GFT
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
889 == RXWBFLAG_UDPON)) {
890 if (flags & RXWBFLAG_IPV4)
52a46ba8 891 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
fa97b924 892 return false;
192570e0
GFT
893 }
894
fa97b924
GFT
895 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
896 == RXWBFLAG_IPV4)) {
52a46ba8 897 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
fa97b924 898 return false;
192570e0
GFT
899 }
900
901 return true;
902}
903
3bf61c55 904static void
42b1055e 905jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 906{
d7699f87 907 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 908 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 909 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 910 struct sk_buff *skb;
3bf61c55 911 int framesize;
d7699f87 912
3bf61c55
GFT
913 rxdesc += idx;
914 rxbi += idx;
d7699f87 915
3bf61c55
GFT
916 skb = rxbi->skb;
917 pci_dma_sync_single_for_cpu(jme->pdev,
918 rxbi->mapping,
919 rxbi->len,
920 PCI_DMA_FROMDEVICE);
921
cd0ff491 922 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
923 pci_dma_sync_single_for_device(jme->pdev,
924 rxbi->mapping,
925 rxbi->len,
926 PCI_DMA_FROMDEVICE);
927
928 ++(NET_STAT(jme).rx_dropped);
cd0ff491 929 } else {
3bf61c55
GFT
930 framesize = le16_to_cpu(rxdesc->descwb.framesize)
931 - RX_PREPAD_SIZE;
932
933 skb_reserve(skb, RX_PREPAD_SIZE);
934 skb_put(skb, framesize);
935 skb->protocol = eth_type_trans(skb, jme->dev);
936
94c5ea02 937 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 938 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 939 else
97984ab7 940 skb_checksum_none_assert(skb);
8c198884 941
94c5ea02 942 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 943 if (jme->vlgrp) {
cdcdc9eb 944 jme->jme_vlan_rx(skb, jme->vlgrp,
94c5ea02 945 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 946 NET_STAT(jme).rx_bytes += 4;
c97b5740 947 } else {
c97b5740 948 dev_kfree_skb(skb);
b3821cc5 949 }
cd0ff491 950 } else {
cdcdc9eb 951 jme->jme_rx(skb);
b3821cc5 952 }
3bf61c55 953
94c5ea02
GFT
954 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
955 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT
956 ++(NET_STAT(jme).multicast);
957
3bf61c55
GFT
958 NET_STAT(jme).rx_bytes += framesize;
959 ++(NET_STAT(jme).rx_packets);
960 }
961
962 jme_set_clean_rxdesc(jme, idx);
963
964}
965
8c198884 966static int
3bf61c55
GFT
967jme_process_receive(struct jme_adapter *jme, int limit)
968{
969 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 970 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 971 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 972
cd0ff491 973 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
974 goto out_inc;
975
cd0ff491 976 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
977 goto out_inc;
978
cd0ff491 979 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
980 goto out_inc;
981
cdcdc9eb 982 i = atomic_read(&rxring->next_to_clean);
fa97b924 983 while (limit > 0) {
3bf61c55
GFT
984 rxdesc = rxring->desc;
985 rxdesc += i;
986
94c5ea02 987 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT
988 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
989 goto out;
fa97b924 990 --limit;
d7699f87 991
1a7a122d 992 rmb();
4330c2f2
GFT
993 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
994
cd0ff491 995 if (unlikely(desccnt > 1 ||
192570e0 996 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 997
cd0ff491 998 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 999 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1000 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
1001 ++(NET_STAT(jme).rx_fifo_errors);
1002 else
1003 ++(NET_STAT(jme).rx_errors);
4330c2f2 1004
cd0ff491 1005 if (desccnt > 1)
3bf61c55 1006 limit -= desccnt - 1;
4330c2f2 1007
cd0ff491 1008 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1009 jme_set_clean_rxdesc(jme, j);
b3821cc5 1010 j = (j + 1) & (mask);
4330c2f2 1011 }
3bf61c55 1012
cd0ff491 1013 } else {
42b1055e 1014 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1015 }
4330c2f2 1016
b3821cc5 1017 i = (i + desccnt) & (mask);
3bf61c55 1018 }
4330c2f2 1019
3bf61c55 1020out:
cdcdc9eb 1021 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1022
192570e0
GFT
1023out_inc:
1024 atomic_inc(&jme->rx_cleaning);
1025
3bf61c55 1026 return limit > 0 ? limit : 0;
4330c2f2 1027
3bf61c55 1028}
d7699f87 1029
3bf61c55 1030static void
79ce639c
GFT
1031jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1032{
cd0ff491 1033 if (likely(atmp == dpi->cur)) {
192570e0 1034 dpi->cnt = 0;
79ce639c 1035 return;
192570e0 1036 }
79ce639c 1037
cd0ff491 1038 if (dpi->attempt == atmp) {
79ce639c 1039 ++(dpi->cnt);
cd0ff491 1040 } else {
79ce639c
GFT
1041 dpi->attempt = atmp;
1042 dpi->cnt = 0;
1043 }
1044
1045}
1046
1047static void
1048jme_dynamic_pcc(struct jme_adapter *jme)
1049{
1050 register struct dynpcc_info *dpi = &(jme->dpi);
1051
cd0ff491 1052 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1053 jme_attempt_pcc(dpi, PCC_P3);
c97b5740
GFT
1054 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1055 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT
1056 jme_attempt_pcc(dpi, PCC_P2);
1057 else
1058 jme_attempt_pcc(dpi, PCC_P1);
1059
cd0ff491
GFT
1060 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1061 if (dpi->attempt < dpi->cur)
1062 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1063 jme_set_rx_pcc(jme, dpi->attempt);
1064 dpi->cur = dpi->attempt;
1065 dpi->cnt = 0;
1066 }
1067}
1068
1069static void
1070jme_start_pcc_timer(struct jme_adapter *jme)
1071{
1072 struct dynpcc_info *dpi = &(jme->dpi);
1073 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1074 dpi->last_pkts = NET_STAT(jme).rx_packets;
1075 dpi->intr_cnt = 0;
1076 jwrite32(jme, JME_TMCSR,
1077 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1078}
1079
cd0ff491 1080static inline void
29bdd921
GFT
1081jme_stop_pcc_timer(struct jme_adapter *jme)
1082{
1083 jwrite32(jme, JME_TMCSR, 0);
1084}
1085
1086static void
cd0ff491
GFT
1087jme_shutdown_nic(struct jme_adapter *jme)
1088{
1089 u32 phylink;
1090
1091 phylink = jme_linkstat_from_phy(jme);
1092
1093 if (!(phylink & PHY_LINK_UP)) {
1094 /*
1095 * Disable all interrupt before issue timer
1096 */
1097 jme_stop_irq(jme);
1098 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1099 }
1100}
1101
1102static void
79ce639c
GFT
1103jme_pcc_tasklet(unsigned long arg)
1104{
cd0ff491 1105 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1106 struct net_device *netdev = jme->dev;
1107
cd0ff491
GFT
1108 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1109 jme_shutdown_nic(jme);
1110 return;
1111 }
29bdd921 1112
cd0ff491 1113 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1114 (atomic_read(&jme->link_changing) != 1)
1115 )) {
1116 jme_stop_pcc_timer(jme);
79ce639c
GFT
1117 return;
1118 }
29bdd921 1119
cd0ff491 1120 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1121 jme_dynamic_pcc(jme);
1122
79ce639c
GFT
1123 jme_start_pcc_timer(jme);
1124}
1125
cd0ff491 1126static inline void
192570e0
GFT
1127jme_polling_mode(struct jme_adapter *jme)
1128{
1129 jme_set_rx_pcc(jme, PCC_OFF);
1130}
1131
cd0ff491 1132static inline void
192570e0
GFT
1133jme_interrupt_mode(struct jme_adapter *jme)
1134{
1135 jme_set_rx_pcc(jme, PCC_P1);
1136}
1137
cd0ff491
GFT
1138static inline int
1139jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1140{
1141 u32 apmc;
1142 apmc = jread32(jme, JME_APMC);
1143 return apmc & JME_APMC_PSEUDO_HP_EN;
1144}
1145
1146static void
1147jme_start_shutdown_timer(struct jme_adapter *jme)
1148{
1149 u32 apmc;
1150
1151 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1152 apmc &= ~JME_APMC_EPIEN_CTRL;
1153 if (!no_extplug) {
1154 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1155 wmb();
1156 }
1157 jwrite32f(jme, JME_APMC, apmc);
1158
1159 jwrite32f(jme, JME_TIMER2, 0);
1160 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1161 jwrite32(jme, JME_TMCSR,
1162 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1163}
1164
1165static void
1166jme_stop_shutdown_timer(struct jme_adapter *jme)
1167{
1168 u32 apmc;
1169
1170 jwrite32f(jme, JME_TMCSR, 0);
1171 jwrite32f(jme, JME_TIMER2, 0);
1172 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1173
1174 apmc = jread32(jme, JME_APMC);
1175 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1176 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1177 wmb();
1178 jwrite32f(jme, JME_APMC, apmc);
1179}
1180
79ce639c 1181static void
3bf61c55
GFT
1182jme_link_change_tasklet(unsigned long arg)
1183{
cd0ff491 1184 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1185 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1186 int rc;
1187
cd0ff491
GFT
1188 while (!atomic_dec_and_test(&jme->link_changing)) {
1189 atomic_inc(&jme->link_changing);
52a46ba8 1190 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
e882564f 1191 while (atomic_read(&jme->link_changing) != 1)
52a46ba8 1192 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1193 }
fcf45b4c 1194
cd0ff491 1195 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1196 goto out;
1197
29bdd921 1198 jme->old_mtu = netdev->mtu;
fcf45b4c 1199 netif_stop_queue(netdev);
cd0ff491
GFT
1200 if (jme_pseudo_hotplug_enabled(jme))
1201 jme_stop_shutdown_timer(jme);
1202
1203 jme_stop_pcc_timer(jme);
1204 tasklet_disable(&jme->txclean_task);
1205 tasklet_disable(&jme->rxclean_task);
1206 tasklet_disable(&jme->rxempty_task);
1207
1208 if (netif_carrier_ok(netdev)) {
1209 jme_reset_ghc_speed(jme);
1210 jme_disable_rx_engine(jme);
1211 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1212 jme_reset_mac_processor(jme);
1213 jme_free_rx_resources(jme);
1214 jme_free_tx_resources(jme);
192570e0 1215
cd0ff491 1216 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1217 jme_polling_mode(jme);
cd0ff491
GFT
1218
1219 netif_carrier_off(netdev);
fcf45b4c
GFT
1220 }
1221
1222 jme_check_link(netdev, 0);
cd0ff491 1223 if (netif_carrier_ok(netdev)) {
fcf45b4c 1224 rc = jme_setup_rx_resources(jme);
cd0ff491 1225 if (rc) {
52a46ba8 1226 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1227 goto out_enable_tasklet;
fcf45b4c
GFT
1228 }
1229
fcf45b4c 1230 rc = jme_setup_tx_resources(jme);
cd0ff491 1231 if (rc) {
52a46ba8 1232 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT
1233 goto err_out_free_rx_resources;
1234 }
1235
1236 jme_enable_rx_engine(jme);
1237 jme_enable_tx_engine(jme);
1238
1239 netif_start_queue(netdev);
192570e0 1240
cd0ff491 1241 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1242 jme_interrupt_mode(jme);
192570e0 1243
79ce639c 1244 jme_start_pcc_timer(jme);
cd0ff491
GFT
1245 } else if (jme_pseudo_hotplug_enabled(jme)) {
1246 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1247 }
1248
cd0ff491 1249 goto out_enable_tasklet;
fcf45b4c
GFT
1250
1251err_out_free_rx_resources:
1252 jme_free_rx_resources(jme);
cd0ff491
GFT
1253out_enable_tasklet:
1254 tasklet_enable(&jme->txclean_task);
1255 tasklet_hi_enable(&jme->rxclean_task);
1256 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1257out:
1258 atomic_inc(&jme->link_changing);
3bf61c55 1259}
d7699f87 1260
3bf61c55
GFT
1261static void
1262jme_rx_clean_tasklet(unsigned long arg)
1263{
cd0ff491 1264 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1265 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1266
192570e0
GFT
1267 jme_process_receive(jme, jme->rx_ring_size);
1268 ++(dpi->intr_cnt);
42b1055e 1269
192570e0 1270}
fcf45b4c 1271
192570e0 1272static int
cdcdc9eb 1273jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1274{
cdcdc9eb 1275 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1276 int rest;
fcf45b4c 1277
cdcdc9eb 1278 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1279
cd0ff491 1280 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1281 atomic_dec(&jme->rx_empty);
192570e0
GFT
1282 ++(NET_STAT(jme).rx_dropped);
1283 jme_restart_rx_engine(jme);
1284 }
1285 atomic_inc(&jme->rx_empty);
1286
cd0ff491 1287 if (rest) {
cdcdc9eb 1288 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1289 jme_interrupt_mode(jme);
1290 }
1291
cdcdc9eb
GFT
1292 JME_NAPI_WEIGHT_SET(budget, rest);
1293 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1294}
1295
1296static void
1297jme_rx_empty_tasklet(unsigned long arg)
1298{
cd0ff491 1299 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1300
cd0ff491 1301 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1302 return;
1303
cd0ff491 1304 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1305 return;
1306
c97b5740 1307 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1308
fcf45b4c 1309 jme_rx_clean_tasklet(arg);
cdcdc9eb 1310
cd0ff491 1311 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1312 atomic_dec(&jme->rx_empty);
1313 ++(NET_STAT(jme).rx_dropped);
1314 jme_restart_rx_engine(jme);
1315 }
1316 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1317}
1318
3bf61c55 1319static void
b3821cc5
GFT
1320jme_wake_queue_if_stopped(struct jme_adapter *jme)
1321{
fa97b924 1322 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1323
1324 smp_wmb();
cd0ff491 1325 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1326 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
52a46ba8 1327 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1328 netif_wake_queue(jme->dev);
b3821cc5
GFT
1329 }
1330
1331}
1332
1333static void
3bf61c55 1334jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1335{
cd0ff491 1336 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1337 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1338 struct txdesc *txdesc = txring->desc;
3bf61c55 1339 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1340 int i, j, cnt = 0, max, err, mask;
3bf61c55 1341
52a46ba8 1342 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT
1343
1344 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1345 goto out;
1346
cd0ff491 1347 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1348 goto out;
1349
cd0ff491 1350 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1351 goto out;
1352
b3821cc5
GFT
1353 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1354 mask = jme->tx_ring_mask;
3bf61c55 1355
cd0ff491 1356 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1357
1358 ctxbi = txbi + i;
1359
cd0ff491 1360 if (likely(ctxbi->skb &&
b3821cc5 1361 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1362
cd0ff491 1363 tx_dbg(jme, "txclean: %d+%d@%lu\n",
52a46ba8 1364 i, ctxbi->nr_desc, jiffies);
3bf61c55 1365
cd0ff491 1366 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1367
cd0ff491 1368 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1369 ttxbi = txbi + ((i + j) & (mask));
1370 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1371
b3821cc5 1372 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1373 ttxbi->mapping,
1374 ttxbi->len,
1375 PCI_DMA_TODEVICE);
1376
3bf61c55
GFT
1377 ttxbi->mapping = 0;
1378 ttxbi->len = 0;
1379 }
1380
1381 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1382
1383 cnt += ctxbi->nr_desc;
1384
cd0ff491 1385 if (unlikely(err)) {
8c198884 1386 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1387 } else {
8c198884 1388 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1389 NET_STAT(jme).tx_bytes += ctxbi->len;
1390 }
1391
1392 ctxbi->skb = NULL;
1393 ctxbi->len = 0;
cdcdc9eb 1394 ctxbi->start_xmit = 0;
cd0ff491
GFT
1395
1396 } else {
3bf61c55
GFT
1397 break;
1398 }
1399
b3821cc5 1400 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1401
1402 ctxbi->nr_desc = 0;
d7699f87
GFT
1403 }
1404
52a46ba8 1405 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1406 atomic_set(&txring->next_to_clean, i);
79ce639c 1407 atomic_add(cnt, &txring->nr_free);
3bf61c55 1408
b3821cc5
GFT
1409 jme_wake_queue_if_stopped(jme);
1410
fcf45b4c
GFT
1411out:
1412 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1413}
1414
79ce639c 1415static void
cd0ff491 1416jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1417{
3bf61c55
GFT
1418 /*
1419 * Disable interrupt
1420 */
1421 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1422
cd0ff491 1423 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1424 /*
1425 * Link change event is critical
1426 * all other events are ignored
1427 */
1428 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1429 tasklet_schedule(&jme->linkch_task);
29bdd921 1430 goto out_reenable;
fcf45b4c 1431 }
d7699f87 1432
cd0ff491 1433 if (intrstat & INTR_TMINTR) {
47220951 1434 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1435 tasklet_schedule(&jme->pcc_task);
47220951 1436 }
79ce639c 1437
cd0ff491 1438 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1439 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1440 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1441 }
1442
cd0ff491 1443 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1444 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1445 INTR_PCCRX0 |
1446 INTR_RX0EMP)) |
1447 INTR_RX0);
1448 }
d7699f87 1449
cd0ff491
GFT
1450 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1451 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1452 atomic_inc(&jme->rx_empty);
1453
cd0ff491
GFT
1454 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1455 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1456 jme_polling_mode(jme);
cdcdc9eb 1457 JME_RX_SCHEDULE(jme);
192570e0
GFT
1458 }
1459 }
cd0ff491
GFT
1460 } else {
1461 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1462 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1463 tasklet_hi_schedule(&jme->rxempty_task);
1464 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1465 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1466 }
4330c2f2 1467 }
d7699f87 1468
29bdd921 1469out_reenable:
3bf61c55 1470 /*
fcf45b4c 1471 * Re-enable interrupt
3bf61c55 1472 */
fcf45b4c 1473 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1474}
1475
1476static irqreturn_t
1477jme_intr(int irq, void *dev_id)
1478{
cd0ff491
GFT
1479 struct net_device *netdev = dev_id;
1480 struct jme_adapter *jme = netdev_priv(netdev);
1481 u32 intrstat;
79ce639c
GFT
1482
1483 intrstat = jread32(jme, JME_IEVE);
1484
1485 /*
1486 * Check if it's really an interrupt for us
1487 */
9b9d55de 1488 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1489 return IRQ_NONE;
79ce639c
GFT
1490
1491 /*
1492 * Check if the device still exist
1493 */
cd0ff491
GFT
1494 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1495 return IRQ_NONE;
79ce639c
GFT
1496
1497 jme_intr_msi(jme, intrstat);
1498
cd0ff491 1499 return IRQ_HANDLED;
d7699f87
GFT
1500}
1501
79ce639c
GFT
1502static irqreturn_t
1503jme_msi(int irq, void *dev_id)
1504{
cd0ff491
GFT
1505 struct net_device *netdev = dev_id;
1506 struct jme_adapter *jme = netdev_priv(netdev);
1507 u32 intrstat;
79ce639c 1508
fa97b924 1509 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT
1510
1511 jme_intr_msi(jme, intrstat);
1512
cd0ff491 1513 return IRQ_HANDLED;
79ce639c
GFT
1514}
1515
79ce639c
GFT
1516static void
1517jme_reset_link(struct jme_adapter *jme)
1518{
1519 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1520}
1521
fcf45b4c
GFT
1522static void
1523jme_restart_an(struct jme_adapter *jme)
1524{
cd0ff491 1525 u32 bmcr;
fcf45b4c 1526
cd0ff491 1527 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1528 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1529 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1530 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1531 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1532}
1533
1534static int
1535jme_request_irq(struct jme_adapter *jme)
1536{
1537 int rc;
cd0ff491
GFT
1538 struct net_device *netdev = jme->dev;
1539 irq_handler_t handler = jme_intr;
1540 int irq_flags = IRQF_SHARED;
1541
1542 if (!pci_enable_msi(jme->pdev)) {
1543 set_bit(JME_FLAG_MSI, &jme->flags);
1544 handler = jme_msi;
1545 irq_flags = 0;
1546 }
1547
1548 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1549 netdev);
1550 if (rc) {
52a46ba8
JP
1551 netdev_err(netdev,
1552 "Unable to request %s interrupt (return: %d)\n",
1553 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1554 rc);
79ce639c 1555
cd0ff491
GFT
1556 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1557 pci_disable_msi(jme->pdev);
1558 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1559 }
cd0ff491 1560 } else {
79ce639c
GFT
1561 netdev->irq = jme->pdev->irq;
1562 }
1563
cd0ff491 1564 return rc;
79ce639c
GFT
1565}
1566
1567static void
1568jme_free_irq(struct jme_adapter *jme)
1569{
cd0ff491
GFT
1570 free_irq(jme->pdev->irq, jme->dev);
1571 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1572 pci_disable_msi(jme->pdev);
1573 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1574 jme->dev->irq = jme->pdev->irq;
cd0ff491 1575 }
fcf45b4c
GFT
1576}
1577
48db98f7
GFT
1578static inline void
1579jme_phy_on(struct jme_adapter *jme)
1580{
1581 u32 bmcr;
1582
1583 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1584 bmcr &= ~BMCR_PDOWN;
1585 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1586}
1587
3bf61c55
GFT
1588static int
1589jme_open(struct net_device *netdev)
d7699f87
GFT
1590{
1591 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1592 int rc;
79ce639c 1593
42b1055e 1594 jme_clear_pm(jme);
cdcdc9eb 1595 JME_NAPI_ENABLE(jme);
d7699f87 1596
fa97b924 1597 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT
1598 tasklet_enable(&jme->txclean_task);
1599 tasklet_hi_enable(&jme->rxclean_task);
1600 tasklet_hi_enable(&jme->rxempty_task);
1601
79ce639c 1602 rc = jme_request_irq(jme);
cd0ff491 1603 if (rc)
4330c2f2 1604 goto err_out;
79ce639c 1605
d7699f87 1606 jme_start_irq(jme);
42b1055e 1607
48db98f7
GFT
1608 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1609 jme_phy_on(jme);
42b1055e 1610 jme_set_settings(netdev, &jme->old_ecmd);
48db98f7 1611 } else {
42b1055e 1612 jme_reset_phy_processor(jme);
48db98f7 1613 }
42b1055e 1614
29bdd921 1615 jme_reset_link(jme);
d7699f87
GFT
1616
1617 return 0;
1618
d7699f87
GFT
1619err_out:
1620 netif_stop_queue(netdev);
1621 netif_carrier_off(netdev);
4330c2f2 1622 return rc;
d7699f87
GFT
1623}
1624
9b9d55de 1625#ifdef CONFIG_PM
42b1055e
GFT
1626static void
1627jme_set_100m_half(struct jme_adapter *jme)
1628{
cd0ff491 1629 u32 bmcr, tmp;
42b1055e
GFT
1630
1631 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1632 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1633 BMCR_SPEED1000 | BMCR_FULLDPLX);
1634 tmp |= BMCR_SPEED100;
1635
1636 if (bmcr != tmp)
1637 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1638
cd0ff491 1639 if (jme->fpgaver)
cdcdc9eb
GFT
1640 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1641 else
1642 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1643}
1644
47220951
GFT
1645#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1646static void
1647jme_wait_link(struct jme_adapter *jme)
1648{
cd0ff491 1649 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1650
1651 mdelay(1000);
1652 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1653 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1654 mdelay(10);
1655 phylink = jme_linkstat_from_phy(jme);
1656 }
1657}
9b9d55de 1658#endif
47220951 1659
cd0ff491 1660static inline void
42b1055e
GFT
1661jme_phy_off(struct jme_adapter *jme)
1662{
1663 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1664}
1665
3bf61c55
GFT
1666static int
1667jme_close(struct net_device *netdev)
d7699f87
GFT
1668{
1669 struct jme_adapter *jme = netdev_priv(netdev);
1670
1671 netif_stop_queue(netdev);
1672 netif_carrier_off(netdev);
1673
1674 jme_stop_irq(jme);
79ce639c 1675 jme_free_irq(jme);
d7699f87 1676
cdcdc9eb 1677 JME_NAPI_DISABLE(jme);
192570e0 1678
fa97b924
GFT
1679 tasklet_disable(&jme->linkch_task);
1680 tasklet_disable(&jme->txclean_task);
1681 tasklet_disable(&jme->rxclean_task);
1682 tasklet_disable(&jme->rxempty_task);
8c198884 1683
cd0ff491
GFT
1684 jme_reset_ghc_speed(jme);
1685 jme_disable_rx_engine(jme);
1686 jme_disable_tx_engine(jme);
8c198884 1687 jme_reset_mac_processor(jme);
d7699f87
GFT
1688 jme_free_rx_resources(jme);
1689 jme_free_tx_resources(jme);
42b1055e 1690 jme->phylink = 0;
b3821cc5
GFT
1691 jme_phy_off(jme);
1692
1693 return 0;
1694}
1695
1696static int
1697jme_alloc_txdesc(struct jme_adapter *jme,
1698 struct sk_buff *skb)
1699{
fa97b924 1700 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1701 int idx, nr_alloc, mask = jme->tx_ring_mask;
1702
1703 idx = txring->next_to_use;
1704 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1705
cd0ff491 1706 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1707 return -1;
1708
1709 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1710
b3821cc5
GFT
1711 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1712
1713 return idx;
1714}
1715
1716static void
1717jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1718 struct txdesc *txdesc,
b3821cc5
GFT
1719 struct jme_buffer_info *txbi,
1720 struct page *page,
cd0ff491
GFT
1721 u32 page_offset,
1722 u32 len,
1723 u8 hidma)
b3821cc5
GFT
1724{
1725 dma_addr_t dmaaddr;
1726
1727 dmaaddr = pci_map_page(pdev,
1728 page,
1729 page_offset,
1730 len,
1731 PCI_DMA_TODEVICE);
1732
1733 pci_dma_sync_single_for_device(pdev,
1734 dmaaddr,
1735 len,
1736 PCI_DMA_TODEVICE);
1737
1738 txdesc->dw[0] = 0;
1739 txdesc->dw[1] = 0;
1740 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1741 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1742 txdesc->desc2.datalen = cpu_to_le16(len);
1743 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1744 txdesc->desc2.bufaddrl = cpu_to_le32(
1745 (__u64)dmaaddr & 0xFFFFFFFFUL);
1746
1747 txbi->mapping = dmaaddr;
1748 txbi->len = len;
1749}
1750
1751static void
1752jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1753{
fa97b924 1754 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1755 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1756 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1757 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1758 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1759 int mask = jme->tx_ring_mask;
1760 struct skb_frag_struct *frag;
cd0ff491 1761 u32 len;
b3821cc5 1762
cd0ff491
GFT
1763 for (i = 0 ; i < nr_frags ; ++i) {
1764 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1765 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1766 ctxbi = txbi + ((idx + i + 2) & (mask));
1767
1768 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1769 frag->page_offset, frag->size, hidma);
42b1055e 1770 }
b3821cc5 1771
cd0ff491 1772 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1773 ctxdesc = txdesc + ((idx + 1) & (mask));
1774 ctxbi = txbi + ((idx + 1) & (mask));
1775 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1776 offset_in_page(skb->data), len, hidma);
1777
1778}
1779
1780static int
1781jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1782{
cd0ff491 1783 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT
1784 skb_header_cloned(skb) &&
1785 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1786 dev_kfree_skb(skb);
1787 return -1;
1788 }
1789
1790 return 0;
1791}
1792
1793static int
94c5ea02 1794jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1795{
94c5ea02 1796 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1797 if (*mss) {
b3821cc5
GFT
1798 *flags |= TXFLAG_LSEN;
1799
cd0ff491 1800 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1801 struct iphdr *iph = ip_hdr(skb);
1802
1803 iph->check = 0;
cd0ff491 1804 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1805 iph->daddr, 0,
1806 IPPROTO_TCP,
1807 0);
cd0ff491 1808 } else {
b3821cc5
GFT
1809 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1810
cd0ff491 1811 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1812 &ip6h->daddr, 0,
1813 IPPROTO_TCP,
1814 0);
1815 }
1816
1817 return 0;
1818 }
1819
1820 return 1;
1821}
1822
1823static void
cd0ff491 1824jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1825{
cd0ff491
GFT
1826 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1827 u8 ip_proto;
b3821cc5
GFT
1828
1829 switch (skb->protocol) {
cd0ff491 1830 case htons(ETH_P_IP):
b3821cc5
GFT
1831 ip_proto = ip_hdr(skb)->protocol;
1832 break;
cd0ff491 1833 case htons(ETH_P_IPV6):
b3821cc5
GFT
1834 ip_proto = ipv6_hdr(skb)->nexthdr;
1835 break;
1836 default:
1837 ip_proto = 0;
1838 break;
1839 }
1840
cd0ff491 1841 switch (ip_proto) {
b3821cc5
GFT
1842 case IPPROTO_TCP:
1843 *flags |= TXFLAG_TCPCS;
1844 break;
1845 case IPPROTO_UDP:
1846 *flags |= TXFLAG_UDPCS;
1847 break;
1848 default:
52a46ba8 1849 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT
1850 break;
1851 }
1852 }
1853}
1854
cd0ff491 1855static inline void
94c5ea02 1856jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 1857{
cd0ff491 1858 if (vlan_tx_tag_present(skb)) {
b3821cc5 1859 *flags |= TXFLAG_TAGON;
94c5ea02 1860 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 1861 }
b3821cc5
GFT
1862}
1863
1864static int
94c5ea02 1865jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 1866{
fa97b924 1867 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1868 struct txdesc *txdesc;
b3821cc5 1869 struct jme_buffer_info *txbi;
cd0ff491 1870 u8 flags;
b3821cc5 1871
cd0ff491 1872 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
1873 txbi = txring->bufinf + idx;
1874
1875 txdesc->dw[0] = 0;
1876 txdesc->dw[1] = 0;
1877 txdesc->dw[2] = 0;
1878 txdesc->dw[3] = 0;
1879 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1880 /*
1881 * Set OWN bit at final.
1882 * When kernel transmit faster than NIC.
1883 * And NIC trying to send this descriptor before we tell
1884 * it to start sending this TX queue.
1885 * Other fields are already filled correctly.
1886 */
1887 wmb();
1888 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
1889 /*
1890 * Set checksum flags while not tso
1891 */
1892 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1893 jme_tx_csum(jme, skb, &flags);
b3821cc5 1894 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 1895 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT
1896 txdesc->desc1.flags = flags;
1897 /*
1898 * Set tx buffer info after telling NIC to send
1899 * For better tx_clean timing
1900 */
1901 wmb();
1902 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1903 txbi->skb = skb;
1904 txbi->len = skb->len;
cd0ff491
GFT
1905 txbi->start_xmit = jiffies;
1906 if (!txbi->start_xmit)
8d27293f 1907 txbi->start_xmit = (0UL-1);
d7699f87
GFT
1908
1909 return 0;
1910}
1911
b3821cc5
GFT
1912static void
1913jme_stop_queue_if_full(struct jme_adapter *jme)
1914{
fa97b924 1915 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT
1916 struct jme_buffer_info *txbi = txring->bufinf;
1917 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 1918
cd0ff491 1919 txbi += idx;
b3821cc5
GFT
1920
1921 smp_wmb();
cd0ff491 1922 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 1923 netif_stop_queue(jme->dev);
52a46ba8 1924 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 1925 smp_wmb();
cd0ff491
GFT
1926 if (atomic_read(&txring->nr_free)
1927 >= (jme->tx_wake_threshold)) {
b3821cc5 1928 netif_wake_queue(jme->dev);
52a46ba8 1929 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT
1930 }
1931 }
1932
cd0ff491 1933 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
1934 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1935 txbi->skb)) {
1936 netif_stop_queue(jme->dev);
52a46ba8
JP
1937 netif_info(jme, tx_queued, jme->dev,
1938 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 1939 }
b3821cc5
GFT
1940}
1941
3bf61c55
GFT
1942/*
1943 * This function is already protected by netif_tx_lock()
1944 */
cd0ff491 1945
c97b5740 1946static netdev_tx_t
3bf61c55 1947jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 1948{
cd0ff491 1949 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 1950 int idx;
d7699f87 1951
cd0ff491 1952 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
1953 ++(NET_STAT(jme).tx_dropped);
1954 return NETDEV_TX_OK;
1955 }
1956
1957 idx = jme_alloc_txdesc(jme, skb);
79ce639c 1958
cd0ff491 1959 if (unlikely(idx < 0)) {
b3821cc5 1960 netif_stop_queue(netdev);
52a46ba8
JP
1961 netif_err(jme, tx_err, jme->dev,
1962 "BUG! Tx ring full when queue awake!\n");
d7699f87 1963
cd0ff491 1964 return NETDEV_TX_BUSY;
b3821cc5
GFT
1965 }
1966
94c5ea02 1967 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 1968
4330c2f2
GFT
1969 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1970 TXCS_SELECT_QUEUE0 |
1971 TXCS_QUEUE0S |
1972 TXCS_ENABLE);
d7699f87 1973
52a46ba8
JP
1974 tx_dbg(jme, "xmit: %d+%d@%lu\n",
1975 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT
1976 jme_stop_queue_if_full(jme);
1977
cd0ff491 1978 return NETDEV_TX_OK;
d7699f87
GFT
1979}
1980
3bf61c55
GFT
1981static int
1982jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 1983{
cd0ff491 1984 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1985 struct sockaddr *addr = p;
cd0ff491 1986 u32 val;
d7699f87 1987
cd0ff491 1988 if (netif_running(netdev))
d7699f87
GFT
1989 return -EBUSY;
1990
cd0ff491 1991 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT
1992 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1993
186fc259
GFT
1994 val = (addr->sa_data[3] & 0xff) << 24 |
1995 (addr->sa_data[2] & 0xff) << 16 |
1996 (addr->sa_data[1] & 0xff) << 8 |
1997 (addr->sa_data[0] & 0xff);
4330c2f2 1998 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
1999 val = (addr->sa_data[5] & 0xff) << 8 |
2000 (addr->sa_data[4] & 0xff);
4330c2f2 2001 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 2002 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
2003
2004 return 0;
2005}
2006
3bf61c55
GFT
2007static void
2008jme_set_multi(struct net_device *netdev)
d7699f87 2009{
3bf61c55 2010 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2011 u32 mc_hash[2] = {};
d7699f87 2012
cd0ff491 2013 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
2014
2015 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2016
cd0ff491 2017 if (netdev->flags & IFF_PROMISC) {
8c198884 2018 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2019 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2020 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2021 } else if (netdev->flags & IFF_MULTICAST) {
d401cb9a 2022 struct netdev_hw_addr *ha;
3bf61c55 2023 int bit_nr;
d7699f87 2024
8c198884 2025 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
d401cb9a
JP
2026 netdev_for_each_mc_addr(ha, netdev) {
2027 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
cd0ff491
GFT
2028 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2029 }
d7699f87 2030
4330c2f2
GFT
2031 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2032 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2033 }
2034
d7699f87 2035 wmb();
8c198884
GFT
2036 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2037
cd0ff491 2038 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2039}
2040
3bf61c55 2041static int
8c198884 2042jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2043{
cd0ff491 2044 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2045
cd0ff491 2046 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2047 return 0;
2048
cd0ff491
GFT
2049 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2050 ((new_mtu) < IPV6_MIN_MTU))
2051 return -EINVAL;
79ce639c 2052
cd0ff491 2053 if (new_mtu > 4000) {
79ce639c
GFT
2054 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2055 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2056 jme_restart_rx_engine(jme);
cd0ff491 2057 } else {
79ce639c
GFT
2058 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2059 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2060 jme_restart_rx_engine(jme);
2061 }
2062
cd0ff491 2063 if (new_mtu > 1900) {
b3821cc5
GFT
2064 netdev->features &= ~(NETIF_F_HW_CSUM |
2065 NETIF_F_TSO |
2066 NETIF_F_TSO6);
cd0ff491
GFT
2067 } else {
2068 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
b3821cc5 2069 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491 2070 if (test_bit(JME_FLAG_TSO, &jme->flags))
b3821cc5 2071 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT
2072 }
2073
cd0ff491
GFT
2074 netdev->mtu = new_mtu;
2075 jme_reset_link(jme);
79ce639c
GFT
2076
2077 return 0;
d7699f87
GFT
2078}
2079
3bf61c55 2080static void
8c198884
GFT
2081jme_tx_timeout(struct net_device *netdev)
2082{
cd0ff491 2083 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2084
cdcdc9eb
GFT
2085 jme->phylink = 0;
2086 jme_reset_phy_processor(jme);
cd0ff491 2087 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2088 jme_set_settings(netdev, &jme->old_ecmd);
2089
8c198884 2090 /*
cdcdc9eb 2091 * Force to Reset the link again
8c198884 2092 */
29bdd921 2093 jme_reset_link(jme);
8c198884
GFT
2094}
2095
f7f428e4
GFT
2096static inline void jme_pause_rx(struct jme_adapter *jme)
2097{
2098 atomic_dec(&jme->link_changing);
2099
2100 jme_set_rx_pcc(jme, PCC_OFF);
2101 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2102 JME_NAPI_DISABLE(jme);
2103 } else {
2104 tasklet_disable(&jme->rxclean_task);
2105 tasklet_disable(&jme->rxempty_task);
2106 }
2107}
2108
2109static inline void jme_resume_rx(struct jme_adapter *jme)
2110{
2111 struct dynpcc_info *dpi = &(jme->dpi);
2112
2113 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2114 JME_NAPI_ENABLE(jme);
2115 } else {
2116 tasklet_hi_enable(&jme->rxclean_task);
2117 tasklet_hi_enable(&jme->rxempty_task);
2118 }
2119 dpi->cur = PCC_P1;
2120 dpi->attempt = PCC_P1;
2121 dpi->cnt = 0;
2122 jme_set_rx_pcc(jme, PCC_P1);
2123
2124 atomic_inc(&jme->link_changing);
2125}
2126
8c198884 2127static void
42b1055e
GFT
2128jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2129{
2130 struct jme_adapter *jme = netdev_priv(netdev);
2131
f7f428e4 2132 jme_pause_rx(jme);
42b1055e 2133 jme->vlgrp = grp;
f7f428e4 2134 jme_resume_rx(jme);
42b1055e
GFT
2135}
2136
2137static void
3bf61c55
GFT
2138jme_get_drvinfo(struct net_device *netdev,
2139 struct ethtool_drvinfo *info)
d7699f87 2140{
cd0ff491 2141 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2142
cd0ff491
GFT
2143 strcpy(info->driver, DRV_NAME);
2144 strcpy(info->version, DRV_VERSION);
2145 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2146}
2147
3bf61c55 2148static int
8c198884
GFT
2149jme_get_regs_len(struct net_device *netdev)
2150{
cd0ff491 2151 return JME_REG_LEN;
8c198884
GFT
2152}
2153
2154static void
cd0ff491 2155mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2156{
2157 int i;
2158
cd0ff491 2159 for (i = 0 ; i < len ; i += 4)
79ce639c 2160 p[i >> 2] = jread32(jme, reg + i);
186fc259 2161}
8c198884 2162
186fc259 2163static void
cd0ff491 2164mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2165{
2166 int i;
cd0ff491 2167 u16 *p16 = (u16 *)p;
186fc259 2168
cd0ff491 2169 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2170 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2171}
2172
2173static void
2174jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2175{
cd0ff491
GFT
2176 struct jme_adapter *jme = netdev_priv(netdev);
2177 u32 *p32 = (u32 *)p;
8c198884 2178
186fc259 2179 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2180
2181 regs->version = 1;
2182 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2183
2184 p32 += 0x100 >> 2;
2185 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2186
2187 p32 += 0x100 >> 2;
2188 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2189
2190 p32 += 0x100 >> 2;
2191 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2192
186fc259
GFT
2193 p32 += 0x100 >> 2;
2194 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2195}
2196
2197static int
2198jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2199{
2200 struct jme_adapter *jme = netdev_priv(netdev);
2201
8c198884
GFT
2202 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2203 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2204
cd0ff491 2205 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2206 ecmd->use_adaptive_rx_coalesce = false;
2207 ecmd->rx_coalesce_usecs = 0;
2208 ecmd->rx_max_coalesced_frames = 0;
2209 return 0;
2210 }
2211
2212 ecmd->use_adaptive_rx_coalesce = true;
2213
cd0ff491 2214 switch (jme->dpi.cur) {
8c198884
GFT
2215 case PCC_P1:
2216 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2217 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2218 break;
2219 case PCC_P2:
2220 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2221 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2222 break;
2223 case PCC_P3:
2224 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2225 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2226 break;
2227 default:
2228 break;
2229 }
2230
2231 return 0;
2232}
2233
192570e0
GFT
2234static int
2235jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2236{
2237 struct jme_adapter *jme = netdev_priv(netdev);
2238 struct dynpcc_info *dpi = &(jme->dpi);
2239
cd0ff491 2240 if (netif_running(netdev))
cdcdc9eb
GFT
2241 return -EBUSY;
2242
c97b5740
GFT
2243 if (ecmd->use_adaptive_rx_coalesce &&
2244 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2245 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2246 jme->jme_rx = netif_rx;
2247 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2248 dpi->cur = PCC_P1;
2249 dpi->attempt = PCC_P1;
2250 dpi->cnt = 0;
2251 jme_set_rx_pcc(jme, PCC_P1);
2252 jme_interrupt_mode(jme);
c97b5740
GFT
2253 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2254 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2255 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2256 jme->jme_rx = netif_receive_skb;
2257 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2258 jme_interrupt_mode(jme);
2259 }
2260
2261 return 0;
2262}
2263
8c198884
GFT
2264static void
2265jme_get_pauseparam(struct net_device *netdev,
2266 struct ethtool_pauseparam *ecmd)
2267{
2268 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2269 u32 val;
8c198884
GFT
2270
2271 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2272 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2273
cd0ff491
GFT
2274 spin_lock_bh(&jme->phy_lock);
2275 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2276 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2277
2278 ecmd->autoneg =
2279 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2280}
2281
2282static int
2283jme_set_pauseparam(struct net_device *netdev,
2284 struct ethtool_pauseparam *ecmd)
2285{
2286 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2287 u32 val;
8c198884 2288
cd0ff491 2289 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2290 (ecmd->tx_pause != 0)) {
2291
cd0ff491 2292 if (ecmd->tx_pause)
8c198884
GFT
2293 jme->reg_txpfc |= TXPFC_PF_EN;
2294 else
2295 jme->reg_txpfc &= ~TXPFC_PF_EN;
2296
2297 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2298 }
2299
cd0ff491
GFT
2300 spin_lock_bh(&jme->rxmcs_lock);
2301 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2302 (ecmd->rx_pause != 0)) {
2303
cd0ff491 2304 if (ecmd->rx_pause)
8c198884
GFT
2305 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2306 else
2307 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2308
2309 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2310 }
cd0ff491 2311 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2312
cd0ff491
GFT
2313 spin_lock_bh(&jme->phy_lock);
2314 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2315 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2316 (ecmd->autoneg != 0)) {
2317
cd0ff491 2318 if (ecmd->autoneg)
8c198884
GFT
2319 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2320 else
2321 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2322
b3821cc5
GFT
2323 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2324 MII_ADVERTISE, val);
8c198884 2325 }
cd0ff491 2326 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2327
2328 return 0;
2329}
2330
29bdd921
GFT
2331static void
2332jme_get_wol(struct net_device *netdev,
2333 struct ethtool_wolinfo *wol)
2334{
2335 struct jme_adapter *jme = netdev_priv(netdev);
2336
2337 wol->supported = WAKE_MAGIC | WAKE_PHY;
2338
2339 wol->wolopts = 0;
2340
cd0ff491 2341 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2342 wol->wolopts |= WAKE_PHY;
2343
cd0ff491 2344 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2345 wol->wolopts |= WAKE_MAGIC;
2346
2347}
2348
2349static int
2350jme_set_wol(struct net_device *netdev,
2351 struct ethtool_wolinfo *wol)
2352{
2353 struct jme_adapter *jme = netdev_priv(netdev);
2354
cd0ff491 2355 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2356 WAKE_UCAST |
2357 WAKE_MCAST |
2358 WAKE_BCAST |
2359 WAKE_ARP))
2360 return -EOPNOTSUPP;
2361
2362 jme->reg_pmcs = 0;
2363
cd0ff491 2364 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2365 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2366
cd0ff491 2367 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2368 jme->reg_pmcs |= PMCS_MFEN;
2369
cd0ff491 2370 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2371
29bdd921
GFT
2372 return 0;
2373}
b3821cc5 2374
8c198884 2375static int
3bf61c55
GFT
2376jme_get_settings(struct net_device *netdev,
2377 struct ethtool_cmd *ecmd)
d7699f87
GFT
2378{
2379 struct jme_adapter *jme = netdev_priv(netdev);
2380 int rc;
8c198884 2381
cd0ff491 2382 spin_lock_bh(&jme->phy_lock);
d7699f87 2383 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2384 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2385 return rc;
2386}
2387
3bf61c55
GFT
2388static int
2389jme_set_settings(struct net_device *netdev,
2390 struct ethtool_cmd *ecmd)
d7699f87
GFT
2391{
2392 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2393 int rc, fdc = 0;
fcf45b4c 2394
cd0ff491 2395 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2396 return -EINVAL;
2397
f79361a6
GFT
2398 /*
2399 * Check If user changed duplex only while force_media.
2400 * Hardware would not generate link change interrupt.
2401 */
cd0ff491 2402 if (jme->mii_if.force_media &&
79ce639c
GFT
2403 ecmd->autoneg != AUTONEG_ENABLE &&
2404 (jme->mii_if.full_duplex != ecmd->duplex))
2405 fdc = 1;
2406
cd0ff491 2407 spin_lock_bh(&jme->phy_lock);
d7699f87 2408 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2409 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2410
cd0ff491 2411 if (!rc) {
f79361a6
GFT
2412 if (fdc)
2413 jme_reset_link(jme);
cd0ff491 2414 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2415 jme->old_ecmd = *ecmd;
2416 }
2417
d7699f87
GFT
2418 return rc;
2419}
2420
cd0ff491 2421static u32
3bf61c55
GFT
2422jme_get_link(struct net_device *netdev)
2423{
d7699f87
GFT
2424 struct jme_adapter *jme = netdev_priv(netdev);
2425 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2426}
2427
8c198884 2428static u32
cd0ff491
GFT
2429jme_get_msglevel(struct net_device *netdev)
2430{
2431 struct jme_adapter *jme = netdev_priv(netdev);
2432 return jme->msg_enable;
2433}
2434
2435static void
2436jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2437{
cd0ff491
GFT
2438 struct jme_adapter *jme = netdev_priv(netdev);
2439 jme->msg_enable = value;
2440}
8c198884 2441
cd0ff491
GFT
2442static u32
2443jme_get_rx_csum(struct net_device *netdev)
2444{
2445 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2446 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2447}
2448
2449static int
2450jme_set_rx_csum(struct net_device *netdev, u32 on)
2451{
cd0ff491 2452 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2453
cd0ff491
GFT
2454 spin_lock_bh(&jme->rxmcs_lock);
2455 if (on)
8c198884
GFT
2456 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2457 else
2458 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2459 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2460 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2461
2462 return 0;
2463}
2464
2465static int
2466jme_set_tx_csum(struct net_device *netdev, u32 on)
2467{
cd0ff491 2468 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2469
cd0ff491
GFT
2470 if (on) {
2471 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2472 if (netdev->mtu <= 1900)
b3821cc5 2473 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491
GFT
2474 } else {
2475 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
8c198884 2476 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2477 }
8c198884
GFT
2478
2479 return 0;
2480}
2481
2482static int
b3821cc5
GFT
2483jme_set_tso(struct net_device *netdev, u32 on)
2484{
cd0ff491 2485 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2486
cd0ff491
GFT
2487 if (on) {
2488 set_bit(JME_FLAG_TSO, &jme->flags);
2489 if (netdev->mtu <= 1900)
b3821cc5 2490 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT
2491 } else {
2492 clear_bit(JME_FLAG_TSO, &jme->flags);
2493 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT
2494 }
2495
cd0ff491 2496 return 0;
b3821cc5
GFT
2497}
2498
2499static int
8c198884
GFT
2500jme_nway_reset(struct net_device *netdev)
2501{
cd0ff491 2502 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2503 jme_restart_an(jme);
2504 return 0;
2505}
2506
cd0ff491 2507static u8
186fc259
GFT
2508jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2509{
cd0ff491 2510 u32 val;
186fc259
GFT
2511 int to;
2512
2513 val = jread32(jme, JME_SMBCSR);
2514 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2515 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2516 msleep(1);
2517 val = jread32(jme, JME_SMBCSR);
2518 }
cd0ff491 2519 if (!to) {
52a46ba8 2520 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2521 return 0xFF;
2522 }
2523
2524 jwrite32(jme, JME_SMBINTF,
2525 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2526 SMBINTF_HWRWN_READ |
2527 SMBINTF_HWCMD);
2528
2529 val = jread32(jme, JME_SMBINTF);
2530 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2531 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2532 msleep(1);
2533 val = jread32(jme, JME_SMBINTF);
2534 }
cd0ff491 2535 if (!to) {
52a46ba8 2536 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2537 return 0xFF;
2538 }
2539
2540 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2541}
2542
2543static void
cd0ff491 2544jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2545{
cd0ff491 2546 u32 val;
186fc259
GFT
2547 int to;
2548
2549 val = jread32(jme, JME_SMBCSR);
2550 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2551 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2552 msleep(1);
2553 val = jread32(jme, JME_SMBCSR);
2554 }
cd0ff491 2555 if (!to) {
52a46ba8 2556 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2557 return;
2558 }
2559
2560 jwrite32(jme, JME_SMBINTF,
2561 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2562 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2563 SMBINTF_HWRWN_WRITE |
2564 SMBINTF_HWCMD);
2565
2566 val = jread32(jme, JME_SMBINTF);
2567 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2568 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2569 msleep(1);
2570 val = jread32(jme, JME_SMBINTF);
2571 }
cd0ff491 2572 if (!to) {
52a46ba8 2573 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2574 return;
2575 }
2576
2577 mdelay(2);
2578}
2579
2580static int
2581jme_get_eeprom_len(struct net_device *netdev)
2582{
cd0ff491
GFT
2583 struct jme_adapter *jme = netdev_priv(netdev);
2584 u32 val;
186fc259 2585 val = jread32(jme, JME_SMBCSR);
cd0ff491 2586 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2587}
2588
2589static int
2590jme_get_eeprom(struct net_device *netdev,
2591 struct ethtool_eeprom *eeprom, u8 *data)
2592{
cd0ff491 2593 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2594 int i, offset = eeprom->offset, len = eeprom->len;
2595
2596 /*
8d27293f 2597 * ethtool will check the boundary for us
186fc259
GFT
2598 */
2599 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2600 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2601 data[i] = jme_smb_read(jme, i + offset);
2602
2603 return 0;
2604}
2605
2606static int
2607jme_set_eeprom(struct net_device *netdev,
2608 struct ethtool_eeprom *eeprom, u8 *data)
2609{
cd0ff491 2610 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2611 int i, offset = eeprom->offset, len = eeprom->len;
2612
2613 if (eeprom->magic != JME_EEPROM_MAGIC)
2614 return -EINVAL;
2615
2616 /*
8d27293f 2617 * ethtool will check the boundary for us
186fc259 2618 */
cd0ff491 2619 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2620 jme_smb_write(jme, i + offset, data[i]);
2621
2622 return 0;
2623}
2624
d7699f87 2625static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2626 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2627 .get_regs_len = jme_get_regs_len,
2628 .get_regs = jme_get_regs,
2629 .get_coalesce = jme_get_coalesce,
192570e0 2630 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2631 .get_pauseparam = jme_get_pauseparam,
2632 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2633 .get_wol = jme_get_wol,
2634 .set_wol = jme_set_wol,
d7699f87
GFT
2635 .get_settings = jme_get_settings,
2636 .set_settings = jme_set_settings,
2637 .get_link = jme_get_link,
cd0ff491
GFT
2638 .get_msglevel = jme_get_msglevel,
2639 .set_msglevel = jme_set_msglevel,
8c198884
GFT
2640 .get_rx_csum = jme_get_rx_csum,
2641 .set_rx_csum = jme_set_rx_csum,
2642 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2643 .set_tso = jme_set_tso,
2644 .set_sg = ethtool_op_set_sg,
8c198884 2645 .nway_reset = jme_nway_reset,
186fc259
GFT
2646 .get_eeprom_len = jme_get_eeprom_len,
2647 .get_eeprom = jme_get_eeprom,
2648 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2649};
2650
3bf61c55
GFT
2651static int
2652jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2653{
94c5ea02 2654 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT
2655 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2656 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT
2657 return 1;
2658
94c5ea02 2659 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT
2660 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2661 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT
2662 return 1;
2663
fa97b924
GFT
2664 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2665 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT
2666 return 0;
2667
2668 return -1;
2669}
2670
cd0ff491 2671static inline void
cdcdc9eb
GFT
2672jme_phy_init(struct jme_adapter *jme)
2673{
cd0ff491 2674 u16 reg26;
cdcdc9eb
GFT
2675
2676 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2677 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2678}
2679
cd0ff491 2680static inline void
cdcdc9eb 2681jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2682{
cd0ff491 2683 u32 chipmode;
cdcdc9eb
GFT
2684
2685 chipmode = jread32(jme, JME_CHIPMODE);
2686
2687 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2688 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
42b1055e
GFT
2689}
2690
94c5ea02
GFT
2691static const struct net_device_ops jme_netdev_ops = {
2692 .ndo_open = jme_open,
2693 .ndo_stop = jme_close,
2694 .ndo_validate_addr = eth_validate_addr,
2695 .ndo_start_xmit = jme_start_xmit,
2696 .ndo_set_mac_address = jme_set_macaddr,
2697 .ndo_set_multicast_list = jme_set_multi,
2698 .ndo_change_mtu = jme_change_mtu,
2699 .ndo_tx_timeout = jme_tx_timeout,
2700 .ndo_vlan_rx_register = jme_vlan_rx_register,
2701};
2702
3bf61c55
GFT
2703static int __devinit
2704jme_init_one(struct pci_dev *pdev,
2705 const struct pci_device_id *ent)
2706{
cdcdc9eb 2707 int rc = 0, using_dac, i;
d7699f87
GFT
2708 struct net_device *netdev;
2709 struct jme_adapter *jme;
cd0ff491
GFT
2710 u16 bmcr, bmsr;
2711 u32 apmc;
d7699f87
GFT
2712
2713 /*
2714 * set up PCI device basics
2715 */
4330c2f2 2716 rc = pci_enable_device(pdev);
cd0ff491 2717 if (rc) {
52a46ba8 2718 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT
2719 goto err_out;
2720 }
d7699f87 2721
3bf61c55 2722 using_dac = jme_pci_dma64(pdev);
cd0ff491 2723 if (using_dac < 0) {
52a46ba8 2724 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT
2725 rc = -EIO;
2726 goto err_out_disable_pdev;
2727 }
2728
cd0ff491 2729 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
52a46ba8 2730 pr_err("No PCI resource region found\n");
4330c2f2
GFT
2731 rc = -ENOMEM;
2732 goto err_out_disable_pdev;
2733 }
d7699f87 2734
4330c2f2 2735 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2736 if (rc) {
52a46ba8 2737 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT
2738 goto err_out_disable_pdev;
2739 }
d7699f87
GFT
2740
2741 pci_set_master(pdev);
2742
2743 /*
2744 * alloc and init net device
2745 */
3bf61c55 2746 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2747 if (!netdev) {
52a46ba8 2748 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT
2749 rc = -ENOMEM;
2750 goto err_out_release_regions;
d7699f87 2751 }
94c5ea02 2752 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2753 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2754 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2755 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT
2756 NETIF_F_SG |
2757 NETIF_F_TSO |
2758 NETIF_F_TSO6 |
42b1055e
GFT
2759 NETIF_F_HW_VLAN_TX |
2760 NETIF_F_HW_VLAN_RX;
cd0ff491 2761 if (using_dac)
8c198884 2762 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2763
2764 SET_NETDEV_DEV(netdev, &pdev->dev);
2765 pci_set_drvdata(pdev, netdev);
2766
2767 /*
2768 * init adapter info
2769 */
2770 jme = netdev_priv(netdev);
2771 jme->pdev = pdev;
2772 jme->dev = netdev;
cdcdc9eb
GFT
2773 jme->jme_rx = netif_rx;
2774 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2775 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2776 jme->phylink = 0;
b3821cc5
GFT
2777 jme->tx_ring_size = 1 << 10;
2778 jme->tx_ring_mask = jme->tx_ring_size - 1;
2779 jme->tx_wake_threshold = 1 << 9;
2780 jme->rx_ring_size = 1 << 9;
2781 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2782 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
2783 jme->regs = ioremap(pci_resource_start(pdev, 0),
2784 pci_resource_len(pdev, 0));
4330c2f2 2785 if (!(jme->regs)) {
52a46ba8 2786 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT
2787 rc = -ENOMEM;
2788 goto err_out_free_netdev;
2789 }
4330c2f2 2790
cd0ff491
GFT
2791 if (no_pseudohp) {
2792 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2793 jwrite32(jme, JME_APMC, apmc);
2794 } else if (force_pseudohp) {
2795 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2796 jwrite32(jme, JME_APMC, apmc);
2797 }
2798
cdcdc9eb 2799 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2800
d7699f87 2801 spin_lock_init(&jme->phy_lock);
fcf45b4c 2802 spin_lock_init(&jme->macaddr_lock);
8c198884 2803 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2804
fcf45b4c
GFT
2805 atomic_set(&jme->link_changing, 1);
2806 atomic_set(&jme->rx_cleaning, 1);
2807 atomic_set(&jme->tx_cleaning, 1);
192570e0 2808 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2809
79ce639c 2810 tasklet_init(&jme->pcc_task,
c97b5740 2811 jme_pcc_tasklet,
79ce639c 2812 (unsigned long) jme);
4330c2f2 2813 tasklet_init(&jme->linkch_task,
c97b5740 2814 jme_link_change_tasklet,
4330c2f2
GFT
2815 (unsigned long) jme);
2816 tasklet_init(&jme->txclean_task,
c97b5740 2817 jme_tx_clean_tasklet,
4330c2f2
GFT
2818 (unsigned long) jme);
2819 tasklet_init(&jme->rxclean_task,
c97b5740 2820 jme_rx_clean_tasklet,
4330c2f2 2821 (unsigned long) jme);
fcf45b4c 2822 tasklet_init(&jme->rxempty_task,
c97b5740 2823 jme_rx_empty_tasklet,
fcf45b4c 2824 (unsigned long) jme);
fa97b924 2825 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT
2826 tasklet_disable_nosync(&jme->txclean_task);
2827 tasklet_disable_nosync(&jme->rxclean_task);
2828 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
2829 jme->dpi.cur = PCC_P1;
2830
cd0ff491 2831 jme->reg_ghc = 0;
79ce639c 2832 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
2833 jme->reg_rxmcs = RXMCS_DEFAULT;
2834 jme->reg_txpfc = 0;
47220951 2835 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT
2836 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2837 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 2838
d7699f87 2839 /*
fcf45b4c
GFT
2840 * Get Max Read Req Size from PCI Config Space
2841 */
cd0ff491
GFT
2842 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2843 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2844 switch (jme->mrrs) {
2845 case MRRS_128B:
2846 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2847 break;
2848 case MRRS_256B:
2849 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2850 break;
2851 default:
2852 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2853 break;
06527f9b 2854 }
fcf45b4c 2855
fcf45b4c 2856 /*
cdcdc9eb 2857 * Must check before reset_mac_processor
d7699f87 2858 */
cdcdc9eb
GFT
2859 jme_check_hw_ver(jme);
2860 jme->mii_if.dev = netdev;
cd0ff491 2861 if (jme->fpgaver) {
cdcdc9eb 2862 jme->mii_if.phy_id = 0;
cd0ff491 2863 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
2864 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2865 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 2866 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
2867 jme->mii_if.phy_id = i;
2868 break;
2869 }
2870 }
2871
cd0ff491 2872 if (!jme->mii_if.phy_id) {
cdcdc9eb 2873 rc = -EIO;
52a46ba8
JP
2874 pr_err("Can not find phy_id\n");
2875 goto err_out_unmap;
cdcdc9eb
GFT
2876 }
2877
2878 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 2879 } else {
cdcdc9eb
GFT
2880 jme->mii_if.phy_id = 1;
2881 }
cd0ff491 2882 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
2883 jme->mii_if.supports_gmii = true;
2884 else
2885 jme->mii_if.supports_gmii = false;
cdcdc9eb
GFT
2886 jme->mii_if.mdio_read = jme_mdio_read;
2887 jme->mii_if.mdio_write = jme_mdio_write;
2888
d7699f87 2889 jme_clear_pm(jme);
e882564f 2890 jme_set_phyfifoa(jme);
cd0ff491
GFT
2891 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2892 if (!jme->fpgaver)
cdcdc9eb 2893 jme_phy_init(jme);
42b1055e 2894 jme_phy_off(jme);
cdcdc9eb
GFT
2895
2896 /*
2897 * Reset MAC processor and reload EEPROM for MAC Address
2898 */
d7699f87 2899 jme_reset_mac_processor(jme);
4330c2f2 2900 rc = jme_reload_eeprom(jme);
cd0ff491 2901 if (rc) {
52a46ba8 2902 pr_err("Reload eeprom for reading MAC Address error\n");
fa97b924 2903 goto err_out_unmap;
4330c2f2 2904 }
d7699f87
GFT
2905 jme_load_macaddr(netdev);
2906
d7699f87
GFT
2907 /*
2908 * Tell stack that we are not ready to work until open()
2909 */
2910 netif_carrier_off(netdev);
2911 netif_stop_queue(netdev);
2912
2913 /*
2914 * Register netdev
2915 */
4330c2f2 2916 rc = register_netdev(netdev);
cd0ff491 2917 if (rc) {
52a46ba8 2918 pr_err("Cannot register net device\n");
fa97b924 2919 goto err_out_unmap;
4330c2f2 2920 }
d7699f87 2921
c97b5740
GFT
2922 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2923 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2924 "JMC250 Gigabit Ethernet" :
2925 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2926 "JMC260 Fast Ethernet" : "Unknown",
2927 (jme->fpgaver != 0) ? " (FPGA)" : "",
2928 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2929 jme->rev, netdev->dev_addr);
d7699f87
GFT
2930
2931 return 0;
2932
2933err_out_unmap:
2934 iounmap(jme->regs);
2935err_out_free_netdev:
2936 pci_set_drvdata(pdev, NULL);
2937 free_netdev(netdev);
4330c2f2
GFT
2938err_out_release_regions:
2939 pci_release_regions(pdev);
d7699f87 2940err_out_disable_pdev:
cd0ff491 2941 pci_disable_device(pdev);
d7699f87 2942err_out:
4330c2f2 2943 return rc;
d7699f87
GFT
2944}
2945
3bf61c55
GFT
2946static void __devexit
2947jme_remove_one(struct pci_dev *pdev)
2948{
d7699f87
GFT
2949 struct net_device *netdev = pci_get_drvdata(pdev);
2950 struct jme_adapter *jme = netdev_priv(netdev);
2951
2952 unregister_netdev(netdev);
2953 iounmap(jme->regs);
2954 pci_set_drvdata(pdev, NULL);
2955 free_netdev(netdev);
2956 pci_release_regions(pdev);
2957 pci_disable_device(pdev);
2958
2959}
2960
9b9d55de 2961#ifdef CONFIG_PM
29bdd921
GFT
2962static int
2963jme_suspend(struct pci_dev *pdev, pm_message_t state)
2964{
2965 struct net_device *netdev = pci_get_drvdata(pdev);
2966 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
2967
2968 atomic_dec(&jme->link_changing);
2969
2970 netif_device_detach(netdev);
2971 netif_stop_queue(netdev);
2972 jme_stop_irq(jme);
29bdd921 2973
cd0ff491
GFT
2974 tasklet_disable(&jme->txclean_task);
2975 tasklet_disable(&jme->rxclean_task);
2976 tasklet_disable(&jme->rxempty_task);
2977
cd0ff491
GFT
2978 if (netif_carrier_ok(netdev)) {
2979 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
2980 jme_polling_mode(jme);
2981
29bdd921 2982 jme_stop_pcc_timer(jme);
cd0ff491
GFT
2983 jme_reset_ghc_speed(jme);
2984 jme_disable_rx_engine(jme);
2985 jme_disable_tx_engine(jme);
29bdd921
GFT
2986 jme_reset_mac_processor(jme);
2987 jme_free_rx_resources(jme);
2988 jme_free_tx_resources(jme);
2989 netif_carrier_off(netdev);
2990 jme->phylink = 0;
2991 }
2992
cd0ff491
GFT
2993 tasklet_enable(&jme->txclean_task);
2994 tasklet_hi_enable(&jme->rxclean_task);
2995 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT
2996
2997 pci_save_state(pdev);
cd0ff491 2998 if (jme->reg_pmcs) {
42b1055e 2999 jme_set_100m_half(jme);
47220951 3000
cd0ff491 3001 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
47220951
GFT
3002 jme_wait_link(jme);
3003
29bdd921 3004 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
cd0ff491 3005
42b1055e 3006 pci_enable_wake(pdev, PCI_D3cold, true);
cd0ff491 3007 } else {
42b1055e 3008 jme_phy_off(jme);
29bdd921 3009 }
cd0ff491 3010 pci_set_power_state(pdev, PCI_D3cold);
29bdd921
GFT
3011
3012 return 0;
3013}
3014
3015static int
3016jme_resume(struct pci_dev *pdev)
3017{
3018 struct net_device *netdev = pci_get_drvdata(pdev);
3019 struct jme_adapter *jme = netdev_priv(netdev);
3020
3021 jme_clear_pm(jme);
3022 pci_restore_state(pdev);
3023
48db98f7
GFT
3024 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3025 jme_phy_on(jme);
29bdd921 3026 jme_set_settings(netdev, &jme->old_ecmd);
48db98f7 3027 } else {
29bdd921 3028 jme_reset_phy_processor(jme);
48db98f7 3029 }
29bdd921 3030
29bdd921
GFT
3031 jme_start_irq(jme);
3032 netif_device_attach(netdev);
3033
3034 atomic_inc(&jme->link_changing);
3035
3036 jme_reset_link(jme);
3037
3038 return 0;
3039}
9b9d55de 3040#endif
29bdd921 3041
c97b5740 3042static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
cd0ff491
GFT
3043 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3044 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3045 { }
3046};
3047
3048static struct pci_driver jme_driver = {
cd0ff491
GFT
3049 .name = DRV_NAME,
3050 .id_table = jme_pci_tbl,
3051 .probe = jme_init_one,
3052 .remove = __devexit_p(jme_remove_one),
d7699f87 3053#ifdef CONFIG_PM
cd0ff491
GFT
3054 .suspend = jme_suspend,
3055 .resume = jme_resume,
d7699f87 3056#endif /* CONFIG_PM */
d7699f87
GFT
3057};
3058
3bf61c55
GFT
3059static int __init
3060jme_init_module(void)
d7699f87 3061{
52a46ba8 3062 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT
3063 return pci_register_driver(&jme_driver);
3064}
3065
3bf61c55
GFT
3066static void __exit
3067jme_cleanup_module(void)
d7699f87
GFT
3068{
3069 pci_unregister_driver(&jme_driver);
3070}
3071
3072module_init(jme_init_module);
3073module_exit(jme_cleanup_module);
3074
3bf61c55 3075MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3076MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3077MODULE_LICENSE("GPL");
3078MODULE_VERSION(DRV_VERSION);
3079MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3080