Import jme 0.9d source
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
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GFT
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
d7699f87
GFT
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24/*
b3821cc5 25 * TODO:
b3821cc5 26 * - Decode register dump for ethtool.
d7699f87
GFT
27 */
28
4330c2f2 29#include <linux/version.h>
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GFT
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
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GFT
40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
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GFT
46#include "jme.h"
47
4330c2f2 48#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
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GFT
49static struct net_device_stats *
50jme_get_stats(struct net_device *netdev)
4330c2f2
GFT
51{
52 struct jme_adapter *jme = netdev_priv(netdev);
53 return &jme->stats;
54}
55#endif
56
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GFT
57static int
58jme_mdio_read(struct net_device *netdev, int phy, int reg)
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GFT
59{
60 struct jme_adapter *jme = netdev_priv(netdev);
186fc259 61 int i, val, again = (reg == MII_BMSR)?1:0;
d7699f87 62
186fc259 63read_again:
d7699f87 64 jwrite32(jme, JME_SMI, SMI_OP_REQ |
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GFT
65 smi_phy_addr(phy) |
66 smi_reg_addr(reg));
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GFT
67
68 wmb();
cdcdc9eb
GFT
69 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
70 udelay(20);
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GFT
71 val = jread32(jme, JME_SMI);
72 if ((val & SMI_OP_REQ) == 0)
3bf61c55 73 break;
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GFT
74 }
75
76 if (i == 0) {
cdcdc9eb 77 jeprintk("jme", "phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 78 return 0;
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GFT
79 }
80
186fc259
GFT
81 if(again--)
82 goto read_again;
83
3bf61c55 84 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
d7699f87
GFT
85}
86
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GFT
87static void
88jme_mdio_write(struct net_device *netdev,
89 int phy, int reg, int val)
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GFT
90{
91 struct jme_adapter *jme = netdev_priv(netdev);
92 int i;
93
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GFT
94 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
95 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
96 smi_phy_addr(phy) | smi_reg_addr(reg));
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97
98 wmb();
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GFT
99 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
100 udelay(20);
8d27293f 101 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
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102 break;
103 }
d7699f87 104
3bf61c55 105 if (i == 0)
cdcdc9eb 106 jeprintk("jme", "phy(%d) write timeout : %d\n", phy, reg);
d7699f87 107
3bf61c55 108 return;
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109}
110
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GFT
111__always_inline static void
112jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 113{
fcf45b4c 114 __u32 val;
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GFT
115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
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GFT
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 120
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GFT
121 if(jme->pdev->device == JME_GE_DEVICE)
122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 126
fcf45b4c
GFT
127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
134
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GFT
135 return;
136}
137
b3821cc5
GFT
138static void
139jme_setup_wakeup_frame(struct jme_adapter *jme,
140 __u32 *mask, __u32 crc, int fnr)
141{
142 int i;
143
144 /*
145 * Setup CRC pattern
146 */
147 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
148 wmb();
149 jwrite32(jme, JME_WFODP, crc);
150 wmb();
151
152 /*
153 * Setup Mask
154 */
155 for(i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
156 jwrite32(jme, JME_WFOI,
157 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
158 (fnr & WFOI_FRAME_SEL));
159 wmb();
160 jwrite32(jme, JME_WFODP, mask[i]);
161 wmb();
162 }
163}
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GFT
164
165__always_inline static void
166jme_reset_mac_processor(struct jme_adapter *jme)
167{
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168 __u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0,0,0,0};
169 __u32 crc = 0xCDCDCDCD;
cdcdc9eb 170 __u32 gpreg0;
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GFT
171 int i;
172
3bf61c55 173 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 174 udelay(2);
3bf61c55 175 jwrite32(jme, JME_GHC, jme->reg_ghc);
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GFT
176 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
177 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
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178 for(i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
179 jme_setup_wakeup_frame(jme, mask, crc, i);
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GFT
180 if(jme->fpgaver)
181 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
182 else
183 gpreg0 = GPREG0_DEFAULT;
184 jwrite32(jme, JME_GPREG0, gpreg0);
4330c2f2 185 jwrite32(jme, JME_GPREG1, 0);
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GFT
186}
187
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GFT
188__always_inline static void
189jme_clear_pm(struct jme_adapter *jme)
d7699f87 190{
29bdd921 191 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 192 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 193 pci_enable_wake(jme->pdev, PCI_D0, false);
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194}
195
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196static int
197jme_reload_eeprom(struct jme_adapter *jme)
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198{
199 __u32 val;
200 int i;
201
202 val = jread32(jme, JME_SMBCSR);
203
204 if(val & SMBCSR_EEPROMD)
205 {
206 val |= SMBCSR_CNACK;
207 jwrite32(jme, JME_SMBCSR, val);
208 val |= SMBCSR_RELOAD;
209 jwrite32(jme, JME_SMBCSR, val);
210 mdelay(12);
211
186fc259 212 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i)
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GFT
213 {
214 mdelay(1);
215 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
216 break;
217 }
218
219 if(i == 0) {
186fc259 220 jeprintk("jme", "eeprom reload timeout\n");
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221 return -EIO;
222 }
223 }
3bf61c55 224
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225 return 0;
226}
227
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228static void
229jme_load_macaddr(struct net_device *netdev)
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GFT
230{
231 struct jme_adapter *jme = netdev_priv(netdev);
232 unsigned char macaddr[6];
233 __u32 val;
234
fcf45b4c 235 spin_lock(&jme->macaddr_lock);
4330c2f2 236 val = jread32(jme, JME_RXUMA_LO);
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GFT
237 macaddr[0] = (val >> 0) & 0xFF;
238 macaddr[1] = (val >> 8) & 0xFF;
239 macaddr[2] = (val >> 16) & 0xFF;
240 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 241 val = jread32(jme, JME_RXUMA_HI);
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GFT
242 macaddr[4] = (val >> 0) & 0xFF;
243 macaddr[5] = (val >> 8) & 0xFF;
244 memcpy(netdev->dev_addr, macaddr, 6);
fcf45b4c 245 spin_unlock(&jme->macaddr_lock);
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GFT
246}
247
fcf45b4c 248__always_inline static void
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249jme_set_rx_pcc(struct jme_adapter *jme, int p)
250{
251 switch(p) {
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GFT
252 case PCC_OFF:
253 jwrite32(jme, JME_PCCRX0,
254 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
255 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
256 break;
3bf61c55
GFT
257 case PCC_P1:
258 jwrite32(jme, JME_PCCRX0,
259 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
260 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
261 break;
262 case PCC_P2:
263 jwrite32(jme, JME_PCCRX0,
264 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
265 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
266 break;
267 case PCC_P3:
268 jwrite32(jme, JME_PCCRX0,
269 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
270 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 break;
272 default:
273 break;
274 }
192570e0 275 wmb();
3bf61c55 276
192570e0
GFT
277 if(!(jme->flags & JME_FLAG_POLL))
278 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
d7699f87
GFT
279}
280
fcf45b4c 281static void
3bf61c55 282jme_start_irq(struct jme_adapter *jme)
d7699f87 283{
3bf61c55
GFT
284 register struct dynpcc_info *dpi = &(jme->dpi);
285
286 jme_set_rx_pcc(jme, PCC_P1);
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GFT
287 dpi->cur = PCC_P1;
288 dpi->attempt = PCC_P1;
289 dpi->cnt = 0;
290
291 jwrite32(jme, JME_PCCTX,
8c198884
GFT
292 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
293 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
294 PCCTXQ0_EN
295 );
296
d7699f87
GFT
297 /*
298 * Enable Interrupts
299 */
300 jwrite32(jme, JME_IENS, INTR_ENABLE);
301}
302
3bf61c55
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303__always_inline static void
304jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
305{
306 /*
307 * Disable Interrupts
308 */
309 jwrite32(jme, JME_IENC, INTR_ENABLE);
310}
311
4330c2f2 312
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GFT
313__always_inline static void
314jme_enable_shadow(struct jme_adapter *jme)
4330c2f2
GFT
315{
316 jwrite32(jme,
317 JME_SHBA_LO,
318 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
319}
320
3bf61c55
GFT
321__always_inline static void
322jme_disable_shadow(struct jme_adapter *jme)
4330c2f2
GFT
323{
324 jwrite32(jme, JME_SHBA_LO, 0x0);
325}
326
cdcdc9eb
GFT
327static __u32
328jme_linkstat_from_phy(struct jme_adapter *jme)
329{
330 __u32 phylink, bmsr;
331
332 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
333 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
8d27293f 334 if(bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
335 phylink |= PHY_LINK_AUTONEG_COMPLETE;
336
337 return phylink;
338}
339
fcf45b4c
GFT
340static int
341jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
342{
343 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 344 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 345 char linkmsg[64];
fcf45b4c 346 int rc = 0;
d7699f87 347
b3821cc5 348 linkmsg[0] = '\0';
cdcdc9eb
GFT
349
350 if(jme->fpgaver)
351 phylink = jme_linkstat_from_phy(jme);
352 else
353 phylink = jread32(jme, JME_PHY_LINK);
d7699f87
GFT
354
355 if (phylink & PHY_LINK_UP) {
8c198884
GFT
356 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
357 /*
358 * If we did not enable AN
359 * Speed/Duplex Info should be obtained from SMI
360 */
361 phylink = PHY_LINK_UP;
362
363 bmcr = jme_mdio_read(jme->dev,
364 jme->mii_if.phy_id,
365 MII_BMCR);
366
79ce639c 367
8c198884
GFT
368 phylink |= ((bmcr & BMCR_SPEED1000) &&
369 (bmcr & BMCR_SPEED100) == 0) ?
370 PHY_LINK_SPEED_1000M :
371 (bmcr & BMCR_SPEED100) ?
372 PHY_LINK_SPEED_100M :
373 PHY_LINK_SPEED_10M;
374
375 phylink |= (bmcr & BMCR_FULLDPLX) ?
376 PHY_LINK_DUPLEX : 0;
79ce639c 377
b3821cc5 378 strcat(linkmsg, "Forced: ");
8c198884
GFT
379 }
380 else {
381 /*
382 * Keep polling for speed/duplex resolve complete
383 */
384 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
385 --cnt) {
386
387 udelay(1);
8c198884 388
cdcdc9eb
GFT
389 if(jme->fpgaver)
390 phylink = jme_linkstat_from_phy(jme);
391 else
392 phylink = jread32(jme, JME_PHY_LINK);
8c198884
GFT
393 }
394
395 if(!cnt)
396 jeprintk(netdev->name,
397 "Waiting speed resolve timeout.\n");
79ce639c 398
b3821cc5 399 strcat(linkmsg, "ANed: ");
d7699f87
GFT
400 }
401
fcf45b4c
GFT
402 if(jme->phylink == phylink) {
403 rc = 1;
404 goto out;
405 }
406 if(testonly)
407 goto out;
408
409 jme->phylink = phylink;
410
cdcdc9eb
GFT
411 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
412 GHC_SPEED_100M |
413 GHC_SPEED_1000M |
414 GHC_DPX);
d7699f87
GFT
415 switch(phylink & PHY_LINK_SPEED_MASK) {
416 case PHY_LINK_SPEED_10M:
cdcdc9eb 417 ghc |= GHC_SPEED_10M;
b3821cc5 418 strcat(linkmsg, "10 Mbps, ");
d7699f87
GFT
419 break;
420 case PHY_LINK_SPEED_100M:
cdcdc9eb 421 ghc |= GHC_SPEED_100M;
b3821cc5 422 strcat(linkmsg, "100 Mbps, ");
d7699f87
GFT
423 break;
424 case PHY_LINK_SPEED_1000M:
cdcdc9eb 425 ghc |= GHC_SPEED_1000M;
b3821cc5 426 strcat(linkmsg, "1000 Mbps, ");
d7699f87
GFT
427 break;
428 default:
d7699f87
GFT
429 break;
430 }
431 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
fcf45b4c 432
d7699f87 433 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
fcf45b4c
GFT
434 "Full-Duplex, " :
435 "Half-Duplex, ");
436
437 if(phylink & PHY_LINK_MDI_STAT)
fcf45b4c 438 strcat(linkmsg, "MDI-X");
8c198884
GFT
439 else
440 strcat(linkmsg, "MDI");
d7699f87
GFT
441
442 if(phylink & PHY_LINK_DUPLEX)
443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
8c198884 444 else {
d7699f87 445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
446 TXMCS_BACKOFF |
447 TXMCS_CARRIERSENSE |
448 TXMCS_COLLISION);
8c198884
GFT
449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
451 TXTRHD_TXREN |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
453 }
d7699f87 454
fcf45b4c
GFT
455 jme->reg_ghc = ghc;
456 jwrite32(jme, JME_GHC, ghc);
457
4330c2f2 458 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
d7699f87
GFT
459 netif_carrier_on(netdev);
460 }
461 else {
fcf45b4c
GFT
462 if(testonly)
463 goto out;
464
4330c2f2 465 jprintk(netdev->name, "Link is down.\n");
fcf45b4c 466 jme->phylink = 0;
d7699f87
GFT
467 netif_carrier_off(netdev);
468 }
fcf45b4c
GFT
469
470out:
471 return rc;
d7699f87
GFT
472}
473
3bf61c55
GFT
474static int
475jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 476{
d7699f87
GFT
477 struct jme_ring *txring = &(jme->txring[0]);
478
479 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
480 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
481 &(txring->dmaalloc),
482 GFP_ATOMIC);
fcf45b4c 483
4330c2f2
GFT
484 if(!txring->alloc) {
485 txring->desc = NULL;
486 txring->dmaalloc = 0;
487 txring->dma = 0;
d7699f87 488 return -ENOMEM;
4330c2f2 489 }
d7699f87
GFT
490
491 /*
492 * 16 Bytes align
493 */
3bf61c55
GFT
494 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
495 RING_DESC_ALIGN);
4330c2f2 496 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 497 txring->next_to_use = 0;
cdcdc9eb 498 atomic_set(&txring->next_to_clean, 0);
b3821cc5 499 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87
GFT
500
501 /*
b3821cc5 502 * Initialize Transmit Descriptors
d7699f87 503 */
b3821cc5 504 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 505 memset(txring->bufinf, 0,
b3821cc5 506 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
507
508 return 0;
509}
510
3bf61c55
GFT
511static void
512jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
513{
514 int i;
515 struct jme_ring *txring = &(jme->txring[0]);
4330c2f2 516 struct jme_buffer_info *txbi = txring->bufinf;
d7699f87
GFT
517
518 if(txring->alloc) {
b3821cc5 519 for(i = 0 ; i < jme->tx_ring_size ; ++i) {
4330c2f2
GFT
520 txbi = txring->bufinf + i;
521 if(txbi->skb) {
522 dev_kfree_skb(txbi->skb);
523 txbi->skb = NULL;
d7699f87 524 }
3bf61c55
GFT
525 txbi->mapping = 0;
526 txbi->len = 0;
527 txbi->nr_desc = 0;
d7699f87
GFT
528 }
529
530 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 531 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
532 txring->alloc,
533 txring->dmaalloc);
3bf61c55
GFT
534
535 txring->alloc = NULL;
536 txring->desc = NULL;
537 txring->dmaalloc = 0;
538 txring->dma = 0;
d7699f87 539 }
3bf61c55 540 txring->next_to_use = 0;
cdcdc9eb 541 atomic_set(&txring->next_to_clean, 0);
79ce639c 542 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
543
544}
545
3bf61c55
GFT
546__always_inline static void
547jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
548{
549 /*
550 * Select Queue 0
551 */
552 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
553
554 /*
555 * Setup TX Queue 0 DMA Bass Address
556 */
fcf45b4c 557 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 558 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 559 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
560
561 /*
562 * Setup TX Descptor Count
563 */
b3821cc5 564 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
565
566 /*
567 * Enable TX Engine
568 */
569 wmb();
4330c2f2
GFT
570 jwrite32(jme, JME_TXCS, jme->reg_txcs |
571 TXCS_SELECT_QUEUE0 |
572 TXCS_ENABLE);
d7699f87
GFT
573
574}
575
3bf61c55 576__always_inline static void
29bdd921
GFT
577jme_restart_tx_engine(struct jme_adapter *jme)
578{
579 /*
580 * Restart TX Engine
581 */
582 jwrite32(jme, JME_TXCS, jme->reg_txcs |
583 TXCS_SELECT_QUEUE0 |
584 TXCS_ENABLE);
585}
586
587__always_inline static void
3bf61c55 588jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
589{
590 int i;
591 __u32 val;
592
593 /*
594 * Disable TX Engine
595 */
fcf45b4c 596 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
d7699f87
GFT
597
598 val = jread32(jme, JME_TXCS);
599 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
600 {
fcf45b4c 601 mdelay(1);
d7699f87
GFT
602 val = jread32(jme, JME_TXCS);
603 }
604
8c198884 605 if(!i) {
4330c2f2 606 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
8c198884
GFT
607 jme_reset_mac_processor(jme);
608 }
d7699f87
GFT
609
610
611}
612
3bf61c55
GFT
613static void
614jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87
GFT
615{
616 struct jme_ring *rxring = jme->rxring;
3bf61c55 617 register volatile struct rxdesc* rxdesc = rxring->desc;
4330c2f2
GFT
618 struct jme_buffer_info *rxbi = rxring->bufinf;
619 rxdesc += i;
620 rxbi += i;
621
622 rxdesc->dw[0] = 0;
623 rxdesc->dw[1] = 0;
3bf61c55 624 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
625 rxdesc->desc1.bufaddrl = cpu_to_le32(
626 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55
GFT
627 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
628 if(jme->dev->features & NETIF_F_HIGHDMA)
629 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 630 wmb();
3bf61c55 631 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
632}
633
3bf61c55
GFT
634static int
635jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
636{
637 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 638 struct jme_buffer_info *rxbi = rxring->bufinf + i;
4330c2f2
GFT
639 unsigned long offset;
640 struct sk_buff* skb;
641
79ce639c
GFT
642 skb = netdev_alloc_skb(jme->dev,
643 jme->dev->mtu + RX_EXTRA_LEN);
4330c2f2
GFT
644 if(unlikely(!skb))
645 return -ENOMEM;
3bf61c55 646
3bf61c55
GFT
647 if(unlikely(offset =
648 (unsigned long)(skb->data)
79ce639c 649 & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
4330c2f2 650 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
4330c2f2 651
4330c2f2 652 rxbi->skb = skb;
3bf61c55 653 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
654 rxbi->mapping = pci_map_page(jme->pdev,
655 virt_to_page(skb->data),
656 offset_in_page(skb->data),
657 rxbi->len,
658 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
659
660 return 0;
661}
662
3bf61c55
GFT
663static void
664jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
665{
666 struct jme_ring *rxring = &(jme->rxring[0]);
667 struct jme_buffer_info *rxbi = rxring->bufinf;
668 rxbi += i;
669
670 if(rxbi->skb) {
b3821cc5 671 pci_unmap_page(jme->pdev,
4330c2f2 672 rxbi->mapping,
3bf61c55 673 rxbi->len,
4330c2f2
GFT
674 PCI_DMA_FROMDEVICE);
675 dev_kfree_skb(rxbi->skb);
676 rxbi->skb = NULL;
677 rxbi->mapping = 0;
3bf61c55 678 rxbi->len = 0;
4330c2f2
GFT
679 }
680}
681
3bf61c55
GFT
682static void
683jme_free_rx_resources(struct jme_adapter *jme)
684{
685 int i;
686 struct jme_ring *rxring = &(jme->rxring[0]);
687
688 if(rxring->alloc) {
b3821cc5 689 for(i = 0 ; i < jme->rx_ring_size ; ++i)
3bf61c55
GFT
690 jme_free_rx_buf(jme, i);
691
692 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 693 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
694 rxring->alloc,
695 rxring->dmaalloc);
696 rxring->alloc = NULL;
697 rxring->desc = NULL;
698 rxring->dmaalloc = 0;
699 rxring->dma = 0;
700 }
701 rxring->next_to_use = 0;
cdcdc9eb 702 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
703}
704
705static int
706jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
707{
708 int i;
709 struct jme_ring *rxring = &(jme->rxring[0]);
710
711 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
712 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
713 &(rxring->dmaalloc),
714 GFP_ATOMIC);
4330c2f2
GFT
715 if(!rxring->alloc) {
716 rxring->desc = NULL;
717 rxring->dmaalloc = 0;
718 rxring->dma = 0;
d7699f87 719 return -ENOMEM;
4330c2f2 720 }
d7699f87
GFT
721
722 /*
723 * 16 Bytes align
724 */
3bf61c55
GFT
725 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
726 RING_DESC_ALIGN);
4330c2f2 727 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 728 rxring->next_to_use = 0;
cdcdc9eb 729 atomic_set(&rxring->next_to_clean, 0);
d7699f87 730
d7699f87
GFT
731 /*
732 * Initiallize Receive Descriptors
733 */
b3821cc5 734 for(i = 0 ; i < jme->rx_ring_size ; ++i) {
3bf61c55
GFT
735 if(unlikely(jme_make_new_rx_buf(jme, i))) {
736 jme_free_rx_resources(jme);
737 return -ENOMEM;
738 }
d7699f87
GFT
739
740 jme_set_clean_rxdesc(jme, i);
741 }
742
d7699f87
GFT
743 return 0;
744}
745
3bf61c55
GFT
746__always_inline static void
747jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 748{
d7699f87
GFT
749 /*
750 * Setup RX DMA Bass Address
751 */
fcf45b4c 752 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
3bf61c55 753 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fcf45b4c 754 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
755
756 /*
b3821cc5 757 * Setup RX Descriptor Count
d7699f87 758 */
b3821cc5 759 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 760
3bf61c55 761 /*
d7699f87
GFT
762 * Setup Unicast Filter
763 */
764 jme_set_multi(jme->dev);
765
766 /*
767 * Enable RX Engine
768 */
769 wmb();
79ce639c 770 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
771 RXCS_QUEUESEL_Q0 |
772 RXCS_ENABLE |
773 RXCS_QST);
d7699f87
GFT
774}
775
3bf61c55
GFT
776__always_inline static void
777jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
778{
779 /*
3bf61c55 780 * Start RX Engine
4330c2f2 781 */
79ce639c 782 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
783 RXCS_QUEUESEL_Q0 |
784 RXCS_ENABLE |
785 RXCS_QST);
786}
787
788
3bf61c55
GFT
789__always_inline static void
790jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
791{
792 int i;
793 __u32 val;
794
795 /*
796 * Disable RX Engine
797 */
29bdd921 798 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
d7699f87
GFT
799
800 val = jread32(jme, JME_RXCS);
801 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
802 {
29bdd921 803 mdelay(1);
d7699f87
GFT
804 val = jread32(jme, JME_RXCS);
805 }
806
807 if(!i)
4330c2f2 808 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
d7699f87
GFT
809
810}
811
192570e0
GFT
812static int
813jme_rxsum_ok(struct jme_adapter *jme, __u16 flags)
814{
815 if(!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
816 return false;
817
818 if(unlikely((flags & RXWBFLAG_TCPON) &&
819 !(flags & RXWBFLAG_TCPCS))) {
820 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
cdcdc9eb 821 goto out_sumerr;
192570e0
GFT
822 }
823
824 if(unlikely((flags & RXWBFLAG_UDPON) &&
825 !(flags & RXWBFLAG_UDPCS))) {
826 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
cdcdc9eb 827 goto out_sumerr;
192570e0
GFT
828 }
829
830 if(unlikely((flags & RXWBFLAG_IPV4) &&
831 !(flags & RXWBFLAG_IPCS))) {
832 csum_dbg(jme->dev->name, "IPv4 Checksum error.\n");
cdcdc9eb 833 goto out_sumerr;
192570e0
GFT
834 }
835
836 return true;
cdcdc9eb
GFT
837
838out_sumerr:
839 csum_dbg(jme->dev->name, "%s%s%s%s\n",
840 (flags & RXWBFLAG_IPV4)?"IPv4 ":"",
841 (flags & RXWBFLAG_IPV6)?"IPv6 ":"",
842 (flags & RXWBFLAG_UDPON)?"UDP ":"",
843 (flags & RXWBFLAG_TCPON)?"TCP":"");
844 return false;
192570e0
GFT
845}
846
3bf61c55 847static void
42b1055e 848jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 849{
d7699f87 850 struct jme_ring *rxring = &(jme->rxring[0]);
3bf61c55
GFT
851 volatile struct rxdesc *rxdesc = rxring->desc;
852 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 853 struct sk_buff *skb;
3bf61c55 854 int framesize;
d7699f87 855
3bf61c55
GFT
856 rxdesc += idx;
857 rxbi += idx;
d7699f87 858
3bf61c55
GFT
859 skb = rxbi->skb;
860 pci_dma_sync_single_for_cpu(jme->pdev,
861 rxbi->mapping,
862 rxbi->len,
863 PCI_DMA_FROMDEVICE);
864
865 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
866 pci_dma_sync_single_for_device(jme->pdev,
867 rxbi->mapping,
868 rxbi->len,
869 PCI_DMA_FROMDEVICE);
870
871 ++(NET_STAT(jme).rx_dropped);
872 }
873 else {
874 framesize = le16_to_cpu(rxdesc->descwb.framesize)
875 - RX_PREPAD_SIZE;
876
877 skb_reserve(skb, RX_PREPAD_SIZE);
878 skb_put(skb, framesize);
879 skb->protocol = eth_type_trans(skb, jme->dev);
880
192570e0 881 if(jme_rxsum_ok(jme, rxdesc->descwb.flags))
8c198884 882 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921
GFT
883 else
884 skb->ip_summed = CHECKSUM_NONE;
8c198884 885
b3821cc5
GFT
886
887 if(rxdesc->descwb.flags & RXWBFLAG_TAGON) {
888 vlan_dbg(jme->dev->name, "VLAN: %04x\n",
889 rxdesc->descwb.vlan);
890 if(jme->vlgrp) {
891 vlan_dbg(jme->dev->name,
892 "VLAN Passed to kernel.\n");
cdcdc9eb 893 jme->jme_vlan_rx(skb, jme->vlgrp,
42b1055e 894 le32_to_cpu(rxdesc->descwb.vlan));
b3821cc5
GFT
895 NET_STAT(jme).rx_bytes += 4;
896 }
897 }
898 else {
cdcdc9eb 899 jme->jme_rx(skb);
b3821cc5 900 }
3bf61c55 901
b3821cc5
GFT
902 if((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
903 RXWBFLAG_DEST_MUL)
3bf61c55
GFT
904 ++(NET_STAT(jme).multicast);
905
906 jme->dev->last_rx = jiffies;
907 NET_STAT(jme).rx_bytes += framesize;
908 ++(NET_STAT(jme).rx_packets);
909 }
910
911 jme_set_clean_rxdesc(jme, idx);
912
913}
914
192570e0 915
8c198884
GFT
916
917static int
3bf61c55
GFT
918jme_process_receive(struct jme_adapter *jme, int limit)
919{
920 struct jme_ring *rxring = &(jme->rxring[0]);
921 volatile struct rxdesc *rxdesc = rxring->desc;
b3821cc5 922 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 923
192570e0
GFT
924 if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
925 goto out_inc;
926
927 if(unlikely(atomic_read(&jme->link_changing) != 1))
928 goto out_inc;
929
930 if(unlikely(!netif_carrier_ok(jme->dev)))
931 goto out_inc;
932
cdcdc9eb 933 i = atomic_read(&rxring->next_to_clean);
3bf61c55 934 while( limit-- > 0 )
d7699f87 935 {
3bf61c55
GFT
936 rxdesc = rxring->desc;
937 rxdesc += i;
938
4330c2f2 939 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
3bf61c55
GFT
940 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
941 goto out;
d7699f87 942
4330c2f2
GFT
943 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
944
3bf61c55 945 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
4330c2f2 946
8c198884 947 if(unlikely(desccnt > 1 ||
192570e0 948 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 949
3bf61c55
GFT
950 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
951 ++(NET_STAT(jme).rx_crc_errors);
952 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
953 ++(NET_STAT(jme).rx_fifo_errors);
954 else
955 ++(NET_STAT(jme).rx_errors);
4330c2f2 956
79ce639c
GFT
957 if(desccnt > 1) {
958 rx_dbg(jme->dev->name,
959 "RX: More than one(%d) descriptor, "
960 "framelen=%d\n",
961 desccnt, le16_to_cpu(rxdesc->descwb.framesize));
3bf61c55 962 limit -= desccnt - 1;
79ce639c 963 }
4330c2f2 964
3bf61c55 965 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 966 jme_set_clean_rxdesc(jme, j);
b3821cc5 967 j = (j + 1) & (mask);
4330c2f2 968 }
3bf61c55 969
d7699f87
GFT
970 }
971 else {
42b1055e 972 jme_alloc_and_feed_skb(jme, i);
3bf61c55 973 }
4330c2f2 974
b3821cc5 975 i = (i + desccnt) & (mask);
3bf61c55 976 }
4330c2f2 977
192570e0 978
3bf61c55
GFT
979out:
980 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
981 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
982 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
983 >> 4);
4330c2f2 984
cdcdc9eb 985 atomic_set(&rxring->next_to_clean, i);
4330c2f2 986
192570e0
GFT
987out_inc:
988 atomic_inc(&jme->rx_cleaning);
989
3bf61c55 990 return limit > 0 ? limit : 0;
4330c2f2 991
3bf61c55 992}
d7699f87 993
3bf61c55 994static void
79ce639c
GFT
995jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
996{
192570e0
GFT
997 if(likely(atmp == dpi->cur)) {
998 dpi->cnt = 0;
79ce639c 999 return;
192570e0 1000 }
79ce639c
GFT
1001
1002 if(dpi->attempt == atmp) {
1003 ++(dpi->cnt);
1004 }
1005 else {
1006 dpi->attempt = atmp;
1007 dpi->cnt = 0;
1008 }
1009
1010}
1011
1012static void
1013jme_dynamic_pcc(struct jme_adapter *jme)
1014{
1015 register struct dynpcc_info *dpi = &(jme->dpi);
1016
1017 if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1018 jme_attempt_pcc(dpi, PCC_P3);
192570e0 1019 else if((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
79ce639c
GFT
1020 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1021 jme_attempt_pcc(dpi, PCC_P2);
1022 else
1023 jme_attempt_pcc(dpi, PCC_P1);
1024
192570e0 1025 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
79ce639c
GFT
1026 jme_set_rx_pcc(jme, dpi->attempt);
1027 dpi->cur = dpi->attempt;
1028 dpi->cnt = 0;
1029 }
1030}
1031
1032static void
1033jme_start_pcc_timer(struct jme_adapter *jme)
1034{
1035 struct dynpcc_info *dpi = &(jme->dpi);
1036 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1037 dpi->last_pkts = NET_STAT(jme).rx_packets;
1038 dpi->intr_cnt = 0;
1039 jwrite32(jme, JME_TMCSR,
1040 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1041}
1042
192570e0 1043__always_inline static void
29bdd921
GFT
1044jme_stop_pcc_timer(struct jme_adapter *jme)
1045{
1046 jwrite32(jme, JME_TMCSR, 0);
1047}
1048
1049static void
79ce639c
GFT
1050jme_pcc_tasklet(unsigned long arg)
1051{
1052 struct jme_adapter *jme = (struct jme_adapter*)arg;
1053 struct net_device *netdev = jme->dev;
1054
29bdd921 1055
b3821cc5 1056 if(unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1057 (atomic_read(&jme->link_changing) != 1)
1058 )) {
1059 jme_stop_pcc_timer(jme);
79ce639c
GFT
1060 return;
1061 }
29bdd921 1062
192570e0
GFT
1063 if(!(jme->flags & JME_FLAG_POLL))
1064 jme_dynamic_pcc(jme);
1065
79ce639c
GFT
1066 jme_start_pcc_timer(jme);
1067}
1068
192570e0
GFT
1069__always_inline static void
1070jme_polling_mode(struct jme_adapter *jme)
1071{
1072 jme_set_rx_pcc(jme, PCC_OFF);
1073}
1074
1075__always_inline static void
1076jme_interrupt_mode(struct jme_adapter *jme)
1077{
1078 jme_set_rx_pcc(jme, PCC_P1);
1079}
1080
79ce639c 1081static void
3bf61c55
GFT
1082jme_link_change_tasklet(unsigned long arg)
1083{
1084 struct jme_adapter *jme = (struct jme_adapter*)arg;
fcf45b4c
GFT
1085 struct net_device *netdev = jme->dev;
1086 int timeout = WAIT_TASKLET_TIMEOUT;
1087 int rc;
1088
1089 if(!atomic_dec_and_test(&jme->link_changing))
1090 goto out;
1091
29bdd921 1092 if(jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1093 goto out;
1094
29bdd921 1095 jme->old_mtu = netdev->mtu;
fcf45b4c
GFT
1096 netif_stop_queue(netdev);
1097
1098 while(--timeout > 0 &&
1099 (
1100 atomic_read(&jme->rx_cleaning) != 1 ||
1101 atomic_read(&jme->tx_cleaning) != 1
1102 )) {
1103
1104 mdelay(1);
1105 }
1106
1107 if(netif_carrier_ok(netdev)) {
29bdd921 1108 jme_stop_pcc_timer(jme);
fcf45b4c
GFT
1109 jme_reset_mac_processor(jme);
1110 jme_free_rx_resources(jme);
1111 jme_free_tx_resources(jme);
192570e0 1112
cdcdc9eb 1113 if(jme->flags & JME_FLAG_POLL)
192570e0 1114 jme_polling_mode(jme);
fcf45b4c
GFT
1115 }
1116
1117 jme_check_link(netdev, 0);
1118 if(netif_carrier_ok(netdev)) {
1119 rc = jme_setup_rx_resources(jme);
1120 if(rc) {
1121 jeprintk(netdev->name,
1122 "Allocating resources for RX error"
1123 ", Device STOPPED!\n");
1124 goto out;
1125 }
1126
1127
1128 rc = jme_setup_tx_resources(jme);
1129 if(rc) {
1130 jeprintk(netdev->name,
1131 "Allocating resources for TX error"
1132 ", Device STOPPED!\n");
1133 goto err_out_free_rx_resources;
1134 }
1135
1136 jme_enable_rx_engine(jme);
1137 jme_enable_tx_engine(jme);
1138
1139 netif_start_queue(netdev);
192570e0 1140
cdcdc9eb 1141 if(jme->flags & JME_FLAG_POLL)
192570e0 1142 jme_interrupt_mode(jme);
192570e0 1143
79ce639c 1144 jme_start_pcc_timer(jme);
fcf45b4c
GFT
1145 }
1146
1147 goto out;
1148
1149err_out_free_rx_resources:
1150 jme_free_rx_resources(jme);
1151out:
1152 atomic_inc(&jme->link_changing);
3bf61c55 1153}
d7699f87 1154
3bf61c55
GFT
1155static void
1156jme_rx_clean_tasklet(unsigned long arg)
1157{
1158 struct jme_adapter *jme = (struct jme_adapter*)arg;
79ce639c 1159 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1160
192570e0
GFT
1161 jme_process_receive(jme, jme->rx_ring_size);
1162 ++(dpi->intr_cnt);
42b1055e 1163
192570e0 1164}
fcf45b4c 1165
192570e0 1166static int
cdcdc9eb 1167jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1168{
cdcdc9eb 1169 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0
GFT
1170 struct net_device *netdev = jme->dev;
1171 int rest;
fcf45b4c 1172
cdcdc9eb 1173 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1174
cdcdc9eb
GFT
1175 while(atomic_read(&jme->rx_empty) > 0) {
1176 atomic_dec(&jme->rx_empty);
192570e0
GFT
1177 ++(NET_STAT(jme).rx_dropped);
1178 jme_restart_rx_engine(jme);
1179 }
1180 atomic_inc(&jme->rx_empty);
1181
1182 if(rest) {
cdcdc9eb 1183 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1184 jme_interrupt_mode(jme);
1185 }
1186
cdcdc9eb
GFT
1187 JME_NAPI_WEIGHT_SET(budget, rest);
1188 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1189}
1190
1191static void
1192jme_rx_empty_tasklet(unsigned long arg)
1193{
1194 struct jme_adapter *jme = (struct jme_adapter*)arg;
1195
79ce639c 1196 if(unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1197 return;
1198
b3821cc5 1199 if(unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1200 return;
1201
b3821cc5 1202 queue_dbg(jme->dev->name, "RX Queue Full!\n");
29bdd921 1203
fcf45b4c 1204 jme_rx_clean_tasklet(arg);
cdcdc9eb
GFT
1205
1206 while(atomic_read(&jme->rx_empty) > 0) {
1207 atomic_dec(&jme->rx_empty);
1208 ++(NET_STAT(jme).rx_dropped);
1209 jme_restart_rx_engine(jme);
1210 }
1211 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1212}
1213
3bf61c55 1214static void
b3821cc5
GFT
1215jme_wake_queue_if_stopped(struct jme_adapter *jme)
1216{
1217 struct jme_ring *txring = jme->txring;
1218
1219 smp_wmb();
1220 if(unlikely(netif_queue_stopped(jme->dev) &&
1221 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1222
1223 queue_dbg(jme->dev->name, "TX Queue Waked.\n");
1224 netif_wake_queue(jme->dev);
1225
1226 }
1227
1228}
1229
1230static void
3bf61c55 1231jme_tx_clean_tasklet(unsigned long arg)
4330c2f2
GFT
1232{
1233 struct jme_adapter *jme = (struct jme_adapter*)arg;
3bf61c55
GFT
1234 struct jme_ring *txring = &(jme->txring[0]);
1235 volatile struct txdesc *txdesc = txring->desc;
1236 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1237 int i, j, cnt = 0, max, err, mask;
3bf61c55 1238
79ce639c 1239 if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1240 goto out;
1241
79ce639c 1242 if(unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1243 goto out;
1244
b3821cc5 1245 if(unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1246 goto out;
1247
b3821cc5
GFT
1248 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1249 mask = jme->tx_ring_mask;
3bf61c55
GFT
1250
1251 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1252
cdcdc9eb 1253 for(i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1254
1255 ctxbi = txbi + i;
1256
b3821cc5
GFT
1257 if(likely(ctxbi->skb &&
1258 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884
GFT
1259
1260 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55
GFT
1261
1262 tx_dbg(jme->dev->name,
1263 "Tx Tasklet: Clean %d+%d\n",
1264 i, ctxbi->nr_desc);
1265
1266 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1267 ttxbi = txbi + ((i + j) & (mask));
1268 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1269
b3821cc5 1270 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1271 ttxbi->mapping,
1272 ttxbi->len,
1273 PCI_DMA_TODEVICE);
1274
3bf61c55
GFT
1275 ttxbi->mapping = 0;
1276 ttxbi->len = 0;
1277 }
1278
1279 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1280
1281 cnt += ctxbi->nr_desc;
1282
8c198884
GFT
1283 if(unlikely(err))
1284 ++(NET_STAT(jme).tx_carrier_errors);
b3821cc5 1285 else {
8c198884 1286 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1287 NET_STAT(jme).tx_bytes += ctxbi->len;
1288 }
1289
1290 ctxbi->skb = NULL;
1291 ctxbi->len = 0;
cdcdc9eb 1292 ctxbi->start_xmit = 0;
3bf61c55
GFT
1293 }
1294 else {
1295 if(!ctxbi->skb)
1296 tx_dbg(jme->dev->name,
1297 "Tx Tasklet:"
b3821cc5 1298 " Stopped due to no skb.\n");
3bf61c55
GFT
1299 else
1300 tx_dbg(jme->dev->name,
1301 "Tx Tasklet:"
b3821cc5 1302 "Stopped due to not done.\n");
3bf61c55
GFT
1303 break;
1304 }
1305
b3821cc5 1306 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1307
1308 ctxbi->nr_desc = 0;
d7699f87
GFT
1309 }
1310
3bf61c55
GFT
1311 tx_dbg(jme->dev->name,
1312 "Tx Tasklet: Stop %d Jiffies %lu\n",
1313 i, jiffies);
3bf61c55 1314
cdcdc9eb 1315 atomic_set(&txring->next_to_clean, i);
79ce639c 1316 atomic_add(cnt, &txring->nr_free);
3bf61c55 1317
b3821cc5
GFT
1318 jme_wake_queue_if_stopped(jme);
1319
fcf45b4c
GFT
1320out:
1321 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1322}
1323
79ce639c
GFT
1324static void
1325jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
d7699f87 1326{
3bf61c55
GFT
1327 /*
1328 * Disable interrupt
1329 */
1330 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1331
29bdd921
GFT
1332 /*
1333 * Write 1 clear interrupt status
1334 */
1335 jwrite32f(jme, JME_IEVE, intrstat);
1336
79ce639c 1337 if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
3bf61c55 1338 tasklet_schedule(&jme->linkch_task);
29bdd921 1339 goto out_reenable;
fcf45b4c 1340 }
d7699f87 1341
79ce639c
GFT
1342 if(intrstat & INTR_TMINTR)
1343 tasklet_schedule(&jme->pcc_task);
1344
3bf61c55 1345 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
4330c2f2 1346 tasklet_schedule(&jme->txclean_task);
d7699f87 1347
192570e0
GFT
1348 if(jme->flags & JME_FLAG_POLL) {
1349 if(intrstat & INTR_RX0EMP)
1350 atomic_inc(&jme->rx_empty);
1351
1352 if((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
cdcdc9eb 1353 if(likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1354 jme_polling_mode(jme);
cdcdc9eb 1355 JME_RX_SCHEDULE(jme);
192570e0
GFT
1356 }
1357 }
1358 }
1359 else {
cdcdc9eb
GFT
1360 if(intrstat & INTR_RX0EMP) {
1361 atomic_inc(&jme->rx_empty);
192570e0 1362 tasklet_schedule(&jme->rxempty_task);
cdcdc9eb 1363 }
192570e0
GFT
1364
1365 if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1366 tasklet_schedule(&jme->rxclean_task);
4330c2f2 1367 }
d7699f87 1368
29bdd921 1369out_reenable:
3bf61c55 1370 /*
fcf45b4c 1371 * Re-enable interrupt
3bf61c55 1372 */
fcf45b4c 1373 jwrite32f(jme, JME_IENS, INTR_ENABLE);
3bf61c55 1374
79ce639c
GFT
1375
1376}
1377
1378static irqreturn_t
1379jme_intr(int irq, void *dev_id)
1380{
1381 struct net_device *netdev = dev_id;
1382 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c
GFT
1383 __u32 intrstat;
1384
1385 intrstat = jread32(jme, JME_IEVE);
1386
1387 /*
1388 * Check if it's really an interrupt for us
1389 */
29bdd921
GFT
1390 if(unlikely(intrstat == 0))
1391 return IRQ_NONE;
79ce639c
GFT
1392
1393 /*
1394 * Check if the device still exist
1395 */
29bdd921
GFT
1396 if(unlikely(intrstat == ~((typeof(intrstat))0)))
1397 return IRQ_NONE;
79ce639c
GFT
1398
1399 jme_intr_msi(jme, intrstat);
1400
29bdd921 1401 return IRQ_HANDLED;
d7699f87
GFT
1402}
1403
79ce639c
GFT
1404static irqreturn_t
1405jme_msi(int irq, void *dev_id)
1406{
1407 struct net_device *netdev = dev_id;
1408 struct jme_adapter *jme = netdev_priv(netdev);
1409 __u32 intrstat;
1410
1411 pci_dma_sync_single_for_cpu(jme->pdev,
1412 jme->shadow_dma,
1413 sizeof(__u32) * SHADOW_REG_NR,
1414 PCI_DMA_FROMDEVICE);
1415 intrstat = jme->shadow_regs[SHADOW_IEVE];
1416 jme->shadow_regs[SHADOW_IEVE] = 0;
1417
1418 jme_intr_msi(jme, intrstat);
1419
1420 return IRQ_HANDLED;
1421}
1422
1423
1424static void
1425jme_reset_link(struct jme_adapter *jme)
1426{
1427 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1428}
1429
fcf45b4c
GFT
1430static void
1431jme_restart_an(struct jme_adapter *jme)
1432{
1433 __u32 bmcr;
79ce639c 1434 unsigned long flags;
fcf45b4c 1435
79ce639c 1436 spin_lock_irqsave(&jme->phy_lock, flags);
fcf45b4c
GFT
1437 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1438 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1439 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
79ce639c
GFT
1440 spin_unlock_irqrestore(&jme->phy_lock, flags);
1441}
1442
1443static int
1444jme_request_irq(struct jme_adapter *jme)
1445{
1446 int rc;
1447 struct net_device *netdev = jme->dev;
1448 irq_handler_t handler = jme_intr;
1449 int irq_flags = IRQF_SHARED;
1450
1451 if (!pci_enable_msi(jme->pdev)) {
1452 jme->flags |= JME_FLAG_MSI;
1453 handler = jme_msi;
1454 irq_flags = 0;
1455 }
1456
1457 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1458 netdev);
1459 if(rc) {
1460 jeprintk(netdev->name,
b3821cc5 1461 "Unable to request %s interrupt (return: %d)\n",
29bdd921 1462 jme->flags & JME_FLAG_MSI ? "MSI":"INTx", rc);
79ce639c
GFT
1463
1464 if(jme->flags & JME_FLAG_MSI) {
1465 pci_disable_msi(jme->pdev);
1466 jme->flags &= ~JME_FLAG_MSI;
1467 }
1468 }
1469 else {
1470 netdev->irq = jme->pdev->irq;
1471 }
1472
1473 return rc;
1474}
1475
1476static void
1477jme_free_irq(struct jme_adapter *jme)
1478{
1479 free_irq(jme->pdev->irq, jme->dev);
1480 if (jme->flags & JME_FLAG_MSI) {
1481 pci_disable_msi(jme->pdev);
1482 jme->flags &= ~JME_FLAG_MSI;
1483 jme->dev->irq = jme->pdev->irq;
1484 }
fcf45b4c
GFT
1485}
1486
3bf61c55
GFT
1487static int
1488jme_open(struct net_device *netdev)
d7699f87
GFT
1489{
1490 struct jme_adapter *jme = netdev_priv(netdev);
cdcdc9eb 1491 int rc, timeout = 10;
fcf45b4c
GFT
1492
1493 while(
1494 --timeout > 0 &&
1495 (
1496 atomic_read(&jme->link_changing) != 1 ||
1497 atomic_read(&jme->rx_cleaning) != 1 ||
1498 atomic_read(&jme->tx_cleaning) != 1
1499 )
1500 )
cdcdc9eb 1501 msleep(1);
fcf45b4c 1502
79ce639c
GFT
1503 if(!timeout) {
1504 rc = -EBUSY;
1505 goto err_out;
1506 }
1507
42b1055e 1508 jme_clear_pm(jme);
fcf45b4c 1509 jme_reset_mac_processor(jme);
cdcdc9eb 1510 JME_NAPI_ENABLE(jme);
d7699f87 1511
79ce639c
GFT
1512 rc = jme_request_irq(jme);
1513 if(rc)
4330c2f2 1514 goto err_out;
79ce639c 1515
4330c2f2 1516 jme_enable_shadow(jme);
d7699f87 1517 jme_start_irq(jme);
42b1055e
GFT
1518
1519 if(jme->flags & JME_FLAG_SSET)
1520 jme_set_settings(netdev, &jme->old_ecmd);
1521 else
1522 jme_reset_phy_processor(jme);
1523
29bdd921 1524 jme_reset_link(jme);
d7699f87
GFT
1525
1526 return 0;
1527
d7699f87
GFT
1528err_out:
1529 netif_stop_queue(netdev);
1530 netif_carrier_off(netdev);
4330c2f2 1531 return rc;
d7699f87
GFT
1532}
1533
42b1055e
GFT
1534static void
1535jme_set_100m_half(struct jme_adapter *jme)
1536{
1537 __u32 bmcr, tmp;
1538
1539 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1540 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1541 BMCR_SPEED1000 | BMCR_FULLDPLX);
1542 tmp |= BMCR_SPEED100;
1543
1544 if (bmcr != tmp)
1545 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1546
cdcdc9eb
GFT
1547 if(jme->fpgaver)
1548 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1549 else
1550 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1551}
1552
1553static void
1554jme_phy_off(struct jme_adapter *jme)
1555{
1556 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1557}
1558
1559
3bf61c55
GFT
1560static int
1561jme_close(struct net_device *netdev)
d7699f87
GFT
1562{
1563 struct jme_adapter *jme = netdev_priv(netdev);
1564
1565 netif_stop_queue(netdev);
1566 netif_carrier_off(netdev);
1567
1568 jme_stop_irq(jme);
4330c2f2 1569 jme_disable_shadow(jme);
79ce639c 1570 jme_free_irq(jme);
d7699f87 1571
cdcdc9eb 1572 JME_NAPI_DISABLE(jme);
192570e0 1573
4330c2f2
GFT
1574 tasklet_kill(&jme->linkch_task);
1575 tasklet_kill(&jme->txclean_task);
1576 tasklet_kill(&jme->rxclean_task);
fcf45b4c 1577 tasklet_kill(&jme->rxempty_task);
8c198884
GFT
1578
1579 jme_reset_mac_processor(jme);
d7699f87
GFT
1580 jme_free_rx_resources(jme);
1581 jme_free_tx_resources(jme);
42b1055e 1582 jme->phylink = 0;
b3821cc5
GFT
1583 jme_phy_off(jme);
1584
1585 return 0;
1586}
1587
1588static int
1589jme_alloc_txdesc(struct jme_adapter *jme,
1590 struct sk_buff *skb)
1591{
1592 struct jme_ring *txring = jme->txring;
1593 int idx, nr_alloc, mask = jme->tx_ring_mask;
1594
1595 idx = txring->next_to_use;
1596 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1597
1598 if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1599 return -1;
1600
1601 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1602
b3821cc5
GFT
1603 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1604
1605 return idx;
1606}
1607
1608static void
1609jme_fill_tx_map(struct pci_dev *pdev,
1610 volatile struct txdesc *txdesc,
1611 struct jme_buffer_info *txbi,
1612 struct page *page,
1613 __u32 page_offset,
1614 __u32 len,
1615 __u8 hidma)
1616{
1617 dma_addr_t dmaaddr;
1618
1619 dmaaddr = pci_map_page(pdev,
1620 page,
1621 page_offset,
1622 len,
1623 PCI_DMA_TODEVICE);
1624
1625 pci_dma_sync_single_for_device(pdev,
1626 dmaaddr,
1627 len,
1628 PCI_DMA_TODEVICE);
1629
1630 txdesc->dw[0] = 0;
1631 txdesc->dw[1] = 0;
1632 txdesc->desc2.flags = TXFLAG_OWN;
1633 txdesc->desc2.flags |= (hidma)?TXFLAG_64BIT:0;
1634 txdesc->desc2.datalen = cpu_to_le16(len);
1635 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1636 txdesc->desc2.bufaddrl = cpu_to_le32(
1637 (__u64)dmaaddr & 0xFFFFFFFFUL);
1638
1639 txbi->mapping = dmaaddr;
1640 txbi->len = len;
1641}
1642
1643static void
1644jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1645{
1646 struct jme_ring *txring = jme->txring;
1647 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
1648 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1649 __u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1650 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1651 int mask = jme->tx_ring_mask;
1652 struct skb_frag_struct *frag;
1653 __u32 len;
1654
1655 for(i = 0 ; i < nr_frags ; ++i) {
1656 frag = &skb_shinfo(skb)->frags[i];
1657 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1658 ctxbi = txbi + ((idx + i + 2) & (mask));
1659
1660 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1661 frag->page_offset, frag->size, hidma);
42b1055e 1662 }
b3821cc5
GFT
1663
1664 len = skb_is_nonlinear(skb)?skb_headlen(skb):skb->len;
1665 ctxdesc = txdesc + ((idx + 1) & (mask));
1666 ctxbi = txbi + ((idx + 1) & (mask));
1667 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1668 offset_in_page(skb->data), len, hidma);
1669
1670}
1671
1672static int
1673jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1674{
1675 if(unlikely(skb_shinfo(skb)->gso_size &&
1676 skb_header_cloned(skb) &&
1677 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1678 dev_kfree_skb(skb);
1679 return -1;
1680 }
1681
1682 return 0;
1683}
1684
1685static int
1686jme_tx_tso(struct sk_buff *skb,
1687 volatile __u16 *mss, __u8 *flags)
1688{
1689 if((*mss = (skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT))) {
1690 *flags |= TXFLAG_LSEN;
1691
1692 if(skb->protocol == __constant_htons(ETH_P_IP)) {
1693 struct iphdr *iph = ip_hdr(skb);
1694
1695 iph->check = 0;
1696 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1697 iph->daddr, 0,
1698 IPPROTO_TCP,
1699 0);
1700 }
1701 else {
1702 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1703
1704 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1705 &ip6h->daddr, 0,
1706 IPPROTO_TCP,
1707 0);
1708 }
1709
1710 return 0;
1711 }
1712
1713 return 1;
1714}
1715
1716static void
1717jme_tx_csum(struct sk_buff *skb, __u8 *flags)
1718{
1719 if(skb->ip_summed == CHECKSUM_PARTIAL) {
1720 __u8 ip_proto;
1721
1722 switch (skb->protocol) {
1723 case __constant_htons(ETH_P_IP):
1724 ip_proto = ip_hdr(skb)->protocol;
1725 break;
1726 case __constant_htons(ETH_P_IPV6):
1727 ip_proto = ipv6_hdr(skb)->nexthdr;
1728 break;
1729 default:
1730 ip_proto = 0;
1731 break;
1732 }
1733
1734 switch(ip_proto) {
1735 case IPPROTO_TCP:
1736 *flags |= TXFLAG_TCPCS;
1737 break;
1738 case IPPROTO_UDP:
1739 *flags |= TXFLAG_UDPCS;
1740 break;
1741 default:
1742 jeprintk("jme", "Error upper layer protocol.\n");
1743 break;
1744 }
1745 }
1746}
1747
1748__always_inline static void
1749jme_tx_vlan(struct sk_buff *skb, volatile __u16 *vlan, __u8 *flags)
1750{
1751 if(vlan_tx_tag_present(skb)) {
1752 vlan_dbg("jme", "Tag found!(%04x)\n", vlan_tx_tag_get(skb));
1753 *flags |= TXFLAG_TAGON;
1754 *vlan = vlan_tx_tag_get(skb);
42b1055e 1755 }
b3821cc5
GFT
1756}
1757
1758static int
1759jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1760{
1761 struct jme_ring *txring = jme->txring;
1762 volatile struct txdesc *txdesc;
1763 struct jme_buffer_info *txbi;
1764 __u8 flags;
1765
1766 txdesc = (volatile struct txdesc*)txring->desc + idx;
1767 txbi = txring->bufinf + idx;
1768
1769 txdesc->dw[0] = 0;
1770 txdesc->dw[1] = 0;
1771 txdesc->dw[2] = 0;
1772 txdesc->dw[3] = 0;
1773 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1774 /*
1775 * Set OWN bit at final.
1776 * When kernel transmit faster than NIC.
1777 * And NIC trying to send this descriptor before we tell
1778 * it to start sending this TX queue.
1779 * Other fields are already filled correctly.
1780 */
1781 wmb();
1782 flags = TXFLAG_OWN | TXFLAG_INT;
1783 //Set checksum flags while not tso
1784 if(jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1785 jme_tx_csum(skb, &flags);
1786 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1787 txdesc->desc1.flags = flags;
1788 /*
1789 * Set tx buffer info after telling NIC to send
1790 * For better tx_clean timing
1791 */
1792 wmb();
1793 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1794 txbi->skb = skb;
1795 txbi->len = skb->len;
cdcdc9eb 1796 if(!(txbi->start_xmit = jiffies))
8d27293f 1797 txbi->start_xmit = (0UL-1);
d7699f87
GFT
1798
1799 return 0;
1800}
1801
b3821cc5
GFT
1802static void
1803jme_stop_queue_if_full(struct jme_adapter *jme)
1804{
1805 struct jme_ring *txring = jme->txring;
cdcdc9eb
GFT
1806 struct jme_buffer_info *txbi = txring->bufinf;
1807
1808 txbi += atomic_read(&txring->next_to_clean);
b3821cc5
GFT
1809
1810 smp_wmb();
1811 if(unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1812 netif_stop_queue(jme->dev);
1813 queue_dbg(jme->dev->name, "TX Queue Paused.\n");
1814 smp_wmb();
1815 if (atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold)) {
1816 netif_wake_queue(jme->dev);
1817 queue_dbg(jme->dev->name, "TX Queue Fast Waked.\n");
1818 }
1819 }
1820
cdcdc9eb
GFT
1821 if(unlikely( txbi->start_xmit &&
1822 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1823 txbi->skb)) {
1824 netif_stop_queue(jme->dev);
1825 }
b3821cc5
GFT
1826}
1827
3bf61c55
GFT
1828/*
1829 * This function is already protected by netif_tx_lock()
1830 */
1831static int
1832jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87
GFT
1833{
1834 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 1835 int idx;
d7699f87 1836
b3821cc5
GFT
1837 if(skb_shinfo(skb)->nr_frags) {
1838 tx_dbg(netdev->name, "Frags: %d Headlen: %d Len: %d MSS: %d Sum:%d\n",
1839 skb_shinfo(skb)->nr_frags,
1840 skb_headlen(skb),
1841 skb->len,
1842 skb_shinfo(skb)->gso_size,
1843 skb->ip_summed);
1844 }
1845
1846 if(unlikely(jme_expand_header(jme, skb))) {
1847 ++(NET_STAT(jme).tx_dropped);
1848 return NETDEV_TX_OK;
1849 }
1850
1851 idx = jme_alloc_txdesc(jme, skb);
79ce639c 1852
b3821cc5
GFT
1853 if(unlikely(idx<0)) {
1854 netif_stop_queue(netdev);
1855 jeprintk(netdev->name,
1856 "BUG! Tx ring full when queue awake!\n");
d7699f87 1857
b3821cc5
GFT
1858 return NETDEV_TX_BUSY;
1859 }
1860
1861 jme_map_tx_skb(jme, skb, idx);
1862 jme_fill_first_tx_desc(jme, skb, idx);
1863
1864 tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, skb_shinfo(skb)->nr_frags + 2);
d7699f87 1865
4330c2f2
GFT
1866 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1867 TXCS_SELECT_QUEUE0 |
1868 TXCS_QUEUE0S |
1869 TXCS_ENABLE);
d7699f87
GFT
1870 netdev->trans_start = jiffies;
1871
b3821cc5
GFT
1872 jme_stop_queue_if_full(jme);
1873
4330c2f2 1874 return NETDEV_TX_OK;
d7699f87
GFT
1875}
1876
3bf61c55
GFT
1877static int
1878jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87
GFT
1879{
1880 struct jme_adapter *jme = netdev_priv(netdev);
1881 struct sockaddr *addr = p;
1882 __u32 val;
1883
1884 if(netif_running(netdev))
1885 return -EBUSY;
1886
fcf45b4c 1887 spin_lock(&jme->macaddr_lock);
d7699f87
GFT
1888 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1889
186fc259
GFT
1890 val = (addr->sa_data[3] & 0xff) << 24 |
1891 (addr->sa_data[2] & 0xff) << 16 |
1892 (addr->sa_data[1] & 0xff) << 8 |
1893 (addr->sa_data[0] & 0xff);
4330c2f2 1894 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
1895 val = (addr->sa_data[5] & 0xff) << 8 |
1896 (addr->sa_data[4] & 0xff);
4330c2f2 1897 jwrite32(jme, JME_RXUMA_HI, val);
fcf45b4c 1898 spin_unlock(&jme->macaddr_lock);
d7699f87
GFT
1899
1900 return 0;
1901}
1902
3bf61c55
GFT
1903static void
1904jme_set_multi(struct net_device *netdev)
d7699f87 1905{
3bf61c55 1906 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1907 u32 mc_hash[2] = {};
d7699f87 1908 int i;
8c198884 1909 unsigned long flags;
d7699f87 1910
8c198884
GFT
1911 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1912
1913 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 1914
3bf61c55 1915 if (netdev->flags & IFF_PROMISC) {
8c198884 1916 jme->reg_rxmcs |= RXMCS_ALLFRAME;
3bf61c55
GFT
1917 }
1918 else if (netdev->flags & IFF_ALLMULTI) {
8c198884 1919 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
3bf61c55 1920 }
d7699f87 1921 else if(netdev->flags & IFF_MULTICAST) {
3bf61c55
GFT
1922 struct dev_mc_list *mclist;
1923 int bit_nr;
d7699f87 1924
8c198884 1925 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
3bf61c55
GFT
1926 for (i = 0, mclist = netdev->mc_list;
1927 mclist && i < netdev->mc_count;
1928 ++i, mclist = mclist->next) {
1929
d7699f87
GFT
1930 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1931 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
d7699f87
GFT
1932 }
1933
4330c2f2
GFT
1934 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1935 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
1936 }
1937
d7699f87 1938 wmb();
8c198884
GFT
1939 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1940
1941 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
d7699f87
GFT
1942}
1943
3bf61c55 1944static int
8c198884 1945jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 1946{
79ce639c
GFT
1947 struct jme_adapter *jme = netdev_priv(netdev);
1948
29bdd921
GFT
1949 if(new_mtu == jme->old_mtu)
1950 return 0;
1951
79ce639c 1952 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
42b1055e 1953 ((new_mtu) < IPV6_MIN_MTU))
79ce639c
GFT
1954 return -EINVAL;
1955
1956 if(new_mtu > 4000) {
1957 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1958 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1959 jme_restart_rx_engine(jme);
1960 }
1961 else {
1962 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1963 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1964 jme_restart_rx_engine(jme);
1965 }
1966
1967 if(new_mtu > 1900) {
b3821cc5
GFT
1968 netdev->features &= ~(NETIF_F_HW_CSUM |
1969 NETIF_F_TSO |
1970 NETIF_F_TSO6);
79ce639c
GFT
1971 }
1972 else {
b3821cc5
GFT
1973 if(jme->flags & JME_FLAG_TXCSUM)
1974 netdev->features |= NETIF_F_HW_CSUM;
1975 if(jme->flags & JME_FLAG_TSO)
1976 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT
1977 }
1978
1979 netdev->mtu = new_mtu;
1980 jme_reset_link(jme);
1981
1982 return 0;
d7699f87
GFT
1983}
1984
3bf61c55 1985static void
8c198884
GFT
1986jme_tx_timeout(struct net_device *netdev)
1987{
1988 struct jme_adapter *jme = netdev_priv(netdev);
1989
cdcdc9eb
GFT
1990 jme->phylink = 0;
1991 jme_reset_phy_processor(jme);
1992 if(jme->flags & JME_FLAG_SSET)
1993 jme_set_settings(netdev, &jme->old_ecmd);
1994
8c198884 1995 /*
cdcdc9eb 1996 * Force to Reset the link again
8c198884 1997 */
29bdd921 1998 jme_reset_link(jme);
8c198884
GFT
1999}
2000
2001static void
42b1055e
GFT
2002jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2003{
2004 struct jme_adapter *jme = netdev_priv(netdev);
2005
2006 jme->vlgrp = grp;
2007}
2008
2009static void
3bf61c55
GFT
2010jme_get_drvinfo(struct net_device *netdev,
2011 struct ethtool_drvinfo *info)
d7699f87
GFT
2012{
2013 struct jme_adapter *jme = netdev_priv(netdev);
2014
2015 strcpy(info->driver, DRV_NAME);
2016 strcpy(info->version, DRV_VERSION);
2017 strcpy(info->bus_info, pci_name(jme->pdev));
2018}
2019
3bf61c55 2020static int
8c198884
GFT
2021jme_get_regs_len(struct net_device *netdev)
2022{
186fc259 2023 return JME_REG_LEN;
8c198884
GFT
2024}
2025
2026static void
2027mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
2028{
2029 int i;
2030
2031 for(i = 0 ; i < len ; i += 4)
79ce639c 2032 p[i >> 2] = jread32(jme, reg + i);
186fc259 2033}
8c198884 2034
186fc259
GFT
2035static void
2036mdio_memcpy(struct jme_adapter *jme, __u32 *p, int reg_nr)
2037{
2038 int i;
2039 __u16 *p16 = (__u16*)p;
2040
2041 for(i = 0 ; i < reg_nr ; ++i)
2042 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2043}
2044
2045static void
2046jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2047{
2048 struct jme_adapter *jme = netdev_priv(netdev);
2049 __u32 *p32 = (__u32*)p;
2050
186fc259 2051 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2052
2053 regs->version = 1;
2054 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2055
2056 p32 += 0x100 >> 2;
2057 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2058
2059 p32 += 0x100 >> 2;
2060 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2061
2062 p32 += 0x100 >> 2;
2063 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2064
186fc259
GFT
2065 p32 += 0x100 >> 2;
2066 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2067}
2068
2069static int
2070jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2071{
2072 struct jme_adapter *jme = netdev_priv(netdev);
2073
8c198884
GFT
2074 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2075 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2076
cdcdc9eb
GFT
2077 if(jme->flags & JME_FLAG_POLL) {
2078 ecmd->use_adaptive_rx_coalesce = false;
2079 ecmd->rx_coalesce_usecs = 0;
2080 ecmd->rx_max_coalesced_frames = 0;
2081 return 0;
2082 }
2083
2084 ecmd->use_adaptive_rx_coalesce = true;
2085
8c198884
GFT
2086 switch(jme->dpi.cur) {
2087 case PCC_P1:
2088 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2089 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2090 break;
2091 case PCC_P2:
2092 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2093 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2094 break;
2095 case PCC_P3:
2096 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2097 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2098 break;
2099 default:
2100 break;
2101 }
2102
2103 return 0;
2104}
2105
192570e0
GFT
2106static int
2107jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2108{
2109 struct jme_adapter *jme = netdev_priv(netdev);
2110 struct dynpcc_info *dpi = &(jme->dpi);
2111
cdcdc9eb
GFT
2112 if(netif_running(netdev))
2113 return -EBUSY;
2114
192570e0
GFT
2115 if(ecmd->use_adaptive_rx_coalesce
2116 && (jme->flags & JME_FLAG_POLL)) {
2117 jme->flags &= ~JME_FLAG_POLL;
cdcdc9eb
GFT
2118 jme->jme_rx = netif_rx;
2119 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2120 dpi->cur = PCC_P1;
2121 dpi->attempt = PCC_P1;
2122 dpi->cnt = 0;
2123 jme_set_rx_pcc(jme, PCC_P1);
2124 jme_interrupt_mode(jme);
2125 }
2126 else if(!(ecmd->use_adaptive_rx_coalesce)
2127 && !(jme->flags & JME_FLAG_POLL)) {
2128 jme->flags |= JME_FLAG_POLL;
cdcdc9eb
GFT
2129 jme->jme_rx = netif_receive_skb;
2130 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2131 jme_interrupt_mode(jme);
2132 }
2133
2134 return 0;
2135}
2136
8c198884
GFT
2137static void
2138jme_get_pauseparam(struct net_device *netdev,
2139 struct ethtool_pauseparam *ecmd)
2140{
2141 struct jme_adapter *jme = netdev_priv(netdev);
2142 unsigned long flags;
2143 __u32 val;
2144
2145 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2146 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2147
2148 spin_lock_irqsave(&jme->phy_lock, flags);
2149 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2150 spin_unlock_irqrestore(&jme->phy_lock, flags);
b3821cc5
GFT
2151
2152 ecmd->autoneg =
2153 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2154}
2155
2156static int
2157jme_set_pauseparam(struct net_device *netdev,
2158 struct ethtool_pauseparam *ecmd)
2159{
2160 struct jme_adapter *jme = netdev_priv(netdev);
2161 unsigned long flags;
2162 __u32 val;
2163
2164 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
2165 (ecmd->tx_pause != 0)) {
2166
2167 if(ecmd->tx_pause)
2168 jme->reg_txpfc |= TXPFC_PF_EN;
2169 else
2170 jme->reg_txpfc &= ~TXPFC_PF_EN;
2171
2172 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2173 }
2174
2175 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2176 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
2177 (ecmd->rx_pause != 0)) {
2178
2179 if(ecmd->rx_pause)
2180 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2181 else
2182 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2183
2184 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2185 }
2186 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2187
2188 spin_lock_irqsave(&jme->phy_lock, flags);
2189 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
b3821cc5 2190 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
8c198884
GFT
2191 (ecmd->autoneg != 0)) {
2192
2193 if(ecmd->autoneg)
2194 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2195 else
2196 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2197
b3821cc5
GFT
2198 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2199 MII_ADVERTISE, val);
8c198884
GFT
2200 }
2201 spin_unlock_irqrestore(&jme->phy_lock, flags);
2202
2203 return 0;
2204}
2205
29bdd921
GFT
2206static void
2207jme_get_wol(struct net_device *netdev,
2208 struct ethtool_wolinfo *wol)
2209{
2210 struct jme_adapter *jme = netdev_priv(netdev);
2211
2212 wol->supported = WAKE_MAGIC | WAKE_PHY;
2213
2214 wol->wolopts = 0;
2215
2216 if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2217 wol->wolopts |= WAKE_PHY;
2218
2219 if(jme->reg_pmcs & PMCS_MFEN)
2220 wol->wolopts |= WAKE_MAGIC;
2221
2222}
2223
2224static int
2225jme_set_wol(struct net_device *netdev,
2226 struct ethtool_wolinfo *wol)
2227{
2228 struct jme_adapter *jme = netdev_priv(netdev);
2229
2230 if(wol->wolopts & (WAKE_MAGICSECURE |
2231 WAKE_UCAST |
2232 WAKE_MCAST |
2233 WAKE_BCAST |
2234 WAKE_ARP))
2235 return -EOPNOTSUPP;
2236
2237 jme->reg_pmcs = 0;
2238
2239 if(wol->wolopts & WAKE_PHY)
2240 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2241
2242 if(wol->wolopts & WAKE_MAGIC)
2243 jme->reg_pmcs |= PMCS_MFEN;
2244
42b1055e 2245
29bdd921
GFT
2246 return 0;
2247}
b3821cc5 2248
8c198884 2249static int
3bf61c55
GFT
2250jme_get_settings(struct net_device *netdev,
2251 struct ethtool_cmd *ecmd)
d7699f87
GFT
2252{
2253 struct jme_adapter *jme = netdev_priv(netdev);
2254 int rc;
79ce639c 2255 unsigned long flags;
8c198884 2256
79ce639c 2257 spin_lock_irqsave(&jme->phy_lock, flags);
d7699f87 2258 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
79ce639c 2259 spin_unlock_irqrestore(&jme->phy_lock, flags);
d7699f87
GFT
2260 return rc;
2261}
2262
3bf61c55
GFT
2263static int
2264jme_set_settings(struct net_device *netdev,
2265 struct ethtool_cmd *ecmd)
d7699f87
GFT
2266{
2267 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2268 int rc, fdc=0;
fcf45b4c
GFT
2269 unsigned long flags;
2270
8c198884
GFT
2271 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2272 return -EINVAL;
2273
79ce639c
GFT
2274 if(jme->mii_if.force_media &&
2275 ecmd->autoneg != AUTONEG_ENABLE &&
2276 (jme->mii_if.full_duplex != ecmd->duplex))
2277 fdc = 1;
2278
fcf45b4c 2279 spin_lock_irqsave(&jme->phy_lock, flags);
d7699f87 2280 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
fcf45b4c
GFT
2281 spin_unlock_irqrestore(&jme->phy_lock, flags);
2282
79ce639c
GFT
2283 if(!rc && fdc)
2284 jme_reset_link(jme);
2285
29bdd921
GFT
2286 if(!rc) {
2287 jme->flags |= JME_FLAG_SSET;
2288 jme->old_ecmd = *ecmd;
2289 }
2290
d7699f87
GFT
2291 return rc;
2292}
2293
3bf61c55
GFT
2294static __u32
2295jme_get_link(struct net_device *netdev)
2296{
d7699f87
GFT
2297 struct jme_adapter *jme = netdev_priv(netdev);
2298 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2299}
2300
8c198884
GFT
2301static u32
2302jme_get_rx_csum(struct net_device *netdev)
2303{
2304 struct jme_adapter *jme = netdev_priv(netdev);
2305
2306 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2307}
2308
2309static int
2310jme_set_rx_csum(struct net_device *netdev, u32 on)
2311{
2312 struct jme_adapter *jme = netdev_priv(netdev);
2313 unsigned long flags;
b3821cc5 2314
8c198884
GFT
2315 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2316 if(on)
2317 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2318 else
2319 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2320 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2321 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2322
2323 return 0;
2324}
2325
2326static int
2327jme_set_tx_csum(struct net_device *netdev, u32 on)
2328{
b3821cc5
GFT
2329 struct jme_adapter *jme = netdev_priv(netdev);
2330
2331 if(on) {
2332 jme->flags |= JME_FLAG_TXCSUM;
2333 if(netdev->mtu <= 1900)
2334 netdev->features |= NETIF_F_HW_CSUM;
2335 }
2336 else {
2337 jme->flags &= ~JME_FLAG_TXCSUM;
8c198884 2338 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2339 }
8c198884
GFT
2340
2341 return 0;
2342}
2343
2344static int
b3821cc5
GFT
2345jme_set_tso(struct net_device *netdev, u32 on)
2346{
2347 struct jme_adapter *jme = netdev_priv(netdev);
2348
2349 if (on) {
2350 jme->flags |= JME_FLAG_TSO;
2351 if(netdev->mtu <= 1900)
2352 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2353 }
2354 else {
2355 jme->flags &= ~JME_FLAG_TSO;
2356 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2357 }
2358
2359 return 0;
2360}
2361
2362static int
8c198884
GFT
2363jme_nway_reset(struct net_device *netdev)
2364{
2365 struct jme_adapter *jme = netdev_priv(netdev);
2366 jme_restart_an(jme);
2367 return 0;
2368}
2369
186fc259
GFT
2370static __u8
2371jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2372{
2373 __u32 val;
2374 int to;
2375
2376 val = jread32(jme, JME_SMBCSR);
2377 to = JME_SMB_BUSY_TIMEOUT;
2378 while((val & SMBCSR_BUSY) && --to) {
2379 msleep(1);
2380 val = jread32(jme, JME_SMBCSR);
2381 }
2382 if(!to) {
2383 jeprintk(jme->dev->name, "SMB Bus Busy.\n");
2384 return 0xFF;
2385 }
2386
2387 jwrite32(jme, JME_SMBINTF,
2388 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2389 SMBINTF_HWRWN_READ |
2390 SMBINTF_HWCMD);
2391
2392 val = jread32(jme, JME_SMBINTF);
2393 to = JME_SMB_BUSY_TIMEOUT;
2394 while((val & SMBINTF_HWCMD) && --to) {
2395 msleep(1);
2396 val = jread32(jme, JME_SMBINTF);
2397 }
2398 if(!to) {
2399 jeprintk(jme->dev->name, "SMB Bus Busy.\n");
2400 return 0xFF;
2401 }
2402
2403 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2404}
2405
2406static void
2407jme_smb_write(struct jme_adapter *jme, unsigned int addr, __u8 data)
2408{
2409 __u32 val;
2410 int to;
2411
2412 val = jread32(jme, JME_SMBCSR);
2413 to = JME_SMB_BUSY_TIMEOUT;
2414 while((val & SMBCSR_BUSY) && --to) {
2415 msleep(1);
2416 val = jread32(jme, JME_SMBCSR);
2417 }
2418 if(!to) {
2419 jeprintk(jme->dev->name, "SMB Bus Busy.\n");
2420 return;
2421 }
2422
2423 jwrite32(jme, JME_SMBINTF,
2424 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2425 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2426 SMBINTF_HWRWN_WRITE |
2427 SMBINTF_HWCMD);
2428
2429 val = jread32(jme, JME_SMBINTF);
2430 to = JME_SMB_BUSY_TIMEOUT;
2431 while((val & SMBINTF_HWCMD) && --to) {
2432 msleep(1);
2433 val = jread32(jme, JME_SMBINTF);
2434 }
2435 if(!to) {
2436 jeprintk(jme->dev->name, "SMB Bus Busy.\n");
2437 return;
2438 }
2439
2440 mdelay(2);
2441}
2442
2443static int
2444jme_get_eeprom_len(struct net_device *netdev)
2445{
2446 struct jme_adapter *jme = netdev_priv(netdev);
2447 __u32 val;
2448 val = jread32(jme, JME_SMBCSR);
2449 return (val & SMBCSR_EEPROMD)?JME_SMB_LEN:0;
2450}
2451
2452static int
2453jme_get_eeprom(struct net_device *netdev,
2454 struct ethtool_eeprom *eeprom, u8 *data)
2455{
2456 struct jme_adapter *jme = netdev_priv(netdev);
2457 int i, offset = eeprom->offset, len = eeprom->len;
2458
2459 /*
8d27293f 2460 * ethtool will check the boundary for us
186fc259
GFT
2461 */
2462 eeprom->magic = JME_EEPROM_MAGIC;
2463 for(i = 0 ; i < len ; ++i)
2464 data[i] = jme_smb_read(jme, i + offset);
2465
2466 return 0;
2467}
2468
2469static int
2470jme_set_eeprom(struct net_device *netdev,
2471 struct ethtool_eeprom *eeprom, u8 *data)
2472{
2473 struct jme_adapter *jme = netdev_priv(netdev);
2474 int i, offset = eeprom->offset, len = eeprom->len;
2475
2476 if (eeprom->magic != JME_EEPROM_MAGIC)
2477 return -EINVAL;
2478
2479 /*
8d27293f 2480 * ethtool will check the boundary for us
186fc259
GFT
2481 */
2482 for(i = 0 ; i < len ; ++i)
2483 jme_smb_write(jme, i + offset, data[i]);
2484
2485 return 0;
2486}
2487
d7699f87
GFT
2488static const struct ethtool_ops jme_ethtool_ops = {
2489 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2490 .get_regs_len = jme_get_regs_len,
2491 .get_regs = jme_get_regs,
2492 .get_coalesce = jme_get_coalesce,
192570e0 2493 .set_coalesce = jme_set_coalesce,
8c198884
GFT
2494 .get_pauseparam = jme_get_pauseparam,
2495 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2496 .get_wol = jme_get_wol,
2497 .set_wol = jme_set_wol,
d7699f87
GFT
2498 .get_settings = jme_get_settings,
2499 .set_settings = jme_set_settings,
2500 .get_link = jme_get_link,
8c198884
GFT
2501 .get_rx_csum = jme_get_rx_csum,
2502 .set_rx_csum = jme_set_rx_csum,
2503 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2504 .set_tso = jme_set_tso,
2505 .set_sg = ethtool_op_set_sg,
8c198884 2506 .nway_reset = jme_nway_reset,
186fc259
GFT
2507 .get_eeprom_len = jme_get_eeprom_len,
2508 .get_eeprom = jme_get_eeprom,
2509 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2510};
2511
3bf61c55
GFT
2512static int
2513jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2514{
3bf61c55 2515 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
42b1055e
GFT
2516 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
2517 dprintk("jme", "64Bit DMA Selected.\n");
3bf61c55 2518 return 1;
42b1055e 2519 }
3bf61c55 2520
8c198884 2521 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
42b1055e
GFT
2522 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK)) {
2523 dprintk("jme", "40Bit DMA Selected.\n");
8c198884 2524 return 1;
42b1055e 2525 }
8c198884 2526
3bf61c55 2527 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
42b1055e
GFT
2528 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
2529 dprintk("jme", "32Bit DMA Selected.\n");
3bf61c55 2530 return 0;
42b1055e 2531 }
3bf61c55
GFT
2532
2533 return -1;
2534}
2535
42b1055e 2536__always_inline static void
cdcdc9eb
GFT
2537jme_phy_init(struct jme_adapter *jme)
2538{
2539 __u16 reg26;
2540
2541 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2542 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2543}
2544
2545__always_inline static void
2546jme_set_gmii(struct jme_adapter *jme)
2547{
2548 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
2549}
2550
2551static void
2552jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2553{
cdcdc9eb
GFT
2554 __u32 chipmode;
2555
2556 chipmode = jread32(jme, JME_CHIPMODE);
2557
2558 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2559 jme->chipver = (chipmode & CM_CHIPVER_MASK) >> CM_CHIPVER_SHIFT;
42b1055e
GFT
2560}
2561
3bf61c55
GFT
2562static int __devinit
2563jme_init_one(struct pci_dev *pdev,
2564 const struct pci_device_id *ent)
2565{
cdcdc9eb 2566 int rc = 0, using_dac, i;
d7699f87
GFT
2567 struct net_device *netdev;
2568 struct jme_adapter *jme;
cdcdc9eb 2569 __u16 bmcr, bmsr;
d7699f87
GFT
2570
2571 /*
2572 * set up PCI device basics
2573 */
4330c2f2
GFT
2574 rc = pci_enable_device(pdev);
2575 if(rc) {
2576 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2577 goto err_out;
2578 }
d7699f87 2579
3bf61c55
GFT
2580 using_dac = jme_pci_dma64(pdev);
2581 if(using_dac < 0) {
2582 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2583 rc = -EIO;
2584 goto err_out_disable_pdev;
2585 }
2586
4330c2f2
GFT
2587 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2588 printk(KERN_ERR PFX "No PCI resource region found.\n");
2589 rc = -ENOMEM;
2590 goto err_out_disable_pdev;
2591 }
d7699f87 2592
4330c2f2
GFT
2593 rc = pci_request_regions(pdev, DRV_NAME);
2594 if(rc) {
2595 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2596 goto err_out_disable_pdev;
2597 }
d7699f87
GFT
2598
2599 pci_set_master(pdev);
2600
2601 /*
2602 * alloc and init net device
2603 */
3bf61c55 2604 netdev = alloc_etherdev(sizeof(*jme));
d7699f87 2605 if(!netdev) {
42b1055e 2606 printk(KERN_ERR PFX "Cannot allocate netdev structure.\n");
4330c2f2
GFT
2607 rc = -ENOMEM;
2608 goto err_out_release_regions;
d7699f87
GFT
2609 }
2610 netdev->open = jme_open;
2611 netdev->stop = jme_close;
2612 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT
2613 netdev->set_mac_address = jme_set_macaddr;
2614 netdev->set_multicast_list = jme_set_multi;
2615 netdev->change_mtu = jme_change_mtu;
2616 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884
GFT
2617 netdev->tx_timeout = jme_tx_timeout;
2618 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2619 netdev->vlan_rx_register = jme_vlan_rx_register;
3bf61c55 2620 NETDEV_GET_STATS(netdev, &jme_get_stats);
42b1055e 2621 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT
2622 NETIF_F_SG |
2623 NETIF_F_TSO |
2624 NETIF_F_TSO6 |
42b1055e
GFT
2625 NETIF_F_HW_VLAN_TX |
2626 NETIF_F_HW_VLAN_RX;
3bf61c55 2627 if(using_dac)
8c198884 2628 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2629
2630 SET_NETDEV_DEV(netdev, &pdev->dev);
2631 pci_set_drvdata(pdev, netdev);
2632
2633 /*
2634 * init adapter info
2635 */
2636 jme = netdev_priv(netdev);
2637 jme->pdev = pdev;
2638 jme->dev = netdev;
cdcdc9eb
GFT
2639 jme->jme_rx = netif_rx;
2640 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2641 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2642 jme->phylink = 0;
b3821cc5
GFT
2643 jme->tx_ring_size = 1 << 10;
2644 jme->tx_ring_mask = jme->tx_ring_size - 1;
2645 jme->tx_wake_threshold = 1 << 9;
2646 jme->rx_ring_size = 1 << 9;
2647 jme->rx_ring_mask = jme->rx_ring_size - 1;
d7699f87
GFT
2648 jme->regs = ioremap(pci_resource_start(pdev, 0),
2649 pci_resource_len(pdev, 0));
4330c2f2 2650 if (!(jme->regs)) {
42b1055e 2651 printk(KERN_ERR PFX "Mapping PCI resource region error.\n");
d7699f87
GFT
2652 rc = -ENOMEM;
2653 goto err_out_free_netdev;
2654 }
4330c2f2
GFT
2655 jme->shadow_regs = pci_alloc_consistent(pdev,
2656 sizeof(__u32) * SHADOW_REG_NR,
2657 &(jme->shadow_dma));
2658 if (!(jme->shadow_regs)) {
42b1055e 2659 printk(KERN_ERR PFX "Allocating shadow register mapping error.\n");
4330c2f2
GFT
2660 rc = -ENOMEM;
2661 goto err_out_unmap;
2662 }
2663
cdcdc9eb 2664 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2665
d7699f87 2666 spin_lock_init(&jme->phy_lock);
fcf45b4c 2667 spin_lock_init(&jme->macaddr_lock);
8c198884 2668 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2669
fcf45b4c
GFT
2670 atomic_set(&jme->link_changing, 1);
2671 atomic_set(&jme->rx_cleaning, 1);
2672 atomic_set(&jme->tx_cleaning, 1);
192570e0 2673 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2674
79ce639c
GFT
2675 tasklet_init(&jme->pcc_task,
2676 &jme_pcc_tasklet,
2677 (unsigned long) jme);
4330c2f2
GFT
2678 tasklet_init(&jme->linkch_task,
2679 &jme_link_change_tasklet,
2680 (unsigned long) jme);
2681 tasklet_init(&jme->txclean_task,
2682 &jme_tx_clean_tasklet,
2683 (unsigned long) jme);
2684 tasklet_init(&jme->rxclean_task,
2685 &jme_rx_clean_tasklet,
2686 (unsigned long) jme);
fcf45b4c
GFT
2687 tasklet_init(&jme->rxempty_task,
2688 &jme_rx_empty_tasklet,
2689 (unsigned long) jme);
8c198884
GFT
2690 jme->dpi.cur = PCC_P1;
2691
8d27293f
GFT
2692 if(pdev->device == JME_GE_DEVICE)
2693 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
2694 else
2695 jme->reg_ghc = GHC_DPX | GHC_SPEED_100M;
79ce639c 2696 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
2697 jme->reg_rxmcs = RXMCS_DEFAULT;
2698 jme->reg_txpfc = 0;
b3821cc5 2699 jme->reg_pmcs = PMCS_LFEN | PMCS_LREN | PMCS_MFEN;
cdcdc9eb 2700 jme->flags = JME_FLAG_TXCSUM | JME_FLAG_TSO;
192570e0 2701
d7699f87 2702 /*
fcf45b4c
GFT
2703 * Get Max Read Req Size from PCI Config Space
2704 */
2705 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2706 switch(jme->mrrs) {
2707 case MRRS_128B:
2708 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2709 break;
2710 case MRRS_256B:
2711 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2712 break;
2713 default:
2714 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2715 break;
2716 };
2717
2718
2719 /*
cdcdc9eb 2720 * Must check before reset_mac_processor
d7699f87 2721 */
cdcdc9eb
GFT
2722 jme_check_hw_ver(jme);
2723 jme->mii_if.dev = netdev;
2724 if(jme->fpgaver) {
2725 jme->mii_if.phy_id = 0;
2726 for(i = 1 ; i < 32 ; ++i) {
2727 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2728 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2729 if(bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2730 jme->mii_if.phy_id = i;
2731 break;
2732 }
2733 }
2734
2735 if(!jme->mii_if.phy_id) {
2736 rc = -EIO;
2737 printk(KERN_ERR PFX "Can not find phy_id.\n");
2738 goto err_out_free_shadow;
2739 }
2740
2741 jme->reg_ghc |= GHC_LINK_POLL;
2742 }
2743 else {
2744 jme->mii_if.phy_id = 1;
2745 }
8d27293f
GFT
2746 if(pdev->device == JME_GE_DEVICE)
2747 jme->mii_if.supports_gmii = true;
2748 else
2749 jme->mii_if.supports_gmii = false;
cdcdc9eb
GFT
2750 jme->mii_if.mdio_read = jme_mdio_read;
2751 jme->mii_if.mdio_write = jme_mdio_write;
2752
d7699f87 2753 jme_clear_pm(jme);
cdcdc9eb
GFT
2754 if(jme->fpgaver)
2755 jme_set_gmii(jme);
2756 else
2757 jme_phy_init(jme);
42b1055e 2758 jme_phy_off(jme);
cdcdc9eb
GFT
2759
2760 /*
2761 * Reset MAC processor and reload EEPROM for MAC Address
2762 */
d7699f87 2763 jme_reset_mac_processor(jme);
4330c2f2
GFT
2764 rc = jme_reload_eeprom(jme);
2765 if(rc) {
3bf61c55 2766 printk(KERN_ERR PFX
b3821cc5 2767 "Reload eeprom for reading MAC Address error.\n");
4330c2f2
GFT
2768 goto err_out_free_shadow;
2769 }
d7699f87
GFT
2770 jme_load_macaddr(netdev);
2771
2772
2773 /*
2774 * Tell stack that we are not ready to work until open()
2775 */
2776 netif_carrier_off(netdev);
2777 netif_stop_queue(netdev);
2778
2779 /*
2780 * Register netdev
2781 */
4330c2f2
GFT
2782 rc = register_netdev(netdev);
2783 if(rc) {
2784 printk(KERN_ERR PFX "Cannot register net device.\n");
2785 goto err_out_free_shadow;
2786 }
d7699f87 2787
4330c2f2 2788 jprintk(netdev->name,
cdcdc9eb
GFT
2789 "JMC250 gigabit%s ver:%u eth %02x:%02x:%02x:%02x:%02x:%02x\n",
2790 (jme->fpgaver != 0)?" (FPGA)":"",
2791 (jme->fpgaver != 0)?jme->fpgaver:jme->chipver,
4330c2f2
GFT
2792 netdev->dev_addr[0],
2793 netdev->dev_addr[1],
2794 netdev->dev_addr[2],
2795 netdev->dev_addr[3],
2796 netdev->dev_addr[4],
8c198884 2797 netdev->dev_addr[5]);
d7699f87
GFT
2798
2799 return 0;
2800
4330c2f2
GFT
2801err_out_free_shadow:
2802 pci_free_consistent(pdev,
2803 sizeof(__u32) * SHADOW_REG_NR,
2804 jme->shadow_regs,
2805 jme->shadow_dma);
d7699f87
GFT
2806err_out_unmap:
2807 iounmap(jme->regs);
2808err_out_free_netdev:
2809 pci_set_drvdata(pdev, NULL);
2810 free_netdev(netdev);
4330c2f2
GFT
2811err_out_release_regions:
2812 pci_release_regions(pdev);
d7699f87
GFT
2813err_out_disable_pdev:
2814 pci_disable_device(pdev);
d7699f87 2815err_out:
4330c2f2 2816 return rc;
d7699f87
GFT
2817}
2818
3bf61c55
GFT
2819static void __devexit
2820jme_remove_one(struct pci_dev *pdev)
2821{
d7699f87
GFT
2822 struct net_device *netdev = pci_get_drvdata(pdev);
2823 struct jme_adapter *jme = netdev_priv(netdev);
2824
2825 unregister_netdev(netdev);
4330c2f2
GFT
2826 pci_free_consistent(pdev,
2827 sizeof(__u32) * SHADOW_REG_NR,
2828 jme->shadow_regs,
2829 jme->shadow_dma);
d7699f87
GFT
2830 iounmap(jme->regs);
2831 pci_set_drvdata(pdev, NULL);
2832 free_netdev(netdev);
2833 pci_release_regions(pdev);
2834 pci_disable_device(pdev);
2835
2836}
2837
29bdd921
GFT
2838static int
2839jme_suspend(struct pci_dev *pdev, pm_message_t state)
2840{
2841 struct net_device *netdev = pci_get_drvdata(pdev);
2842 struct jme_adapter *jme = netdev_priv(netdev);
2843 int timeout = 100;
2844
2845 atomic_dec(&jme->link_changing);
2846
2847 netif_device_detach(netdev);
2848 netif_stop_queue(netdev);
2849 jme_stop_irq(jme);
2850 jme_free_irq(jme);
2851
2852 while(--timeout > 0 &&
2853 (
2854 atomic_read(&jme->rx_cleaning) != 1 ||
2855 atomic_read(&jme->tx_cleaning) != 1
2856 )) {
2857 mdelay(1);
2858 }
2859 if(!timeout) {
2860 jeprintk(netdev->name, "Waiting tasklets timeout.\n");
2861 return -EBUSY;
2862 }
2863 jme_disable_shadow(jme);
2864
2865 if(netif_carrier_ok(netdev)) {
2866 jme_stop_pcc_timer(jme);
2867 jme_reset_mac_processor(jme);
2868 jme_free_rx_resources(jme);
2869 jme_free_tx_resources(jme);
2870 netif_carrier_off(netdev);
2871 jme->phylink = 0;
192570e0 2872
cdcdc9eb 2873 if(jme->flags & JME_FLAG_POLL)
192570e0 2874 jme_polling_mode(jme);
29bdd921
GFT
2875 }
2876
29bdd921
GFT
2877
2878 pci_save_state(pdev);
2879 if(jme->reg_pmcs) {
42b1055e 2880 jme_set_100m_half(jme);
29bdd921 2881 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e
GFT
2882 pci_enable_wake(pdev, PCI_D3hot, true);
2883 pci_enable_wake(pdev, PCI_D3cold, true);
29bdd921
GFT
2884 }
2885 else {
42b1055e
GFT
2886 jme_phy_off(jme);
2887 pci_enable_wake(pdev, PCI_D3hot, false);
2888 pci_enable_wake(pdev, PCI_D3cold, false);
29bdd921
GFT
2889 }
2890 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2891
2892 return 0;
2893}
2894
2895static int
2896jme_resume(struct pci_dev *pdev)
2897{
2898 struct net_device *netdev = pci_get_drvdata(pdev);
2899 struct jme_adapter *jme = netdev_priv(netdev);
2900
2901 jme_clear_pm(jme);
2902 pci_restore_state(pdev);
2903
2904 if(jme->flags & JME_FLAG_SSET)
2905 jme_set_settings(netdev, &jme->old_ecmd);
2906 else
2907 jme_reset_phy_processor(jme);
2908
2909 jme_reset_mac_processor(jme);
2910 jme_enable_shadow(jme);
2911 jme_request_irq(jme);
2912 jme_start_irq(jme);
2913 netif_device_attach(netdev);
2914
2915 atomic_inc(&jme->link_changing);
2916
2917 jme_reset_link(jme);
2918
2919 return 0;
2920}
2921
d7699f87 2922static struct pci_device_id jme_pci_tbl[] = {
8d27293f
GFT
2923 { PCI_VDEVICE(JMICRON, JME_GE_DEVICE) },
2924 { PCI_VDEVICE(JMICRON, JME_FE_DEVICE) },
d7699f87
GFT
2925 { }
2926};
2927
2928static struct pci_driver jme_driver = {
2929 .name = DRV_NAME,
2930 .id_table = jme_pci_tbl,
2931 .probe = jme_init_one,
2932 .remove = __devexit_p(jme_remove_one),
d7699f87
GFT
2933#ifdef CONFIG_PM
2934 .suspend = jme_suspend,
2935 .resume = jme_resume,
2936#endif /* CONFIG_PM */
d7699f87
GFT
2937};
2938
3bf61c55
GFT
2939static int __init
2940jme_init_module(void)
d7699f87 2941{
4330c2f2
GFT
2942 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2943 "driver version %s\n", DRV_VERSION);
d7699f87
GFT
2944 return pci_register_driver(&jme_driver);
2945}
2946
3bf61c55
GFT
2947static void __exit
2948jme_cleanup_module(void)
d7699f87
GFT
2949{
2950 pci_unregister_driver(&jme_driver);
2951}
2952
2953module_init(jme_init_module);
2954module_exit(jme_cleanup_module);
2955
3bf61c55 2956MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
2957MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2958MODULE_LICENSE("GPL");
2959MODULE_VERSION(DRV_VERSION);
2960MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
2961