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Import jme 1.0.5 source
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
3bf61c55
GFT		 7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
d7699f87
GFT		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
d7699f87
GFT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/mii.h>
31#include <linux/crc32.h>
4330c2f2 32#include <linux/delay.h>
29bdd921 33#include <linux/spinlock.h>
8c198884
GFT		 34#include <linux/in.h>
35#include <linux/ip.h>
79ce639c
GFT		 36#include <linux/ipv6.h>
37#include <linux/tcp.h>
38#include <linux/udp.h>
42b1055e 39#include <linux/if_vlan.h>
94c5ea02 40#include <net/ip6_checksum.h>
d7699f87
GFT		 41#include "jme.h"
42
cd0ff491
GFT		 43static int force_pseudohp = -1;
44static int no_pseudohp = -1;
45static int no_extplug = -1;
46module_param(force_pseudohp, int, 0);
47MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49module_param(no_pseudohp, int, 0);
50MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51module_param(no_extplug, int, 0);
52MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 54
3bf61c55
GFT		 55static int
56jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 57{
58 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 60
186fc259 61read_again:
cd0ff491 62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
d7699f87
GFT		 65
66 wmb();
cd0ff491 67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 68 udelay(20);
b3821cc5
GFT		 69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
3bf61c55 71 break;
cd0ff491 72 }
d7699f87 73
cd0ff491
GFT		 74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 76 return 0;
cd0ff491 77 }
d7699f87 78
cd0ff491 79 if (again--)
186fc259
GFT		 80 goto read_again;
81
cd0ff491 82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 83}
84
3bf61c55
GFT		 85static void
86jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
d7699f87
GFT		 88{
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
3bf61c55
GFT		 92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 95
96 wmb();
cdcdc9eb
GFT		 97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
8d27293f 99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 100 break;
101 }
d7699f87 102
3bf61c55 103 if (i == 0)
cd0ff491 104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
d7699f87 105
3bf61c55 106 return;
d7699f87
GFT		 107}
108
cd0ff491 109static inline void
3bf61c55 110jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 111{
cd0ff491 112 u32 val;
3bf61c55
GFT		 113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
8c198884
GFT		 116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 118
cd0ff491 119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 124
fcf45b4c
GFT		 125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
3bf61c55
GFT		 133 return;
134}
135
b3821cc5
GFT		 136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
cd0ff491 138 u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
cd0ff491 153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55 162
cd0ff491 163static inline void
3bf61c55
GFT		 164jme_reset_mac_processor(struct jme_adapter *jme)
165{
cd0ff491
GFT		 166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
b3821cc5
GFT		 169 int i;
170
3bf61c55 171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 172 udelay(2);
3bf61c55 173 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT		 174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
4330c2f2
GFT		 184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 187 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 188 if (jme->fpgaver)
cdcdc9eb
GFT		 189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
9b9d55de 193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT		 194}
195
cd0ff491
GFT		 196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
3bf61c55 204jme_clear_pm(struct jme_adapter *jme)
d7699f87 205{
29bdd921 206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 207 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 208 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT		 209}
210
3bf61c55
GFT		 211static int
212jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 213{
cd0ff491 214 u32 val;
d7699f87
GFT		 215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
cd0ff491 219 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
cd0ff491 226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
cd0ff491
GFT		 232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
d7699f87
GFT		 234 return -EIO;
235 }
236 }
3bf61c55 237
d7699f87
GFT		 238 return 0;
239}
240
3bf61c55
GFT		 241static void
242jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 243{
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
cd0ff491 246 u32 val;
d7699f87 247
cd0ff491 248 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 249 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 254 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 259}
260
cd0ff491 261static inline void
3bf61c55
GFT		 262jme_set_rx_pcc(struct jme_adapter *jme, int p)
263{
cd0ff491 264 switch (p) {
192570e0
GFT		 265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
3bf61c55
GFT		 270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
192570e0 288 wmb();
3bf61c55 289
cd0ff491
GFT		 290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 292}
293
fcf45b4c 294static void
3bf61c55 295jme_start_irq(struct jme_adapter *jme)
d7699f87 296{
3bf61c55
GFT		 297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 307 PCCTXQ0_EN
308 );
309
d7699f87
GFT		 310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314}
315
cd0ff491 316static inline void
3bf61c55 317jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 318{
319 /*
320 * Disable Interrupts
321 */
cd0ff491 322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 323}
324
cd0ff491 325static u32
cdcdc9eb
GFT		 326jme_linkstat_from_phy(struct jme_adapter *jme)
327{
cd0ff491 328 u32 phylink, bmsr;
cdcdc9eb
GFT		 329
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 332 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335 return phylink;
336}
337
cd0ff491 338static inline void
e882564f 339jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT		 340{
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342}
343
344static inline void
e882564f 345jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT		 346{
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348}
349
fcf45b4c
GFT		 350static int
351jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 352{
353 struct jme_adapter *jme = netdev_priv(netdev);
9b9d55de 354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 355 char linkmsg[64];
fcf45b4c 356 int rc = 0;
d7699f87 357
b3821cc5 358 linkmsg[0] = '\0';
cdcdc9eb 359
cd0ff491 360 if (jme->fpgaver)
cdcdc9eb
GFT		 361 phylink = jme_linkstat_from_phy(jme);
362 else
363 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 364
cd0ff491
GFT		 365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 367 /*
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
370 */
371 phylink = PHY_LINK_UP;
372
373 bmcr = jme_mdio_read(jme->dev,
374 jme->mii_if.phy_id,
375 MII_BMCR);
376
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
382 PHY_LINK_SPEED_10M;
383
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
385 PHY_LINK_DUPLEX : 0;
79ce639c 386
b3821cc5 387 strcat(linkmsg, "Forced: ");
cd0ff491 388 } else {
8c198884
GFT		 389 /*
390 * Keep polling for speed/duplex resolve complete
391 */
cd0ff491 392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 393 --cnt) {
394
395 udelay(1);
8c198884 396
cd0ff491 397 if (jme->fpgaver)
cdcdc9eb
GFT		 398 phylink = jme_linkstat_from_phy(jme);
399 else
400 phylink = jread32(jme, JME_PHY_LINK);
8c198884 401 }
cd0ff491
GFT		 402 if (!cnt)
403 jeprintk(jme->pdev,
8c198884 404 "Waiting speed resolve timeout.\n");
79ce639c 405
b3821cc5 406 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 407 }
408
cd0ff491 409 if (jme->phylink == phylink) {
fcf45b4c
GFT		 410 rc = 1;
411 goto out;
412 }
cd0ff491 413 if (testonly)
fcf45b4c
GFT		 414 goto out;
415
416 jme->phylink = phylink;
417
94c5ea02
GFT		 418 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
419 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
420 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
cd0ff491
GFT		 421 switch (phylink & PHY_LINK_SPEED_MASK) {
422 case PHY_LINK_SPEED_10M:
94c5ea02
GFT		 423 ghc |= GHC_SPEED_10M |
424 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 425 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 426 break;
427 case PHY_LINK_SPEED_100M:
94c5ea02
GFT		 428 ghc |= GHC_SPEED_100M |
429 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 430 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 431 break;
432 case PHY_LINK_SPEED_1000M:
94c5ea02
GFT		 433 ghc |= GHC_SPEED_1000M |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
cd0ff491 435 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 436 break;
437 default:
438 break;
d7699f87 439 }
d7699f87 440
cd0ff491 441 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
9b9d55de 443 ghc |= GHC_DPX;
cd0ff491 444 } else {
d7699f87 445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 446 TXMCS_BACKOFF |
447 TXMCS_CARRIERSENSE |
448 TXMCS_COLLISION);
8c198884
GFT		 449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
451 TXTRHD_TXREN |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
453 }
9b9d55de
GFT		 454
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifoa(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
463 break;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifob(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
467 break;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifoa(jme);
470 break;
471 default:
472 break;
473 }
474 }
d7699f87 475
94c5ea02 476 jwrite32(jme, JME_GPREG1, gpreg1);
fcf45b4c 477 jwrite32(jme, JME_GHC, ghc);
94c5ea02 478 jme->reg_ghc = ghc;
fcf45b4c 479
94c5ea02
GFT		 480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
481 "Full-Duplex, " :
482 "Half-Duplex, ");
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
484 "MDI-X" :
485 "MDI");
cd0ff491
GFT		 486 msg_link(jme, "Link is up at %s.\n", linkmsg);
487 netif_carrier_on(netdev);
488 } else {
489 if (testonly)
fcf45b4c
GFT		 490 goto out;
491
cd0ff491 492 msg_link(jme, "Link is down.\n");
fcf45b4c 493 jme->phylink = 0;
cd0ff491 494 netif_carrier_off(netdev);
d7699f87 495 }
fcf45b4c
GFT		 496
497out:
498 return rc;
d7699f87
GFT		 499}
500
3bf61c55
GFT		 501static int
502jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 503{
d7699f87
GFT		 504 struct jme_ring *txring = &(jme->txring[0]);
505
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
508 &(txring->dmaalloc),
509 GFP_ATOMIC);
fcf45b4c 510
fa97b924
GFT		 511 if (!txring->alloc)
512 goto err_set_null;
d7699f87
GFT		 513
514 /*
515 * 16 Bytes align
516 */
cd0ff491 517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 518 RING_DESC_ALIGN);
4330c2f2 519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 520 txring->next_to_use = 0;
cdcdc9eb 521 atomic_set(&txring->next_to_clean, 0);
b3821cc5 522 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 523
fa97b924
GFT		 524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
528
d7699f87 529 /*
b3821cc5 530 * Initialize Transmit Descriptors
d7699f87 531 */
b3821cc5 532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 533 memset(txring->bufinf, 0,
b3821cc5 534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 535
536 return 0;
fa97b924
GFT		 537
538err_free_txring:
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
541 txring->alloc,
542 txring->dmaalloc);
543
544err_set_null:
545 txring->desc = NULL;
546 txring->dmaalloc = 0;
547 txring->dma = 0;
548 txring->bufinf = NULL;
549
550 return -ENOMEM;
d7699f87
GFT		 551}
552
3bf61c55
GFT		 553static void
554jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 555{
556 int i;
557 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 558 struct jme_buffer_info *txbi;
d7699f87 559
cd0ff491 560 if (txring->alloc) {
fa97b924
GFT		 561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
564 if (txbi->skb) {
565 dev_kfree_skb(txbi->skb);
566 txbi->skb = NULL;
567 }
568 txbi->mapping = 0;
569 txbi->len = 0;
570 txbi->nr_desc = 0;
571 txbi->start_xmit = 0;
d7699f87 572 }
fa97b924 573 kfree(txring->bufinf);
d7699f87
GFT		 574 }
575
576 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 578 txring->alloc,
579 txring->dmaalloc);
3bf61c55
GFT		 580
581 txring->alloc = NULL;
582 txring->desc = NULL;
583 txring->dmaalloc = 0;
584 txring->dma = 0;
fa97b924 585 txring->bufinf = NULL;
d7699f87 586 }
3bf61c55 587 txring->next_to_use = 0;
cdcdc9eb 588 atomic_set(&txring->next_to_clean, 0);
79ce639c 589 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 590}
591
cd0ff491 592static inline void
3bf61c55 593jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 594{
595 /*
596 * Select Queue 0
597 */
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 599 wmb();
d7699f87
GFT		 600
601 /*
602 * Setup TX Queue 0 DMA Bass Address
603 */
fcf45b4c 604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 607
608 /*
609 * Setup TX Descptor Count
610 */
b3821cc5 611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 612
613 /*
614 * Enable TX Engine
615 */
616 wmb();
4330c2f2
GFT		 617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
618 TXCS_SELECT_QUEUE0 |
619 TXCS_ENABLE);
d7699f87
GFT		 620
621}
622
cd0ff491 623static inline void
29bdd921
GFT		 624jme_restart_tx_engine(struct jme_adapter *jme)
625{
626 /*
627 * Restart TX Engine
628 */
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
630 TXCS_SELECT_QUEUE0 |
631 TXCS_ENABLE);
632}
633
cd0ff491 634static inline void
3bf61c55 635jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 636{
637 int i;
cd0ff491 638 u32 val;
d7699f87
GFT		 639
640 /*
641 * Disable TX Engine
642 */
fcf45b4c 643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 644 wmb();
d7699f87
GFT		 645
646 val = jread32(jme, JME_TXCS);
cd0ff491 647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 648 mdelay(1);
d7699f87 649 val = jread32(jme, JME_TXCS);
cd0ff491 650 rmb();
d7699f87
GFT		 651 }
652
cd0ff491
GFT		 653 if (!i)
654 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
d7699f87
GFT		 655}
656
3bf61c55
GFT		 657static void
658jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 659{
fa97b924 660 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 661 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 662 struct jme_buffer_info *rxbi = rxring->bufinf;
663 rxdesc += i;
664 rxbi += i;
665
666 rxdesc->dw[0] = 0;
667 rxdesc->dw[1] = 0;
3bf61c55 668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 672 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 673 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 674 wmb();
3bf61c55 675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 676}
677
3bf61c55
GFT		 678static int
679jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 680{
681 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 683 struct sk_buff *skb;
4330c2f2 684
79ce639c
GFT		 685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 687 if (unlikely(!skb))
4330c2f2 688 return -ENOMEM;
3bf61c55 689
4330c2f2 690 rxbi->skb = skb;
3bf61c55 691 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT		 692 rxbi->mapping = pci_map_page(jme->pdev,
693 virt_to_page(skb->data),
694 offset_in_page(skb->data),
695 rxbi->len,
696 PCI_DMA_FROMDEVICE);
4330c2f2
GFT		 697
698 return 0;
699}
700
3bf61c55
GFT		 701static void
702jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 703{
704 struct jme_ring *rxring = &(jme->rxring[0]);
705 struct jme_buffer_info *rxbi = rxring->bufinf;
706 rxbi += i;
707
cd0ff491 708 if (rxbi->skb) {
b3821cc5 709 pci_unmap_page(jme->pdev,
4330c2f2 710 rxbi->mapping,
3bf61c55 711 rxbi->len,
4330c2f2
GFT		 712 PCI_DMA_FROMDEVICE);
713 dev_kfree_skb(rxbi->skb);
714 rxbi->skb = NULL;
715 rxbi->mapping = 0;
3bf61c55 716 rxbi->len = 0;
4330c2f2
GFT		 717 }
718}
719
3bf61c55
GFT		 720static void
721jme_free_rx_resources(struct jme_adapter *jme)
722{
723 int i;
724 struct jme_ring *rxring = &(jme->rxring[0]);
725
cd0ff491 726 if (rxring->alloc) {
fa97b924
GFT		 727 if (rxring->bufinf) {
728 for (i = 0 ; i < jme->rx_ring_size ; ++i)
729 jme_free_rx_buf(jme, i);
730 kfree(rxring->bufinf);
731 }
3bf61c55
GFT		 732
733 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 734 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 735 rxring->alloc,
736 rxring->dmaalloc);
737 rxring->alloc = NULL;
738 rxring->desc = NULL;
739 rxring->dmaalloc = 0;
740 rxring->dma = 0;
fa97b924 741 rxring->bufinf = NULL;
3bf61c55
GFT		 742 }
743 rxring->next_to_use = 0;
cdcdc9eb 744 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 745}
746
747static int
748jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 749{
750 int i;
751 struct jme_ring *rxring = &(jme->rxring[0]);
752
753 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 754 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
755 &(rxring->dmaalloc),
756 GFP_ATOMIC);
fa97b924
GFT		 757 if (!rxring->alloc)
758 goto err_set_null;
d7699f87
GFT		 759
760 /*
761 * 16 Bytes align
762 */
cd0ff491 763 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 764 RING_DESC_ALIGN);
4330c2f2 765 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 766 rxring->next_to_use = 0;
cdcdc9eb 767 atomic_set(&rxring->next_to_clean, 0);
d7699f87 768
fa97b924
GFT		 769 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
770 jme->rx_ring_size, GFP_ATOMIC);
771 if (unlikely(!(rxring->bufinf)))
772 goto err_free_rxring;
773
d7699f87
GFT		 774 /*
775 * Initiallize Receive Descriptors
776 */
fa97b924
GFT		 777 memset(rxring->bufinf, 0,
778 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 779 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
780 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 781 jme_free_rx_resources(jme);
782 return -ENOMEM;
783 }
d7699f87
GFT		 784
785 jme_set_clean_rxdesc(jme, i);
786 }
787
d7699f87 788 return 0;
fa97b924
GFT		 789
790err_free_rxring:
791 dma_free_coherent(&(jme->pdev->dev),
792 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
793 rxring->alloc,
794 rxring->dmaalloc);
795err_set_null:
796 rxring->desc = NULL;
797 rxring->dmaalloc = 0;
798 rxring->dma = 0;
799 rxring->bufinf = NULL;
800
801 return -ENOMEM;
d7699f87
GFT		 802}
803
cd0ff491 804static inline void
3bf61c55 805jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 806{
cd0ff491
GFT		 807 /*
808 * Select Queue 0
809 */
810 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
811 RXCS_QUEUESEL_Q0);
812 wmb();
813
d7699f87
GFT		 814 /*
815 * Setup RX DMA Bass Address
816 */
fa97b924 817 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 818 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 819 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 820
821 /*
b3821cc5 822 * Setup RX Descriptor Count
d7699f87 823 */
b3821cc5 824 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 825
3bf61c55 826 /*
d7699f87
GFT		 827 * Setup Unicast Filter
828 */
829 jme_set_multi(jme->dev);
830
831 /*
832 * Enable RX Engine
833 */
834 wmb();
79ce639c 835 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 836 RXCS_QUEUESEL_Q0 |
837 RXCS_ENABLE |
838 RXCS_QST);
d7699f87
GFT		 839}
840
cd0ff491 841static inline void
3bf61c55 842jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 843{
844 /*
3bf61c55 845 * Start RX Engine
4330c2f2 846 */
79ce639c 847 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 848 RXCS_QUEUESEL_Q0 |
849 RXCS_ENABLE |
850 RXCS_QST);
851}
852
cd0ff491 853static inline void
3bf61c55 854jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 855{
856 int i;
cd0ff491 857 u32 val;
d7699f87
GFT		 858
859 /*
860 * Disable RX Engine
861 */
29bdd921 862 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 863 wmb();
d7699f87
GFT		 864
865 val = jread32(jme, JME_RXCS);
cd0ff491 866 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 867 mdelay(1);
d7699f87 868 val = jread32(jme, JME_RXCS);
cd0ff491 869 rmb();
d7699f87
GFT		 870 }
871
cd0ff491
GFT		 872 if (!i)
873 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
d7699f87
GFT		 874
875}
876
192570e0 877static int
cd0ff491 878jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 879{
cd0ff491 880 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 881 return false;
882
fa97b924
GFT		 883 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
884 == RXWBFLAG_TCPON)) {
885 if (flags & RXWBFLAG_IPV4)
886 msg_rx_err(jme, "TCP Checksum error\n");
887 return false;
192570e0
GFT		 888 }
889
fa97b924
GFT		 890 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
891 == RXWBFLAG_UDPON)) {
892 if (flags & RXWBFLAG_IPV4)
893 msg_rx_err(jme, "UDP Checksum error.\n");
894 return false;
192570e0
GFT		 895 }
896
fa97b924
GFT		 897 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
898 == RXWBFLAG_IPV4)) {
cd0ff491 899 msg_rx_err(jme, "IPv4 Checksum error.\n");
fa97b924 900 return false;
192570e0
GFT		 901 }
902
903 return true;
904}
905
3bf61c55 906static void
42b1055e 907jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 908{
d7699f87 909 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 910 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 911 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 912 struct sk_buff *skb;
3bf61c55 913 int framesize;
d7699f87 914
3bf61c55
GFT		 915 rxdesc += idx;
916 rxbi += idx;
d7699f87 917
3bf61c55
GFT		 918 skb = rxbi->skb;
919 pci_dma_sync_single_for_cpu(jme->pdev,
920 rxbi->mapping,
921 rxbi->len,
922 PCI_DMA_FROMDEVICE);
923
cd0ff491 924 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 925 pci_dma_sync_single_for_device(jme->pdev,
926 rxbi->mapping,
927 rxbi->len,
928 PCI_DMA_FROMDEVICE);
929
930 ++(NET_STAT(jme).rx_dropped);
cd0ff491 931 } else {
3bf61c55
GFT		 932 framesize = le16_to_cpu(rxdesc->descwb.framesize)
933 - RX_PREPAD_SIZE;
934
935 skb_reserve(skb, RX_PREPAD_SIZE);
936 skb_put(skb, framesize);
937 skb->protocol = eth_type_trans(skb, jme->dev);
938
94c5ea02 939 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 940 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921
GFT		 941 else
942 skb->ip_summed = CHECKSUM_NONE;
8c198884 943
94c5ea02 944 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 945 if (jme->vlgrp) {
cdcdc9eb 946 jme->jme_vlan_rx(skb, jme->vlgrp,
94c5ea02 947 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5
GFT		 948 NET_STAT(jme).rx_bytes += 4;
949 }
cd0ff491 950 } else {
cdcdc9eb 951 jme->jme_rx(skb);
b3821cc5 952 }
3bf61c55 953
94c5ea02
GFT		 954 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
955 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 956 ++(NET_STAT(jme).multicast);
957
3bf61c55
GFT		 958 NET_STAT(jme).rx_bytes += framesize;
959 ++(NET_STAT(jme).rx_packets);
960 }
961
962 jme_set_clean_rxdesc(jme, idx);
963
964}
965
966static int
967jme_process_receive(struct jme_adapter *jme, int limit)
968{
969 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 970 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 971 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 972
cd0ff491 973 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 974 goto out_inc;
975
cd0ff491 976 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 977 goto out_inc;
978
cd0ff491 979 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 980 goto out_inc;
981
cdcdc9eb 982 i = atomic_read(&rxring->next_to_clean);
fa97b924 983 while (limit > 0) {
3bf61c55
GFT		 984 rxdesc = rxring->desc;
985 rxdesc += i;
986
94c5ea02 987 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 988 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
989 goto out;
fa97b924 990 --limit;
d7699f87 991
4330c2f2
GFT		 992 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
993
cd0ff491 994 if (unlikely(desccnt > 1 ||
192570e0 995 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 996
cd0ff491 997 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 998 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 999 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1000 ++(NET_STAT(jme).rx_fifo_errors);
1001 else
1002 ++(NET_STAT(jme).rx_errors);
4330c2f2 1003
cd0ff491 1004 if (desccnt > 1)
3bf61c55 1005 limit -= desccnt - 1;
4330c2f2 1006
cd0ff491 1007 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1008 jme_set_clean_rxdesc(jme, j);
b3821cc5 1009 j = (j + 1) & (mask);
4330c2f2 1010 }
3bf61c55 1011
cd0ff491 1012 } else {
42b1055e 1013 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1014 }
4330c2f2 1015
b3821cc5 1016 i = (i + desccnt) & (mask);
3bf61c55 1017 }
4330c2f2 1018
3bf61c55 1019out:
cdcdc9eb 1020 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1021
192570e0
GFT		 1022out_inc:
1023 atomic_inc(&jme->rx_cleaning);
1024
3bf61c55 1025 return limit > 0 ? limit : 0;
4330c2f2 1026
3bf61c55 1027}
d7699f87 1028
79ce639c
GFT		 1029static void
1030jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1031{
cd0ff491 1032 if (likely(atmp == dpi->cur)) {
192570e0 1033 dpi->cnt = 0;
79ce639c 1034 return;
192570e0 1035 }
79ce639c 1036
cd0ff491 1037 if (dpi->attempt == atmp) {
79ce639c 1038 ++(dpi->cnt);
cd0ff491 1039 } else {
79ce639c
GFT		 1040 dpi->attempt = atmp;
1041 dpi->cnt = 0;
1042 }
1043
1044}
1045
1046static void
1047jme_dynamic_pcc(struct jme_adapter *jme)
1048{
1049 register struct dynpcc_info *dpi = &(jme->dpi);
1050
cd0ff491 1051 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1052 jme_attempt_pcc(dpi, PCC_P3);
cd0ff491 1053 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
79ce639c
GFT		 1054 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1055 jme_attempt_pcc(dpi, PCC_P2);
1056 else
1057 jme_attempt_pcc(dpi, PCC_P1);
1058
cd0ff491
GFT		 1059 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1060 if (dpi->attempt < dpi->cur)
1061 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1062 jme_set_rx_pcc(jme, dpi->attempt);
1063 dpi->cur = dpi->attempt;
1064 dpi->cnt = 0;
1065 }
1066}
1067
1068static void
1069jme_start_pcc_timer(struct jme_adapter *jme)
1070{
1071 struct dynpcc_info *dpi = &(jme->dpi);
1072 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1073 dpi->last_pkts = NET_STAT(jme).rx_packets;
1074 dpi->intr_cnt = 0;
1075 jwrite32(jme, JME_TMCSR,
1076 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1077}
1078
cd0ff491 1079static inline void
29bdd921
GFT		 1080jme_stop_pcc_timer(struct jme_adapter *jme)
1081{
1082 jwrite32(jme, JME_TMCSR, 0);
1083}
1084
cd0ff491
GFT		 1085static void
1086jme_shutdown_nic(struct jme_adapter *jme)
1087{
1088 u32 phylink;
1089
1090 phylink = jme_linkstat_from_phy(jme);
1091
1092 if (!(phylink & PHY_LINK_UP)) {
1093 /*
1094 * Disable all interrupt before issue timer
1095 */
1096 jme_stop_irq(jme);
1097 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1098 }
1099}
1100
79ce639c
GFT		 1101static void
1102jme_pcc_tasklet(unsigned long arg)
1103{
cd0ff491 1104 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1105 struct net_device *netdev = jme->dev;
1106
cd0ff491
GFT		 1107 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1108 jme_shutdown_nic(jme);
1109 return;
1110 }
29bdd921 1111
cd0ff491 1112 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1113 (atomic_read(&jme->link_changing) != 1)
1114 )) {
1115 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1116 return;
1117 }
29bdd921 1118
cd0ff491 1119 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1120 jme_dynamic_pcc(jme);
1121
79ce639c
GFT		 1122 jme_start_pcc_timer(jme);
1123}
1124
cd0ff491 1125static inline void
192570e0
GFT		 1126jme_polling_mode(struct jme_adapter *jme)
1127{
1128 jme_set_rx_pcc(jme, PCC_OFF);
1129}
1130
cd0ff491 1131static inline void
192570e0
GFT		 1132jme_interrupt_mode(struct jme_adapter *jme)
1133{
1134 jme_set_rx_pcc(jme, PCC_P1);
1135}
1136
cd0ff491
GFT		 1137static inline int
1138jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1139{
1140 u32 apmc;
1141 apmc = jread32(jme, JME_APMC);
1142 return apmc & JME_APMC_PSEUDO_HP_EN;
1143}
1144
1145static void
1146jme_start_shutdown_timer(struct jme_adapter *jme)
1147{
1148 u32 apmc;
1149
1150 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1151 apmc &= ~JME_APMC_EPIEN_CTRL;
1152 if (!no_extplug) {
1153 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1154 wmb();
1155 }
1156 jwrite32f(jme, JME_APMC, apmc);
1157
1158 jwrite32f(jme, JME_TIMER2, 0);
1159 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1160 jwrite32(jme, JME_TMCSR,
1161 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1162}
1163
1164static void
1165jme_stop_shutdown_timer(struct jme_adapter *jme)
1166{
1167 u32 apmc;
1168
1169 jwrite32f(jme, JME_TMCSR, 0);
1170 jwrite32f(jme, JME_TIMER2, 0);
1171 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1172
1173 apmc = jread32(jme, JME_APMC);
1174 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1175 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1176 wmb();
1177 jwrite32f(jme, JME_APMC, apmc);
1178}
1179
3bf61c55
GFT		 1180static void
1181jme_link_change_tasklet(unsigned long arg)
1182{
cd0ff491 1183 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1184 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1185 int rc;
1186
cd0ff491
GFT		 1187 while (!atomic_dec_and_test(&jme->link_changing)) {
1188 atomic_inc(&jme->link_changing);
1189 msg_intr(jme, "Get link change lock failed.\n");
e882564f 1190 while (atomic_read(&jme->link_changing) != 1)
cd0ff491
GFT		 1191 msg_intr(jme, "Waiting link change lock.\n");
1192 }
fcf45b4c 1193
cd0ff491 1194 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1195 goto out;
1196
29bdd921 1197 jme->old_mtu = netdev->mtu;
fcf45b4c 1198 netif_stop_queue(netdev);
cd0ff491
GFT		 1199 if (jme_pseudo_hotplug_enabled(jme))
1200 jme_stop_shutdown_timer(jme);
1201
1202 jme_stop_pcc_timer(jme);
1203 tasklet_disable(&jme->txclean_task);
1204 tasklet_disable(&jme->rxclean_task);
1205 tasklet_disable(&jme->rxempty_task);
1206
1207 if (netif_carrier_ok(netdev)) {
1208 jme_reset_ghc_speed(jme);
1209 jme_disable_rx_engine(jme);
1210 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1211 jme_reset_mac_processor(jme);
1212 jme_free_rx_resources(jme);
1213 jme_free_tx_resources(jme);
192570e0 1214
cd0ff491 1215 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1216 jme_polling_mode(jme);
cd0ff491
GFT		 1217
1218 netif_carrier_off(netdev);
fcf45b4c
GFT		 1219 }
1220
1221 jme_check_link(netdev, 0);
cd0ff491 1222 if (netif_carrier_ok(netdev)) {
fcf45b4c 1223 rc = jme_setup_rx_resources(jme);
cd0ff491
GFT		 1224 if (rc) {
1225 jeprintk(jme->pdev, "Allocating resources for RX error"
fcf45b4c 1226 ", Device STOPPED!\n");
cd0ff491 1227 goto out_enable_tasklet;
fcf45b4c
GFT		 1228 }
1229
fcf45b4c 1230 rc = jme_setup_tx_resources(jme);
cd0ff491
GFT		 1231 if (rc) {
1232 jeprintk(jme->pdev, "Allocating resources for TX error"
fcf45b4c
GFT		 1233 ", Device STOPPED!\n");
1234 goto err_out_free_rx_resources;
1235 }
1236
1237 jme_enable_rx_engine(jme);
1238 jme_enable_tx_engine(jme);
1239
1240 netif_start_queue(netdev);
192570e0 1241
cd0ff491 1242 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1243 jme_interrupt_mode(jme);
192570e0 1244
79ce639c 1245 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1246 } else if (jme_pseudo_hotplug_enabled(jme)) {
1247 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1248 }
1249
cd0ff491 1250 goto out_enable_tasklet;
fcf45b4c
GFT		 1251
1252err_out_free_rx_resources:
1253 jme_free_rx_resources(jme);
cd0ff491
GFT		 1254out_enable_tasklet:
1255 tasklet_enable(&jme->txclean_task);
1256 tasklet_hi_enable(&jme->rxclean_task);
1257 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1258out:
1259 atomic_inc(&jme->link_changing);
3bf61c55 1260}
d7699f87 1261
3bf61c55
GFT		 1262static void
1263jme_rx_clean_tasklet(unsigned long arg)
1264{
cd0ff491 1265 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1266 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1267
192570e0
GFT		 1268 jme_process_receive(jme, jme->rx_ring_size);
1269 ++(dpi->intr_cnt);
42b1055e 1270
192570e0 1271}
fcf45b4c 1272
192570e0 1273static int
cdcdc9eb 1274jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1275{
cdcdc9eb 1276 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1277 int rest;
fcf45b4c 1278
cdcdc9eb 1279 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1280
cd0ff491 1281 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1282 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1283 ++(NET_STAT(jme).rx_dropped);
1284 jme_restart_rx_engine(jme);
1285 }
1286 atomic_inc(&jme->rx_empty);
1287
cd0ff491 1288 if (rest) {
cdcdc9eb 1289 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1290 jme_interrupt_mode(jme);
1291 }
1292
cdcdc9eb
GFT		 1293 JME_NAPI_WEIGHT_SET(budget, rest);
1294 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1295}
1296
1297static void
1298jme_rx_empty_tasklet(unsigned long arg)
1299{
cd0ff491 1300 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1301
cd0ff491 1302 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1303 return;
1304
cd0ff491 1305 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1306 return;
1307
cd0ff491 1308 msg_rx_status(jme, "RX Queue Full!\n");
29bdd921 1309
fcf45b4c 1310 jme_rx_clean_tasklet(arg);
cdcdc9eb 1311
cd0ff491 1312 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1313 atomic_dec(&jme->rx_empty);
1314 ++(NET_STAT(jme).rx_dropped);
1315 jme_restart_rx_engine(jme);
1316 }
1317 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1318}
1319
b3821cc5
GFT		 1320static void
1321jme_wake_queue_if_stopped(struct jme_adapter *jme)
1322{
fa97b924 1323 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1324
1325 smp_wmb();
cd0ff491 1326 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1327 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
cd0ff491 1328 msg_tx_done(jme, "TX Queue Waked.\n");
b3821cc5 1329 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1330 }
1331
1332}
1333
3bf61c55
GFT		 1334static void
1335jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1336{
cd0ff491 1337 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1338 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1339 struct txdesc *txdesc = txring->desc;
3bf61c55 1340 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1341 int i, j, cnt = 0, max, err, mask;
3bf61c55 1342
cd0ff491
GFT		 1343 tx_dbg(jme, "Into txclean.\n");
1344
1345 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1346 goto out;
1347
cd0ff491 1348 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1349 goto out;
1350
cd0ff491 1351 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1352 goto out;
1353
b3821cc5
GFT		 1354 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1355 mask = jme->tx_ring_mask;
3bf61c55 1356
cd0ff491 1357 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1358
1359 ctxbi = txbi + i;
1360
cd0ff491 1361 if (likely(ctxbi->skb &&
b3821cc5 1362 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1363
cd0ff491
GFT		 1364 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1365 i, ctxbi->nr_desc, jiffies);
3bf61c55 1366
cd0ff491 1367 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1368
cd0ff491 1369 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1370 ttxbi = txbi + ((i + j) & (mask));
1371 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1372
b3821cc5 1373 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1374 ttxbi->mapping,
1375 ttxbi->len,
1376 PCI_DMA_TODEVICE);
1377
3bf61c55
GFT		 1378 ttxbi->mapping = 0;
1379 ttxbi->len = 0;
1380 }
1381
1382 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1383
1384 cnt += ctxbi->nr_desc;
1385
cd0ff491 1386 if (unlikely(err)) {
8c198884 1387 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1388 } else {
8c198884 1389 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1390 NET_STAT(jme).tx_bytes += ctxbi->len;
1391 }
1392
1393 ctxbi->skb = NULL;
1394 ctxbi->len = 0;
cdcdc9eb 1395 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1396
1397 } else {
3bf61c55
GFT		 1398 break;
1399 }
1400
b3821cc5 1401 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1402
1403 ctxbi->nr_desc = 0;
d7699f87
GFT		 1404 }
1405
cd0ff491 1406 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
cdcdc9eb 1407 atomic_set(&txring->next_to_clean, i);
79ce639c 1408 atomic_add(cnt, &txring->nr_free);
3bf61c55 1409
b3821cc5
GFT		 1410 jme_wake_queue_if_stopped(jme);
1411
fcf45b4c
GFT		 1412out:
1413 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1414}
1415
79ce639c 1416static void
cd0ff491 1417jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1418{
3bf61c55
GFT		 1419 /*
1420 * Disable interrupt
1421 */
1422 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1423
cd0ff491 1424 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1425 /*
1426 * Link change event is critical
1427 * all other events are ignored
1428 */
1429 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1430 tasklet_schedule(&jme->linkch_task);
29bdd921 1431 goto out_reenable;
fcf45b4c 1432 }
d7699f87 1433
cd0ff491 1434 if (intrstat & INTR_TMINTR) {
47220951 1435 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1436 tasklet_schedule(&jme->pcc_task);
47220951 1437 }
79ce639c 1438
cd0ff491 1439 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1440 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1441 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1442 }
1443
cd0ff491 1444 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1445 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1446 INTR_PCCRX0 |
1447 INTR_RX0EMP)) |
1448 INTR_RX0);
1449 }
d7699f87 1450
cd0ff491
GFT		 1451 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1452 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1453 atomic_inc(&jme->rx_empty);
1454
cd0ff491
GFT		 1455 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1456 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1457 jme_polling_mode(jme);
cdcdc9eb 1458 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1459 }
1460 }
cd0ff491
GFT		 1461 } else {
1462 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1463 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1464 tasklet_hi_schedule(&jme->rxempty_task);
1465 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1466 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1467 }
4330c2f2 1468 }
d7699f87 1469
29bdd921 1470out_reenable:
3bf61c55 1471 /*
fcf45b4c 1472 * Re-enable interrupt
3bf61c55 1473 */
fcf45b4c 1474 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1475}
1476
1477static irqreturn_t
1478jme_intr(int irq, void *dev_id)
1479{
cd0ff491
GFT		 1480 struct net_device *netdev = dev_id;
1481 struct jme_adapter *jme = netdev_priv(netdev);
1482 u32 intrstat;
79ce639c
GFT		 1483
1484 intrstat = jread32(jme, JME_IEVE);
1485
1486 /*
1487 * Check if it's really an interrupt for us
1488 */
9b9d55de 1489 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1490 return IRQ_NONE;
79ce639c
GFT		 1491
1492 /*
1493 * Check if the device still exist
1494 */
cd0ff491
GFT		 1495 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1496 return IRQ_NONE;
79ce639c
GFT		 1497
1498 jme_intr_msi(jme, intrstat);
1499
cd0ff491 1500 return IRQ_HANDLED;
d7699f87
GFT		 1501}
1502
79ce639c
GFT		 1503static irqreturn_t
1504jme_msi(int irq, void *dev_id)
1505{
cd0ff491
GFT		 1506 struct net_device *netdev = dev_id;
1507 struct jme_adapter *jme = netdev_priv(netdev);
1508 u32 intrstat;
79ce639c 1509
fa97b924 1510 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1511
1512 jme_intr_msi(jme, intrstat);
1513
cd0ff491 1514 return IRQ_HANDLED;
79ce639c
GFT		 1515}
1516
79ce639c
GFT		 1517static void
1518jme_reset_link(struct jme_adapter *jme)
1519{
1520 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1521}
1522
fcf45b4c
GFT		 1523static void
1524jme_restart_an(struct jme_adapter *jme)
1525{
cd0ff491 1526 u32 bmcr;
fcf45b4c 1527
cd0ff491 1528 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1529 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1530 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1531 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1532 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1533}
1534
1535static int
1536jme_request_irq(struct jme_adapter *jme)
1537{
1538 int rc;
cd0ff491
GFT		 1539 struct net_device *netdev = jme->dev;
1540 irq_handler_t handler = jme_intr;
1541 int irq_flags = IRQF_SHARED;
1542
1543 if (!pci_enable_msi(jme->pdev)) {
1544 set_bit(JME_FLAG_MSI, &jme->flags);
1545 handler = jme_msi;
1546 irq_flags = 0;
1547 }
1548
1549 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1550 netdev);
1551 if (rc) {
1552 jeprintk(jme->pdev,
b3821cc5 1553 "Unable to request %s interrupt (return: %d)\n",
cd0ff491
GFT		 1554 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1555 rc);
79ce639c 1556
cd0ff491
GFT		 1557 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1558 pci_disable_msi(jme->pdev);
1559 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1560 }
cd0ff491 1561 } else {
79ce639c
GFT		 1562 netdev->irq = jme->pdev->irq;
1563 }
1564
cd0ff491 1565 return rc;
79ce639c
GFT		 1566}
1567
1568static void
1569jme_free_irq(struct jme_adapter *jme)
1570{
cd0ff491
GFT		 1571 free_irq(jme->pdev->irq, jme->dev);
1572 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1573 pci_disable_msi(jme->pdev);
1574 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1575 jme->dev->irq = jme->pdev->irq;
cd0ff491 1576 }
fcf45b4c
GFT		 1577}
1578
3bf61c55
GFT		 1579static int
1580jme_open(struct net_device *netdev)
d7699f87
GFT		 1581{
1582 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1583 int rc;
79ce639c 1584
42b1055e 1585 jme_clear_pm(jme);
cdcdc9eb 1586 JME_NAPI_ENABLE(jme);
d7699f87 1587
fa97b924 1588 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1589 tasklet_enable(&jme->txclean_task);
1590 tasklet_hi_enable(&jme->rxclean_task);
1591 tasklet_hi_enable(&jme->rxempty_task);
1592
79ce639c 1593 rc = jme_request_irq(jme);
cd0ff491 1594 if (rc)
4330c2f2 1595 goto err_out;
79ce639c 1596
d7699f87 1597 jme_start_irq(jme);
42b1055e 1598
cd0ff491 1599 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e
GFT		 1600 jme_set_settings(netdev, &jme->old_ecmd);
1601 else
1602 jme_reset_phy_processor(jme);
1603
29bdd921 1604 jme_reset_link(jme);
d7699f87
GFT		 1605
1606 return 0;
1607
d7699f87
GFT		 1608err_out:
1609 netif_stop_queue(netdev);
1610 netif_carrier_off(netdev);
4330c2f2 1611 return rc;
d7699f87
GFT		 1612}
1613
9b9d55de 1614#ifdef CONFIG_PM
42b1055e
GFT		 1615static void
1616jme_set_100m_half(struct jme_adapter *jme)
1617{
cd0ff491 1618 u32 bmcr, tmp;
42b1055e
GFT		 1619
1620 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1621 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1622 BMCR_SPEED1000 | BMCR_FULLDPLX);
1623 tmp |= BMCR_SPEED100;
1624
1625 if (bmcr != tmp)
1626 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1627
cd0ff491 1628 if (jme->fpgaver)
cdcdc9eb
GFT		 1629 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1630 else
1631 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1632}
1633
47220951
GFT		 1634#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1635static void
1636jme_wait_link(struct jme_adapter *jme)
1637{
cd0ff491 1638 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1639
1640 mdelay(1000);
1641 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1642 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1643 mdelay(10);
1644 phylink = jme_linkstat_from_phy(jme);
1645 }
1646}
9b9d55de 1647#endif
47220951 1648
cd0ff491 1649static inline void
42b1055e
GFT		 1650jme_phy_off(struct jme_adapter *jme)
1651{
1652 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1653}
1654
3bf61c55
GFT		 1655static int
1656jme_close(struct net_device *netdev)
d7699f87
GFT		 1657{
1658 struct jme_adapter *jme = netdev_priv(netdev);
1659
1660 netif_stop_queue(netdev);
1661 netif_carrier_off(netdev);
1662
1663 jme_stop_irq(jme);
79ce639c 1664 jme_free_irq(jme);
d7699f87 1665
cdcdc9eb 1666 JME_NAPI_DISABLE(jme);
192570e0 1667
fa97b924
GFT		 1668 tasklet_disable(&jme->linkch_task);
1669 tasklet_disable(&jme->txclean_task);
1670 tasklet_disable(&jme->rxclean_task);
1671 tasklet_disable(&jme->rxempty_task);
8c198884 1672
cd0ff491
GFT		 1673 jme_reset_ghc_speed(jme);
1674 jme_disable_rx_engine(jme);
1675 jme_disable_tx_engine(jme);
8c198884 1676 jme_reset_mac_processor(jme);
d7699f87
GFT		 1677 jme_free_rx_resources(jme);
1678 jme_free_tx_resources(jme);
42b1055e 1679 jme->phylink = 0;
b3821cc5
GFT		 1680 jme_phy_off(jme);
1681
1682 return 0;
1683}
1684
1685static int
1686jme_alloc_txdesc(struct jme_adapter *jme,
1687 struct sk_buff *skb)
1688{
fa97b924 1689 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1690 int idx, nr_alloc, mask = jme->tx_ring_mask;
1691
1692 idx = txring->next_to_use;
1693 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1694
cd0ff491 1695 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1696 return -1;
1697
1698 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1699
b3821cc5
GFT		 1700 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1701
1702 return idx;
1703}
1704
1705static void
1706jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1707 struct txdesc *txdesc,
b3821cc5
GFT		 1708 struct jme_buffer_info *txbi,
1709 struct page *page,
cd0ff491
GFT		 1710 u32 page_offset,
1711 u32 len,
1712 u8 hidma)
b3821cc5
GFT		 1713{
1714 dma_addr_t dmaaddr;
1715
1716 dmaaddr = pci_map_page(pdev,
1717 page,
1718 page_offset,
1719 len,
1720 PCI_DMA_TODEVICE);
1721
1722 pci_dma_sync_single_for_device(pdev,
1723 dmaaddr,
1724 len,
1725 PCI_DMA_TODEVICE);
1726
1727 txdesc->dw[0] = 0;
1728 txdesc->dw[1] = 0;
1729 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1730 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1731 txdesc->desc2.datalen = cpu_to_le16(len);
1732 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1733 txdesc->desc2.bufaddrl = cpu_to_le32(
1734 (__u64)dmaaddr & 0xFFFFFFFFUL);
1735
1736 txbi->mapping = dmaaddr;
1737 txbi->len = len;
1738}
1739
1740static void
1741jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1742{
fa97b924 1743 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1744 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1745 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1746 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1747 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1748 int mask = jme->tx_ring_mask;
1749 struct skb_frag_struct *frag;
cd0ff491 1750 u32 len;
b3821cc5 1751
cd0ff491
GFT		 1752 for (i = 0 ; i < nr_frags ; ++i) {
1753 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1754 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1755 ctxbi = txbi + ((idx + i + 2) & (mask));
1756
1757 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1758 frag->page_offset, frag->size, hidma);
42b1055e 1759 }
b3821cc5 1760
cd0ff491 1761 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 1762 ctxdesc = txdesc + ((idx + 1) & (mask));
1763 ctxbi = txbi + ((idx + 1) & (mask));
1764 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1765 offset_in_page(skb->data), len, hidma);
1766
1767}
1768
1769static int
1770jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1771{
cd0ff491 1772 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT		 1773 skb_header_cloned(skb) &&
1774 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1775 dev_kfree_skb(skb);
1776 return -1;
1777 }
1778
1779 return 0;
1780}
1781
1782static int
94c5ea02 1783jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1784{
94c5ea02 1785 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1786 if (*mss) {
b3821cc5
GFT		 1787 *flags |= TXFLAG_LSEN;
1788
cd0ff491 1789 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 1790 struct iphdr *iph = ip_hdr(skb);
1791
1792 iph->check = 0;
cd0ff491 1793 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 1794 iph->daddr, 0,
1795 IPPROTO_TCP,
1796 0);
cd0ff491 1797 } else {
b3821cc5
GFT		 1798 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1799
cd0ff491 1800 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 1801 &ip6h->daddr, 0,
1802 IPPROTO_TCP,
1803 0);
1804 }
1805
1806 return 0;
1807 }
1808
1809 return 1;
1810}
1811
1812static void
cd0ff491 1813jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1814{
cd0ff491
GFT		 1815 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1816 u8 ip_proto;
b3821cc5
GFT		 1817
1818 switch (skb->protocol) {
cd0ff491 1819 case htons(ETH_P_IP):
b3821cc5
GFT		 1820 ip_proto = ip_hdr(skb)->protocol;
1821 break;
cd0ff491 1822 case htons(ETH_P_IPV6):
b3821cc5
GFT		 1823 ip_proto = ipv6_hdr(skb)->nexthdr;
1824 break;
1825 default:
1826 ip_proto = 0;
1827 break;
1828 }
1829
cd0ff491 1830 switch (ip_proto) {
b3821cc5
GFT		 1831 case IPPROTO_TCP:
1832 *flags |= TXFLAG_TCPCS;
1833 break;
1834 case IPPROTO_UDP:
1835 *flags |= TXFLAG_UDPCS;
1836 break;
1837 default:
cd0ff491 1838 msg_tx_err(jme, "Error upper layer protocol.\n");
b3821cc5
GFT		 1839 break;
1840 }
1841 }
1842}
1843
cd0ff491 1844static inline void
94c5ea02 1845jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 1846{
cd0ff491 1847 if (vlan_tx_tag_present(skb)) {
b3821cc5 1848 *flags |= TXFLAG_TAGON;
94c5ea02 1849 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 1850 }
b3821cc5
GFT		 1851}
1852
1853static int
94c5ea02 1854jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 1855{
fa97b924 1856 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1857 struct txdesc *txdesc;
b3821cc5 1858 struct jme_buffer_info *txbi;
cd0ff491 1859 u8 flags;
b3821cc5 1860
cd0ff491 1861 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 1862 txbi = txring->bufinf + idx;
1863
1864 txdesc->dw[0] = 0;
1865 txdesc->dw[1] = 0;
1866 txdesc->dw[2] = 0;
1867 txdesc->dw[3] = 0;
1868 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1869 /*
1870 * Set OWN bit at final.
1871 * When kernel transmit faster than NIC.
1872 * And NIC trying to send this descriptor before we tell
1873 * it to start sending this TX queue.
1874 * Other fields are already filled correctly.
1875 */
1876 wmb();
1877 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 1878 /*
1879 * Set checksum flags while not tso
1880 */
1881 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1882 jme_tx_csum(jme, skb, &flags);
b3821cc5 1883 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 1884 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 1885 txdesc->desc1.flags = flags;
1886 /*
1887 * Set tx buffer info after telling NIC to send
1888 * For better tx_clean timing
1889 */
1890 wmb();
1891 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1892 txbi->skb = skb;
1893 txbi->len = skb->len;
cd0ff491
GFT		 1894 txbi->start_xmit = jiffies;
1895 if (!txbi->start_xmit)
8d27293f 1896 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 1897
1898 return 0;
1899}
1900
b3821cc5
GFT		 1901static void
1902jme_stop_queue_if_full(struct jme_adapter *jme)
1903{
fa97b924 1904 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 1905 struct jme_buffer_info *txbi = txring->bufinf;
1906 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 1907
cd0ff491 1908 txbi += idx;
b3821cc5
GFT		 1909
1910 smp_wmb();
cd0ff491 1911 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 1912 netif_stop_queue(jme->dev);
cd0ff491 1913 msg_tx_queued(jme, "TX Queue Paused.\n");
b3821cc5 1914 smp_wmb();
cd0ff491
GFT		 1915 if (atomic_read(&txring->nr_free)
1916 >= (jme->tx_wake_threshold)) {
b3821cc5 1917 netif_wake_queue(jme->dev);
cd0ff491 1918 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
b3821cc5
GFT		 1919 }
1920 }
1921
cd0ff491 1922 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 1923 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1924 txbi->skb)) {
1925 netif_stop_queue(jme->dev);
cd0ff491 1926 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
cdcdc9eb 1927 }
b3821cc5
GFT		 1928}
1929
3bf61c55
GFT		 1930/*
1931 * This function is already protected by netif_tx_lock()
1932 */
cd0ff491 1933
3bf61c55
GFT		 1934static int
1935jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 1936{
cd0ff491 1937 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 1938 int idx;
d7699f87 1939
cd0ff491 1940 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 1941 ++(NET_STAT(jme).tx_dropped);
1942 return NETDEV_TX_OK;
1943 }
1944
1945 idx = jme_alloc_txdesc(jme, skb);
79ce639c 1946
cd0ff491 1947 if (unlikely(idx < 0)) {
b3821cc5 1948 netif_stop_queue(netdev);
cd0ff491 1949 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
d7699f87 1950
cd0ff491 1951 return NETDEV_TX_BUSY;
b3821cc5
GFT		 1952 }
1953
94c5ea02 1954 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 1955
4330c2f2
GFT		 1956 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1957 TXCS_SELECT_QUEUE0 |
1958 TXCS_QUEUE0S |
1959 TXCS_ENABLE);
d7699f87 1960
cd0ff491
GFT		 1961 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1962 skb_shinfo(skb)->nr_frags + 2,
1963 jiffies);
b3821cc5
GFT		 1964 jme_stop_queue_if_full(jme);
1965
cd0ff491 1966 return NETDEV_TX_OK;
d7699f87
GFT		 1967}
1968
3bf61c55
GFT		 1969static int
1970jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 1971{
cd0ff491 1972 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1973 struct sockaddr *addr = p;
cd0ff491 1974 u32 val;
d7699f87 1975
cd0ff491 1976 if (netif_running(netdev))
d7699f87
GFT		 1977 return -EBUSY;
1978
cd0ff491 1979 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT		 1980 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1981
186fc259
GFT		 1982 val = (addr->sa_data[3] & 0xff) << 24 |
1983 (addr->sa_data[2] & 0xff) << 16 |
1984 (addr->sa_data[1] & 0xff) << 8 |
1985 (addr->sa_data[0] & 0xff);
4330c2f2 1986 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT		 1987 val = (addr->sa_data[5] & 0xff) << 8 |
1988 (addr->sa_data[4] & 0xff);
4330c2f2 1989 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 1990 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 1991
1992 return 0;
1993}
1994
3bf61c55
GFT		 1995static void
1996jme_set_multi(struct net_device *netdev)
d7699f87 1997{
3bf61c55 1998 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1999 u32 mc_hash[2] = {};
d7699f87
GFT		 2000 int i;
2001
cd0ff491 2002 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2003
2004 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2005
cd0ff491 2006 if (netdev->flags & IFF_PROMISC) {
8c198884 2007 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2008 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2009 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2010 } else if (netdev->flags & IFF_MULTICAST) {
3bf61c55
GFT		 2011 struct dev_mc_list *mclist;
2012 int bit_nr;
d7699f87 2013
8c198884 2014 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
3bf61c55
GFT		 2015 for (i = 0, mclist = netdev->mc_list;
2016 mclist && i < netdev->mc_count;
2017 ++i, mclist = mclist->next) {
2018
cd0ff491
GFT		 2019 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2020 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2021 }
d7699f87 2022
4330c2f2
GFT		 2023 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2024 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2025 }
2026
d7699f87 2027 wmb();
8c198884
GFT		 2028 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2029
cd0ff491 2030 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2031}
2032
3bf61c55 2033static int
8c198884 2034jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2035{
cd0ff491 2036 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2037
cd0ff491 2038 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2039 return 0;
2040
cd0ff491
GFT		 2041 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2042 ((new_mtu) < IPV6_MIN_MTU))
2043 return -EINVAL;
79ce639c 2044
cd0ff491 2045 if (new_mtu > 4000) {
79ce639c
GFT		 2046 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2047 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2048 jme_restart_rx_engine(jme);
cd0ff491 2049 } else {
79ce639c
GFT		 2050 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2051 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2052 jme_restart_rx_engine(jme);
2053 }
2054
cd0ff491 2055 if (new_mtu > 1900) {
b3821cc5
GFT		 2056 netdev->features &= ~(NETIF_F_HW_CSUM |
2057 NETIF_F_TSO |
2058 NETIF_F_TSO6);
cd0ff491
GFT		 2059 } else {
2060 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
b3821cc5 2061 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491 2062 if (test_bit(JME_FLAG_TSO, &jme->flags))
b3821cc5 2063 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT		 2064 }
2065
cd0ff491
GFT		 2066 netdev->mtu = new_mtu;
2067 jme_reset_link(jme);
79ce639c
GFT		 2068
2069 return 0;
d7699f87
GFT		 2070}
2071
8c198884
GFT		 2072static void
2073jme_tx_timeout(struct net_device *netdev)
2074{
cd0ff491 2075 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2076
cdcdc9eb
GFT		 2077 jme->phylink = 0;
2078 jme_reset_phy_processor(jme);
cd0ff491 2079 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2080 jme_set_settings(netdev, &jme->old_ecmd);
2081
8c198884 2082 /*
cdcdc9eb 2083 * Force to Reset the link again
8c198884 2084 */
29bdd921 2085 jme_reset_link(jme);
8c198884
GFT		 2086}
2087
42b1055e
GFT		 2088static void
2089jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2090{
2091 struct jme_adapter *jme = netdev_priv(netdev);
2092
2093 jme->vlgrp = grp;
2094}
2095
3bf61c55
GFT		 2096static void
2097jme_get_drvinfo(struct net_device *netdev,
2098 struct ethtool_drvinfo *info)
d7699f87 2099{
cd0ff491 2100 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2101
cd0ff491
GFT		 2102 strcpy(info->driver, DRV_NAME);
2103 strcpy(info->version, DRV_VERSION);
2104 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2105}
2106
8c198884
GFT		 2107static int
2108jme_get_regs_len(struct net_device *netdev)
2109{
cd0ff491 2110 return JME_REG_LEN;
8c198884
GFT		 2111}
2112
2113static void
cd0ff491 2114mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2115{
2116 int i;
2117
cd0ff491 2118 for (i = 0 ; i < len ; i += 4)
79ce639c 2119 p[i >> 2] = jread32(jme, reg + i);
186fc259 2120}
8c198884 2121
186fc259 2122static void
cd0ff491 2123mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2124{
2125 int i;
cd0ff491 2126 u16 *p16 = (u16 *)p;
186fc259 2127
cd0ff491 2128 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2129 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2130}
2131
2132static void
2133jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2134{
cd0ff491
GFT		 2135 struct jme_adapter *jme = netdev_priv(netdev);
2136 u32 *p32 = (u32 *)p;
8c198884 2137
186fc259 2138 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2139
2140 regs->version = 1;
2141 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2142
2143 p32 += 0x100 >> 2;
2144 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2145
2146 p32 += 0x100 >> 2;
2147 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2148
2149 p32 += 0x100 >> 2;
2150 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2151
186fc259
GFT		 2152 p32 += 0x100 >> 2;
2153 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2154}
2155
2156static int
2157jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2158{
2159 struct jme_adapter *jme = netdev_priv(netdev);
2160
8c198884
GFT		 2161 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2162 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2163
cd0ff491 2164 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2165 ecmd->use_adaptive_rx_coalesce = false;
2166 ecmd->rx_coalesce_usecs = 0;
2167 ecmd->rx_max_coalesced_frames = 0;
2168 return 0;
2169 }
2170
2171 ecmd->use_adaptive_rx_coalesce = true;
2172
cd0ff491 2173 switch (jme->dpi.cur) {
8c198884
GFT		 2174 case PCC_P1:
2175 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2176 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2177 break;
2178 case PCC_P2:
2179 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2180 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2181 break;
2182 case PCC_P3:
2183 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2184 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2185 break;
2186 default:
2187 break;
2188 }
2189
2190 return 0;
2191}
2192
192570e0
GFT		 2193static int
2194jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2195{
2196 struct jme_adapter *jme = netdev_priv(netdev);
2197 struct dynpcc_info *dpi = &(jme->dpi);
2198
cd0ff491 2199 if (netif_running(netdev))
cdcdc9eb
GFT		 2200 return -EBUSY;
2201
cd0ff491
GFT		 2202 if (ecmd->use_adaptive_rx_coalesce
2203 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2204 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2205 jme->jme_rx = netif_rx;
2206 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2207 dpi->cur = PCC_P1;
2208 dpi->attempt = PCC_P1;
2209 dpi->cnt = 0;
2210 jme_set_rx_pcc(jme, PCC_P1);
2211 jme_interrupt_mode(jme);
cd0ff491
GFT		 2212 } else if (!(ecmd->use_adaptive_rx_coalesce)
2213 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2214 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2215 jme->jme_rx = netif_receive_skb;
2216 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2217 jme_interrupt_mode(jme);
2218 }
2219
2220 return 0;
2221}
2222
8c198884
GFT		 2223static void
2224jme_get_pauseparam(struct net_device *netdev,
2225 struct ethtool_pauseparam *ecmd)
2226{
2227 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2228 u32 val;
8c198884
GFT		 2229
2230 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2231 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2232
cd0ff491
GFT		 2233 spin_lock_bh(&jme->phy_lock);
2234 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2235 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2236
2237 ecmd->autoneg =
2238 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2239}
2240
2241static int
2242jme_set_pauseparam(struct net_device *netdev,
2243 struct ethtool_pauseparam *ecmd)
2244{
2245 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2246 u32 val;
8c198884 2247
cd0ff491 2248 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2249 (ecmd->tx_pause != 0)) {
2250
cd0ff491 2251 if (ecmd->tx_pause)
8c198884
GFT		 2252 jme->reg_txpfc |= TXPFC_PF_EN;
2253 else
2254 jme->reg_txpfc &= ~TXPFC_PF_EN;
2255
2256 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2257 }
2258
cd0ff491
GFT		 2259 spin_lock_bh(&jme->rxmcs_lock);
2260 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2261 (ecmd->rx_pause != 0)) {
2262
cd0ff491 2263 if (ecmd->rx_pause)
8c198884
GFT		 2264 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2265 else
2266 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2267
2268 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2269 }
cd0ff491 2270 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2271
cd0ff491
GFT		 2272 spin_lock_bh(&jme->phy_lock);
2273 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2274 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2275 (ecmd->autoneg != 0)) {
2276
cd0ff491 2277 if (ecmd->autoneg)
8c198884
GFT		 2278 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2279 else
2280 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2281
b3821cc5
GFT		 2282 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2283 MII_ADVERTISE, val);
8c198884 2284 }
cd0ff491 2285 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2286
2287 return 0;
2288}
2289
29bdd921
GFT		 2290static void
2291jme_get_wol(struct net_device *netdev,
2292 struct ethtool_wolinfo *wol)
2293{
2294 struct jme_adapter *jme = netdev_priv(netdev);
2295
2296 wol->supported = WAKE_MAGIC | WAKE_PHY;
2297
2298 wol->wolopts = 0;
2299
cd0ff491 2300 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2301 wol->wolopts |= WAKE_PHY;
2302
cd0ff491 2303 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2304 wol->wolopts |= WAKE_MAGIC;
2305
2306}
2307
2308static int
2309jme_set_wol(struct net_device *netdev,
2310 struct ethtool_wolinfo *wol)
2311{
2312 struct jme_adapter *jme = netdev_priv(netdev);
2313
cd0ff491 2314 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2315 WAKE_UCAST |
2316 WAKE_MCAST |
2317 WAKE_BCAST |
2318 WAKE_ARP))
2319 return -EOPNOTSUPP;
2320
2321 jme->reg_pmcs = 0;
2322
cd0ff491 2323 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2324 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2325
cd0ff491 2326 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2327 jme->reg_pmcs |= PMCS_MFEN;
2328
cd0ff491 2329 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2330
29bdd921
GFT		 2331 return 0;
2332}
b3821cc5 2333
3bf61c55
GFT		 2334static int
2335jme_get_settings(struct net_device *netdev,
2336 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2337{
2338 struct jme_adapter *jme = netdev_priv(netdev);
2339 int rc;
8c198884 2340
cd0ff491 2341 spin_lock_bh(&jme->phy_lock);
d7699f87 2342 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2343 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2344 return rc;
2345}
2346
3bf61c55
GFT		 2347static int
2348jme_set_settings(struct net_device *netdev,
2349 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2350{
2351 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2352 int rc, fdc = 0;
fcf45b4c 2353
cd0ff491 2354 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2355 return -EINVAL;
2356
cd0ff491 2357 if (jme->mii_if.force_media &&
79ce639c
GFT		 2358 ecmd->autoneg != AUTONEG_ENABLE &&
2359 (jme->mii_if.full_duplex != ecmd->duplex))
2360 fdc = 1;
2361
cd0ff491 2362 spin_lock_bh(&jme->phy_lock);
d7699f87 2363 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2364 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2365
cd0ff491 2366 if (!rc && fdc)
79ce639c
GFT		 2367 jme_reset_link(jme);
2368
cd0ff491
GFT		 2369 if (!rc) {
2370 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2371 jme->old_ecmd = *ecmd;
2372 }
2373
d7699f87
GFT		 2374 return rc;
2375}
2376
cd0ff491 2377static u32
3bf61c55
GFT		 2378jme_get_link(struct net_device *netdev)
2379{
d7699f87
GFT		 2380 struct jme_adapter *jme = netdev_priv(netdev);
2381 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2382}
2383
8c198884 2384static u32
cd0ff491
GFT		 2385jme_get_msglevel(struct net_device *netdev)
2386{
2387 struct jme_adapter *jme = netdev_priv(netdev);
2388 return jme->msg_enable;
2389}
2390
2391static void
2392jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2393{
cd0ff491
GFT		 2394 struct jme_adapter *jme = netdev_priv(netdev);
2395 jme->msg_enable = value;
2396}
8c198884 2397
cd0ff491
GFT		 2398static u32
2399jme_get_rx_csum(struct net_device *netdev)
2400{
2401 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2402 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2403}
2404
2405static int
2406jme_set_rx_csum(struct net_device *netdev, u32 on)
2407{
cd0ff491 2408 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2409
cd0ff491
GFT		 2410 spin_lock_bh(&jme->rxmcs_lock);
2411 if (on)
8c198884
GFT		 2412 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2413 else
2414 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2415 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2416 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2417
2418 return 0;
2419}
2420
2421static int
2422jme_set_tx_csum(struct net_device *netdev, u32 on)
2423{
cd0ff491 2424 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2425
cd0ff491
GFT		 2426 if (on) {
2427 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2428 if (netdev->mtu <= 1900)
b3821cc5 2429 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491
GFT		 2430 } else {
2431 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
8c198884 2432 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2433 }
8c198884
GFT		 2434
2435 return 0;
2436}
2437
b3821cc5
GFT		 2438static int
2439jme_set_tso(struct net_device *netdev, u32 on)
2440{
cd0ff491 2441 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2442
cd0ff491
GFT		 2443 if (on) {
2444 set_bit(JME_FLAG_TSO, &jme->flags);
2445 if (netdev->mtu <= 1900)
b3821cc5 2446 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT		 2447 } else {
2448 clear_bit(JME_FLAG_TSO, &jme->flags);
2449 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT		 2450 }
2451
cd0ff491 2452 return 0;
b3821cc5
GFT		 2453}
2454
8c198884
GFT		 2455static int
2456jme_nway_reset(struct net_device *netdev)
2457{
cd0ff491 2458 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2459 jme_restart_an(jme);
2460 return 0;
2461}
2462
cd0ff491 2463static u8
186fc259
GFT		 2464jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2465{
cd0ff491 2466 u32 val;
186fc259
GFT		 2467 int to;
2468
2469 val = jread32(jme, JME_SMBCSR);
2470 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2471 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2472 msleep(1);
2473 val = jread32(jme, JME_SMBCSR);
2474 }
cd0ff491
GFT		 2475 if (!to) {
2476 msg_hw(jme, "SMB Bus Busy.\n");
186fc259
GFT		 2477 return 0xFF;
2478 }
2479
2480 jwrite32(jme, JME_SMBINTF,
2481 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2482 SMBINTF_HWRWN_READ |
2483 SMBINTF_HWCMD);
2484
2485 val = jread32(jme, JME_SMBINTF);
2486 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2487 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2488 msleep(1);
2489 val = jread32(jme, JME_SMBINTF);
2490 }
cd0ff491
GFT		 2491 if (!to) {
2492 msg_hw(jme, "SMB Bus Busy.\n");
186fc259
GFT		 2493 return 0xFF;
2494 }
2495
2496 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2497}
2498
2499static void
cd0ff491 2500jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2501{
cd0ff491 2502 u32 val;
186fc259
GFT		 2503 int to;
2504
2505 val = jread32(jme, JME_SMBCSR);
2506 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2507 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2508 msleep(1);
2509 val = jread32(jme, JME_SMBCSR);
2510 }
cd0ff491
GFT		 2511 if (!to) {
2512 msg_hw(jme, "SMB Bus Busy.\n");
186fc259
GFT		 2513 return;
2514 }
2515
2516 jwrite32(jme, JME_SMBINTF,
2517 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2518 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2519 SMBINTF_HWRWN_WRITE |
2520 SMBINTF_HWCMD);
2521
2522 val = jread32(jme, JME_SMBINTF);
2523 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2524 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2525 msleep(1);
2526 val = jread32(jme, JME_SMBINTF);
2527 }
cd0ff491
GFT		 2528 if (!to) {
2529 msg_hw(jme, "SMB Bus Busy.\n");
186fc259
GFT		 2530 return;
2531 }
2532
2533 mdelay(2);
2534}
2535
2536static int
2537jme_get_eeprom_len(struct net_device *netdev)
2538{
cd0ff491
GFT		 2539 struct jme_adapter *jme = netdev_priv(netdev);
2540 u32 val;
186fc259 2541 val = jread32(jme, JME_SMBCSR);
cd0ff491 2542 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2543}
2544
2545static int
2546jme_get_eeprom(struct net_device *netdev,
2547 struct ethtool_eeprom *eeprom, u8 *data)
2548{
cd0ff491 2549 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2550 int i, offset = eeprom->offset, len = eeprom->len;
2551
2552 /*
8d27293f 2553 * ethtool will check the boundary for us
186fc259
GFT		 2554 */
2555 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2556 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2557 data[i] = jme_smb_read(jme, i + offset);
2558
2559 return 0;
2560}
2561
2562static int
2563jme_set_eeprom(struct net_device *netdev,
2564 struct ethtool_eeprom *eeprom, u8 *data)
2565{
cd0ff491 2566 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2567 int i, offset = eeprom->offset, len = eeprom->len;
2568
2569 if (eeprom->magic != JME_EEPROM_MAGIC)
2570 return -EINVAL;
2571
2572 /*
8d27293f 2573 * ethtool will check the boundary for us
186fc259 2574 */
cd0ff491 2575 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2576 jme_smb_write(jme, i + offset, data[i]);
2577
2578 return 0;
2579}
2580
d7699f87 2581static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2582 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2583 .get_regs_len = jme_get_regs_len,
2584 .get_regs = jme_get_regs,
2585 .get_coalesce = jme_get_coalesce,
192570e0 2586 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2587 .get_pauseparam = jme_get_pauseparam,
2588 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2589 .get_wol = jme_get_wol,
2590 .set_wol = jme_set_wol,
d7699f87
GFT		 2591 .get_settings = jme_get_settings,
2592 .set_settings = jme_set_settings,
2593 .get_link = jme_get_link,
cd0ff491
GFT		 2594 .get_msglevel = jme_get_msglevel,
2595 .set_msglevel = jme_set_msglevel,
8c198884
GFT		 2596 .get_rx_csum = jme_get_rx_csum,
2597 .set_rx_csum = jme_set_rx_csum,
2598 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 2599 .set_tso = jme_set_tso,
2600 .set_sg = ethtool_op_set_sg,
8c198884 2601 .nway_reset = jme_nway_reset,
186fc259
GFT		 2602 .get_eeprom_len = jme_get_eeprom_len,
2603 .get_eeprom = jme_get_eeprom,
2604 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2605};
2606
3bf61c55
GFT		 2607static int
2608jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2609{
94c5ea02 2610 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2611 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2612 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT		 2613 return 1;
2614
94c5ea02 2615 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2616 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2617 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT		 2618 return 1;
2619
fa97b924
GFT		 2620 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2621 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT		 2622 return 0;
2623
2624 return -1;
2625}
2626
cd0ff491 2627static inline void
cdcdc9eb
GFT		 2628jme_phy_init(struct jme_adapter *jme)
2629{
cd0ff491 2630 u16 reg26;
cdcdc9eb
GFT		 2631
2632 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2633 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2634}
2635
cd0ff491 2636static inline void
cdcdc9eb 2637jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2638{
cd0ff491 2639 u32 chipmode;
cdcdc9eb
GFT		 2640
2641 chipmode = jread32(jme, JME_CHIPMODE);
2642
2643 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2644 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
42b1055e
GFT		 2645}
2646
94c5ea02
GFT		 2647static const struct net_device_ops jme_netdev_ops = {
2648 .ndo_open = jme_open,
2649 .ndo_stop = jme_close,
2650 .ndo_validate_addr = eth_validate_addr,
2651 .ndo_start_xmit = jme_start_xmit,
2652 .ndo_set_mac_address = jme_set_macaddr,
2653 .ndo_set_multicast_list = jme_set_multi,
2654 .ndo_change_mtu = jme_change_mtu,
2655 .ndo_tx_timeout = jme_tx_timeout,
2656 .ndo_vlan_rx_register = jme_vlan_rx_register,
2657};
2658
3bf61c55
GFT		 2659static int __devinit
2660jme_init_one(struct pci_dev *pdev,
2661 const struct pci_device_id *ent)
2662{
cdcdc9eb 2663 int rc = 0, using_dac, i;
d7699f87
GFT		 2664 struct net_device *netdev;
2665 struct jme_adapter *jme;
cd0ff491
GFT		 2666 u16 bmcr, bmsr;
2667 u32 apmc;
d7699f87
GFT		 2668
2669 /*
2670 * set up PCI device basics
2671 */
4330c2f2 2672 rc = pci_enable_device(pdev);
cd0ff491
GFT		 2673 if (rc) {
2674 jeprintk(pdev, "Cannot enable PCI device.\n");
4330c2f2
GFT		 2675 goto err_out;
2676 }
d7699f87 2677
3bf61c55 2678 using_dac = jme_pci_dma64(pdev);
cd0ff491
GFT		 2679 if (using_dac < 0) {
2680 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
3bf61c55
GFT		 2681 rc = -EIO;
2682 goto err_out_disable_pdev;
2683 }
2684
cd0ff491
GFT		 2685 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2686 jeprintk(pdev, "No PCI resource region found.\n");
4330c2f2
GFT		 2687 rc = -ENOMEM;
2688 goto err_out_disable_pdev;
2689 }
d7699f87 2690
4330c2f2 2691 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491
GFT		 2692 if (rc) {
2693 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
4330c2f2
GFT		 2694 goto err_out_disable_pdev;
2695 }
d7699f87
GFT		 2696
2697 pci_set_master(pdev);
2698
2699 /*
2700 * alloc and init net device
2701 */
3bf61c55 2702 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491
GFT		 2703 if (!netdev) {
2704 jeprintk(pdev, "Cannot allocate netdev structure.\n");
4330c2f2
GFT		 2705 rc = -ENOMEM;
2706 goto err_out_release_regions;
d7699f87 2707 }
94c5ea02 2708 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2709 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2710 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2711 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT		 2712 NETIF_F_SG |
2713 NETIF_F_TSO |
2714 NETIF_F_TSO6 |
42b1055e
GFT		 2715 NETIF_F_HW_VLAN_TX |
2716 NETIF_F_HW_VLAN_RX;
cd0ff491 2717 if (using_dac)
8c198884 2718 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 2719
2720 SET_NETDEV_DEV(netdev, &pdev->dev);
2721 pci_set_drvdata(pdev, netdev);
2722
2723 /*
2724 * init adapter info
2725 */
2726 jme = netdev_priv(netdev);
2727 jme->pdev = pdev;
2728 jme->dev = netdev;
cdcdc9eb
GFT		 2729 jme->jme_rx = netif_rx;
2730 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2731 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2732 jme->phylink = 0;
b3821cc5
GFT		 2733 jme->tx_ring_size = 1 << 10;
2734 jme->tx_ring_mask = jme->tx_ring_size - 1;
2735 jme->tx_wake_threshold = 1 << 9;
2736 jme->rx_ring_size = 1 << 9;
2737 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2738 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 2739 jme->regs = ioremap(pci_resource_start(pdev, 0),
2740 pci_resource_len(pdev, 0));
4330c2f2 2741 if (!(jme->regs)) {
cd0ff491 2742 jeprintk(pdev, "Mapping PCI resource region error.\n");
d7699f87
GFT		 2743 rc = -ENOMEM;
2744 goto err_out_free_netdev;
2745 }
4330c2f2 2746
cd0ff491
GFT		 2747 if (no_pseudohp) {
2748 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2749 jwrite32(jme, JME_APMC, apmc);
2750 } else if (force_pseudohp) {
2751 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2752 jwrite32(jme, JME_APMC, apmc);
2753 }
2754
cdcdc9eb 2755 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2756
d7699f87 2757 spin_lock_init(&jme->phy_lock);
fcf45b4c 2758 spin_lock_init(&jme->macaddr_lock);
8c198884 2759 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2760
fcf45b4c
GFT		 2761 atomic_set(&jme->link_changing, 1);
2762 atomic_set(&jme->rx_cleaning, 1);
2763 atomic_set(&jme->tx_cleaning, 1);
192570e0 2764 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2765
79ce639c
GFT		 2766 tasklet_init(&jme->pcc_task,
2767 &jme_pcc_tasklet,
2768 (unsigned long) jme);
4330c2f2
GFT		 2769 tasklet_init(&jme->linkch_task,
2770 &jme_link_change_tasklet,
2771 (unsigned long) jme);
2772 tasklet_init(&jme->txclean_task,
2773 &jme_tx_clean_tasklet,
2774 (unsigned long) jme);
2775 tasklet_init(&jme->rxclean_task,
2776 &jme_rx_clean_tasklet,
2777 (unsigned long) jme);
fcf45b4c
GFT		 2778 tasklet_init(&jme->rxempty_task,
2779 &jme_rx_empty_tasklet,
2780 (unsigned long) jme);
fa97b924 2781 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 2782 tasklet_disable_nosync(&jme->txclean_task);
2783 tasklet_disable_nosync(&jme->rxclean_task);
2784 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 2785 jme->dpi.cur = PCC_P1;
2786
cd0ff491 2787 jme->reg_ghc = 0;
79ce639c 2788 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 2789 jme->reg_rxmcs = RXMCS_DEFAULT;
2790 jme->reg_txpfc = 0;
47220951 2791 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT		 2792 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2793 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 2794
fcf45b4c
GFT		 2795 /*
2796 * Get Max Read Req Size from PCI Config Space
2797 */
cd0ff491
GFT		 2798 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2799 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2800 switch (jme->mrrs) {
2801 case MRRS_128B:
2802 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2803 break;
2804 case MRRS_256B:
2805 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2806 break;
2807 default:
2808 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2809 break;
fcf45b4c
GFT		 2810 };
2811
d7699f87 2812 /*
cdcdc9eb 2813 * Must check before reset_mac_processor
d7699f87 2814 */
cdcdc9eb
GFT		 2815 jme_check_hw_ver(jme);
2816 jme->mii_if.dev = netdev;
cd0ff491 2817 if (jme->fpgaver) {
cdcdc9eb 2818 jme->mii_if.phy_id = 0;
cd0ff491 2819 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 2820 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2821 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 2822 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 2823 jme->mii_if.phy_id = i;
2824 break;
2825 }
2826 }
2827
cd0ff491 2828 if (!jme->mii_if.phy_id) {
cdcdc9eb 2829 rc = -EIO;
cd0ff491 2830 jeprintk(pdev, "Can not find phy_id.\n");
fa97b924 2831 goto err_out_unmap;
cdcdc9eb
GFT		 2832 }
2833
2834 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 2835 } else {
cdcdc9eb
GFT		 2836 jme->mii_if.phy_id = 1;
2837 }
cd0ff491 2838 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 2839 jme->mii_if.supports_gmii = true;
2840 else
2841 jme->mii_if.supports_gmii = false;
cdcdc9eb
GFT		 2842 jme->mii_if.mdio_read = jme_mdio_read;
2843 jme->mii_if.mdio_write = jme_mdio_write;
2844
d7699f87 2845 jme_clear_pm(jme);
e882564f 2846 jme_set_phyfifoa(jme);
cd0ff491
GFT		 2847 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2848 if (!jme->fpgaver)
cdcdc9eb 2849 jme_phy_init(jme);
42b1055e 2850 jme_phy_off(jme);
cdcdc9eb
GFT		 2851
2852 /*
2853 * Reset MAC processor and reload EEPROM for MAC Address
2854 */
d7699f87 2855 jme_reset_mac_processor(jme);
4330c2f2 2856 rc = jme_reload_eeprom(jme);
cd0ff491
GFT		 2857 if (rc) {
2858 jeprintk(pdev,
b3821cc5 2859 "Reload eeprom for reading MAC Address error.\n");
fa97b924 2860 goto err_out_unmap;
4330c2f2 2861 }
d7699f87
GFT		 2862 jme_load_macaddr(netdev);
2863
d7699f87
GFT		 2864 /*
2865 * Tell stack that we are not ready to work until open()
2866 */
2867 netif_carrier_off(netdev);
2868 netif_stop_queue(netdev);
2869
2870 /*
2871 * Register netdev
2872 */
4330c2f2 2873 rc = register_netdev(netdev);
cd0ff491
GFT		 2874 if (rc) {
2875 jeprintk(pdev, "Cannot register net device.\n");
fa97b924 2876 goto err_out_unmap;
4330c2f2 2877 }
d7699f87 2878
94c5ea02
GFT		 2879 msg_probe(jme, "%s%s ver:%x rev:%x macaddr:%pM\n",
2880 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2881 "JMC250 Gigabit Ethernet" :
2882 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2883 "JMC260 Fast Ethernet" : "Unknown",
cd0ff491 2884 (jme->fpgaver != 0) ? " (FPGA)" : "",
e882564f 2885 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
94c5ea02 2886 jme->rev, netdev->dev_addr);
d7699f87
GFT		 2887
2888 return 0;
2889
2890err_out_unmap:
2891 iounmap(jme->regs);
2892err_out_free_netdev:
2893 pci_set_drvdata(pdev, NULL);
2894 free_netdev(netdev);
4330c2f2
GFT		 2895err_out_release_regions:
2896 pci_release_regions(pdev);
d7699f87 2897err_out_disable_pdev:
cd0ff491 2898 pci_disable_device(pdev);
d7699f87 2899err_out:
4330c2f2 2900 return rc;
d7699f87
GFT		 2901}
2902
3bf61c55
GFT		 2903static void __devexit
2904jme_remove_one(struct pci_dev *pdev)
2905{
d7699f87
GFT		 2906 struct net_device *netdev = pci_get_drvdata(pdev);
2907 struct jme_adapter *jme = netdev_priv(netdev);
2908
2909 unregister_netdev(netdev);
2910 iounmap(jme->regs);
2911 pci_set_drvdata(pdev, NULL);
2912 free_netdev(netdev);
2913 pci_release_regions(pdev);
2914 pci_disable_device(pdev);
2915
2916}
2917
9b9d55de 2918#ifdef CONFIG_PM
29bdd921
GFT		 2919static int
2920jme_suspend(struct pci_dev *pdev, pm_message_t state)
2921{
2922 struct net_device *netdev = pci_get_drvdata(pdev);
2923 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 2924
2925 atomic_dec(&jme->link_changing);
2926
2927 netif_device_detach(netdev);
2928 netif_stop_queue(netdev);
2929 jme_stop_irq(jme);
29bdd921 2930
cd0ff491
GFT		 2931 tasklet_disable(&jme->txclean_task);
2932 tasklet_disable(&jme->rxclean_task);
2933 tasklet_disable(&jme->rxempty_task);
2934
cd0ff491
GFT		 2935 if (netif_carrier_ok(netdev)) {
2936 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 2937 jme_polling_mode(jme);
2938
29bdd921 2939 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 2940 jme_reset_ghc_speed(jme);
2941 jme_disable_rx_engine(jme);
2942 jme_disable_tx_engine(jme);
29bdd921
GFT		 2943 jme_reset_mac_processor(jme);
2944 jme_free_rx_resources(jme);
2945 jme_free_tx_resources(jme);
2946 netif_carrier_off(netdev);
2947 jme->phylink = 0;
2948 }
2949
cd0ff491
GFT		 2950 tasklet_enable(&jme->txclean_task);
2951 tasklet_hi_enable(&jme->rxclean_task);
2952 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT		 2953
2954 pci_save_state(pdev);
cd0ff491 2955 if (jme->reg_pmcs) {
42b1055e 2956 jme_set_100m_half(jme);
47220951 2957
cd0ff491 2958 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
47220951
GFT		 2959 jme_wait_link(jme);
2960
29bdd921 2961 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
cd0ff491 2962
42b1055e 2963 pci_enable_wake(pdev, PCI_D3cold, true);
cd0ff491 2964 } else {
42b1055e 2965 jme_phy_off(jme);
29bdd921 2966 }
cd0ff491 2967 pci_set_power_state(pdev, PCI_D3cold);
29bdd921
GFT		 2968
2969 return 0;
2970}
2971
2972static int
2973jme_resume(struct pci_dev *pdev)
2974{
2975 struct net_device *netdev = pci_get_drvdata(pdev);
2976 struct jme_adapter *jme = netdev_priv(netdev);
2977
2978 jme_clear_pm(jme);
2979 pci_restore_state(pdev);
2980
cd0ff491 2981 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921
GFT		 2982 jme_set_settings(netdev, &jme->old_ecmd);
2983 else
2984 jme_reset_phy_processor(jme);
2985
29bdd921
GFT		 2986 jme_start_irq(jme);
2987 netif_device_attach(netdev);
2988
2989 atomic_inc(&jme->link_changing);
2990
2991 jme_reset_link(jme);
2992
2993 return 0;
2994}
9b9d55de 2995#endif
29bdd921 2996
d7699f87 2997static struct pci_device_id jme_pci_tbl[] = {
cd0ff491
GFT		 2998 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
2999 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3000 { }
3001};
3002
3003static struct pci_driver jme_driver = {
cd0ff491
GFT		 3004 .name = DRV_NAME,
3005 .id_table = jme_pci_tbl,
3006 .probe = jme_init_one,
3007 .remove = __devexit_p(jme_remove_one),
d7699f87 3008#ifdef CONFIG_PM
cd0ff491
GFT		 3009 .suspend = jme_suspend,
3010 .resume = jme_resume,
d7699f87 3011#endif /* CONFIG_PM */
d7699f87
GFT		 3012};
3013
3bf61c55
GFT		 3014static int __init
3015jme_init_module(void)
d7699f87 3016{
94c5ea02 3017 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
4330c2f2 3018 "driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3019 return pci_register_driver(&jme_driver);
3020}
3021
3bf61c55
GFT		 3022static void __exit
3023jme_cleanup_module(void)
d7699f87
GFT		 3024{
3025 pci_unregister_driver(&jme_driver);
3026}
3027
3028module_init(jme_init_module);
3029module_exit(jme_cleanup_module);
3030
3bf61c55 3031MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3032MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3033MODULE_LICENSE("GPL");
3034MODULE_VERSION(DRV_VERSION);
3035MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3036
JMicron Ethernet Linux driver