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jme: Cleanup PM operations after using new PM API
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
eee57828 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
52a46ba8
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
d7699f87
GFT		 27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/crc32.h>
4330c2f2 35#include <linux/delay.h>
29bdd921 36#include <linux/spinlock.h>
8c198884
GFT		 37#include <linux/in.h>
38#include <linux/ip.h>
79ce639c
GFT		 39#include <linux/ipv6.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42b1055e 42#include <linux/if_vlan.h>
6d641c63 43#include <linux/slab.h>
94c5ea02 44#include <net/ip6_checksum.h>
d7699f87
GFT		 45#include "jme.h"
46
cd0ff491
GFT		 47static int force_pseudohp = -1;
48static int no_pseudohp = -1;
49static int no_extplug = -1;
50module_param(force_pseudohp, int, 0);
51MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53module_param(no_pseudohp, int, 0);
54MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55module_param(no_extplug, int, 0);
56MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 58
3bf61c55
GFT		 59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 61{
62 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 64
186fc259 65read_again:
cd0ff491 66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
d7699f87
GFT		 69
70 wmb();
cd0ff491 71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 72 udelay(20);
b3821cc5
GFT		 73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
3bf61c55 75 break;
cd0ff491 76 }
d7699f87 77
cd0ff491 78 if (i == 0) {
52a46ba8 79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 80 return 0;
cd0ff491 81 }
d7699f87 82
cd0ff491 83 if (again--)
186fc259
GFT		 84 goto read_again;
85
cd0ff491 86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 87}
88
3bf61c55
GFT		 89static void
90jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
d7699f87
GFT		 92{
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
3bf61c55
GFT		 96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 99
100 wmb();
cdcdc9eb
GFT		 101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
8d27293f 103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 104 break;
105 }
d7699f87 106
3bf61c55 107 if (i == 0)
52a46ba8 108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 109}
110
cd0ff491 111static inline void
3bf61c55 112jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 113{
cd0ff491 114 u32 val;
3bf61c55
GFT		 115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
8c198884
GFT		 118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 120
cd0ff491 121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 126
fcf45b4c
GFT		 127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 134}
135
b3821cc5
GFT		 136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
0d8a2973 138 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
cd0ff491 153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55 162
ed830419
GFT		 163static inline void
164jme_mac_rxclk_off(struct jme_adapter *jme)
165{
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168}
169
170static inline void
171jme_mac_rxclk_on(struct jme_adapter *jme)
172{
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175}
176
177static inline void
178jme_mac_txclk_off(struct jme_adapter *jme)
179{
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
182}
183
184static inline void
185jme_mac_txclk_on(struct jme_adapter *jme)
186{
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190 else
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
193}
194
195static inline void
196jme_reset_ghc_speed(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_reset_250A2_workaround(struct jme_adapter *jme)
204{
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206 GPREG1_RSSPATCH);
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208}
209
210static inline void
211jme_assert_ghc_reset(struct jme_adapter *jme)
212{
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215}
216
217static inline void
218jme_clear_ghc_reset(struct jme_adapter *jme)
219{
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
222}
223
cd0ff491 224static inline void
3bf61c55
GFT		 225jme_reset_mac_processor(struct jme_adapter *jme)
226{
0d8a2973 227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 228 u32 crc = 0xCDCDCDCD;
229 u32 gpreg0;
b3821cc5
GFT		 230 int i;
231
ed830419
GFT		 232 jme_reset_ghc_speed(jme);
233 jme_reset_250A2_workaround(jme);
234
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
237 udelay(1);
238 jme_assert_ghc_reset(jme);
239 udelay(1);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
242 udelay(1);
243 jme_clear_ghc_reset(jme);
244 udelay(1);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
247 udelay(1);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
cd0ff491
GFT		 250
251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253 jwrite32(jme, JME_RXQDC, 0x00000000);
254 jwrite32(jme, JME_RXNDA, 0x00000000);
255 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257 jwrite32(jme, JME_TXQDC, 0x00000000);
258 jwrite32(jme, JME_TXNDA, 0x00000000);
259
4330c2f2
GFT		 260 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 262 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 263 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 264 if (jme->fpgaver)
cdcdc9eb
GFT		 265 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266 else
267 gpreg0 = GPREG0_DEFAULT;
268 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 269}
270
271static inline void
3bf61c55 272jme_clear_pm(struct jme_adapter *jme)
d7699f87 273{
45b025cf 274 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT		 275}
276
3bf61c55
GFT		 277static int
278jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 279{
cd0ff491 280 u32 val;
d7699f87
GFT		 281 int i;
282
283 val = jread32(jme, JME_SMBCSR);
284
cd0ff491 285 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 286 val |= SMBCSR_CNACK;
287 jwrite32(jme, JME_SMBCSR, val);
288 val |= SMBCSR_RELOAD;
289 jwrite32(jme, JME_SMBCSR, val);
290 mdelay(12);
291
cd0ff491 292 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 293 mdelay(1);
294 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
295 break;
296 }
297
cd0ff491 298 if (i == 0) {
52a46ba8 299 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 300 return -EIO;
301 }
302 }
3bf61c55 303
d7699f87
GFT		 304 return 0;
305}
306
3bf61c55
GFT		 307static void
308jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 309{
310 struct jme_adapter *jme = netdev_priv(netdev);
311 unsigned char macaddr[6];
cd0ff491 312 u32 val;
d7699f87 313
cd0ff491 314 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 315 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 316 macaddr[0] = (val >> 0) & 0xFF;
317 macaddr[1] = (val >> 8) & 0xFF;
318 macaddr[2] = (val >> 16) & 0xFF;
319 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 320 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 321 macaddr[4] = (val >> 0) & 0xFF;
322 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 323 memcpy(netdev->dev_addr, macaddr, 6);
324 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 325}
326
cd0ff491 327static inline void
3bf61c55
GFT		 328jme_set_rx_pcc(struct jme_adapter *jme, int p)
329{
cd0ff491 330 switch (p) {
192570e0
GFT		 331 case PCC_OFF:
332 jwrite32(jme, JME_PCCRX0,
333 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
334 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
335 break;
3bf61c55
GFT		 336 case PCC_P1:
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340 break;
341 case PCC_P2:
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345 break;
346 case PCC_P3:
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350 break;
351 default:
352 break;
353 }
192570e0 354 wmb();
3bf61c55 355
cd0ff491 356 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
c97b5740 357 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 358}
359
fcf45b4c 360static void
3bf61c55 361jme_start_irq(struct jme_adapter *jme)
d7699f87 362{
3bf61c55
GFT		 363 register struct dynpcc_info *dpi = &(jme->dpi);
364
365 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 366 dpi->cur = PCC_P1;
367 dpi->attempt = PCC_P1;
368 dpi->cnt = 0;
369
370 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 371 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
372 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 373 PCCTXQ0_EN
374 );
375
d7699f87
GFT		 376 /*
377 * Enable Interrupts
378 */
379 jwrite32(jme, JME_IENS, INTR_ENABLE);
380}
381
cd0ff491 382static inline void
3bf61c55 383jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 384{
385 /*
386 * Disable Interrupts
387 */
cd0ff491 388 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 389}
390
cd0ff491 391static u32
cdcdc9eb
GFT		 392jme_linkstat_from_phy(struct jme_adapter *jme)
393{
cd0ff491 394 u32 phylink, bmsr;
cdcdc9eb
GFT		 395
396 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
397 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 398 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 399 phylink |= PHY_LINK_AUTONEG_COMPLETE;
400
401 return phylink;
402}
403
cd0ff491 404static inline void
06168a20 405jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 406{
407 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
408}
409
410static inline void
06168a20 411jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 412{
413 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
414}
415
fcf45b4c
GFT		 416static int
417jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 418{
419 struct jme_adapter *jme = netdev_priv(netdev);
ed830419 420 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 421 char linkmsg[64];
fcf45b4c 422 int rc = 0;
d7699f87 423
b3821cc5 424 linkmsg[0] = '\0';
cdcdc9eb 425
cd0ff491 426 if (jme->fpgaver)
cdcdc9eb
GFT		 427 phylink = jme_linkstat_from_phy(jme);
428 else
429 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 430
cd0ff491
GFT		 431 if (phylink & PHY_LINK_UP) {
432 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 433 /*
434 * If we did not enable AN
435 * Speed/Duplex Info should be obtained from SMI
436 */
437 phylink = PHY_LINK_UP;
438
439 bmcr = jme_mdio_read(jme->dev,
440 jme->mii_if.phy_id,
441 MII_BMCR);
442
443 phylink |= ((bmcr & BMCR_SPEED1000) &&
444 (bmcr & BMCR_SPEED100) == 0) ?
445 PHY_LINK_SPEED_1000M :
446 (bmcr & BMCR_SPEED100) ?
447 PHY_LINK_SPEED_100M :
448 PHY_LINK_SPEED_10M;
449
450 phylink |= (bmcr & BMCR_FULLDPLX) ?
451 PHY_LINK_DUPLEX : 0;
79ce639c 452
b3821cc5 453 strcat(linkmsg, "Forced: ");
cd0ff491 454 } else {
8c198884
GFT		 455 /*
456 * Keep polling for speed/duplex resolve complete
457 */
cd0ff491 458 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 459 --cnt) {
460
461 udelay(1);
8c198884 462
cd0ff491 463 if (jme->fpgaver)
cdcdc9eb
GFT		 464 phylink = jme_linkstat_from_phy(jme);
465 else
466 phylink = jread32(jme, JME_PHY_LINK);
8c198884 467 }
cd0ff491 468 if (!cnt)
52a46ba8 469 pr_err("Waiting speed resolve timeout\n");
79ce639c 470
b3821cc5 471 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 472 }
473
cd0ff491 474 if (jme->phylink == phylink) {
fcf45b4c
GFT		 475 rc = 1;
476 goto out;
477 }
cd0ff491 478 if (testonly)
fcf45b4c
GFT		 479 goto out;
480
481 jme->phylink = phylink;
482
ed830419
GFT		 483 /*
484 * The speed/duplex setting of jme->reg_ghc already cleared
485 * by jme_reset_mac_processor()
486 */
cd0ff491
GFT		 487 switch (phylink & PHY_LINK_SPEED_MASK) {
488 case PHY_LINK_SPEED_10M:
ed830419 489 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 490 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 491 break;
492 case PHY_LINK_SPEED_100M:
ed830419 493 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 494 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 495 break;
496 case PHY_LINK_SPEED_1000M:
ed830419 497 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 498 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 499 break;
500 default:
501 break;
d7699f87 502 }
d7699f87 503
cd0ff491 504 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 505 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
19bbc546 506 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
ed830419 507 jme->reg_ghc |= GHC_DPX;
cd0ff491 508 } else {
d7699f87 509 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 510 TXMCS_BACKOFF |
511 TXMCS_CARRIERSENSE |
512 TXMCS_COLLISION);
19bbc546 513 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 514 }
9b9d55de 515
ed830419
GFT		 516 jwrite32(jme, JME_GHC, jme->reg_ghc);
517
9b9d55de 518 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
ed830419
GFT		 519 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
520 GPREG1_RSSPATCH);
9b9d55de 521 if (!(phylink & PHY_LINK_DUPLEX))
ed830419 522 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
9b9d55de
GFT		 523 switch (phylink & PHY_LINK_SPEED_MASK) {
524 case PHY_LINK_SPEED_10M:
06168a20 525 jme_set_phyfifo_8level(jme);
ed830419 526 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
9b9d55de
GFT		 527 break;
528 case PHY_LINK_SPEED_100M:
06168a20 529 jme_set_phyfifo_5level(jme);
ed830419 530 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
9b9d55de
GFT		 531 break;
532 case PHY_LINK_SPEED_1000M:
06168a20 533 jme_set_phyfifo_8level(jme);
9b9d55de
GFT		 534 break;
535 default:
536 break;
537 }
538 }
ed830419 539 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 540
94c5ea02
GFT		 541 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
542 "Full-Duplex, " :
543 "Half-Duplex, ");
544 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
545 "MDI-X" :
546 "MDI");
52a46ba8 547 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 548 netif_carrier_on(netdev);
549 } else {
550 if (testonly)
fcf45b4c
GFT		 551 goto out;
552
52a46ba8 553 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 554 jme->phylink = 0;
cd0ff491 555 netif_carrier_off(netdev);
d7699f87 556 }
fcf45b4c
GFT		 557
558out:
559 return rc;
d7699f87
GFT		 560}
561
3bf61c55
GFT		 562static int
563jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 564{
d7699f87
GFT		 565 struct jme_ring *txring = &(jme->txring[0]);
566
567 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 568 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
569 &(txring->dmaalloc),
570 GFP_ATOMIC);
fcf45b4c 571
fa97b924
GFT		 572 if (!txring->alloc)
573 goto err_set_null;
d7699f87
GFT		 574
575 /*
576 * 16 Bytes align
577 */
cd0ff491 578 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 579 RING_DESC_ALIGN);
4330c2f2 580 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 581 txring->next_to_use = 0;
cdcdc9eb 582 atomic_set(&txring->next_to_clean, 0);
b3821cc5 583 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 584
fa97b924
GFT		 585 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
586 jme->tx_ring_size, GFP_ATOMIC);
587 if (unlikely(!(txring->bufinf)))
588 goto err_free_txring;
589
d7699f87 590 /*
b3821cc5 591 * Initialize Transmit Descriptors
d7699f87 592 */
b3821cc5 593 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 594 memset(txring->bufinf, 0,
b3821cc5 595 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 596
597 return 0;
fa97b924
GFT		 598
599err_free_txring:
600 dma_free_coherent(&(jme->pdev->dev),
601 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
602 txring->alloc,
603 txring->dmaalloc);
604
605err_set_null:
606 txring->desc = NULL;
607 txring->dmaalloc = 0;
608 txring->dma = 0;
609 txring->bufinf = NULL;
610
611 return -ENOMEM;
d7699f87
GFT		 612}
613
3bf61c55
GFT		 614static void
615jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 616{
617 int i;
618 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 619 struct jme_buffer_info *txbi;
d7699f87 620
cd0ff491 621 if (txring->alloc) {
fa97b924
GFT		 622 if (txring->bufinf) {
623 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
624 txbi = txring->bufinf + i;
625 if (txbi->skb) {
626 dev_kfree_skb(txbi->skb);
627 txbi->skb = NULL;
628 }
629 txbi->mapping = 0;
630 txbi->len = 0;
631 txbi->nr_desc = 0;
632 txbi->start_xmit = 0;
d7699f87 633 }
fa97b924 634 kfree(txring->bufinf);
d7699f87
GFT		 635 }
636
637 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 638 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 639 txring->alloc,
640 txring->dmaalloc);
3bf61c55
GFT		 641
642 txring->alloc = NULL;
643 txring->desc = NULL;
644 txring->dmaalloc = 0;
645 txring->dma = 0;
fa97b924 646 txring->bufinf = NULL;
d7699f87 647 }
3bf61c55 648 txring->next_to_use = 0;
cdcdc9eb 649 atomic_set(&txring->next_to_clean, 0);
79ce639c 650 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 651}
652
cd0ff491 653static inline void
3bf61c55 654jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 655{
656 /*
657 * Select Queue 0
658 */
659 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 660 wmb();
d7699f87
GFT		 661
662 /*
663 * Setup TX Queue 0 DMA Bass Address
664 */
fcf45b4c 665 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 666 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 667 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 668
669 /*
670 * Setup TX Descptor Count
671 */
b3821cc5 672 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 673
674 /*
675 * Enable TX Engine
676 */
677 wmb();
ed830419 678 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 679 TXCS_SELECT_QUEUE0 |
680 TXCS_ENABLE);
d7699f87 681
ed830419
GFT		 682 /*
683 * Start clock for TX MAC Processor
684 */
685 jme_mac_txclk_on(jme);
d7699f87
GFT		 686}
687
cd0ff491 688static inline void
29bdd921
GFT		 689jme_restart_tx_engine(struct jme_adapter *jme)
690{
691 /*
692 * Restart TX Engine
693 */
694 jwrite32(jme, JME_TXCS, jme->reg_txcs |
695 TXCS_SELECT_QUEUE0 |
696 TXCS_ENABLE);
697}
698
cd0ff491 699static inline void
3bf61c55 700jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 701{
702 int i;
cd0ff491 703 u32 val;
d7699f87
GFT		 704
705 /*
706 * Disable TX Engine
707 */
fcf45b4c 708 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 709 wmb();
d7699f87
GFT		 710
711 val = jread32(jme, JME_TXCS);
cd0ff491 712 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 713 mdelay(1);
d7699f87 714 val = jread32(jme, JME_TXCS);
cd0ff491 715 rmb();
d7699f87
GFT		 716 }
717
cd0ff491 718 if (!i)
52a46ba8 719 pr_err("Disable TX engine timeout\n");
ed830419
GFT		 720
721 /*
722 * Stop clock for TX MAC Processor
723 */
724 jme_mac_txclk_off(jme);
d7699f87
GFT		 725}
726
3bf61c55
GFT		 727static void
728jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 729{
fa97b924 730 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 731 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 732 struct jme_buffer_info *rxbi = rxring->bufinf;
733 rxdesc += i;
734 rxbi += i;
735
736 rxdesc->dw[0] = 0;
737 rxdesc->dw[1] = 0;
3bf61c55 738 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 739 rxdesc->desc1.bufaddrl = cpu_to_le32(
740 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 741 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 742 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 743 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 744 wmb();
3bf61c55 745 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 746}
747
3bf61c55
GFT		 748static int
749jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 750{
751 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 752 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 753 struct sk_buff *skb;
4330c2f2 754
79ce639c
GFT		 755 skb = netdev_alloc_skb(jme->dev,
756 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 757 if (unlikely(!skb))
4330c2f2 758 return -ENOMEM;
3bf61c55 759
4330c2f2 760 rxbi->skb = skb;
3bf61c55 761 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT		 762 rxbi->mapping = pci_map_page(jme->pdev,
763 virt_to_page(skb->data),
764 offset_in_page(skb->data),
765 rxbi->len,
766 PCI_DMA_FROMDEVICE);
4330c2f2
GFT		 767
768 return 0;
769}
770
3bf61c55
GFT		 771static void
772jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 773{
774 struct jme_ring *rxring = &(jme->rxring[0]);
775 struct jme_buffer_info *rxbi = rxring->bufinf;
776 rxbi += i;
777
cd0ff491 778 if (rxbi->skb) {
b3821cc5 779 pci_unmap_page(jme->pdev,
4330c2f2 780 rxbi->mapping,
3bf61c55 781 rxbi->len,
4330c2f2
GFT		 782 PCI_DMA_FROMDEVICE);
783 dev_kfree_skb(rxbi->skb);
784 rxbi->skb = NULL;
785 rxbi->mapping = 0;
3bf61c55 786 rxbi->len = 0;
4330c2f2
GFT		 787 }
788}
789
3bf61c55
GFT		 790static void
791jme_free_rx_resources(struct jme_adapter *jme)
792{
793 int i;
794 struct jme_ring *rxring = &(jme->rxring[0]);
795
cd0ff491 796 if (rxring->alloc) {
fa97b924
GFT		 797 if (rxring->bufinf) {
798 for (i = 0 ; i < jme->rx_ring_size ; ++i)
799 jme_free_rx_buf(jme, i);
800 kfree(rxring->bufinf);
801 }
3bf61c55
GFT		 802
803 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 804 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 805 rxring->alloc,
806 rxring->dmaalloc);
807 rxring->alloc = NULL;
808 rxring->desc = NULL;
809 rxring->dmaalloc = 0;
810 rxring->dma = 0;
fa97b924 811 rxring->bufinf = NULL;
3bf61c55
GFT		 812 }
813 rxring->next_to_use = 0;
cdcdc9eb 814 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 815}
816
817static int
818jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 819{
820 int i;
821 struct jme_ring *rxring = &(jme->rxring[0]);
822
823 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 824 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
825 &(rxring->dmaalloc),
826 GFP_ATOMIC);
fa97b924
GFT		 827 if (!rxring->alloc)
828 goto err_set_null;
d7699f87
GFT		 829
830 /*
831 * 16 Bytes align
832 */
cd0ff491 833 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 834 RING_DESC_ALIGN);
4330c2f2 835 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 836 rxring->next_to_use = 0;
cdcdc9eb 837 atomic_set(&rxring->next_to_clean, 0);
d7699f87 838
fa97b924
GFT		 839 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
840 jme->rx_ring_size, GFP_ATOMIC);
841 if (unlikely(!(rxring->bufinf)))
842 goto err_free_rxring;
843
d7699f87
GFT		 844 /*
845 * Initiallize Receive Descriptors
846 */
fa97b924
GFT		 847 memset(rxring->bufinf, 0,
848 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 849 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
850 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 851 jme_free_rx_resources(jme);
852 return -ENOMEM;
853 }
d7699f87
GFT		 854
855 jme_set_clean_rxdesc(jme, i);
856 }
857
d7699f87 858 return 0;
fa97b924
GFT		 859
860err_free_rxring:
861 dma_free_coherent(&(jme->pdev->dev),
862 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
863 rxring->alloc,
864 rxring->dmaalloc);
865err_set_null:
866 rxring->desc = NULL;
867 rxring->dmaalloc = 0;
868 rxring->dma = 0;
869 rxring->bufinf = NULL;
870
871 return -ENOMEM;
d7699f87
GFT		 872}
873
cd0ff491 874static inline void
3bf61c55 875jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 876{
cd0ff491
GFT		 877 /*
878 * Select Queue 0
879 */
880 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
881 RXCS_QUEUESEL_Q0);
882 wmb();
883
d7699f87
GFT		 884 /*
885 * Setup RX DMA Bass Address
886 */
fa97b924 887 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 888 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 889 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 890
891 /*
b3821cc5 892 * Setup RX Descriptor Count
d7699f87 893 */
b3821cc5 894 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 895
3bf61c55 896 /*
d7699f87
GFT		 897 * Setup Unicast Filter
898 */
bb4c5c8c 899 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 900 jme_set_multi(jme->dev);
901
902 /*
903 * Enable RX Engine
904 */
905 wmb();
ed830419 906 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 907 RXCS_QUEUESEL_Q0 |
908 RXCS_ENABLE |
909 RXCS_QST);
ed830419
GFT		 910
911 /*
912 * Start clock for RX MAC Processor
913 */
914 jme_mac_rxclk_on(jme);
d7699f87
GFT		 915}
916
cd0ff491 917static inline void
3bf61c55 918jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 919{
920 /*
3bf61c55 921 * Start RX Engine
4330c2f2 922 */
79ce639c 923 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 924 RXCS_QUEUESEL_Q0 |
925 RXCS_ENABLE |
926 RXCS_QST);
927}
928
cd0ff491 929static inline void
3bf61c55 930jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 931{
932 int i;
cd0ff491 933 u32 val;
d7699f87
GFT		 934
935 /*
936 * Disable RX Engine
937 */
29bdd921 938 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 939 wmb();
d7699f87
GFT		 940
941 val = jread32(jme, JME_RXCS);
cd0ff491 942 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 943 mdelay(1);
d7699f87 944 val = jread32(jme, JME_RXCS);
cd0ff491 945 rmb();
d7699f87
GFT		 946 }
947
cd0ff491 948 if (!i)
52a46ba8 949 pr_err("Disable RX engine timeout\n");
d7699f87 950
ed830419
GFT		 951 /*
952 * Stop clock for RX MAC Processor
953 */
954 jme_mac_rxclk_off(jme);
d7699f87
GFT		 955}
956
a452eef1
GFT		 957static u16
958jme_udpsum(struct sk_buff *skb)
959{
960 u16 csum = 0xFFFFu;
961
962 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
963 return csum;
964 if (skb->protocol != htons(ETH_P_IP))
965 return csum;
966 skb_set_network_header(skb, ETH_HLEN);
967 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
968 (skb->len < (ETH_HLEN +
969 (ip_hdr(skb)->ihl << 2) +
970 sizeof(struct udphdr)))) {
971 skb_reset_network_header(skb);
972 return csum;
973 }
974 skb_set_transport_header(skb,
975 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
976 csum = udp_hdr(skb)->check;
977 skb_reset_transport_header(skb);
978 skb_reset_network_header(skb);
979
980 return csum;
981}
982
192570e0 983static int
a452eef1 984jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 985{
cd0ff491 986 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 987 return false;
988
fa97b924
GFT		 989 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
990 == RXWBFLAG_TCPON)) {
991 if (flags & RXWBFLAG_IPV4)
c97b5740 992 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
fa97b924 993 return false;
192570e0
GFT		 994 }
995
fa97b924 996 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
a452eef1 997 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
fa97b924 998 if (flags & RXWBFLAG_IPV4)
52a46ba8 999 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
fa97b924 1000 return false;
192570e0
GFT		 1001 }
1002
fa97b924
GFT		 1003 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1004 == RXWBFLAG_IPV4)) {
52a46ba8 1005 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
fa97b924 1006 return false;
192570e0
GFT		 1007 }
1008
1009 return true;
1010}
1011
3bf61c55 1012static void
42b1055e 1013jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1014{
d7699f87 1015 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1016 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1017 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1018 struct sk_buff *skb;
3bf61c55 1019 int framesize;
d7699f87 1020
3bf61c55
GFT		 1021 rxdesc += idx;
1022 rxbi += idx;
d7699f87 1023
3bf61c55
GFT		 1024 skb = rxbi->skb;
1025 pci_dma_sync_single_for_cpu(jme->pdev,
1026 rxbi->mapping,
1027 rxbi->len,
1028 PCI_DMA_FROMDEVICE);
1029
cd0ff491 1030 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1031 pci_dma_sync_single_for_device(jme->pdev,
1032 rxbi->mapping,
1033 rxbi->len,
1034 PCI_DMA_FROMDEVICE);
1035
1036 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1037 } else {
3bf61c55
GFT		 1038 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1039 - RX_PREPAD_SIZE;
1040
1041 skb_reserve(skb, RX_PREPAD_SIZE);
1042 skb_put(skb, framesize);
1043 skb->protocol = eth_type_trans(skb, jme->dev);
1044
a452eef1 1045 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1046 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1047 else
97984ab7 1048 skb_checksum_none_assert(skb);
8c198884 1049
94c5ea02 1050 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1051 if (jme->vlgrp) {
cdcdc9eb 1052 jme->jme_vlan_rx(skb, jme->vlgrp,
94c5ea02 1053 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1054 NET_STAT(jme).rx_bytes += 4;
c97b5740 1055 } else {
c97b5740 1056 dev_kfree_skb(skb);
b3821cc5 1057 }
cd0ff491 1058 } else {
cdcdc9eb 1059 jme->jme_rx(skb);
b3821cc5 1060 }
3bf61c55 1061
94c5ea02
GFT		 1062 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1063 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1064 ++(NET_STAT(jme).multicast);
1065
3bf61c55
GFT		 1066 NET_STAT(jme).rx_bytes += framesize;
1067 ++(NET_STAT(jme).rx_packets);
1068 }
1069
1070 jme_set_clean_rxdesc(jme, idx);
1071
1072}
1073
1074static int
1075jme_process_receive(struct jme_adapter *jme, int limit)
1076{
1077 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1078 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1079 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1080
cd0ff491 1081 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1082 goto out_inc;
1083
cd0ff491 1084 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1085 goto out_inc;
1086
cd0ff491 1087 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1088 goto out_inc;
1089
cdcdc9eb 1090 i = atomic_read(&rxring->next_to_clean);
fa97b924 1091 while (limit > 0) {
3bf61c55
GFT		 1092 rxdesc = rxring->desc;
1093 rxdesc += i;
1094
94c5ea02 1095 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1096 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1097 goto out;
fa97b924 1098 --limit;
d7699f87 1099
1a7a122d 1100 rmb();
4330c2f2
GFT		 1101 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1102
cd0ff491 1103 if (unlikely(desccnt > 1 ||
192570e0 1104 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1105
cd0ff491 1106 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1107 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1108 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1109 ++(NET_STAT(jme).rx_fifo_errors);
1110 else
1111 ++(NET_STAT(jme).rx_errors);
4330c2f2 1112
cd0ff491 1113 if (desccnt > 1)
3bf61c55 1114 limit -= desccnt - 1;
4330c2f2 1115
cd0ff491 1116 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1117 jme_set_clean_rxdesc(jme, j);
b3821cc5 1118 j = (j + 1) & (mask);
4330c2f2 1119 }
3bf61c55 1120
cd0ff491 1121 } else {
42b1055e 1122 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1123 }
4330c2f2 1124
b3821cc5 1125 i = (i + desccnt) & (mask);
3bf61c55 1126 }
4330c2f2 1127
3bf61c55 1128out:
cdcdc9eb 1129 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1130
192570e0
GFT		 1131out_inc:
1132 atomic_inc(&jme->rx_cleaning);
1133
3bf61c55 1134 return limit > 0 ? limit : 0;
4330c2f2 1135
3bf61c55 1136}
d7699f87 1137
79ce639c
GFT		 1138static void
1139jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1140{
cd0ff491 1141 if (likely(atmp == dpi->cur)) {
192570e0 1142 dpi->cnt = 0;
79ce639c 1143 return;
192570e0 1144 }
79ce639c 1145
cd0ff491 1146 if (dpi->attempt == atmp) {
79ce639c 1147 ++(dpi->cnt);
cd0ff491 1148 } else {
79ce639c
GFT		 1149 dpi->attempt = atmp;
1150 dpi->cnt = 0;
1151 }
1152
1153}
1154
1155static void
1156jme_dynamic_pcc(struct jme_adapter *jme)
1157{
1158 register struct dynpcc_info *dpi = &(jme->dpi);
1159
cd0ff491 1160 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1161 jme_attempt_pcc(dpi, PCC_P3);
c97b5740
GFT		 1162 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1163 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1164 jme_attempt_pcc(dpi, PCC_P2);
1165 else
1166 jme_attempt_pcc(dpi, PCC_P1);
1167
cd0ff491
GFT		 1168 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1169 if (dpi->attempt < dpi->cur)
1170 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1171 jme_set_rx_pcc(jme, dpi->attempt);
1172 dpi->cur = dpi->attempt;
1173 dpi->cnt = 0;
1174 }
1175}
1176
1177static void
1178jme_start_pcc_timer(struct jme_adapter *jme)
1179{
1180 struct dynpcc_info *dpi = &(jme->dpi);
1181 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1182 dpi->last_pkts = NET_STAT(jme).rx_packets;
1183 dpi->intr_cnt = 0;
1184 jwrite32(jme, JME_TMCSR,
1185 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1186}
1187
cd0ff491 1188static inline void
29bdd921
GFT		 1189jme_stop_pcc_timer(struct jme_adapter *jme)
1190{
1191 jwrite32(jme, JME_TMCSR, 0);
1192}
1193
cd0ff491
GFT		 1194static void
1195jme_shutdown_nic(struct jme_adapter *jme)
1196{
1197 u32 phylink;
1198
1199 phylink = jme_linkstat_from_phy(jme);
1200
1201 if (!(phylink & PHY_LINK_UP)) {
1202 /*
1203 * Disable all interrupt before issue timer
1204 */
1205 jme_stop_irq(jme);
1206 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1207 }
1208}
1209
79ce639c
GFT		 1210static void
1211jme_pcc_tasklet(unsigned long arg)
1212{
cd0ff491 1213 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1214 struct net_device *netdev = jme->dev;
1215
cd0ff491
GFT		 1216 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1217 jme_shutdown_nic(jme);
1218 return;
1219 }
29bdd921 1220
cd0ff491 1221 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1222 (atomic_read(&jme->link_changing) != 1)
1223 )) {
1224 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1225 return;
1226 }
29bdd921 1227
cd0ff491 1228 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1229 jme_dynamic_pcc(jme);
1230
79ce639c
GFT		 1231 jme_start_pcc_timer(jme);
1232}
1233
cd0ff491 1234static inline void
192570e0
GFT		 1235jme_polling_mode(struct jme_adapter *jme)
1236{
1237 jme_set_rx_pcc(jme, PCC_OFF);
1238}
1239
cd0ff491 1240static inline void
192570e0
GFT		 1241jme_interrupt_mode(struct jme_adapter *jme)
1242{
1243 jme_set_rx_pcc(jme, PCC_P1);
1244}
1245
cd0ff491
GFT		 1246static inline int
1247jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1248{
1249 u32 apmc;
1250 apmc = jread32(jme, JME_APMC);
1251 return apmc & JME_APMC_PSEUDO_HP_EN;
1252}
1253
1254static void
1255jme_start_shutdown_timer(struct jme_adapter *jme)
1256{
1257 u32 apmc;
1258
1259 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1260 apmc &= ~JME_APMC_EPIEN_CTRL;
1261 if (!no_extplug) {
1262 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1263 wmb();
1264 }
1265 jwrite32f(jme, JME_APMC, apmc);
1266
1267 jwrite32f(jme, JME_TIMER2, 0);
1268 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1269 jwrite32(jme, JME_TMCSR,
1270 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1271}
1272
1273static void
1274jme_stop_shutdown_timer(struct jme_adapter *jme)
1275{
1276 u32 apmc;
1277
1278 jwrite32f(jme, JME_TMCSR, 0);
1279 jwrite32f(jme, JME_TIMER2, 0);
1280 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1281
1282 apmc = jread32(jme, JME_APMC);
1283 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1284 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1285 wmb();
1286 jwrite32f(jme, JME_APMC, apmc);
1287}
1288
3bf61c55
GFT		 1289static void
1290jme_link_change_tasklet(unsigned long arg)
1291{
cd0ff491 1292 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1293 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1294 int rc;
1295
cd0ff491
GFT		 1296 while (!atomic_dec_and_test(&jme->link_changing)) {
1297 atomic_inc(&jme->link_changing);
52a46ba8 1298 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
e882564f 1299 while (atomic_read(&jme->link_changing) != 1)
52a46ba8 1300 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1301 }
fcf45b4c 1302
cd0ff491 1303 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1304 goto out;
1305
29bdd921 1306 jme->old_mtu = netdev->mtu;
fcf45b4c 1307 netif_stop_queue(netdev);
cd0ff491
GFT		 1308 if (jme_pseudo_hotplug_enabled(jme))
1309 jme_stop_shutdown_timer(jme);
1310
1311 jme_stop_pcc_timer(jme);
1312 tasklet_disable(&jme->txclean_task);
1313 tasklet_disable(&jme->rxclean_task);
1314 tasklet_disable(&jme->rxempty_task);
1315
1316 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1317 jme_disable_rx_engine(jme);
1318 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1319 jme_reset_mac_processor(jme);
1320 jme_free_rx_resources(jme);
1321 jme_free_tx_resources(jme);
192570e0 1322
cd0ff491 1323 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1324 jme_polling_mode(jme);
cd0ff491
GFT		 1325
1326 netif_carrier_off(netdev);
fcf45b4c
GFT		 1327 }
1328
1329 jme_check_link(netdev, 0);
cd0ff491 1330 if (netif_carrier_ok(netdev)) {
fcf45b4c 1331 rc = jme_setup_rx_resources(jme);
cd0ff491 1332 if (rc) {
52a46ba8 1333 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1334 goto out_enable_tasklet;
fcf45b4c
GFT		 1335 }
1336
fcf45b4c 1337 rc = jme_setup_tx_resources(jme);
cd0ff491 1338 if (rc) {
52a46ba8 1339 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1340 goto err_out_free_rx_resources;
1341 }
1342
1343 jme_enable_rx_engine(jme);
1344 jme_enable_tx_engine(jme);
1345
1346 netif_start_queue(netdev);
192570e0 1347
cd0ff491 1348 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1349 jme_interrupt_mode(jme);
192570e0 1350
79ce639c 1351 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1352 } else if (jme_pseudo_hotplug_enabled(jme)) {
1353 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1354 }
1355
cd0ff491 1356 goto out_enable_tasklet;
fcf45b4c
GFT		 1357
1358err_out_free_rx_resources:
1359 jme_free_rx_resources(jme);
cd0ff491
GFT		 1360out_enable_tasklet:
1361 tasklet_enable(&jme->txclean_task);
1362 tasklet_hi_enable(&jme->rxclean_task);
1363 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1364out:
1365 atomic_inc(&jme->link_changing);
3bf61c55 1366}
d7699f87 1367
3bf61c55
GFT		 1368static void
1369jme_rx_clean_tasklet(unsigned long arg)
1370{
cd0ff491 1371 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1372 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1373
192570e0
GFT		 1374 jme_process_receive(jme, jme->rx_ring_size);
1375 ++(dpi->intr_cnt);
42b1055e 1376
192570e0 1377}
fcf45b4c 1378
192570e0 1379static int
cdcdc9eb 1380jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1381{
cdcdc9eb 1382 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1383 int rest;
fcf45b4c 1384
cdcdc9eb 1385 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1386
cd0ff491 1387 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1388 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1389 ++(NET_STAT(jme).rx_dropped);
1390 jme_restart_rx_engine(jme);
1391 }
1392 atomic_inc(&jme->rx_empty);
1393
cd0ff491 1394 if (rest) {
cdcdc9eb 1395 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1396 jme_interrupt_mode(jme);
1397 }
1398
cdcdc9eb
GFT		 1399 JME_NAPI_WEIGHT_SET(budget, rest);
1400 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1401}
1402
1403static void
1404jme_rx_empty_tasklet(unsigned long arg)
1405{
cd0ff491 1406 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1407
cd0ff491 1408 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1409 return;
1410
cd0ff491 1411 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1412 return;
1413
c97b5740 1414 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1415
fcf45b4c 1416 jme_rx_clean_tasklet(arg);
cdcdc9eb 1417
cd0ff491 1418 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1419 atomic_dec(&jme->rx_empty);
1420 ++(NET_STAT(jme).rx_dropped);
1421 jme_restart_rx_engine(jme);
1422 }
1423 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1424}
1425
b3821cc5
GFT		 1426static void
1427jme_wake_queue_if_stopped(struct jme_adapter *jme)
1428{
fa97b924 1429 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1430
1431 smp_wmb();
cd0ff491 1432 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1433 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
52a46ba8 1434 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1435 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1436 }
1437
1438}
1439
3bf61c55
GFT		 1440static void
1441jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1442{
cd0ff491 1443 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1444 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1445 struct txdesc *txdesc = txring->desc;
3bf61c55 1446 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1447 int i, j, cnt = 0, max, err, mask;
3bf61c55 1448
52a46ba8 1449 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1450
1451 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1452 goto out;
1453
cd0ff491 1454 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1455 goto out;
1456
cd0ff491 1457 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1458 goto out;
1459
b3821cc5
GFT		 1460 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1461 mask = jme->tx_ring_mask;
3bf61c55 1462
cd0ff491 1463 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1464
1465 ctxbi = txbi + i;
1466
cd0ff491 1467 if (likely(ctxbi->skb &&
b3821cc5 1468 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1469
cd0ff491 1470 tx_dbg(jme, "txclean: %d+%d@%lu\n",
52a46ba8 1471 i, ctxbi->nr_desc, jiffies);
3bf61c55 1472
cd0ff491 1473 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1474
cd0ff491 1475 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1476 ttxbi = txbi + ((i + j) & (mask));
1477 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1478
b3821cc5 1479 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1480 ttxbi->mapping,
1481 ttxbi->len,
1482 PCI_DMA_TODEVICE);
1483
3bf61c55
GFT		 1484 ttxbi->mapping = 0;
1485 ttxbi->len = 0;
1486 }
1487
1488 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1489
1490 cnt += ctxbi->nr_desc;
1491
cd0ff491 1492 if (unlikely(err)) {
8c198884 1493 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1494 } else {
8c198884 1495 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1496 NET_STAT(jme).tx_bytes += ctxbi->len;
1497 }
1498
1499 ctxbi->skb = NULL;
1500 ctxbi->len = 0;
cdcdc9eb 1501 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1502
1503 } else {
3bf61c55
GFT		 1504 break;
1505 }
1506
b3821cc5 1507 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1508
1509 ctxbi->nr_desc = 0;
d7699f87
GFT		 1510 }
1511
52a46ba8 1512 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1513 atomic_set(&txring->next_to_clean, i);
79ce639c 1514 atomic_add(cnt, &txring->nr_free);
3bf61c55 1515
b3821cc5
GFT		 1516 jme_wake_queue_if_stopped(jme);
1517
fcf45b4c
GFT		 1518out:
1519 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1520}
1521
79ce639c 1522static void
cd0ff491 1523jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1524{
3bf61c55
GFT		 1525 /*
1526 * Disable interrupt
1527 */
1528 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1529
cd0ff491 1530 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1531 /*
1532 * Link change event is critical
1533 * all other events are ignored
1534 */
1535 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1536 tasklet_schedule(&jme->linkch_task);
29bdd921 1537 goto out_reenable;
fcf45b4c 1538 }
d7699f87 1539
cd0ff491 1540 if (intrstat & INTR_TMINTR) {
47220951 1541 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1542 tasklet_schedule(&jme->pcc_task);
47220951 1543 }
79ce639c 1544
cd0ff491 1545 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1546 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1547 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1548 }
1549
cd0ff491 1550 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1551 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1552 INTR_PCCRX0 |
1553 INTR_RX0EMP)) |
1554 INTR_RX0);
1555 }
d7699f87 1556
cd0ff491
GFT		 1557 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1558 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1559 atomic_inc(&jme->rx_empty);
1560
cd0ff491
GFT		 1561 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1562 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1563 jme_polling_mode(jme);
cdcdc9eb 1564 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1565 }
1566 }
cd0ff491
GFT		 1567 } else {
1568 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1569 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1570 tasklet_hi_schedule(&jme->rxempty_task);
1571 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1572 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1573 }
4330c2f2 1574 }
d7699f87 1575
29bdd921 1576out_reenable:
3bf61c55 1577 /*
fcf45b4c 1578 * Re-enable interrupt
3bf61c55 1579 */
fcf45b4c 1580 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1581}
1582
1583static irqreturn_t
1584jme_intr(int irq, void *dev_id)
1585{
cd0ff491
GFT		 1586 struct net_device *netdev = dev_id;
1587 struct jme_adapter *jme = netdev_priv(netdev);
1588 u32 intrstat;
79ce639c
GFT		 1589
1590 intrstat = jread32(jme, JME_IEVE);
1591
1592 /*
1593 * Check if it's really an interrupt for us
1594 */
9b9d55de 1595 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1596 return IRQ_NONE;
79ce639c
GFT		 1597
1598 /*
1599 * Check if the device still exist
1600 */
cd0ff491
GFT		 1601 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1602 return IRQ_NONE;
79ce639c
GFT		 1603
1604 jme_intr_msi(jme, intrstat);
1605
cd0ff491 1606 return IRQ_HANDLED;
d7699f87
GFT		 1607}
1608
79ce639c
GFT		 1609static irqreturn_t
1610jme_msi(int irq, void *dev_id)
1611{
cd0ff491
GFT		 1612 struct net_device *netdev = dev_id;
1613 struct jme_adapter *jme = netdev_priv(netdev);
1614 u32 intrstat;
79ce639c 1615
fa97b924 1616 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1617
1618 jme_intr_msi(jme, intrstat);
1619
cd0ff491 1620 return IRQ_HANDLED;
79ce639c
GFT		 1621}
1622
79ce639c
GFT		 1623static void
1624jme_reset_link(struct jme_adapter *jme)
1625{
1626 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1627}
1628
fcf45b4c
GFT		 1629static void
1630jme_restart_an(struct jme_adapter *jme)
1631{
cd0ff491 1632 u32 bmcr;
fcf45b4c 1633
cd0ff491 1634 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1635 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1636 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1637 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1638 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1639}
1640
1641static int
1642jme_request_irq(struct jme_adapter *jme)
1643{
1644 int rc;
cd0ff491
GFT		 1645 struct net_device *netdev = jme->dev;
1646 irq_handler_t handler = jme_intr;
1647 int irq_flags = IRQF_SHARED;
1648
1649 if (!pci_enable_msi(jme->pdev)) {
1650 set_bit(JME_FLAG_MSI, &jme->flags);
1651 handler = jme_msi;
1652 irq_flags = 0;
1653 }
1654
1655 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1656 netdev);
1657 if (rc) {
52a46ba8
JP		 1658 netdev_err(netdev,
1659 "Unable to request %s interrupt (return: %d)\n",
1660 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1661 rc);
79ce639c 1662
cd0ff491
GFT		 1663 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1664 pci_disable_msi(jme->pdev);
1665 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1666 }
cd0ff491 1667 } else {
79ce639c
GFT		 1668 netdev->irq = jme->pdev->irq;
1669 }
1670
cd0ff491 1671 return rc;
79ce639c
GFT		 1672}
1673
1674static void
1675jme_free_irq(struct jme_adapter *jme)
1676{
cd0ff491
GFT		 1677 free_irq(jme->pdev->irq, jme->dev);
1678 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1679 pci_disable_msi(jme->pdev);
1680 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1681 jme->dev->irq = jme->pdev->irq;
cd0ff491 1682 }
fcf45b4c
GFT		 1683}
1684
e4610a83
GFT		 1685static inline void
1686jme_new_phy_on(struct jme_adapter *jme)
1687{
1688 u32 reg;
1689
1690 reg = jread32(jme, JME_PHY_PWR);
1691 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1692 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1693 jwrite32(jme, JME_PHY_PWR, reg);
1694
1695 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1696 reg &= ~PE1_GPREG0_PBG;
1697 reg |= PE1_GPREG0_ENBG;
1698 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1699}
1700
1701static inline void
1702jme_new_phy_off(struct jme_adapter *jme)
1703{
1704 u32 reg;
1705
1706 reg = jread32(jme, JME_PHY_PWR);
1707 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1708 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1709 jwrite32(jme, JME_PHY_PWR, reg);
1710
1711 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1712 reg &= ~PE1_GPREG0_PBG;
1713 reg |= PE1_GPREG0_PDD3COLD;
1714 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1715}
1716
48db98f7
GFT		 1717static inline void
1718jme_phy_on(struct jme_adapter *jme)
1719{
1720 u32 bmcr;
1721
1722 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1723 bmcr &= ~BMCR_PDOWN;
1724 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
e4610a83
GFT		 1725
1726 if (new_phy_power_ctrl(jme->chip_main_rev))
1727 jme_new_phy_on(jme);
1728}
1729
1730static inline void
1731jme_phy_off(struct jme_adapter *jme)
1732{
1733 u32 bmcr;
1734
1735 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1736 bmcr |= BMCR_PDOWN;
1737 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1738
1739 if (new_phy_power_ctrl(jme->chip_main_rev))
1740 jme_new_phy_off(jme);
48db98f7
GFT		 1741}
1742
3bf61c55
GFT		 1743static int
1744jme_open(struct net_device *netdev)
d7699f87
GFT		 1745{
1746 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1747 int rc;
79ce639c 1748
42b1055e 1749 jme_clear_pm(jme);
cdcdc9eb 1750 JME_NAPI_ENABLE(jme);
d7699f87 1751
fa97b924 1752 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1753 tasklet_enable(&jme->txclean_task);
1754 tasklet_hi_enable(&jme->rxclean_task);
1755 tasklet_hi_enable(&jme->rxempty_task);
1756
79ce639c 1757 rc = jme_request_irq(jme);
cd0ff491 1758 if (rc)
4330c2f2 1759 goto err_out;
79ce639c 1760
d7699f87 1761 jme_start_irq(jme);
42b1055e 1762
e4610a83
GFT		 1763 jme_phy_on(jme);
1764 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1765 jme_set_settings(netdev, &jme->old_ecmd);
e4610a83 1766 else
42b1055e
GFT		 1767 jme_reset_phy_processor(jme);
1768
29bdd921 1769 jme_reset_link(jme);
d7699f87
GFT		 1770
1771 return 0;
1772
d7699f87
GFT		 1773err_out:
1774 netif_stop_queue(netdev);
1775 netif_carrier_off(netdev);
4330c2f2 1776 return rc;
d7699f87
GFT		 1777}
1778
42b1055e
GFT		 1779static void
1780jme_set_100m_half(struct jme_adapter *jme)
1781{
cd0ff491 1782 u32 bmcr, tmp;
42b1055e 1783
fba4bc0c 1784 jme_phy_on(jme);
42b1055e
GFT		 1785 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1786 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1787 BMCR_SPEED1000 | BMCR_FULLDPLX);
1788 tmp |= BMCR_SPEED100;
1789
1790 if (bmcr != tmp)
1791 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1792
cd0ff491 1793 if (jme->fpgaver)
cdcdc9eb
GFT		 1794 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1795 else
1796 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1797}
1798
47220951
GFT		 1799#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1800static void
1801jme_wait_link(struct jme_adapter *jme)
1802{
cd0ff491 1803 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1804
1805 mdelay(1000);
1806 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1807 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1808 mdelay(10);
1809 phylink = jme_linkstat_from_phy(jme);
1810 }
1811}
1812
fba4bc0c
GFT		 1813static void
1814jme_powersave_phy(struct jme_adapter *jme)
1815{
1816 if (jme->reg_pmcs) {
1817 jme_set_100m_half(jme);
1818
1819 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1820 jme_wait_link(jme);
1821
1822 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1823 } else {
1824 jme_phy_off(jme);
1825 }
1826}
1827
3bf61c55
GFT		 1828static int
1829jme_close(struct net_device *netdev)
d7699f87
GFT		 1830{
1831 struct jme_adapter *jme = netdev_priv(netdev);
1832
1833 netif_stop_queue(netdev);
1834 netif_carrier_off(netdev);
1835
1836 jme_stop_irq(jme);
79ce639c 1837 jme_free_irq(jme);
d7699f87 1838
cdcdc9eb 1839 JME_NAPI_DISABLE(jme);
192570e0 1840
fa97b924
GFT		 1841 tasklet_disable(&jme->linkch_task);
1842 tasklet_disable(&jme->txclean_task);
1843 tasklet_disable(&jme->rxclean_task);
1844 tasklet_disable(&jme->rxempty_task);
8c198884 1845
cd0ff491
GFT		 1846 jme_disable_rx_engine(jme);
1847 jme_disable_tx_engine(jme);
8c198884 1848 jme_reset_mac_processor(jme);
d7699f87
GFT		 1849 jme_free_rx_resources(jme);
1850 jme_free_tx_resources(jme);
42b1055e 1851 jme->phylink = 0;
b3821cc5
GFT		 1852 jme_phy_off(jme);
1853
1854 return 0;
1855}
1856
1857static int
1858jme_alloc_txdesc(struct jme_adapter *jme,
1859 struct sk_buff *skb)
1860{
fa97b924 1861 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1862 int idx, nr_alloc, mask = jme->tx_ring_mask;
1863
1864 idx = txring->next_to_use;
1865 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1866
cd0ff491 1867 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1868 return -1;
1869
1870 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1871
b3821cc5
GFT		 1872 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1873
1874 return idx;
1875}
1876
1877static void
1878jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1879 struct txdesc *txdesc,
b3821cc5
GFT		 1880 struct jme_buffer_info *txbi,
1881 struct page *page,
cd0ff491
GFT		 1882 u32 page_offset,
1883 u32 len,
1884 u8 hidma)
b3821cc5
GFT		 1885{
1886 dma_addr_t dmaaddr;
1887
1888 dmaaddr = pci_map_page(pdev,
1889 page,
1890 page_offset,
1891 len,
1892 PCI_DMA_TODEVICE);
1893
1894 pci_dma_sync_single_for_device(pdev,
1895 dmaaddr,
1896 len,
1897 PCI_DMA_TODEVICE);
1898
1899 txdesc->dw[0] = 0;
1900 txdesc->dw[1] = 0;
1901 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1902 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1903 txdesc->desc2.datalen = cpu_to_le16(len);
1904 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1905 txdesc->desc2.bufaddrl = cpu_to_le32(
1906 (__u64)dmaaddr & 0xFFFFFFFFUL);
1907
1908 txbi->mapping = dmaaddr;
1909 txbi->len = len;
1910}
1911
1912static void
1913jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1914{
fa97b924 1915 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1916 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1917 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1918 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1919 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1920 int mask = jme->tx_ring_mask;
1921 struct skb_frag_struct *frag;
cd0ff491 1922 u32 len;
b3821cc5 1923
cd0ff491
GFT		 1924 for (i = 0 ; i < nr_frags ; ++i) {
1925 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1926 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1927 ctxbi = txbi + ((idx + i + 2) & (mask));
1928
1929 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1930 frag->page_offset, frag->size, hidma);
42b1055e 1931 }
b3821cc5 1932
cd0ff491 1933 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 1934 ctxdesc = txdesc + ((idx + 1) & (mask));
1935 ctxbi = txbi + ((idx + 1) & (mask));
1936 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1937 offset_in_page(skb->data), len, hidma);
1938
1939}
1940
1941static int
1942jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1943{
cd0ff491 1944 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT		 1945 skb_header_cloned(skb) &&
1946 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1947 dev_kfree_skb(skb);
1948 return -1;
1949 }
1950
1951 return 0;
1952}
1953
1954static int
94c5ea02 1955jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1956{
94c5ea02 1957 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1958 if (*mss) {
b3821cc5
GFT		 1959 *flags |= TXFLAG_LSEN;
1960
cd0ff491 1961 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 1962 struct iphdr *iph = ip_hdr(skb);
1963
1964 iph->check = 0;
cd0ff491 1965 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 1966 iph->daddr, 0,
1967 IPPROTO_TCP,
1968 0);
cd0ff491 1969 } else {
b3821cc5
GFT		 1970 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1971
cd0ff491 1972 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 1973 &ip6h->daddr, 0,
1974 IPPROTO_TCP,
1975 0);
1976 }
1977
1978 return 0;
1979 }
1980
1981 return 1;
1982}
1983
1984static void
cd0ff491 1985jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1986{
cd0ff491
GFT		 1987 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1988 u8 ip_proto;
b3821cc5
GFT		 1989
1990 switch (skb->protocol) {
cd0ff491 1991 case htons(ETH_P_IP):
b3821cc5
GFT		 1992 ip_proto = ip_hdr(skb)->protocol;
1993 break;
cd0ff491 1994 case htons(ETH_P_IPV6):
b3821cc5
GFT		 1995 ip_proto = ipv6_hdr(skb)->nexthdr;
1996 break;
1997 default:
1998 ip_proto = 0;
1999 break;
2000 }
2001
cd0ff491 2002 switch (ip_proto) {
b3821cc5
GFT		 2003 case IPPROTO_TCP:
2004 *flags |= TXFLAG_TCPCS;
2005 break;
2006 case IPPROTO_UDP:
2007 *flags |= TXFLAG_UDPCS;
2008 break;
2009 default:
52a46ba8 2010 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2011 break;
2012 }
2013 }
2014}
2015
cd0ff491 2016static inline void
94c5ea02 2017jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2018{
cd0ff491 2019 if (vlan_tx_tag_present(skb)) {
b3821cc5 2020 *flags |= TXFLAG_TAGON;
94c5ea02 2021 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2022 }
b3821cc5
GFT		 2023}
2024
2025static int
94c5ea02 2026jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2027{
fa97b924 2028 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2029 struct txdesc *txdesc;
b3821cc5 2030 struct jme_buffer_info *txbi;
cd0ff491 2031 u8 flags;
b3821cc5 2032
cd0ff491 2033 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2034 txbi = txring->bufinf + idx;
2035
2036 txdesc->dw[0] = 0;
2037 txdesc->dw[1] = 0;
2038 txdesc->dw[2] = 0;
2039 txdesc->dw[3] = 0;
2040 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2041 /*
2042 * Set OWN bit at final.
2043 * When kernel transmit faster than NIC.
2044 * And NIC trying to send this descriptor before we tell
2045 * it to start sending this TX queue.
2046 * Other fields are already filled correctly.
2047 */
2048 wmb();
2049 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2050 /*
2051 * Set checksum flags while not tso
2052 */
2053 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2054 jme_tx_csum(jme, skb, &flags);
b3821cc5 2055 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 2056 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2057 txdesc->desc1.flags = flags;
2058 /*
2059 * Set tx buffer info after telling NIC to send
2060 * For better tx_clean timing
2061 */
2062 wmb();
2063 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2064 txbi->skb = skb;
2065 txbi->len = skb->len;
cd0ff491
GFT		 2066 txbi->start_xmit = jiffies;
2067 if (!txbi->start_xmit)
8d27293f 2068 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2069
2070 return 0;
2071}
2072
b3821cc5
GFT		 2073static void
2074jme_stop_queue_if_full(struct jme_adapter *jme)
2075{
fa97b924 2076 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2077 struct jme_buffer_info *txbi = txring->bufinf;
2078 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2079
cd0ff491 2080 txbi += idx;
b3821cc5
GFT		 2081
2082 smp_wmb();
cd0ff491 2083 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2084 netif_stop_queue(jme->dev);
52a46ba8 2085 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2086 smp_wmb();
cd0ff491
GFT		 2087 if (atomic_read(&txring->nr_free)
2088 >= (jme->tx_wake_threshold)) {
b3821cc5 2089 netif_wake_queue(jme->dev);
52a46ba8 2090 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2091 }
2092 }
2093
cd0ff491 2094 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2095 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2096 txbi->skb)) {
2097 netif_stop_queue(jme->dev);
52a46ba8
JP		 2098 netif_info(jme, tx_queued, jme->dev,
2099 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2100 }
b3821cc5
GFT		 2101}
2102
3bf61c55
GFT		 2103/*
2104 * This function is already protected by netif_tx_lock()
2105 */
cd0ff491 2106
c97b5740 2107static netdev_tx_t
3bf61c55 2108jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2109{
cd0ff491 2110 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2111 int idx;
d7699f87 2112
cd0ff491 2113 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2114 ++(NET_STAT(jme).tx_dropped);
2115 return NETDEV_TX_OK;
2116 }
2117
2118 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2119
cd0ff491 2120 if (unlikely(idx < 0)) {
b3821cc5 2121 netif_stop_queue(netdev);
52a46ba8
JP		 2122 netif_err(jme, tx_err, jme->dev,
2123 "BUG! Tx ring full when queue awake!\n");
d7699f87 2124
cd0ff491 2125 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2126 }
2127
94c5ea02 2128 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2129
4330c2f2
GFT		 2130 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2131 TXCS_SELECT_QUEUE0 |
2132 TXCS_QUEUE0S |
2133 TXCS_ENABLE);
d7699f87 2134
52a46ba8
JP		 2135 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2136 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2137 jme_stop_queue_if_full(jme);
2138
cd0ff491 2139 return NETDEV_TX_OK;
d7699f87
GFT		 2140}
2141
bb4c5c8c
GFT		 2142static void
2143jme_set_unicastaddr(struct net_device *netdev)
2144{
2145 struct jme_adapter *jme = netdev_priv(netdev);
2146 u32 val;
2147
2148 val = (netdev->dev_addr[3] & 0xff) << 24 |
2149 (netdev->dev_addr[2] & 0xff) << 16 |
2150 (netdev->dev_addr[1] & 0xff) << 8 |
2151 (netdev->dev_addr[0] & 0xff);
2152 jwrite32(jme, JME_RXUMA_LO, val);
2153 val = (netdev->dev_addr[5] & 0xff) << 8 |
2154 (netdev->dev_addr[4] & 0xff);
2155 jwrite32(jme, JME_RXUMA_HI, val);
2156}
2157
3bf61c55
GFT		 2158static int
2159jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2160{
cd0ff491 2161 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2162 struct sockaddr *addr = p;
d7699f87 2163
cd0ff491 2164 if (netif_running(netdev))
d7699f87
GFT		 2165 return -EBUSY;
2166
cd0ff491 2167 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2168 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
bb4c5c8c 2169 jme_set_unicastaddr(netdev);
cd0ff491 2170 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2171
2172 return 0;
2173}
2174
3bf61c55
GFT		 2175static void
2176jme_set_multi(struct net_device *netdev)
d7699f87 2177{
3bf61c55 2178 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2179 u32 mc_hash[2] = {};
d7699f87 2180
cd0ff491 2181 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2182
2183 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2184
cd0ff491 2185 if (netdev->flags & IFF_PROMISC) {
8c198884 2186 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2187 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2188 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2189 } else if (netdev->flags & IFF_MULTICAST) {
d401cb9a 2190 struct netdev_hw_addr *ha;
3bf61c55 2191 int bit_nr;
d7699f87 2192
8c198884 2193 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
d401cb9a
JP		 2194 netdev_for_each_mc_addr(ha, netdev) {
2195 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
cd0ff491
GFT		 2196 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2197 }
d7699f87 2198
4330c2f2
GFT		 2199 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2200 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2201 }
2202
d7699f87 2203 wmb();
8c198884
GFT		 2204 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2205
cd0ff491 2206 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2207}
2208
3bf61c55 2209static int
8c198884 2210jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2211{
cd0ff491 2212 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2213
cd0ff491 2214 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2215 return 0;
2216
cd0ff491
GFT		 2217 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2218 ((new_mtu) < IPV6_MIN_MTU))
2219 return -EINVAL;
79ce639c 2220
cd0ff491 2221 if (new_mtu > 4000) {
79ce639c
GFT		 2222 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2223 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2224 jme_restart_rx_engine(jme);
cd0ff491 2225 } else {
79ce639c
GFT		 2226 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2227 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2228 jme_restart_rx_engine(jme);
2229 }
2230
cd0ff491 2231 netdev->mtu = new_mtu;
aa4d6a67
MM		 2232 netdev_update_features(netdev);
2233
cd0ff491 2234 jme_reset_link(jme);
79ce639c
GFT		 2235
2236 return 0;
d7699f87
GFT		 2237}
2238
8c198884
GFT		 2239static void
2240jme_tx_timeout(struct net_device *netdev)
2241{
cd0ff491 2242 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2243
cdcdc9eb
GFT		 2244 jme->phylink = 0;
2245 jme_reset_phy_processor(jme);
cd0ff491 2246 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2247 jme_set_settings(netdev, &jme->old_ecmd);
2248
8c198884 2249 /*
cdcdc9eb 2250 * Force to Reset the link again
8c198884 2251 */
29bdd921 2252 jme_reset_link(jme);
8c198884
GFT		 2253}
2254
f7f428e4
GFT		 2255static inline void jme_pause_rx(struct jme_adapter *jme)
2256{
2257 atomic_dec(&jme->link_changing);
2258
2259 jme_set_rx_pcc(jme, PCC_OFF);
2260 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2261 JME_NAPI_DISABLE(jme);
2262 } else {
2263 tasklet_disable(&jme->rxclean_task);
2264 tasklet_disable(&jme->rxempty_task);
2265 }
2266}
2267
2268static inline void jme_resume_rx(struct jme_adapter *jme)
2269{
2270 struct dynpcc_info *dpi = &(jme->dpi);
2271
2272 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2273 JME_NAPI_ENABLE(jme);
2274 } else {
2275 tasklet_hi_enable(&jme->rxclean_task);
2276 tasklet_hi_enable(&jme->rxempty_task);
2277 }
2278 dpi->cur = PCC_P1;
2279 dpi->attempt = PCC_P1;
2280 dpi->cnt = 0;
2281 jme_set_rx_pcc(jme, PCC_P1);
2282
2283 atomic_inc(&jme->link_changing);
2284}
2285
42b1055e
GFT		 2286static void
2287jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2288{
2289 struct jme_adapter *jme = netdev_priv(netdev);
2290
f7f428e4 2291 jme_pause_rx(jme);
42b1055e 2292 jme->vlgrp = grp;
f7f428e4 2293 jme_resume_rx(jme);
42b1055e
GFT		 2294}
2295
3bf61c55
GFT		 2296static void
2297jme_get_drvinfo(struct net_device *netdev,
2298 struct ethtool_drvinfo *info)
d7699f87 2299{
cd0ff491 2300 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2301
cd0ff491
GFT		 2302 strcpy(info->driver, DRV_NAME);
2303 strcpy(info->version, DRV_VERSION);
2304 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2305}
2306
8c198884
GFT		 2307static int
2308jme_get_regs_len(struct net_device *netdev)
2309{
cd0ff491 2310 return JME_REG_LEN;
8c198884
GFT		 2311}
2312
2313static void
cd0ff491 2314mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2315{
2316 int i;
2317
cd0ff491 2318 for (i = 0 ; i < len ; i += 4)
79ce639c 2319 p[i >> 2] = jread32(jme, reg + i);
186fc259 2320}
8c198884 2321
186fc259 2322static void
cd0ff491 2323mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2324{
2325 int i;
cd0ff491 2326 u16 *p16 = (u16 *)p;
186fc259 2327
cd0ff491 2328 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2329 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2330}
2331
2332static void
2333jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2334{
cd0ff491
GFT		 2335 struct jme_adapter *jme = netdev_priv(netdev);
2336 u32 *p32 = (u32 *)p;
8c198884 2337
186fc259 2338 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2339
2340 regs->version = 1;
2341 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2342
2343 p32 += 0x100 >> 2;
2344 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2345
2346 p32 += 0x100 >> 2;
2347 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2348
2349 p32 += 0x100 >> 2;
2350 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2351
186fc259
GFT		 2352 p32 += 0x100 >> 2;
2353 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2354}
2355
2356static int
2357jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2358{
2359 struct jme_adapter *jme = netdev_priv(netdev);
2360
8c198884
GFT		 2361 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2362 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2363
cd0ff491 2364 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2365 ecmd->use_adaptive_rx_coalesce = false;
2366 ecmd->rx_coalesce_usecs = 0;
2367 ecmd->rx_max_coalesced_frames = 0;
2368 return 0;
2369 }
2370
2371 ecmd->use_adaptive_rx_coalesce = true;
2372
cd0ff491 2373 switch (jme->dpi.cur) {
8c198884
GFT		 2374 case PCC_P1:
2375 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2376 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2377 break;
2378 case PCC_P2:
2379 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2380 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2381 break;
2382 case PCC_P3:
2383 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2384 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2385 break;
2386 default:
2387 break;
2388 }
2389
2390 return 0;
2391}
2392
192570e0
GFT		 2393static int
2394jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2395{
2396 struct jme_adapter *jme = netdev_priv(netdev);
2397 struct dynpcc_info *dpi = &(jme->dpi);
2398
cd0ff491 2399 if (netif_running(netdev))
cdcdc9eb
GFT		 2400 return -EBUSY;
2401
c97b5740
GFT		 2402 if (ecmd->use_adaptive_rx_coalesce &&
2403 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2404 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2405 jme->jme_rx = netif_rx;
2406 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2407 dpi->cur = PCC_P1;
2408 dpi->attempt = PCC_P1;
2409 dpi->cnt = 0;
2410 jme_set_rx_pcc(jme, PCC_P1);
2411 jme_interrupt_mode(jme);
c97b5740
GFT		 2412 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2413 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2414 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2415 jme->jme_rx = netif_receive_skb;
2416 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2417 jme_interrupt_mode(jme);
2418 }
2419
2420 return 0;
2421}
2422
8c198884
GFT		 2423static void
2424jme_get_pauseparam(struct net_device *netdev,
2425 struct ethtool_pauseparam *ecmd)
2426{
2427 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2428 u32 val;
8c198884
GFT		 2429
2430 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2431 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2432
cd0ff491
GFT		 2433 spin_lock_bh(&jme->phy_lock);
2434 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2435 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2436
2437 ecmd->autoneg =
2438 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2439}
2440
2441static int
2442jme_set_pauseparam(struct net_device *netdev,
2443 struct ethtool_pauseparam *ecmd)
2444{
2445 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2446 u32 val;
8c198884 2447
cd0ff491 2448 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2449 (ecmd->tx_pause != 0)) {
2450
cd0ff491 2451 if (ecmd->tx_pause)
8c198884
GFT		 2452 jme->reg_txpfc |= TXPFC_PF_EN;
2453 else
2454 jme->reg_txpfc &= ~TXPFC_PF_EN;
2455
2456 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2457 }
2458
cd0ff491
GFT		 2459 spin_lock_bh(&jme->rxmcs_lock);
2460 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2461 (ecmd->rx_pause != 0)) {
2462
cd0ff491 2463 if (ecmd->rx_pause)
8c198884
GFT		 2464 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2465 else
2466 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2467
2468 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2469 }
cd0ff491 2470 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2471
cd0ff491
GFT		 2472 spin_lock_bh(&jme->phy_lock);
2473 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2474 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2475 (ecmd->autoneg != 0)) {
2476
cd0ff491 2477 if (ecmd->autoneg)
8c198884
GFT		 2478 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2479 else
2480 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2481
b3821cc5
GFT		 2482 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2483 MII_ADVERTISE, val);
8c198884 2484 }
cd0ff491 2485 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2486
2487 return 0;
2488}
2489
29bdd921
GFT		 2490static void
2491jme_get_wol(struct net_device *netdev,
2492 struct ethtool_wolinfo *wol)
2493{
2494 struct jme_adapter *jme = netdev_priv(netdev);
2495
2496 wol->supported = WAKE_MAGIC | WAKE_PHY;
2497
2498 wol->wolopts = 0;
2499
cd0ff491 2500 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2501 wol->wolopts |= WAKE_PHY;
2502
cd0ff491 2503 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2504 wol->wolopts |= WAKE_MAGIC;
2505
2506}
2507
2508static int
2509jme_set_wol(struct net_device *netdev,
2510 struct ethtool_wolinfo *wol)
2511{
2512 struct jme_adapter *jme = netdev_priv(netdev);
2513
cd0ff491 2514 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2515 WAKE_UCAST |
2516 WAKE_MCAST |
2517 WAKE_BCAST |
2518 WAKE_ARP))
2519 return -EOPNOTSUPP;
2520
2521 jme->reg_pmcs = 0;
2522
cd0ff491 2523 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2524 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2525
cd0ff491 2526 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2527 jme->reg_pmcs |= PMCS_MFEN;
2528
cd0ff491 2529 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
45b025cf 2530 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
8ad2ddac 2531
29bdd921
GFT		 2532 return 0;
2533}
b3821cc5 2534
3bf61c55
GFT		 2535static int
2536jme_get_settings(struct net_device *netdev,
2537 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2538{
2539 struct jme_adapter *jme = netdev_priv(netdev);
2540 int rc;
8c198884 2541
cd0ff491 2542 spin_lock_bh(&jme->phy_lock);
d7699f87 2543 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2544 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2545 return rc;
2546}
2547
3bf61c55
GFT		 2548static int
2549jme_set_settings(struct net_device *netdev,
2550 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2551{
2552 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2553 int rc, fdc = 0;
fcf45b4c 2554
035550c9
DD		 2555 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2556 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2557 return -EINVAL;
2558
f79361a6
GFT		 2559 /*
2560 * Check If user changed duplex only while force_media.
2561 * Hardware would not generate link change interrupt.
2562 */
cd0ff491 2563 if (jme->mii_if.force_media &&
79ce639c
GFT		 2564 ecmd->autoneg != AUTONEG_ENABLE &&
2565 (jme->mii_if.full_duplex != ecmd->duplex))
2566 fdc = 1;
2567
cd0ff491 2568 spin_lock_bh(&jme->phy_lock);
d7699f87 2569 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2570 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2571
cd0ff491 2572 if (!rc) {
f79361a6
GFT		 2573 if (fdc)
2574 jme_reset_link(jme);
29bdd921 2575 jme->old_ecmd = *ecmd;
43e4651b
GFT		 2576 set_bit(JME_FLAG_SSET, &jme->flags);
2577 }
2578
2579 return rc;
2580}
2581
2582static int
2583jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2584{
2585 int rc;
2586 struct jme_adapter *jme = netdev_priv(netdev);
2587 struct mii_ioctl_data *mii_data = if_mii(rq);
2588 unsigned int duplex_chg;
2589
2590 if (cmd == SIOCSMIIREG) {
2591 u16 val = mii_data->val_in;
2592 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2593 (val & BMCR_SPEED1000))
2594 return -EINVAL;
2595 }
2596
2597 spin_lock_bh(&jme->phy_lock);
2598 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2599 spin_unlock_bh(&jme->phy_lock);
2600
2601 if (!rc && (cmd == SIOCSMIIREG)) {
2602 if (duplex_chg)
2603 jme_reset_link(jme);
2604 jme_get_settings(netdev, &jme->old_ecmd);
2605 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2606 }
2607
d7699f87
GFT		 2608 return rc;
2609}
2610
cd0ff491 2611static u32
3bf61c55
GFT		 2612jme_get_link(struct net_device *netdev)
2613{
d7699f87
GFT		 2614 struct jme_adapter *jme = netdev_priv(netdev);
2615 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2616}
2617
8c198884 2618static u32
cd0ff491
GFT		 2619jme_get_msglevel(struct net_device *netdev)
2620{
2621 struct jme_adapter *jme = netdev_priv(netdev);
2622 return jme->msg_enable;
2623}
2624
2625static void
2626jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2627{
cd0ff491
GFT		 2628 struct jme_adapter *jme = netdev_priv(netdev);
2629 jme->msg_enable = value;
2630}
8c198884 2631
cd0ff491 2632static u32
aa4d6a67 2633jme_fix_features(struct net_device *netdev, u32 features)
cd0ff491 2634{
aa4d6a67
MM		 2635 if (netdev->mtu > 1900)
2636 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2637 return features;
8c198884
GFT		 2638}
2639
2640static int
aa4d6a67 2641jme_set_features(struct net_device *netdev, u32 features)
8c198884 2642{
cd0ff491 2643 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2644
cd0ff491 2645 spin_lock_bh(&jme->rxmcs_lock);
aa4d6a67 2646 if (features & NETIF_F_RXCSUM)
8c198884
GFT		 2647 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2648 else
2649 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2650 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2651 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2652
2653 return 0;
2654}
2655
8c198884
GFT		 2656static int
2657jme_nway_reset(struct net_device *netdev)
2658{
cd0ff491 2659 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2660 jme_restart_an(jme);
2661 return 0;
2662}
2663
cd0ff491 2664static u8
186fc259
GFT		 2665jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2666{
cd0ff491 2667 u32 val;
186fc259
GFT		 2668 int to;
2669
2670 val = jread32(jme, JME_SMBCSR);
2671 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2672 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2673 msleep(1);
2674 val = jread32(jme, JME_SMBCSR);
2675 }
cd0ff491 2676 if (!to) {
52a46ba8 2677 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2678 return 0xFF;
2679 }
2680
2681 jwrite32(jme, JME_SMBINTF,
2682 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2683 SMBINTF_HWRWN_READ |
2684 SMBINTF_HWCMD);
2685
2686 val = jread32(jme, JME_SMBINTF);
2687 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2688 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2689 msleep(1);
2690 val = jread32(jme, JME_SMBINTF);
2691 }
cd0ff491 2692 if (!to) {
52a46ba8 2693 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2694 return 0xFF;
2695 }
2696
2697 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2698}
2699
2700static void
cd0ff491 2701jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2702{
cd0ff491 2703 u32 val;
186fc259
GFT		 2704 int to;
2705
2706 val = jread32(jme, JME_SMBCSR);
2707 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2708 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2709 msleep(1);
2710 val = jread32(jme, JME_SMBCSR);
2711 }
cd0ff491 2712 if (!to) {
52a46ba8 2713 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2714 return;
2715 }
2716
2717 jwrite32(jme, JME_SMBINTF,
2718 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2719 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2720 SMBINTF_HWRWN_WRITE |
2721 SMBINTF_HWCMD);
2722
2723 val = jread32(jme, JME_SMBINTF);
2724 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2725 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2726 msleep(1);
2727 val = jread32(jme, JME_SMBINTF);
2728 }
cd0ff491 2729 if (!to) {
52a46ba8 2730 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2731 return;
2732 }
2733
2734 mdelay(2);
2735}
2736
2737static int
2738jme_get_eeprom_len(struct net_device *netdev)
2739{
cd0ff491
GFT		 2740 struct jme_adapter *jme = netdev_priv(netdev);
2741 u32 val;
186fc259 2742 val = jread32(jme, JME_SMBCSR);
cd0ff491 2743 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2744}
2745
2746static int
2747jme_get_eeprom(struct net_device *netdev,
2748 struct ethtool_eeprom *eeprom, u8 *data)
2749{
cd0ff491 2750 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2751 int i, offset = eeprom->offset, len = eeprom->len;
2752
2753 /*
8d27293f 2754 * ethtool will check the boundary for us
186fc259
GFT		 2755 */
2756 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2757 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2758 data[i] = jme_smb_read(jme, i + offset);
2759
2760 return 0;
2761}
2762
2763static int
2764jme_set_eeprom(struct net_device *netdev,
2765 struct ethtool_eeprom *eeprom, u8 *data)
2766{
cd0ff491 2767 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2768 int i, offset = eeprom->offset, len = eeprom->len;
2769
2770 if (eeprom->magic != JME_EEPROM_MAGIC)
2771 return -EINVAL;
2772
2773 /*
8d27293f 2774 * ethtool will check the boundary for us
186fc259 2775 */
cd0ff491 2776 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2777 jme_smb_write(jme, i + offset, data[i]);
2778
2779 return 0;
2780}
2781
d7699f87 2782static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2783 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2784 .get_regs_len = jme_get_regs_len,
2785 .get_regs = jme_get_regs,
2786 .get_coalesce = jme_get_coalesce,
192570e0 2787 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2788 .get_pauseparam = jme_get_pauseparam,
2789 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2790 .get_wol = jme_get_wol,
2791 .set_wol = jme_set_wol,
d7699f87
GFT		 2792 .get_settings = jme_get_settings,
2793 .set_settings = jme_set_settings,
2794 .get_link = jme_get_link,
cd0ff491
GFT		 2795 .get_msglevel = jme_get_msglevel,
2796 .set_msglevel = jme_set_msglevel,
8c198884 2797 .nway_reset = jme_nway_reset,
186fc259
GFT		 2798 .get_eeprom_len = jme_get_eeprom_len,
2799 .get_eeprom = jme_get_eeprom,
2800 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2801};
2802
3bf61c55
GFT		 2803static int
2804jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2805{
94c5ea02 2806 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2807 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2808 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT		 2809 return 1;
2810
94c5ea02 2811 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2812 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2813 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT		 2814 return 1;
2815
fa97b924
GFT		 2816 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2817 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT		 2818 return 0;
2819
2820 return -1;
2821}
2822
cd0ff491 2823static inline void
cdcdc9eb
GFT		 2824jme_phy_init(struct jme_adapter *jme)
2825{
cd0ff491 2826 u16 reg26;
cdcdc9eb
GFT		 2827
2828 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2829 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2830}
2831
cd0ff491 2832static inline void
cdcdc9eb 2833jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2834{
cd0ff491 2835 u32 chipmode;
cdcdc9eb
GFT		 2836
2837 chipmode = jread32(jme, JME_CHIPMODE);
2838
2839 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2840 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
4400ae98
GFT		 2841 jme->chip_main_rev = jme->chiprev & 0xF;
2842 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 2843}
2844
94c5ea02
GFT		 2845static const struct net_device_ops jme_netdev_ops = {
2846 .ndo_open = jme_open,
2847 .ndo_stop = jme_close,
2848 .ndo_validate_addr = eth_validate_addr,
43e4651b 2849 .ndo_do_ioctl = jme_ioctl,
94c5ea02
GFT		 2850 .ndo_start_xmit = jme_start_xmit,
2851 .ndo_set_mac_address = jme_set_macaddr,
2852 .ndo_set_multicast_list = jme_set_multi,
2853 .ndo_change_mtu = jme_change_mtu,
2854 .ndo_tx_timeout = jme_tx_timeout,
2855 .ndo_vlan_rx_register = jme_vlan_rx_register,
aa4d6a67
MM		 2856 .ndo_fix_features = jme_fix_features,
2857 .ndo_set_features = jme_set_features,
94c5ea02
GFT		 2858};
2859
3bf61c55
GFT		 2860static int __devinit
2861jme_init_one(struct pci_dev *pdev,
2862 const struct pci_device_id *ent)
2863{
cdcdc9eb 2864 int rc = 0, using_dac, i;
d7699f87
GFT		 2865 struct net_device *netdev;
2866 struct jme_adapter *jme;
cd0ff491
GFT		 2867 u16 bmcr, bmsr;
2868 u32 apmc;
d7699f87
GFT		 2869
2870 /*
2871 * set up PCI device basics
2872 */
4330c2f2 2873 rc = pci_enable_device(pdev);
cd0ff491 2874 if (rc) {
52a46ba8 2875 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 2876 goto err_out;
2877 }
d7699f87 2878
3bf61c55 2879 using_dac = jme_pci_dma64(pdev);
cd0ff491 2880 if (using_dac < 0) {
52a46ba8 2881 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 2882 rc = -EIO;
2883 goto err_out_disable_pdev;
2884 }
2885
cd0ff491 2886 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
52a46ba8 2887 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 2888 rc = -ENOMEM;
2889 goto err_out_disable_pdev;
2890 }
d7699f87 2891
4330c2f2 2892 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2893 if (rc) {
52a46ba8 2894 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 2895 goto err_out_disable_pdev;
2896 }
d7699f87
GFT		 2897
2898 pci_set_master(pdev);
2899
2900 /*
2901 * alloc and init net device
2902 */
3bf61c55 2903 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2904 if (!netdev) {
52a46ba8 2905 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT		 2906 rc = -ENOMEM;
2907 goto err_out_release_regions;
d7699f87 2908 }
94c5ea02 2909 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2910 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2911 netdev->watchdog_timeo = TX_TIMEOUT;
aa4d6a67
MM		 2912 netdev->hw_features = NETIF_F_IP_CSUM |
2913 NETIF_F_IPV6_CSUM |
2914 NETIF_F_SG |
2915 NETIF_F_TSO |
2916 NETIF_F_TSO6 |
2917 NETIF_F_RXCSUM;
9a08cd10
MM		 2918 netdev->features = NETIF_F_IP_CSUM |
2919 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 2920 NETIF_F_SG |
2921 NETIF_F_TSO |
2922 NETIF_F_TSO6 |
42b1055e
GFT		 2923 NETIF_F_HW_VLAN_TX |
2924 NETIF_F_HW_VLAN_RX;
cd0ff491 2925 if (using_dac)
8c198884 2926 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 2927
2928 SET_NETDEV_DEV(netdev, &pdev->dev);
2929 pci_set_drvdata(pdev, netdev);
2930
2931 /*
2932 * init adapter info
2933 */
2934 jme = netdev_priv(netdev);
2935 jme->pdev = pdev;
2936 jme->dev = netdev;
cdcdc9eb
GFT		 2937 jme->jme_rx = netif_rx;
2938 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2939 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2940 jme->phylink = 0;
b3821cc5
GFT		 2941 jme->tx_ring_size = 1 << 10;
2942 jme->tx_ring_mask = jme->tx_ring_size - 1;
2943 jme->tx_wake_threshold = 1 << 9;
2944 jme->rx_ring_size = 1 << 9;
2945 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2946 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 2947 jme->regs = ioremap(pci_resource_start(pdev, 0),
2948 pci_resource_len(pdev, 0));
4330c2f2 2949 if (!(jme->regs)) {
52a46ba8 2950 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 2951 rc = -ENOMEM;
2952 goto err_out_free_netdev;
2953 }
4330c2f2 2954
cd0ff491
GFT		 2955 if (no_pseudohp) {
2956 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2957 jwrite32(jme, JME_APMC, apmc);
2958 } else if (force_pseudohp) {
2959 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2960 jwrite32(jme, JME_APMC, apmc);
2961 }
2962
cdcdc9eb 2963 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2964
d7699f87 2965 spin_lock_init(&jme->phy_lock);
fcf45b4c 2966 spin_lock_init(&jme->macaddr_lock);
8c198884 2967 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2968
fcf45b4c
GFT		 2969 atomic_set(&jme->link_changing, 1);
2970 atomic_set(&jme->rx_cleaning, 1);
2971 atomic_set(&jme->tx_cleaning, 1);
192570e0 2972 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2973
79ce639c 2974 tasklet_init(&jme->pcc_task,
c97b5740 2975 jme_pcc_tasklet,
79ce639c 2976 (unsigned long) jme);
4330c2f2 2977 tasklet_init(&jme->linkch_task,
c97b5740 2978 jme_link_change_tasklet,
4330c2f2
GFT		 2979 (unsigned long) jme);
2980 tasklet_init(&jme->txclean_task,
c97b5740 2981 jme_tx_clean_tasklet,
4330c2f2
GFT		 2982 (unsigned long) jme);
2983 tasklet_init(&jme->rxclean_task,
c97b5740 2984 jme_rx_clean_tasklet,
4330c2f2 2985 (unsigned long) jme);
fcf45b4c 2986 tasklet_init(&jme->rxempty_task,
c97b5740 2987 jme_rx_empty_tasklet,
fcf45b4c 2988 (unsigned long) jme);
fa97b924 2989 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 2990 tasklet_disable_nosync(&jme->txclean_task);
2991 tasklet_disable_nosync(&jme->rxclean_task);
2992 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 2993 jme->dpi.cur = PCC_P1;
2994
cd0ff491 2995 jme->reg_ghc = 0;
79ce639c 2996 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 2997 jme->reg_rxmcs = RXMCS_DEFAULT;
2998 jme->reg_txpfc = 0;
47220951 2999 jme->reg_pmcs = PMCS_MFEN;
ed830419 3000 jme->reg_gpreg1 = GPREG1_DEFAULT;
aa4d6a67 3001
45b025cf
GFT		 3002 jme_clear_pm(jme);
3003 pci_set_power_state(jme->pdev, PCI_D0);
3004 device_set_wakeup_enable(&pdev->dev, true);
3005
aa4d6a67
MM		 3006 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3007 netdev->features |= NETIF_F_RXCSUM;
192570e0 3008
fcf45b4c
GFT		 3009 /*
3010 * Get Max Read Req Size from PCI Config Space
3011 */
cd0ff491
GFT		 3012 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3013 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3014 switch (jme->mrrs) {
3015 case MRRS_128B:
3016 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3017 break;
3018 case MRRS_256B:
3019 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3020 break;
3021 default:
3022 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3023 break;
06527f9b 3024 }
fcf45b4c 3025
d7699f87 3026 /*
cdcdc9eb 3027 * Must check before reset_mac_processor
d7699f87 3028 */
cdcdc9eb
GFT		 3029 jme_check_hw_ver(jme);
3030 jme->mii_if.dev = netdev;
cd0ff491 3031 if (jme->fpgaver) {
cdcdc9eb 3032 jme->mii_if.phy_id = 0;
cd0ff491 3033 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3034 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3035 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3036 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3037 jme->mii_if.phy_id = i;
3038 break;
3039 }
3040 }
3041
cd0ff491 3042 if (!jme->mii_if.phy_id) {
cdcdc9eb 3043 rc = -EIO;
52a46ba8
JP		 3044 pr_err("Can not find phy_id\n");
3045 goto err_out_unmap;
cdcdc9eb
GFT		 3046 }
3047
3048 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3049 } else {
cdcdc9eb
GFT		 3050 jme->mii_if.phy_id = 1;
3051 }
cd0ff491 3052 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3053 jme->mii_if.supports_gmii = true;
3054 else
3055 jme->mii_if.supports_gmii = false;
43e4651b
GFT		 3056 jme->mii_if.phy_id_mask = 0x1F;
3057 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3058 jme->mii_if.mdio_read = jme_mdio_read;
3059 jme->mii_if.mdio_write = jme_mdio_write;
3060
06168a20 3061 jme_set_phyfifo_5level(jme);
6db67aa5 3062 jme->pcirev = pdev->revision;
cd0ff491 3063 if (!jme->fpgaver)
cdcdc9eb 3064 jme_phy_init(jme);
42b1055e 3065 jme_phy_off(jme);
cdcdc9eb
GFT		 3066
3067 /*
3068 * Reset MAC processor and reload EEPROM for MAC Address
3069 */
d7699f87 3070 jme_reset_mac_processor(jme);
4330c2f2 3071 rc = jme_reload_eeprom(jme);
cd0ff491 3072 if (rc) {
52a46ba8 3073 pr_err("Reload eeprom for reading MAC Address error\n");
fa97b924 3074 goto err_out_unmap;
4330c2f2 3075 }
d7699f87
GFT		 3076 jme_load_macaddr(netdev);
3077
d7699f87
GFT		 3078 /*
3079 * Tell stack that we are not ready to work until open()
3080 */
3081 netif_carrier_off(netdev);
d7699f87 3082
4330c2f2 3083 rc = register_netdev(netdev);
cd0ff491 3084 if (rc) {
52a46ba8 3085 pr_err("Cannot register net device\n");
fa97b924 3086 goto err_out_unmap;
4330c2f2 3087 }
d7699f87 3088
4400ae98 3089 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
c97b5740
GFT		 3090 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3091 "JMC250 Gigabit Ethernet" :
3092 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3093 "JMC260 Fast Ethernet" : "Unknown",
3094 (jme->fpgaver != 0) ? " (FPGA)" : "",
3095 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
4400ae98 3096 jme->pcirev, netdev->dev_addr);
d7699f87
GFT		 3097
3098 return 0;
3099
3100err_out_unmap:
3101 iounmap(jme->regs);
3102err_out_free_netdev:
3103 pci_set_drvdata(pdev, NULL);
3104 free_netdev(netdev);
4330c2f2
GFT		 3105err_out_release_regions:
3106 pci_release_regions(pdev);
d7699f87 3107err_out_disable_pdev:
cd0ff491 3108 pci_disable_device(pdev);
d7699f87 3109err_out:
4330c2f2 3110 return rc;
d7699f87
GFT		 3111}
3112
3bf61c55
GFT		 3113static void __devexit
3114jme_remove_one(struct pci_dev *pdev)
3115{
d7699f87
GFT		 3116 struct net_device *netdev = pci_get_drvdata(pdev);
3117 struct jme_adapter *jme = netdev_priv(netdev);
3118
3119 unregister_netdev(netdev);
3120 iounmap(jme->regs);
3121 pci_set_drvdata(pdev, NULL);
3122 free_netdev(netdev);
3123 pci_release_regions(pdev);
3124 pci_disable_device(pdev);
3125
3126}
3127
fba4bc0c
GFT		 3128static void
3129jme_shutdown(struct pci_dev *pdev)
3130{
3131 struct net_device *netdev = pci_get_drvdata(pdev);
3132 struct jme_adapter *jme = netdev_priv(netdev);
3133
45b025cf
GFT		 3134 if (jme->reg_pmcs) {
3135 jme_powersave_phy(jme);
3136 jme_clear_pm(jme);
3137 pci_pme_active(pdev, true);
3138 } else {
3139 jme_phy_off(jme);
3140 }
fba4bc0c
GFT		 3141}
3142
e10cd037 3143#ifdef CONFIG_PM_SLEEP
45b025cf
GFT		 3144static int
3145jme_suspend(struct device *dev)
29bdd921 3146{
8ad2ddac 3147 struct pci_dev *pdev = to_pci_dev(dev);
29bdd921
GFT		 3148 struct net_device *netdev = pci_get_drvdata(pdev);
3149 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3150
3151 atomic_dec(&jme->link_changing);
3152
3153 netif_device_detach(netdev);
3154 netif_stop_queue(netdev);
3155 jme_stop_irq(jme);
29bdd921 3156
cd0ff491
GFT		 3157 tasklet_disable(&jme->txclean_task);
3158 tasklet_disable(&jme->rxclean_task);
3159 tasklet_disable(&jme->rxempty_task);
3160
cd0ff491
GFT		 3161 if (netif_carrier_ok(netdev)) {
3162 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3163 jme_polling_mode(jme);
3164
29bdd921 3165 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3166 jme_disable_rx_engine(jme);
3167 jme_disable_tx_engine(jme);
29bdd921
GFT		 3168 jme_reset_mac_processor(jme);
3169 jme_free_rx_resources(jme);
3170 jme_free_tx_resources(jme);
3171 netif_carrier_off(netdev);
3172 jme->phylink = 0;
3173 }
3174
cd0ff491
GFT		 3175 tasklet_enable(&jme->txclean_task);
3176 tasklet_hi_enable(&jme->rxclean_task);
3177 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3178
fba4bc0c 3179 jme_powersave_phy(jme);
45b025cf 3180 jme_clear_pm(jme);
29bdd921
GFT		 3181
3182 return 0;
3183}
3184
45b025cf
GFT		 3185static int
3186jme_resume(struct device *dev)
29bdd921 3187{
8ad2ddac 3188 struct pci_dev *pdev = to_pci_dev(dev);
29bdd921
GFT		 3189 struct net_device *netdev = pci_get_drvdata(pdev);
3190 struct jme_adapter *jme = netdev_priv(netdev);
3191
45b025cf 3192 jme_clear_pm(jme);
e4610a83
GFT		 3193 jme_phy_on(jme);
3194 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3195 jme_set_settings(netdev, &jme->old_ecmd);
e4610a83 3196 else
29bdd921
GFT		 3197 jme_reset_phy_processor(jme);
3198
29bdd921
GFT		 3199 jme_start_irq(jme);
3200 netif_device_attach(netdev);
3201
3202 atomic_inc(&jme->link_changing);
3203
3204 jme_reset_link(jme);
3205
3206 return 0;
3207}
8ad2ddac
RW		 3208
3209static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3210#define JME_PM_OPS (&jme_pm_ops)
3211
3212#else
3213
3214#define JME_PM_OPS NULL
9b9d55de 3215#endif
29bdd921 3216
c97b5740 3217static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
cd0ff491
GFT		 3218 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3219 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3220 { }
3221};
3222
3223static struct pci_driver jme_driver = {
cd0ff491
GFT		 3224 .name = DRV_NAME,
3225 .id_table = jme_pci_tbl,
3226 .probe = jme_init_one,
3227 .remove = __devexit_p(jme_remove_one),
fba4bc0c 3228 .shutdown = jme_shutdown,
8ad2ddac 3229 .driver.pm = JME_PM_OPS,
d7699f87
GFT		 3230};
3231
3bf61c55
GFT		 3232static int __init
3233jme_init_module(void)
d7699f87 3234{
52a46ba8 3235 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3236 return pci_register_driver(&jme_driver);
3237}
3238
3bf61c55
GFT		 3239static void __exit
3240jme_cleanup_module(void)
d7699f87
GFT		 3241{
3242 pci_unregister_driver(&jme_driver);
3243}
3244
3245module_init(jme_init_module);
3246module_exit(jme_cleanup_module);
3247
3bf61c55 3248MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3249MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3250MODULE_LICENSE("GPL");
3251MODULE_VERSION(DRV_VERSION);
3252MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3253
JMicron Ethernet Linux driver