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jme: Fix unmap error (Causing system freeze)
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
eee57828 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
52a46ba8
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
d7699f87
GFT		 27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/crc32.h>
4330c2f2 35#include <linux/delay.h>
29bdd921 36#include <linux/spinlock.h>
8c198884
GFT		 37#include <linux/in.h>
38#include <linux/ip.h>
79ce639c
GFT		 39#include <linux/ipv6.h>
40#include <linux/tcp.h>
41#include <linux/udp.h>
42b1055e 42#include <linux/if_vlan.h>
6d641c63 43#include <linux/slab.h>
94c5ea02 44#include <net/ip6_checksum.h>
d7699f87
GFT		 45#include "jme.h"
46
cd0ff491
GFT		 47static int force_pseudohp = -1;
48static int no_pseudohp = -1;
49static int no_extplug = -1;
50module_param(force_pseudohp, int, 0);
51MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53module_param(no_pseudohp, int, 0);
54MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55module_param(no_extplug, int, 0);
56MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 58
3bf61c55
GFT		 59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 61{
62 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 64
186fc259 65read_again:
cd0ff491 66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
d7699f87
GFT		 69
70 wmb();
cd0ff491 71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 72 udelay(20);
b3821cc5
GFT		 73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
3bf61c55 75 break;
cd0ff491 76 }
d7699f87 77
cd0ff491 78 if (i == 0) {
52a46ba8 79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 80 return 0;
cd0ff491 81 }
d7699f87 82
cd0ff491 83 if (again--)
186fc259
GFT		 84 goto read_again;
85
cd0ff491 86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 87}
88
3bf61c55
GFT		 89static void
90jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
d7699f87
GFT		 92{
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
3bf61c55
GFT		 96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 99
100 wmb();
cdcdc9eb
GFT		 101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
8d27293f 103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 104 break;
105 }
d7699f87 106
3bf61c55 107 if (i == 0)
52a46ba8 108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 109}
110
cd0ff491 111static inline void
3bf61c55 112jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 113{
cd0ff491 114 u32 val;
3bf61c55
GFT		 115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
8c198884
GFT		 118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 120
cd0ff491 121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 126
fcf45b4c
GFT		 127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 134}
135
b3821cc5
GFT		 136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
0d8a2973 138 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
cd0ff491 153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55 162
ed830419
GFT		 163static inline void
164jme_mac_rxclk_off(struct jme_adapter *jme)
165{
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168}
169
170static inline void
171jme_mac_rxclk_on(struct jme_adapter *jme)
172{
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175}
176
177static inline void
178jme_mac_txclk_off(struct jme_adapter *jme)
179{
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
182}
183
184static inline void
185jme_mac_txclk_on(struct jme_adapter *jme)
186{
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190 else
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
193}
194
195static inline void
196jme_reset_ghc_speed(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_reset_250A2_workaround(struct jme_adapter *jme)
204{
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206 GPREG1_RSSPATCH);
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208}
209
210static inline void
211jme_assert_ghc_reset(struct jme_adapter *jme)
212{
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215}
216
217static inline void
218jme_clear_ghc_reset(struct jme_adapter *jme)
219{
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
222}
223
cd0ff491 224static inline void
3bf61c55
GFT		 225jme_reset_mac_processor(struct jme_adapter *jme)
226{
0d8a2973 227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 228 u32 crc = 0xCDCDCDCD;
229 u32 gpreg0;
b3821cc5
GFT		 230 int i;
231
ed830419
GFT		 232 jme_reset_ghc_speed(jme);
233 jme_reset_250A2_workaround(jme);
234
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
237 udelay(1);
238 jme_assert_ghc_reset(jme);
239 udelay(1);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
242 udelay(1);
243 jme_clear_ghc_reset(jme);
244 udelay(1);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
247 udelay(1);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
cd0ff491
GFT		 250
251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253 jwrite32(jme, JME_RXQDC, 0x00000000);
254 jwrite32(jme, JME_RXNDA, 0x00000000);
255 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257 jwrite32(jme, JME_TXQDC, 0x00000000);
258 jwrite32(jme, JME_TXNDA, 0x00000000);
259
4330c2f2
GFT		 260 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 262 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 263 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 264 if (jme->fpgaver)
cdcdc9eb
GFT		 265 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266 else
267 gpreg0 = GPREG0_DEFAULT;
268 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 269}
270
271static inline void
3bf61c55 272jme_clear_pm(struct jme_adapter *jme)
d7699f87 273{
18783c49 274 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT		 275}
276
3bf61c55
GFT		 277static int
278jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 279{
cd0ff491 280 u32 val;
d7699f87
GFT		 281 int i;
282
283 val = jread32(jme, JME_SMBCSR);
284
cd0ff491 285 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 286 val |= SMBCSR_CNACK;
287 jwrite32(jme, JME_SMBCSR, val);
288 val |= SMBCSR_RELOAD;
289 jwrite32(jme, JME_SMBCSR, val);
290 mdelay(12);
291
cd0ff491 292 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 293 mdelay(1);
294 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
295 break;
296 }
297
cd0ff491 298 if (i == 0) {
52a46ba8 299 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 300 return -EIO;
301 }
302 }
3bf61c55 303
d7699f87
GFT		 304 return 0;
305}
306
3bf61c55
GFT		 307static void
308jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 309{
310 struct jme_adapter *jme = netdev_priv(netdev);
311 unsigned char macaddr[6];
cd0ff491 312 u32 val;
d7699f87 313
cd0ff491 314 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 315 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 316 macaddr[0] = (val >> 0) & 0xFF;
317 macaddr[1] = (val >> 8) & 0xFF;
318 macaddr[2] = (val >> 16) & 0xFF;
319 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 320 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 321 macaddr[4] = (val >> 0) & 0xFF;
322 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 323 memcpy(netdev->dev_addr, macaddr, 6);
324 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 325}
326
cd0ff491 327static inline void
3bf61c55
GFT		 328jme_set_rx_pcc(struct jme_adapter *jme, int p)
329{
cd0ff491 330 switch (p) {
192570e0
GFT		 331 case PCC_OFF:
332 jwrite32(jme, JME_PCCRX0,
333 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
334 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
335 break;
3bf61c55
GFT		 336 case PCC_P1:
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340 break;
341 case PCC_P2:
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345 break;
346 case PCC_P3:
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350 break;
351 default:
352 break;
353 }
192570e0 354 wmb();
3bf61c55 355
cd0ff491 356 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
c97b5740 357 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 358}
359
fcf45b4c 360static void
3bf61c55 361jme_start_irq(struct jme_adapter *jme)
d7699f87 362{
3bf61c55
GFT		 363 register struct dynpcc_info *dpi = &(jme->dpi);
364
365 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 366 dpi->cur = PCC_P1;
367 dpi->attempt = PCC_P1;
368 dpi->cnt = 0;
369
370 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 371 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
372 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 373 PCCTXQ0_EN
374 );
375
d7699f87
GFT		 376 /*
377 * Enable Interrupts
378 */
379 jwrite32(jme, JME_IENS, INTR_ENABLE);
380}
381
cd0ff491 382static inline void
3bf61c55 383jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 384{
385 /*
386 * Disable Interrupts
387 */
cd0ff491 388 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 389}
390
cd0ff491 391static u32
cdcdc9eb
GFT		 392jme_linkstat_from_phy(struct jme_adapter *jme)
393{
cd0ff491 394 u32 phylink, bmsr;
cdcdc9eb
GFT		 395
396 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
397 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 398 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 399 phylink |= PHY_LINK_AUTONEG_COMPLETE;
400
401 return phylink;
402}
403
cd0ff491 404static inline void
06168a20 405jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 406{
407 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
408}
409
410static inline void
06168a20 411jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 412{
413 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
414}
415
fcf45b4c
GFT		 416static int
417jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 418{
419 struct jme_adapter *jme = netdev_priv(netdev);
ed830419 420 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 421 char linkmsg[64];
fcf45b4c 422 int rc = 0;
d7699f87 423
b3821cc5 424 linkmsg[0] = '\0';
cdcdc9eb 425
cd0ff491 426 if (jme->fpgaver)
cdcdc9eb
GFT		 427 phylink = jme_linkstat_from_phy(jme);
428 else
429 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 430
cd0ff491
GFT		 431 if (phylink & PHY_LINK_UP) {
432 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 433 /*
434 * If we did not enable AN
435 * Speed/Duplex Info should be obtained from SMI
436 */
437 phylink = PHY_LINK_UP;
438
439 bmcr = jme_mdio_read(jme->dev,
440 jme->mii_if.phy_id,
441 MII_BMCR);
442
443 phylink |= ((bmcr & BMCR_SPEED1000) &&
444 (bmcr & BMCR_SPEED100) == 0) ?
445 PHY_LINK_SPEED_1000M :
446 (bmcr & BMCR_SPEED100) ?
447 PHY_LINK_SPEED_100M :
448 PHY_LINK_SPEED_10M;
449
450 phylink |= (bmcr & BMCR_FULLDPLX) ?
451 PHY_LINK_DUPLEX : 0;
79ce639c 452
b3821cc5 453 strcat(linkmsg, "Forced: ");
cd0ff491 454 } else {
8c198884
GFT		 455 /*
456 * Keep polling for speed/duplex resolve complete
457 */
cd0ff491 458 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 459 --cnt) {
460
461 udelay(1);
8c198884 462
cd0ff491 463 if (jme->fpgaver)
cdcdc9eb
GFT		 464 phylink = jme_linkstat_from_phy(jme);
465 else
466 phylink = jread32(jme, JME_PHY_LINK);
8c198884 467 }
cd0ff491 468 if (!cnt)
52a46ba8 469 pr_err("Waiting speed resolve timeout\n");
79ce639c 470
b3821cc5 471 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 472 }
473
cd0ff491 474 if (jme->phylink == phylink) {
fcf45b4c
GFT		 475 rc = 1;
476 goto out;
477 }
cd0ff491 478 if (testonly)
fcf45b4c
GFT		 479 goto out;
480
481 jme->phylink = phylink;
482
ed830419
GFT		 483 /*
484 * The speed/duplex setting of jme->reg_ghc already cleared
485 * by jme_reset_mac_processor()
486 */
cd0ff491
GFT		 487 switch (phylink & PHY_LINK_SPEED_MASK) {
488 case PHY_LINK_SPEED_10M:
ed830419 489 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 490 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 491 break;
492 case PHY_LINK_SPEED_100M:
ed830419 493 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 494 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 495 break;
496 case PHY_LINK_SPEED_1000M:
ed830419 497 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 498 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 499 break;
500 default:
501 break;
d7699f87 502 }
d7699f87 503
cd0ff491 504 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 505 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
19bbc546 506 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
ed830419 507 jme->reg_ghc |= GHC_DPX;
cd0ff491 508 } else {
d7699f87 509 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 510 TXMCS_BACKOFF |
511 TXMCS_CARRIERSENSE |
512 TXMCS_COLLISION);
19bbc546 513 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 514 }
9b9d55de 515
ed830419
GFT		 516 jwrite32(jme, JME_GHC, jme->reg_ghc);
517
9b9d55de 518 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
ed830419
GFT		 519 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
520 GPREG1_RSSPATCH);
9b9d55de 521 if (!(phylink & PHY_LINK_DUPLEX))
ed830419 522 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
9b9d55de
GFT		 523 switch (phylink & PHY_LINK_SPEED_MASK) {
524 case PHY_LINK_SPEED_10M:
06168a20 525 jme_set_phyfifo_8level(jme);
ed830419 526 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
9b9d55de
GFT		 527 break;
528 case PHY_LINK_SPEED_100M:
06168a20 529 jme_set_phyfifo_5level(jme);
ed830419 530 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
9b9d55de
GFT		 531 break;
532 case PHY_LINK_SPEED_1000M:
06168a20 533 jme_set_phyfifo_8level(jme);
9b9d55de
GFT		 534 break;
535 default:
536 break;
537 }
538 }
ed830419 539 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 540
94c5ea02
GFT		 541 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
542 "Full-Duplex, " :
543 "Half-Duplex, ");
544 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
545 "MDI-X" :
546 "MDI");
52a46ba8 547 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 548 netif_carrier_on(netdev);
549 } else {
550 if (testonly)
fcf45b4c
GFT		 551 goto out;
552
52a46ba8 553 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 554 jme->phylink = 0;
cd0ff491 555 netif_carrier_off(netdev);
d7699f87 556 }
fcf45b4c
GFT		 557
558out:
559 return rc;
d7699f87
GFT		 560}
561
3bf61c55
GFT		 562static int
563jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 564{
d7699f87
GFT		 565 struct jme_ring *txring = &(jme->txring[0]);
566
567 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 568 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
569 &(txring->dmaalloc),
570 GFP_ATOMIC);
fcf45b4c 571
fa97b924
GFT		 572 if (!txring->alloc)
573 goto err_set_null;
d7699f87
GFT		 574
575 /*
576 * 16 Bytes align
577 */
cd0ff491 578 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 579 RING_DESC_ALIGN);
4330c2f2 580 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 581 txring->next_to_use = 0;
cdcdc9eb 582 atomic_set(&txring->next_to_clean, 0);
b3821cc5 583 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 584
fa97b924
GFT		 585 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
586 jme->tx_ring_size, GFP_ATOMIC);
587 if (unlikely(!(txring->bufinf)))
588 goto err_free_txring;
589
d7699f87 590 /*
b3821cc5 591 * Initialize Transmit Descriptors
d7699f87 592 */
b3821cc5 593 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 594 memset(txring->bufinf, 0,
b3821cc5 595 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 596
597 return 0;
fa97b924
GFT		 598
599err_free_txring:
600 dma_free_coherent(&(jme->pdev->dev),
601 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
602 txring->alloc,
603 txring->dmaalloc);
604
605err_set_null:
606 txring->desc = NULL;
607 txring->dmaalloc = 0;
608 txring->dma = 0;
609 txring->bufinf = NULL;
610
611 return -ENOMEM;
d7699f87
GFT		 612}
613
3bf61c55
GFT		 614static void
615jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 616{
617 int i;
618 struct jme_ring *txring = &(jme->txring[0]);
fa97b924 619 struct jme_buffer_info *txbi;
d7699f87 620
cd0ff491 621 if (txring->alloc) {
fa97b924
GFT		 622 if (txring->bufinf) {
623 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
624 txbi = txring->bufinf + i;
625 if (txbi->skb) {
626 dev_kfree_skb(txbi->skb);
627 txbi->skb = NULL;
628 }
629 txbi->mapping = 0;
630 txbi->len = 0;
631 txbi->nr_desc = 0;
632 txbi->start_xmit = 0;
d7699f87 633 }
fa97b924 634 kfree(txring->bufinf);
d7699f87
GFT		 635 }
636
637 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 638 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 639 txring->alloc,
640 txring->dmaalloc);
3bf61c55
GFT		 641
642 txring->alloc = NULL;
643 txring->desc = NULL;
644 txring->dmaalloc = 0;
645 txring->dma = 0;
fa97b924 646 txring->bufinf = NULL;
d7699f87 647 }
3bf61c55 648 txring->next_to_use = 0;
cdcdc9eb 649 atomic_set(&txring->next_to_clean, 0);
79ce639c 650 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 651}
652
cd0ff491 653static inline void
3bf61c55 654jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 655{
656 /*
657 * Select Queue 0
658 */
659 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 660 wmb();
d7699f87
GFT		 661
662 /*
663 * Setup TX Queue 0 DMA Bass Address
664 */
fcf45b4c 665 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 666 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 667 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 668
669 /*
670 * Setup TX Descptor Count
671 */
b3821cc5 672 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 673
674 /*
675 * Enable TX Engine
676 */
677 wmb();
ed830419 678 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 679 TXCS_SELECT_QUEUE0 |
680 TXCS_ENABLE);
d7699f87 681
ed830419
GFT		 682 /*
683 * Start clock for TX MAC Processor
684 */
685 jme_mac_txclk_on(jme);
d7699f87
GFT		 686}
687
cd0ff491 688static inline void
29bdd921
GFT		 689jme_restart_tx_engine(struct jme_adapter *jme)
690{
691 /*
692 * Restart TX Engine
693 */
694 jwrite32(jme, JME_TXCS, jme->reg_txcs |
695 TXCS_SELECT_QUEUE0 |
696 TXCS_ENABLE);
697}
698
cd0ff491 699static inline void
3bf61c55 700jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 701{
702 int i;
cd0ff491 703 u32 val;
d7699f87
GFT		 704
705 /*
706 * Disable TX Engine
707 */
fcf45b4c 708 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 709 wmb();
d7699f87
GFT		 710
711 val = jread32(jme, JME_TXCS);
cd0ff491 712 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 713 mdelay(1);
d7699f87 714 val = jread32(jme, JME_TXCS);
cd0ff491 715 rmb();
d7699f87
GFT		 716 }
717
cd0ff491 718 if (!i)
52a46ba8 719 pr_err("Disable TX engine timeout\n");
ed830419
GFT		 720
721 /*
722 * Stop clock for TX MAC Processor
723 */
724 jme_mac_txclk_off(jme);
d7699f87
GFT		 725}
726
3bf61c55
GFT		 727static void
728jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 729{
fa97b924 730 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 731 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 732 struct jme_buffer_info *rxbi = rxring->bufinf;
733 rxdesc += i;
734 rxbi += i;
735
736 rxdesc->dw[0] = 0;
737 rxdesc->dw[1] = 0;
3bf61c55 738 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 739 rxdesc->desc1.bufaddrl = cpu_to_le32(
740 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 741 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 742 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 743 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 744 wmb();
3bf61c55 745 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 746}
747
3bf61c55
GFT		 748static int
749jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 750{
751 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 752 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 753 struct sk_buff *skb;
52edb99a 754 dma_addr_t mapping;
4330c2f2 755
79ce639c
GFT		 756 skb = netdev_alloc_skb(jme->dev,
757 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 758 if (unlikely(!skb))
4330c2f2 759 return -ENOMEM;
3bf61c55 760
52edb99a
GFT		 761 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
762 offset_in_page(skb->data), skb_tailroom(skb),
763 PCI_DMA_FROMDEVICE);
764 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
765 dev_kfree_skb(skb);
766 return -ENOMEM;
767 }
768
769 if (likely(rxbi->mapping))
770 pci_unmap_page(jme->pdev, rxbi->mapping,
771 rxbi->len, PCI_DMA_FROMDEVICE);
772
4330c2f2 773 rxbi->skb = skb;
3bf61c55 774 rxbi->len = skb_tailroom(skb);
52edb99a 775 rxbi->mapping = mapping;
4330c2f2
GFT		 776 return 0;
777}
778
3bf61c55
GFT		 779static void
780jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 781{
782 struct jme_ring *rxring = &(jme->rxring[0]);
783 struct jme_buffer_info *rxbi = rxring->bufinf;
784 rxbi += i;
785
cd0ff491 786 if (rxbi->skb) {
b3821cc5 787 pci_unmap_page(jme->pdev,
4330c2f2 788 rxbi->mapping,
3bf61c55 789 rxbi->len,
4330c2f2
GFT		 790 PCI_DMA_FROMDEVICE);
791 dev_kfree_skb(rxbi->skb);
792 rxbi->skb = NULL;
793 rxbi->mapping = 0;
3bf61c55 794 rxbi->len = 0;
4330c2f2
GFT		 795 }
796}
797
3bf61c55
GFT		 798static void
799jme_free_rx_resources(struct jme_adapter *jme)
800{
801 int i;
802 struct jme_ring *rxring = &(jme->rxring[0]);
803
cd0ff491 804 if (rxring->alloc) {
fa97b924
GFT		 805 if (rxring->bufinf) {
806 for (i = 0 ; i < jme->rx_ring_size ; ++i)
807 jme_free_rx_buf(jme, i);
808 kfree(rxring->bufinf);
809 }
3bf61c55
GFT		 810
811 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 812 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 813 rxring->alloc,
814 rxring->dmaalloc);
815 rxring->alloc = NULL;
816 rxring->desc = NULL;
817 rxring->dmaalloc = 0;
818 rxring->dma = 0;
fa97b924 819 rxring->bufinf = NULL;
3bf61c55
GFT		 820 }
821 rxring->next_to_use = 0;
cdcdc9eb 822 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 823}
824
825static int
826jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 827{
828 int i;
829 struct jme_ring *rxring = &(jme->rxring[0]);
830
831 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 832 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
833 &(rxring->dmaalloc),
834 GFP_ATOMIC);
fa97b924
GFT		 835 if (!rxring->alloc)
836 goto err_set_null;
d7699f87
GFT		 837
838 /*
839 * 16 Bytes align
840 */
cd0ff491 841 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 842 RING_DESC_ALIGN);
4330c2f2 843 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 844 rxring->next_to_use = 0;
cdcdc9eb 845 atomic_set(&rxring->next_to_clean, 0);
d7699f87 846
fa97b924
GFT		 847 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
848 jme->rx_ring_size, GFP_ATOMIC);
849 if (unlikely(!(rxring->bufinf)))
850 goto err_free_rxring;
851
d7699f87
GFT		 852 /*
853 * Initiallize Receive Descriptors
854 */
fa97b924
GFT		 855 memset(rxring->bufinf, 0,
856 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 857 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
858 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 859 jme_free_rx_resources(jme);
860 return -ENOMEM;
861 }
d7699f87
GFT		 862
863 jme_set_clean_rxdesc(jme, i);
864 }
865
d7699f87 866 return 0;
fa97b924
GFT		 867
868err_free_rxring:
869 dma_free_coherent(&(jme->pdev->dev),
870 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
871 rxring->alloc,
872 rxring->dmaalloc);
873err_set_null:
874 rxring->desc = NULL;
875 rxring->dmaalloc = 0;
876 rxring->dma = 0;
877 rxring->bufinf = NULL;
878
879 return -ENOMEM;
d7699f87
GFT		 880}
881
cd0ff491 882static inline void
3bf61c55 883jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 884{
cd0ff491
GFT		 885 /*
886 * Select Queue 0
887 */
888 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
889 RXCS_QUEUESEL_Q0);
890 wmb();
891
d7699f87
GFT		 892 /*
893 * Setup RX DMA Bass Address
894 */
fa97b924 895 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 896 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fa97b924 897 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 898
899 /*
b3821cc5 900 * Setup RX Descriptor Count
d7699f87 901 */
b3821cc5 902 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 903
3bf61c55 904 /*
d7699f87
GFT		 905 * Setup Unicast Filter
906 */
bb4c5c8c 907 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 908 jme_set_multi(jme->dev);
909
910 /*
911 * Enable RX Engine
912 */
913 wmb();
ed830419 914 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 915 RXCS_QUEUESEL_Q0 |
916 RXCS_ENABLE |
917 RXCS_QST);
ed830419
GFT		 918
919 /*
920 * Start clock for RX MAC Processor
921 */
922 jme_mac_rxclk_on(jme);
d7699f87
GFT		 923}
924
cd0ff491 925static inline void
3bf61c55 926jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 927{
928 /*
3bf61c55 929 * Start RX Engine
4330c2f2 930 */
79ce639c 931 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 932 RXCS_QUEUESEL_Q0 |
933 RXCS_ENABLE |
934 RXCS_QST);
935}
936
cd0ff491 937static inline void
3bf61c55 938jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 939{
940 int i;
cd0ff491 941 u32 val;
d7699f87
GFT		 942
943 /*
944 * Disable RX Engine
945 */
29bdd921 946 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 947 wmb();
d7699f87
GFT		 948
949 val = jread32(jme, JME_RXCS);
cd0ff491 950 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 951 mdelay(1);
d7699f87 952 val = jread32(jme, JME_RXCS);
cd0ff491 953 rmb();
d7699f87
GFT		 954 }
955
cd0ff491 956 if (!i)
52a46ba8 957 pr_err("Disable RX engine timeout\n");
d7699f87 958
ed830419
GFT		 959 /*
960 * Stop clock for RX MAC Processor
961 */
962 jme_mac_rxclk_off(jme);
d7699f87
GFT		 963}
964
a452eef1
GFT		 965static u16
966jme_udpsum(struct sk_buff *skb)
967{
968 u16 csum = 0xFFFFu;
969
970 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
971 return csum;
972 if (skb->protocol != htons(ETH_P_IP))
973 return csum;
974 skb_set_network_header(skb, ETH_HLEN);
975 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
976 (skb->len < (ETH_HLEN +
977 (ip_hdr(skb)->ihl << 2) +
978 sizeof(struct udphdr)))) {
979 skb_reset_network_header(skb);
980 return csum;
981 }
982 skb_set_transport_header(skb,
983 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
984 csum = udp_hdr(skb)->check;
985 skb_reset_transport_header(skb);
986 skb_reset_network_header(skb);
987
988 return csum;
989}
990
192570e0 991static int
a452eef1 992jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 993{
cd0ff491 994 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 995 return false;
996
fa97b924
GFT		 997 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
998 == RXWBFLAG_TCPON)) {
999 if (flags & RXWBFLAG_IPV4)
c97b5740 1000 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
fa97b924 1001 return false;
192570e0
GFT		 1002 }
1003
fa97b924 1004 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
a452eef1 1005 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
fa97b924 1006 if (flags & RXWBFLAG_IPV4)
52a46ba8 1007 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
fa97b924 1008 return false;
192570e0
GFT		 1009 }
1010
fa97b924
GFT		 1011 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1012 == RXWBFLAG_IPV4)) {
52a46ba8 1013 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
fa97b924 1014 return false;
192570e0
GFT		 1015 }
1016
1017 return true;
1018}
1019
3bf61c55 1020static void
42b1055e 1021jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1022{
d7699f87 1023 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1024 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1025 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1026 struct sk_buff *skb;
3bf61c55 1027 int framesize;
d7699f87 1028
3bf61c55
GFT		 1029 rxdesc += idx;
1030 rxbi += idx;
d7699f87 1031
3bf61c55
GFT		 1032 skb = rxbi->skb;
1033 pci_dma_sync_single_for_cpu(jme->pdev,
1034 rxbi->mapping,
1035 rxbi->len,
1036 PCI_DMA_FROMDEVICE);
1037
cd0ff491 1038 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1039 pci_dma_sync_single_for_device(jme->pdev,
1040 rxbi->mapping,
1041 rxbi->len,
1042 PCI_DMA_FROMDEVICE);
1043
1044 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1045 } else {
3bf61c55
GFT		 1046 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1047 - RX_PREPAD_SIZE;
1048
1049 skb_reserve(skb, RX_PREPAD_SIZE);
1050 skb_put(skb, framesize);
1051 skb->protocol = eth_type_trans(skb, jme->dev);
1052
a452eef1 1053 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1054 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1055 else
97984ab7 1056 skb_checksum_none_assert(skb);
8c198884 1057
94c5ea02 1058 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1059 if (jme->vlgrp) {
cdcdc9eb 1060 jme->jme_vlan_rx(skb, jme->vlgrp,
94c5ea02 1061 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1062 NET_STAT(jme).rx_bytes += 4;
c97b5740 1063 } else {
c97b5740 1064 dev_kfree_skb(skb);
b3821cc5 1065 }
cd0ff491 1066 } else {
cdcdc9eb 1067 jme->jme_rx(skb);
b3821cc5 1068 }
3bf61c55 1069
94c5ea02
GFT		 1070 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1071 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1072 ++(NET_STAT(jme).multicast);
1073
3bf61c55
GFT		 1074 NET_STAT(jme).rx_bytes += framesize;
1075 ++(NET_STAT(jme).rx_packets);
1076 }
1077
1078 jme_set_clean_rxdesc(jme, idx);
1079
1080}
1081
1082static int
1083jme_process_receive(struct jme_adapter *jme, int limit)
1084{
1085 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1086 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1087 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1088
cd0ff491 1089 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1090 goto out_inc;
1091
cd0ff491 1092 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1093 goto out_inc;
1094
cd0ff491 1095 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1096 goto out_inc;
1097
cdcdc9eb 1098 i = atomic_read(&rxring->next_to_clean);
fa97b924 1099 while (limit > 0) {
3bf61c55
GFT		 1100 rxdesc = rxring->desc;
1101 rxdesc += i;
1102
94c5ea02 1103 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1104 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1105 goto out;
fa97b924 1106 --limit;
d7699f87 1107
1a7a122d 1108 rmb();
4330c2f2
GFT		 1109 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1110
cd0ff491 1111 if (unlikely(desccnt > 1 ||
192570e0 1112 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1113
cd0ff491 1114 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1115 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1116 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1117 ++(NET_STAT(jme).rx_fifo_errors);
1118 else
1119 ++(NET_STAT(jme).rx_errors);
4330c2f2 1120
cd0ff491 1121 if (desccnt > 1)
3bf61c55 1122 limit -= desccnt - 1;
4330c2f2 1123
cd0ff491 1124 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1125 jme_set_clean_rxdesc(jme, j);
b3821cc5 1126 j = (j + 1) & (mask);
4330c2f2 1127 }
3bf61c55 1128
cd0ff491 1129 } else {
42b1055e 1130 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1131 }
4330c2f2 1132
b3821cc5 1133 i = (i + desccnt) & (mask);
3bf61c55 1134 }
4330c2f2 1135
3bf61c55 1136out:
cdcdc9eb 1137 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1138
192570e0
GFT		 1139out_inc:
1140 atomic_inc(&jme->rx_cleaning);
1141
3bf61c55 1142 return limit > 0 ? limit : 0;
4330c2f2 1143
3bf61c55 1144}
d7699f87 1145
79ce639c
GFT		 1146static void
1147jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1148{
cd0ff491 1149 if (likely(atmp == dpi->cur)) {
192570e0 1150 dpi->cnt = 0;
79ce639c 1151 return;
192570e0 1152 }
79ce639c 1153
cd0ff491 1154 if (dpi->attempt == atmp) {
79ce639c 1155 ++(dpi->cnt);
cd0ff491 1156 } else {
79ce639c
GFT		 1157 dpi->attempt = atmp;
1158 dpi->cnt = 0;
1159 }
1160
1161}
1162
1163static void
1164jme_dynamic_pcc(struct jme_adapter *jme)
1165{
1166 register struct dynpcc_info *dpi = &(jme->dpi);
1167
cd0ff491 1168 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1169 jme_attempt_pcc(dpi, PCC_P3);
c97b5740
GFT		 1170 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1171 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1172 jme_attempt_pcc(dpi, PCC_P2);
1173 else
1174 jme_attempt_pcc(dpi, PCC_P1);
1175
cd0ff491
GFT		 1176 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1177 if (dpi->attempt < dpi->cur)
1178 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1179 jme_set_rx_pcc(jme, dpi->attempt);
1180 dpi->cur = dpi->attempt;
1181 dpi->cnt = 0;
1182 }
1183}
1184
1185static void
1186jme_start_pcc_timer(struct jme_adapter *jme)
1187{
1188 struct dynpcc_info *dpi = &(jme->dpi);
1189 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1190 dpi->last_pkts = NET_STAT(jme).rx_packets;
1191 dpi->intr_cnt = 0;
1192 jwrite32(jme, JME_TMCSR,
1193 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1194}
1195
cd0ff491 1196static inline void
29bdd921
GFT		 1197jme_stop_pcc_timer(struct jme_adapter *jme)
1198{
1199 jwrite32(jme, JME_TMCSR, 0);
1200}
1201
cd0ff491
GFT		 1202static void
1203jme_shutdown_nic(struct jme_adapter *jme)
1204{
1205 u32 phylink;
1206
1207 phylink = jme_linkstat_from_phy(jme);
1208
1209 if (!(phylink & PHY_LINK_UP)) {
1210 /*
1211 * Disable all interrupt before issue timer
1212 */
1213 jme_stop_irq(jme);
1214 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1215 }
1216}
1217
79ce639c
GFT		 1218static void
1219jme_pcc_tasklet(unsigned long arg)
1220{
cd0ff491 1221 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1222 struct net_device *netdev = jme->dev;
1223
cd0ff491
GFT		 1224 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1225 jme_shutdown_nic(jme);
1226 return;
1227 }
29bdd921 1228
cd0ff491 1229 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1230 (atomic_read(&jme->link_changing) != 1)
1231 )) {
1232 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1233 return;
1234 }
29bdd921 1235
cd0ff491 1236 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1237 jme_dynamic_pcc(jme);
1238
79ce639c
GFT		 1239 jme_start_pcc_timer(jme);
1240}
1241
cd0ff491 1242static inline void
192570e0
GFT		 1243jme_polling_mode(struct jme_adapter *jme)
1244{
1245 jme_set_rx_pcc(jme, PCC_OFF);
1246}
1247
cd0ff491 1248static inline void
192570e0
GFT		 1249jme_interrupt_mode(struct jme_adapter *jme)
1250{
1251 jme_set_rx_pcc(jme, PCC_P1);
1252}
1253
cd0ff491
GFT		 1254static inline int
1255jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1256{
1257 u32 apmc;
1258 apmc = jread32(jme, JME_APMC);
1259 return apmc & JME_APMC_PSEUDO_HP_EN;
1260}
1261
1262static void
1263jme_start_shutdown_timer(struct jme_adapter *jme)
1264{
1265 u32 apmc;
1266
1267 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1268 apmc &= ~JME_APMC_EPIEN_CTRL;
1269 if (!no_extplug) {
1270 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1271 wmb();
1272 }
1273 jwrite32f(jme, JME_APMC, apmc);
1274
1275 jwrite32f(jme, JME_TIMER2, 0);
1276 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1277 jwrite32(jme, JME_TMCSR,
1278 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1279}
1280
1281static void
1282jme_stop_shutdown_timer(struct jme_adapter *jme)
1283{
1284 u32 apmc;
1285
1286 jwrite32f(jme, JME_TMCSR, 0);
1287 jwrite32f(jme, JME_TIMER2, 0);
1288 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1289
1290 apmc = jread32(jme, JME_APMC);
1291 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1292 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1293 wmb();
1294 jwrite32f(jme, JME_APMC, apmc);
1295}
1296
3bf61c55
GFT		 1297static void
1298jme_link_change_tasklet(unsigned long arg)
1299{
cd0ff491 1300 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1301 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1302 int rc;
1303
cd0ff491
GFT		 1304 while (!atomic_dec_and_test(&jme->link_changing)) {
1305 atomic_inc(&jme->link_changing);
52a46ba8 1306 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
e882564f 1307 while (atomic_read(&jme->link_changing) != 1)
52a46ba8 1308 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1309 }
fcf45b4c 1310
cd0ff491 1311 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1312 goto out;
1313
29bdd921 1314 jme->old_mtu = netdev->mtu;
fcf45b4c 1315 netif_stop_queue(netdev);
cd0ff491
GFT		 1316 if (jme_pseudo_hotplug_enabled(jme))
1317 jme_stop_shutdown_timer(jme);
1318
1319 jme_stop_pcc_timer(jme);
1320 tasklet_disable(&jme->txclean_task);
1321 tasklet_disable(&jme->rxclean_task);
1322 tasklet_disable(&jme->rxempty_task);
1323
1324 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1325 jme_disable_rx_engine(jme);
1326 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1327 jme_reset_mac_processor(jme);
1328 jme_free_rx_resources(jme);
1329 jme_free_tx_resources(jme);
192570e0 1330
cd0ff491 1331 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1332 jme_polling_mode(jme);
cd0ff491
GFT		 1333
1334 netif_carrier_off(netdev);
fcf45b4c
GFT		 1335 }
1336
1337 jme_check_link(netdev, 0);
cd0ff491 1338 if (netif_carrier_ok(netdev)) {
fcf45b4c 1339 rc = jme_setup_rx_resources(jme);
cd0ff491 1340 if (rc) {
52a46ba8 1341 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1342 goto out_enable_tasklet;
fcf45b4c
GFT		 1343 }
1344
fcf45b4c 1345 rc = jme_setup_tx_resources(jme);
cd0ff491 1346 if (rc) {
52a46ba8 1347 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1348 goto err_out_free_rx_resources;
1349 }
1350
1351 jme_enable_rx_engine(jme);
1352 jme_enable_tx_engine(jme);
1353
1354 netif_start_queue(netdev);
192570e0 1355
cd0ff491 1356 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1357 jme_interrupt_mode(jme);
192570e0 1358
79ce639c 1359 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1360 } else if (jme_pseudo_hotplug_enabled(jme)) {
1361 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1362 }
1363
cd0ff491 1364 goto out_enable_tasklet;
fcf45b4c
GFT		 1365
1366err_out_free_rx_resources:
1367 jme_free_rx_resources(jme);
cd0ff491
GFT		 1368out_enable_tasklet:
1369 tasklet_enable(&jme->txclean_task);
1370 tasklet_hi_enable(&jme->rxclean_task);
1371 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1372out:
1373 atomic_inc(&jme->link_changing);
3bf61c55 1374}
d7699f87 1375
3bf61c55
GFT		 1376static void
1377jme_rx_clean_tasklet(unsigned long arg)
1378{
cd0ff491 1379 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1380 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1381
192570e0
GFT		 1382 jme_process_receive(jme, jme->rx_ring_size);
1383 ++(dpi->intr_cnt);
42b1055e 1384
192570e0 1385}
fcf45b4c 1386
192570e0 1387static int
cdcdc9eb 1388jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1389{
cdcdc9eb 1390 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0 1391 int rest;
fcf45b4c 1392
cdcdc9eb 1393 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1394
cd0ff491 1395 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1396 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1397 ++(NET_STAT(jme).rx_dropped);
1398 jme_restart_rx_engine(jme);
1399 }
1400 atomic_inc(&jme->rx_empty);
1401
cd0ff491 1402 if (rest) {
cdcdc9eb 1403 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1404 jme_interrupt_mode(jme);
1405 }
1406
cdcdc9eb
GFT		 1407 JME_NAPI_WEIGHT_SET(budget, rest);
1408 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1409}
1410
1411static void
1412jme_rx_empty_tasklet(unsigned long arg)
1413{
cd0ff491 1414 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1415
cd0ff491 1416 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1417 return;
1418
cd0ff491 1419 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1420 return;
1421
c97b5740 1422 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1423
fcf45b4c 1424 jme_rx_clean_tasklet(arg);
cdcdc9eb 1425
cd0ff491 1426 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1427 atomic_dec(&jme->rx_empty);
1428 ++(NET_STAT(jme).rx_dropped);
1429 jme_restart_rx_engine(jme);
1430 }
1431 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1432}
1433
b3821cc5
GFT		 1434static void
1435jme_wake_queue_if_stopped(struct jme_adapter *jme)
1436{
fa97b924 1437 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1438
1439 smp_wmb();
cd0ff491 1440 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1441 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
52a46ba8 1442 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1443 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1444 }
1445
1446}
1447
3bf61c55
GFT		 1448static void
1449jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1450{
cd0ff491 1451 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1452 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1453 struct txdesc *txdesc = txring->desc;
3bf61c55 1454 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1455 int i, j, cnt = 0, max, err, mask;
3bf61c55 1456
52a46ba8 1457 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1458
1459 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1460 goto out;
1461
cd0ff491 1462 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1463 goto out;
1464
cd0ff491 1465 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1466 goto out;
1467
b3821cc5
GFT		 1468 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1469 mask = jme->tx_ring_mask;
3bf61c55 1470
cd0ff491 1471 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1472
1473 ctxbi = txbi + i;
1474
cd0ff491 1475 if (likely(ctxbi->skb &&
b3821cc5 1476 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1477
cd0ff491 1478 tx_dbg(jme, "txclean: %d+%d@%lu\n",
52a46ba8 1479 i, ctxbi->nr_desc, jiffies);
3bf61c55 1480
cd0ff491 1481 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1482
cd0ff491 1483 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1484 ttxbi = txbi + ((i + j) & (mask));
1485 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1486
b3821cc5 1487 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1488 ttxbi->mapping,
1489 ttxbi->len,
1490 PCI_DMA_TODEVICE);
1491
3bf61c55
GFT		 1492 ttxbi->mapping = 0;
1493 ttxbi->len = 0;
1494 }
1495
1496 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1497
1498 cnt += ctxbi->nr_desc;
1499
cd0ff491 1500 if (unlikely(err)) {
8c198884 1501 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1502 } else {
8c198884 1503 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1504 NET_STAT(jme).tx_bytes += ctxbi->len;
1505 }
1506
1507 ctxbi->skb = NULL;
1508 ctxbi->len = 0;
cdcdc9eb 1509 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1510
1511 } else {
3bf61c55
GFT		 1512 break;
1513 }
1514
b3821cc5 1515 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1516
1517 ctxbi->nr_desc = 0;
d7699f87
GFT		 1518 }
1519
52a46ba8 1520 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1521 atomic_set(&txring->next_to_clean, i);
79ce639c 1522 atomic_add(cnt, &txring->nr_free);
3bf61c55 1523
b3821cc5
GFT		 1524 jme_wake_queue_if_stopped(jme);
1525
fcf45b4c
GFT		 1526out:
1527 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1528}
1529
79ce639c 1530static void
cd0ff491 1531jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1532{
3bf61c55
GFT		 1533 /*
1534 * Disable interrupt
1535 */
1536 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1537
cd0ff491 1538 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1539 /*
1540 * Link change event is critical
1541 * all other events are ignored
1542 */
1543 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1544 tasklet_schedule(&jme->linkch_task);
29bdd921 1545 goto out_reenable;
fcf45b4c 1546 }
d7699f87 1547
cd0ff491 1548 if (intrstat & INTR_TMINTR) {
47220951 1549 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1550 tasklet_schedule(&jme->pcc_task);
47220951 1551 }
79ce639c 1552
cd0ff491 1553 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1554 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1555 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1556 }
1557
cd0ff491 1558 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1559 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1560 INTR_PCCRX0 |
1561 INTR_RX0EMP)) |
1562 INTR_RX0);
1563 }
d7699f87 1564
cd0ff491
GFT		 1565 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1566 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1567 atomic_inc(&jme->rx_empty);
1568
cd0ff491
GFT		 1569 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1570 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1571 jme_polling_mode(jme);
cdcdc9eb 1572 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1573 }
1574 }
cd0ff491
GFT		 1575 } else {
1576 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1577 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1578 tasklet_hi_schedule(&jme->rxempty_task);
1579 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1580 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1581 }
4330c2f2 1582 }
d7699f87 1583
29bdd921 1584out_reenable:
3bf61c55 1585 /*
fcf45b4c 1586 * Re-enable interrupt
3bf61c55 1587 */
fcf45b4c 1588 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1589}
1590
1591static irqreturn_t
1592jme_intr(int irq, void *dev_id)
1593{
cd0ff491
GFT		 1594 struct net_device *netdev = dev_id;
1595 struct jme_adapter *jme = netdev_priv(netdev);
1596 u32 intrstat;
79ce639c
GFT		 1597
1598 intrstat = jread32(jme, JME_IEVE);
1599
1600 /*
1601 * Check if it's really an interrupt for us
1602 */
9b9d55de 1603 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1604 return IRQ_NONE;
79ce639c
GFT		 1605
1606 /*
1607 * Check if the device still exist
1608 */
cd0ff491
GFT		 1609 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1610 return IRQ_NONE;
79ce639c
GFT		 1611
1612 jme_intr_msi(jme, intrstat);
1613
cd0ff491 1614 return IRQ_HANDLED;
d7699f87
GFT		 1615}
1616
79ce639c
GFT		 1617static irqreturn_t
1618jme_msi(int irq, void *dev_id)
1619{
cd0ff491
GFT		 1620 struct net_device *netdev = dev_id;
1621 struct jme_adapter *jme = netdev_priv(netdev);
1622 u32 intrstat;
79ce639c 1623
fa97b924 1624 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1625
1626 jme_intr_msi(jme, intrstat);
1627
cd0ff491 1628 return IRQ_HANDLED;
79ce639c
GFT		 1629}
1630
79ce639c
GFT		 1631static void
1632jme_reset_link(struct jme_adapter *jme)
1633{
1634 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1635}
1636
fcf45b4c
GFT		 1637static void
1638jme_restart_an(struct jme_adapter *jme)
1639{
cd0ff491 1640 u32 bmcr;
fcf45b4c 1641
cd0ff491 1642 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1643 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1644 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1645 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1646 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1647}
1648
1649static int
1650jme_request_irq(struct jme_adapter *jme)
1651{
1652 int rc;
cd0ff491
GFT		 1653 struct net_device *netdev = jme->dev;
1654 irq_handler_t handler = jme_intr;
1655 int irq_flags = IRQF_SHARED;
1656
1657 if (!pci_enable_msi(jme->pdev)) {
1658 set_bit(JME_FLAG_MSI, &jme->flags);
1659 handler = jme_msi;
1660 irq_flags = 0;
1661 }
1662
1663 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1664 netdev);
1665 if (rc) {
52a46ba8
JP		 1666 netdev_err(netdev,
1667 "Unable to request %s interrupt (return: %d)\n",
1668 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1669 rc);
79ce639c 1670
cd0ff491
GFT		 1671 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1672 pci_disable_msi(jme->pdev);
1673 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1674 }
cd0ff491 1675 } else {
79ce639c
GFT		 1676 netdev->irq = jme->pdev->irq;
1677 }
1678
cd0ff491 1679 return rc;
79ce639c
GFT		 1680}
1681
1682static void
1683jme_free_irq(struct jme_adapter *jme)
1684{
cd0ff491
GFT		 1685 free_irq(jme->pdev->irq, jme->dev);
1686 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1687 pci_disable_msi(jme->pdev);
1688 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1689 jme->dev->irq = jme->pdev->irq;
cd0ff491 1690 }
fcf45b4c
GFT		 1691}
1692
e4610a83
GFT		 1693static inline void
1694jme_new_phy_on(struct jme_adapter *jme)
1695{
1696 u32 reg;
1697
1698 reg = jread32(jme, JME_PHY_PWR);
1699 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1700 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1701 jwrite32(jme, JME_PHY_PWR, reg);
1702
1703 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1704 reg &= ~PE1_GPREG0_PBG;
1705 reg |= PE1_GPREG0_ENBG;
1706 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1707}
1708
1709static inline void
1710jme_new_phy_off(struct jme_adapter *jme)
1711{
1712 u32 reg;
1713
1714 reg = jread32(jme, JME_PHY_PWR);
1715 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1716 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1717 jwrite32(jme, JME_PHY_PWR, reg);
1718
1719 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1720 reg &= ~PE1_GPREG0_PBG;
1721 reg |= PE1_GPREG0_PDD3COLD;
1722 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1723}
1724
48db98f7
GFT		 1725static inline void
1726jme_phy_on(struct jme_adapter *jme)
1727{
1728 u32 bmcr;
1729
1730 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1731 bmcr &= ~BMCR_PDOWN;
1732 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
e4610a83
GFT		 1733
1734 if (new_phy_power_ctrl(jme->chip_main_rev))
1735 jme_new_phy_on(jme);
1736}
1737
1738static inline void
1739jme_phy_off(struct jme_adapter *jme)
1740{
1741 u32 bmcr;
1742
1743 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1744 bmcr |= BMCR_PDOWN;
1745 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1746
1747 if (new_phy_power_ctrl(jme->chip_main_rev))
1748 jme_new_phy_off(jme);
48db98f7
GFT		 1749}
1750
3bf61c55
GFT		 1751static int
1752jme_open(struct net_device *netdev)
d7699f87
GFT		 1753{
1754 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1755 int rc;
79ce639c 1756
42b1055e 1757 jme_clear_pm(jme);
cdcdc9eb 1758 JME_NAPI_ENABLE(jme);
d7699f87 1759
fa97b924 1760 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1761 tasklet_enable(&jme->txclean_task);
1762 tasklet_hi_enable(&jme->rxclean_task);
1763 tasklet_hi_enable(&jme->rxempty_task);
1764
79ce639c 1765 rc = jme_request_irq(jme);
cd0ff491 1766 if (rc)
4330c2f2 1767 goto err_out;
79ce639c 1768
d7699f87 1769 jme_start_irq(jme);
42b1055e 1770
e4610a83
GFT		 1771 jme_phy_on(jme);
1772 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1773 jme_set_settings(netdev, &jme->old_ecmd);
e4610a83 1774 else
42b1055e
GFT		 1775 jme_reset_phy_processor(jme);
1776
29bdd921 1777 jme_reset_link(jme);
d7699f87
GFT		 1778
1779 return 0;
1780
d7699f87
GFT		 1781err_out:
1782 netif_stop_queue(netdev);
1783 netif_carrier_off(netdev);
4330c2f2 1784 return rc;
d7699f87
GFT		 1785}
1786
42b1055e
GFT		 1787static void
1788jme_set_100m_half(struct jme_adapter *jme)
1789{
cd0ff491 1790 u32 bmcr, tmp;
42b1055e 1791
fba4bc0c 1792 jme_phy_on(jme);
42b1055e
GFT		 1793 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1794 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1795 BMCR_SPEED1000 | BMCR_FULLDPLX);
1796 tmp |= BMCR_SPEED100;
1797
1798 if (bmcr != tmp)
1799 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1800
cd0ff491 1801 if (jme->fpgaver)
cdcdc9eb
GFT		 1802 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1803 else
1804 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1805}
1806
47220951
GFT		 1807#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1808static void
1809jme_wait_link(struct jme_adapter *jme)
1810{
cd0ff491 1811 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1812
1813 mdelay(1000);
1814 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1815 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1816 mdelay(10);
1817 phylink = jme_linkstat_from_phy(jme);
1818 }
1819}
1820
fba4bc0c
GFT		 1821static void
1822jme_powersave_phy(struct jme_adapter *jme)
1823{
1824 if (jme->reg_pmcs) {
1825 jme_set_100m_half(jme);
fba4bc0c
GFT		 1826 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1827 jme_wait_link(jme);
18783c49 1828 jme_clear_pm(jme);
fba4bc0c
GFT		 1829 } else {
1830 jme_phy_off(jme);
1831 }
1832}
1833
3bf61c55
GFT		 1834static int
1835jme_close(struct net_device *netdev)
d7699f87
GFT		 1836{
1837 struct jme_adapter *jme = netdev_priv(netdev);
1838
1839 netif_stop_queue(netdev);
1840 netif_carrier_off(netdev);
1841
1842 jme_stop_irq(jme);
79ce639c 1843 jme_free_irq(jme);
d7699f87 1844
cdcdc9eb 1845 JME_NAPI_DISABLE(jme);
192570e0 1846
fa97b924
GFT		 1847 tasklet_disable(&jme->linkch_task);
1848 tasklet_disable(&jme->txclean_task);
1849 tasklet_disable(&jme->rxclean_task);
1850 tasklet_disable(&jme->rxempty_task);
8c198884 1851
cd0ff491
GFT		 1852 jme_disable_rx_engine(jme);
1853 jme_disable_tx_engine(jme);
8c198884 1854 jme_reset_mac_processor(jme);
d7699f87
GFT		 1855 jme_free_rx_resources(jme);
1856 jme_free_tx_resources(jme);
42b1055e 1857 jme->phylink = 0;
b3821cc5
GFT		 1858 jme_phy_off(jme);
1859
1860 return 0;
1861}
1862
1863static int
1864jme_alloc_txdesc(struct jme_adapter *jme,
1865 struct sk_buff *skb)
1866{
fa97b924 1867 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1868 int idx, nr_alloc, mask = jme->tx_ring_mask;
1869
1870 idx = txring->next_to_use;
1871 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1872
cd0ff491 1873 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1874 return -1;
1875
1876 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1877
b3821cc5
GFT		 1878 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1879
1880 return idx;
1881}
1882
1883static void
1884jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1885 struct txdesc *txdesc,
b3821cc5
GFT		 1886 struct jme_buffer_info *txbi,
1887 struct page *page,
cd0ff491
GFT		 1888 u32 page_offset,
1889 u32 len,
1890 u8 hidma)
b3821cc5
GFT		 1891{
1892 dma_addr_t dmaaddr;
1893
1894 dmaaddr = pci_map_page(pdev,
1895 page,
1896 page_offset,
1897 len,
1898 PCI_DMA_TODEVICE);
1899
1900 pci_dma_sync_single_for_device(pdev,
1901 dmaaddr,
1902 len,
1903 PCI_DMA_TODEVICE);
1904
1905 txdesc->dw[0] = 0;
1906 txdesc->dw[1] = 0;
1907 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1908 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1909 txdesc->desc2.datalen = cpu_to_le16(len);
1910 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1911 txdesc->desc2.bufaddrl = cpu_to_le32(
1912 (__u64)dmaaddr & 0xFFFFFFFFUL);
1913
1914 txbi->mapping = dmaaddr;
1915 txbi->len = len;
1916}
1917
1918static void
1919jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1920{
fa97b924 1921 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1922 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1923 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1924 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1925 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1926 int mask = jme->tx_ring_mask;
1927 struct skb_frag_struct *frag;
cd0ff491 1928 u32 len;
b3821cc5 1929
cd0ff491
GFT		 1930 for (i = 0 ; i < nr_frags ; ++i) {
1931 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1932 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1933 ctxbi = txbi + ((idx + i + 2) & (mask));
1934
1935 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1936 frag->page_offset, frag->size, hidma);
42b1055e 1937 }
b3821cc5 1938
cd0ff491 1939 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 1940 ctxdesc = txdesc + ((idx + 1) & (mask));
1941 ctxbi = txbi + ((idx + 1) & (mask));
1942 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1943 offset_in_page(skb->data), len, hidma);
1944
1945}
1946
1947static int
1948jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1949{
cd0ff491 1950 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT		 1951 skb_header_cloned(skb) &&
1952 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1953 dev_kfree_skb(skb);
1954 return -1;
1955 }
1956
1957 return 0;
1958}
1959
1960static int
94c5ea02 1961jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1962{
94c5ea02 1963 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
cd0ff491 1964 if (*mss) {
b3821cc5
GFT		 1965 *flags |= TXFLAG_LSEN;
1966
cd0ff491 1967 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 1968 struct iphdr *iph = ip_hdr(skb);
1969
1970 iph->check = 0;
cd0ff491 1971 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 1972 iph->daddr, 0,
1973 IPPROTO_TCP,
1974 0);
cd0ff491 1975 } else {
b3821cc5
GFT		 1976 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1977
cd0ff491 1978 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 1979 &ip6h->daddr, 0,
1980 IPPROTO_TCP,
1981 0);
1982 }
1983
1984 return 0;
1985 }
1986
1987 return 1;
1988}
1989
1990static void
cd0ff491 1991jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1992{
cd0ff491
GFT		 1993 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1994 u8 ip_proto;
b3821cc5
GFT		 1995
1996 switch (skb->protocol) {
cd0ff491 1997 case htons(ETH_P_IP):
b3821cc5
GFT		 1998 ip_proto = ip_hdr(skb)->protocol;
1999 break;
cd0ff491 2000 case htons(ETH_P_IPV6):
b3821cc5
GFT		 2001 ip_proto = ipv6_hdr(skb)->nexthdr;
2002 break;
2003 default:
2004 ip_proto = 0;
2005 break;
2006 }
2007
cd0ff491 2008 switch (ip_proto) {
b3821cc5
GFT		 2009 case IPPROTO_TCP:
2010 *flags |= TXFLAG_TCPCS;
2011 break;
2012 case IPPROTO_UDP:
2013 *flags |= TXFLAG_UDPCS;
2014 break;
2015 default:
52a46ba8 2016 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2017 break;
2018 }
2019 }
2020}
2021
cd0ff491 2022static inline void
94c5ea02 2023jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2024{
cd0ff491 2025 if (vlan_tx_tag_present(skb)) {
b3821cc5 2026 *flags |= TXFLAG_TAGON;
94c5ea02 2027 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2028 }
b3821cc5
GFT		 2029}
2030
2031static int
94c5ea02 2032jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2033{
fa97b924 2034 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2035 struct txdesc *txdesc;
b3821cc5 2036 struct jme_buffer_info *txbi;
cd0ff491 2037 u8 flags;
b3821cc5 2038
cd0ff491 2039 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2040 txbi = txring->bufinf + idx;
2041
2042 txdesc->dw[0] = 0;
2043 txdesc->dw[1] = 0;
2044 txdesc->dw[2] = 0;
2045 txdesc->dw[3] = 0;
2046 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2047 /*
2048 * Set OWN bit at final.
2049 * When kernel transmit faster than NIC.
2050 * And NIC trying to send this descriptor before we tell
2051 * it to start sending this TX queue.
2052 * Other fields are already filled correctly.
2053 */
2054 wmb();
2055 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2056 /*
2057 * Set checksum flags while not tso
2058 */
2059 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2060 jme_tx_csum(jme, skb, &flags);
b3821cc5 2061 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
94c5ea02 2062 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2063 txdesc->desc1.flags = flags;
2064 /*
2065 * Set tx buffer info after telling NIC to send
2066 * For better tx_clean timing
2067 */
2068 wmb();
2069 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2070 txbi->skb = skb;
2071 txbi->len = skb->len;
cd0ff491
GFT		 2072 txbi->start_xmit = jiffies;
2073 if (!txbi->start_xmit)
8d27293f 2074 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2075
2076 return 0;
2077}
2078
b3821cc5
GFT		 2079static void
2080jme_stop_queue_if_full(struct jme_adapter *jme)
2081{
fa97b924 2082 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2083 struct jme_buffer_info *txbi = txring->bufinf;
2084 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2085
cd0ff491 2086 txbi += idx;
b3821cc5
GFT		 2087
2088 smp_wmb();
cd0ff491 2089 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2090 netif_stop_queue(jme->dev);
52a46ba8 2091 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2092 smp_wmb();
cd0ff491
GFT		 2093 if (atomic_read(&txring->nr_free)
2094 >= (jme->tx_wake_threshold)) {
b3821cc5 2095 netif_wake_queue(jme->dev);
52a46ba8 2096 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2097 }
2098 }
2099
cd0ff491 2100 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2101 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2102 txbi->skb)) {
2103 netif_stop_queue(jme->dev);
52a46ba8
JP		 2104 netif_info(jme, tx_queued, jme->dev,
2105 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2106 }
b3821cc5
GFT		 2107}
2108
3bf61c55
GFT		 2109/*
2110 * This function is already protected by netif_tx_lock()
2111 */
cd0ff491 2112
c97b5740 2113static netdev_tx_t
3bf61c55 2114jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2115{
cd0ff491 2116 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2117 int idx;
d7699f87 2118
cd0ff491 2119 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2120 ++(NET_STAT(jme).tx_dropped);
2121 return NETDEV_TX_OK;
2122 }
2123
2124 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2125
cd0ff491 2126 if (unlikely(idx < 0)) {
b3821cc5 2127 netif_stop_queue(netdev);
52a46ba8
JP		 2128 netif_err(jme, tx_err, jme->dev,
2129 "BUG! Tx ring full when queue awake!\n");
d7699f87 2130
cd0ff491 2131 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2132 }
2133
94c5ea02 2134 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2135
4330c2f2
GFT		 2136 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2137 TXCS_SELECT_QUEUE0 |
2138 TXCS_QUEUE0S |
2139 TXCS_ENABLE);
d7699f87 2140
52a46ba8
JP		 2141 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2142 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2143 jme_stop_queue_if_full(jme);
2144
cd0ff491 2145 return NETDEV_TX_OK;
d7699f87
GFT		 2146}
2147
bb4c5c8c
GFT		 2148static void
2149jme_set_unicastaddr(struct net_device *netdev)
2150{
2151 struct jme_adapter *jme = netdev_priv(netdev);
2152 u32 val;
2153
2154 val = (netdev->dev_addr[3] & 0xff) << 24 |
2155 (netdev->dev_addr[2] & 0xff) << 16 |
2156 (netdev->dev_addr[1] & 0xff) << 8 |
2157 (netdev->dev_addr[0] & 0xff);
2158 jwrite32(jme, JME_RXUMA_LO, val);
2159 val = (netdev->dev_addr[5] & 0xff) << 8 |
2160 (netdev->dev_addr[4] & 0xff);
2161 jwrite32(jme, JME_RXUMA_HI, val);
2162}
2163
3bf61c55
GFT		 2164static int
2165jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2166{
cd0ff491 2167 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2168 struct sockaddr *addr = p;
d7699f87 2169
cd0ff491 2170 if (netif_running(netdev))
d7699f87
GFT		 2171 return -EBUSY;
2172
cd0ff491 2173 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2174 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
bb4c5c8c 2175 jme_set_unicastaddr(netdev);
cd0ff491 2176 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2177
2178 return 0;
2179}
2180
3bf61c55
GFT		 2181static void
2182jme_set_multi(struct net_device *netdev)
d7699f87 2183{
3bf61c55 2184 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2185 u32 mc_hash[2] = {};
d7699f87 2186
cd0ff491 2187 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2188
2189 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2190
cd0ff491 2191 if (netdev->flags & IFF_PROMISC) {
8c198884 2192 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2193 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2194 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2195 } else if (netdev->flags & IFF_MULTICAST) {
d401cb9a 2196 struct netdev_hw_addr *ha;
3bf61c55 2197 int bit_nr;
d7699f87 2198
8c198884 2199 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
d401cb9a
JP		 2200 netdev_for_each_mc_addr(ha, netdev) {
2201 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
cd0ff491
GFT		 2202 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2203 }
d7699f87 2204
4330c2f2
GFT		 2205 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2206 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2207 }
2208
d7699f87 2209 wmb();
8c198884
GFT		 2210 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2211
cd0ff491 2212 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2213}
2214
3bf61c55 2215static int
8c198884 2216jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2217{
cd0ff491 2218 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2219
cd0ff491 2220 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2221 return 0;
2222
cd0ff491
GFT		 2223 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2224 ((new_mtu) < IPV6_MIN_MTU))
2225 return -EINVAL;
79ce639c 2226
cd0ff491 2227 if (new_mtu > 4000) {
79ce639c
GFT		 2228 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2229 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2230 jme_restart_rx_engine(jme);
cd0ff491 2231 } else {
79ce639c
GFT		 2232 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2233 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2234 jme_restart_rx_engine(jme);
2235 }
2236
cd0ff491 2237 netdev->mtu = new_mtu;
aa4d6a67
MM		 2238 netdev_update_features(netdev);
2239
cd0ff491 2240 jme_reset_link(jme);
79ce639c
GFT		 2241
2242 return 0;
d7699f87
GFT		 2243}
2244
8c198884
GFT		 2245static void
2246jme_tx_timeout(struct net_device *netdev)
2247{
cd0ff491 2248 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2249
cdcdc9eb
GFT		 2250 jme->phylink = 0;
2251 jme_reset_phy_processor(jme);
cd0ff491 2252 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2253 jme_set_settings(netdev, &jme->old_ecmd);
2254
8c198884 2255 /*
cdcdc9eb 2256 * Force to Reset the link again
8c198884 2257 */
29bdd921 2258 jme_reset_link(jme);
8c198884
GFT		 2259}
2260
f7f428e4
GFT		 2261static inline void jme_pause_rx(struct jme_adapter *jme)
2262{
2263 atomic_dec(&jme->link_changing);
2264
2265 jme_set_rx_pcc(jme, PCC_OFF);
2266 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2267 JME_NAPI_DISABLE(jme);
2268 } else {
2269 tasklet_disable(&jme->rxclean_task);
2270 tasklet_disable(&jme->rxempty_task);
2271 }
2272}
2273
2274static inline void jme_resume_rx(struct jme_adapter *jme)
2275{
2276 struct dynpcc_info *dpi = &(jme->dpi);
2277
2278 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2279 JME_NAPI_ENABLE(jme);
2280 } else {
2281 tasklet_hi_enable(&jme->rxclean_task);
2282 tasklet_hi_enable(&jme->rxempty_task);
2283 }
2284 dpi->cur = PCC_P1;
2285 dpi->attempt = PCC_P1;
2286 dpi->cnt = 0;
2287 jme_set_rx_pcc(jme, PCC_P1);
2288
2289 atomic_inc(&jme->link_changing);
2290}
2291
42b1055e
GFT		 2292static void
2293jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2294{
2295 struct jme_adapter *jme = netdev_priv(netdev);
2296
f7f428e4 2297 jme_pause_rx(jme);
42b1055e 2298 jme->vlgrp = grp;
f7f428e4 2299 jme_resume_rx(jme);
42b1055e
GFT		 2300}
2301
3bf61c55
GFT		 2302static void
2303jme_get_drvinfo(struct net_device *netdev,
2304 struct ethtool_drvinfo *info)
d7699f87 2305{
cd0ff491 2306 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2307
cd0ff491
GFT		 2308 strcpy(info->driver, DRV_NAME);
2309 strcpy(info->version, DRV_VERSION);
2310 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2311}
2312
8c198884
GFT		 2313static int
2314jme_get_regs_len(struct net_device *netdev)
2315{
cd0ff491 2316 return JME_REG_LEN;
8c198884
GFT		 2317}
2318
2319static void
cd0ff491 2320mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2321{
2322 int i;
2323
cd0ff491 2324 for (i = 0 ; i < len ; i += 4)
79ce639c 2325 p[i >> 2] = jread32(jme, reg + i);
186fc259 2326}
8c198884 2327
186fc259 2328static void
cd0ff491 2329mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2330{
2331 int i;
cd0ff491 2332 u16 *p16 = (u16 *)p;
186fc259 2333
cd0ff491 2334 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2335 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2336}
2337
2338static void
2339jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2340{
cd0ff491
GFT		 2341 struct jme_adapter *jme = netdev_priv(netdev);
2342 u32 *p32 = (u32 *)p;
8c198884 2343
186fc259 2344 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2345
2346 regs->version = 1;
2347 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2348
2349 p32 += 0x100 >> 2;
2350 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2351
2352 p32 += 0x100 >> 2;
2353 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2354
2355 p32 += 0x100 >> 2;
2356 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2357
186fc259
GFT		 2358 p32 += 0x100 >> 2;
2359 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2360}
2361
2362static int
2363jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2364{
2365 struct jme_adapter *jme = netdev_priv(netdev);
2366
8c198884
GFT		 2367 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2368 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2369
cd0ff491 2370 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2371 ecmd->use_adaptive_rx_coalesce = false;
2372 ecmd->rx_coalesce_usecs = 0;
2373 ecmd->rx_max_coalesced_frames = 0;
2374 return 0;
2375 }
2376
2377 ecmd->use_adaptive_rx_coalesce = true;
2378
cd0ff491 2379 switch (jme->dpi.cur) {
8c198884
GFT		 2380 case PCC_P1:
2381 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2382 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2383 break;
2384 case PCC_P2:
2385 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2386 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2387 break;
2388 case PCC_P3:
2389 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2390 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2391 break;
2392 default:
2393 break;
2394 }
2395
2396 return 0;
2397}
2398
192570e0
GFT		 2399static int
2400jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2401{
2402 struct jme_adapter *jme = netdev_priv(netdev);
2403 struct dynpcc_info *dpi = &(jme->dpi);
2404
cd0ff491 2405 if (netif_running(netdev))
cdcdc9eb
GFT		 2406 return -EBUSY;
2407
c97b5740
GFT		 2408 if (ecmd->use_adaptive_rx_coalesce &&
2409 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2410 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2411 jme->jme_rx = netif_rx;
2412 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2413 dpi->cur = PCC_P1;
2414 dpi->attempt = PCC_P1;
2415 dpi->cnt = 0;
2416 jme_set_rx_pcc(jme, PCC_P1);
2417 jme_interrupt_mode(jme);
c97b5740
GFT		 2418 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2419 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2420 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2421 jme->jme_rx = netif_receive_skb;
2422 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2423 jme_interrupt_mode(jme);
2424 }
2425
2426 return 0;
2427}
2428
8c198884
GFT		 2429static void
2430jme_get_pauseparam(struct net_device *netdev,
2431 struct ethtool_pauseparam *ecmd)
2432{
2433 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2434 u32 val;
8c198884
GFT		 2435
2436 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2437 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2438
cd0ff491
GFT		 2439 spin_lock_bh(&jme->phy_lock);
2440 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2441 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2442
2443 ecmd->autoneg =
2444 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2445}
2446
2447static int
2448jme_set_pauseparam(struct net_device *netdev,
2449 struct ethtool_pauseparam *ecmd)
2450{
2451 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2452 u32 val;
8c198884 2453
cd0ff491 2454 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2455 (ecmd->tx_pause != 0)) {
2456
cd0ff491 2457 if (ecmd->tx_pause)
8c198884
GFT		 2458 jme->reg_txpfc |= TXPFC_PF_EN;
2459 else
2460 jme->reg_txpfc &= ~TXPFC_PF_EN;
2461
2462 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2463 }
2464
cd0ff491
GFT		 2465 spin_lock_bh(&jme->rxmcs_lock);
2466 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2467 (ecmd->rx_pause != 0)) {
2468
cd0ff491 2469 if (ecmd->rx_pause)
8c198884
GFT		 2470 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2471 else
2472 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2473
2474 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2475 }
cd0ff491 2476 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2477
cd0ff491
GFT		 2478 spin_lock_bh(&jme->phy_lock);
2479 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2480 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2481 (ecmd->autoneg != 0)) {
2482
cd0ff491 2483 if (ecmd->autoneg)
8c198884
GFT		 2484 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2485 else
2486 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2487
b3821cc5
GFT		 2488 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2489 MII_ADVERTISE, val);
8c198884 2490 }
cd0ff491 2491 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2492
2493 return 0;
2494}
2495
29bdd921
GFT		 2496static void
2497jme_get_wol(struct net_device *netdev,
2498 struct ethtool_wolinfo *wol)
2499{
2500 struct jme_adapter *jme = netdev_priv(netdev);
2501
2502 wol->supported = WAKE_MAGIC | WAKE_PHY;
2503
2504 wol->wolopts = 0;
2505
cd0ff491 2506 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2507 wol->wolopts |= WAKE_PHY;
2508
cd0ff491 2509 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2510 wol->wolopts |= WAKE_MAGIC;
2511
2512}
2513
2514static int
2515jme_set_wol(struct net_device *netdev,
2516 struct ethtool_wolinfo *wol)
2517{
2518 struct jme_adapter *jme = netdev_priv(netdev);
2519
cd0ff491 2520 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2521 WAKE_UCAST |
2522 WAKE_MCAST |
2523 WAKE_BCAST |
2524 WAKE_ARP))
2525 return -EOPNOTSUPP;
2526
2527 jme->reg_pmcs = 0;
2528
cd0ff491 2529 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2530 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2531
cd0ff491 2532 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2533 jme->reg_pmcs |= PMCS_MFEN;
2534
cd0ff491 2535 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
18783c49 2536 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
8ad2ddac 2537
29bdd921
GFT		 2538 return 0;
2539}
b3821cc5 2540
3bf61c55
GFT		 2541static int
2542jme_get_settings(struct net_device *netdev,
2543 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2544{
2545 struct jme_adapter *jme = netdev_priv(netdev);
2546 int rc;
8c198884 2547
cd0ff491 2548 spin_lock_bh(&jme->phy_lock);
d7699f87 2549 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2550 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2551 return rc;
2552}
2553
3bf61c55
GFT		 2554static int
2555jme_set_settings(struct net_device *netdev,
2556 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2557{
2558 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2559 int rc, fdc = 0;
fcf45b4c 2560
035550c9
DD		 2561 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2562 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2563 return -EINVAL;
2564
f79361a6
GFT		 2565 /*
2566 * Check If user changed duplex only while force_media.
2567 * Hardware would not generate link change interrupt.
2568 */
cd0ff491 2569 if (jme->mii_if.force_media &&
79ce639c
GFT		 2570 ecmd->autoneg != AUTONEG_ENABLE &&
2571 (jme->mii_if.full_duplex != ecmd->duplex))
2572 fdc = 1;
2573
cd0ff491 2574 spin_lock_bh(&jme->phy_lock);
d7699f87 2575 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2576 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2577
cd0ff491 2578 if (!rc) {
f79361a6
GFT		 2579 if (fdc)
2580 jme_reset_link(jme);
29bdd921 2581 jme->old_ecmd = *ecmd;
43e4651b
GFT		 2582 set_bit(JME_FLAG_SSET, &jme->flags);
2583 }
2584
2585 return rc;
2586}
2587
2588static int
2589jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2590{
2591 int rc;
2592 struct jme_adapter *jme = netdev_priv(netdev);
2593 struct mii_ioctl_data *mii_data = if_mii(rq);
2594 unsigned int duplex_chg;
2595
2596 if (cmd == SIOCSMIIREG) {
2597 u16 val = mii_data->val_in;
2598 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2599 (val & BMCR_SPEED1000))
2600 return -EINVAL;
2601 }
2602
2603 spin_lock_bh(&jme->phy_lock);
2604 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2605 spin_unlock_bh(&jme->phy_lock);
2606
2607 if (!rc && (cmd == SIOCSMIIREG)) {
2608 if (duplex_chg)
2609 jme_reset_link(jme);
2610 jme_get_settings(netdev, &jme->old_ecmd);
2611 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2612 }
2613
d7699f87
GFT		 2614 return rc;
2615}
2616
cd0ff491 2617static u32
3bf61c55
GFT		 2618jme_get_link(struct net_device *netdev)
2619{
d7699f87
GFT		 2620 struct jme_adapter *jme = netdev_priv(netdev);
2621 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2622}
2623
8c198884 2624static u32
cd0ff491
GFT		 2625jme_get_msglevel(struct net_device *netdev)
2626{
2627 struct jme_adapter *jme = netdev_priv(netdev);
2628 return jme->msg_enable;
2629}
2630
2631static void
2632jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2633{
cd0ff491
GFT		 2634 struct jme_adapter *jme = netdev_priv(netdev);
2635 jme->msg_enable = value;
2636}
8c198884 2637
cd0ff491 2638static u32
aa4d6a67 2639jme_fix_features(struct net_device *netdev, u32 features)
cd0ff491 2640{
aa4d6a67
MM		 2641 if (netdev->mtu > 1900)
2642 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2643 return features;
8c198884
GFT		 2644}
2645
2646static int
aa4d6a67 2647jme_set_features(struct net_device *netdev, u32 features)
8c198884 2648{
cd0ff491 2649 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2650
cd0ff491 2651 spin_lock_bh(&jme->rxmcs_lock);
aa4d6a67 2652 if (features & NETIF_F_RXCSUM)
8c198884
GFT		 2653 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2654 else
2655 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2656 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2657 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2658
2659 return 0;
2660}
2661
8c198884
GFT		 2662static int
2663jme_nway_reset(struct net_device *netdev)
2664{
cd0ff491 2665 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2666 jme_restart_an(jme);
2667 return 0;
2668}
2669
cd0ff491 2670static u8
186fc259
GFT		 2671jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2672{
cd0ff491 2673 u32 val;
186fc259
GFT		 2674 int to;
2675
2676 val = jread32(jme, JME_SMBCSR);
2677 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2678 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2679 msleep(1);
2680 val = jread32(jme, JME_SMBCSR);
2681 }
cd0ff491 2682 if (!to) {
52a46ba8 2683 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2684 return 0xFF;
2685 }
2686
2687 jwrite32(jme, JME_SMBINTF,
2688 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2689 SMBINTF_HWRWN_READ |
2690 SMBINTF_HWCMD);
2691
2692 val = jread32(jme, JME_SMBINTF);
2693 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2694 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2695 msleep(1);
2696 val = jread32(jme, JME_SMBINTF);
2697 }
cd0ff491 2698 if (!to) {
52a46ba8 2699 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2700 return 0xFF;
2701 }
2702
2703 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2704}
2705
2706static void
cd0ff491 2707jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2708{
cd0ff491 2709 u32 val;
186fc259
GFT		 2710 int to;
2711
2712 val = jread32(jme, JME_SMBCSR);
2713 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2714 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2715 msleep(1);
2716 val = jread32(jme, JME_SMBCSR);
2717 }
cd0ff491 2718 if (!to) {
52a46ba8 2719 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2720 return;
2721 }
2722
2723 jwrite32(jme, JME_SMBINTF,
2724 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2725 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2726 SMBINTF_HWRWN_WRITE |
2727 SMBINTF_HWCMD);
2728
2729 val = jread32(jme, JME_SMBINTF);
2730 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2731 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2732 msleep(1);
2733 val = jread32(jme, JME_SMBINTF);
2734 }
cd0ff491 2735 if (!to) {
52a46ba8 2736 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2737 return;
2738 }
2739
2740 mdelay(2);
2741}
2742
2743static int
2744jme_get_eeprom_len(struct net_device *netdev)
2745{
cd0ff491
GFT		 2746 struct jme_adapter *jme = netdev_priv(netdev);
2747 u32 val;
186fc259 2748 val = jread32(jme, JME_SMBCSR);
cd0ff491 2749 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2750}
2751
2752static int
2753jme_get_eeprom(struct net_device *netdev,
2754 struct ethtool_eeprom *eeprom, u8 *data)
2755{
cd0ff491 2756 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2757 int i, offset = eeprom->offset, len = eeprom->len;
2758
2759 /*
8d27293f 2760 * ethtool will check the boundary for us
186fc259
GFT		 2761 */
2762 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2763 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2764 data[i] = jme_smb_read(jme, i + offset);
2765
2766 return 0;
2767}
2768
2769static int
2770jme_set_eeprom(struct net_device *netdev,
2771 struct ethtool_eeprom *eeprom, u8 *data)
2772{
cd0ff491 2773 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2774 int i, offset = eeprom->offset, len = eeprom->len;
2775
2776 if (eeprom->magic != JME_EEPROM_MAGIC)
2777 return -EINVAL;
2778
2779 /*
8d27293f 2780 * ethtool will check the boundary for us
186fc259 2781 */
cd0ff491 2782 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2783 jme_smb_write(jme, i + offset, data[i]);
2784
2785 return 0;
2786}
2787
d7699f87 2788static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2789 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2790 .get_regs_len = jme_get_regs_len,
2791 .get_regs = jme_get_regs,
2792 .get_coalesce = jme_get_coalesce,
192570e0 2793 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2794 .get_pauseparam = jme_get_pauseparam,
2795 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2796 .get_wol = jme_get_wol,
2797 .set_wol = jme_set_wol,
d7699f87
GFT		 2798 .get_settings = jme_get_settings,
2799 .set_settings = jme_set_settings,
2800 .get_link = jme_get_link,
cd0ff491
GFT		 2801 .get_msglevel = jme_get_msglevel,
2802 .set_msglevel = jme_set_msglevel,
8c198884 2803 .nway_reset = jme_nway_reset,
186fc259
GFT		 2804 .get_eeprom_len = jme_get_eeprom_len,
2805 .get_eeprom = jme_get_eeprom,
2806 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2807};
2808
3bf61c55
GFT		 2809static int
2810jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2811{
94c5ea02 2812 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2813 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2814 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3bf61c55
GFT		 2815 return 1;
2816
94c5ea02 2817 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
fa97b924
GFT		 2818 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2819 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
8c198884
GFT		 2820 return 1;
2821
fa97b924
GFT		 2822 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2823 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3bf61c55
GFT		 2824 return 0;
2825
2826 return -1;
2827}
2828
cd0ff491 2829static inline void
cdcdc9eb
GFT		 2830jme_phy_init(struct jme_adapter *jme)
2831{
cd0ff491 2832 u16 reg26;
cdcdc9eb
GFT		 2833
2834 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2835 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2836}
2837
cd0ff491 2838static inline void
cdcdc9eb 2839jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2840{
cd0ff491 2841 u32 chipmode;
cdcdc9eb
GFT		 2842
2843 chipmode = jread32(jme, JME_CHIPMODE);
2844
2845 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
e882564f 2846 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
4400ae98
GFT		 2847 jme->chip_main_rev = jme->chiprev & 0xF;
2848 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 2849}
2850
94c5ea02
GFT		 2851static const struct net_device_ops jme_netdev_ops = {
2852 .ndo_open = jme_open,
2853 .ndo_stop = jme_close,
2854 .ndo_validate_addr = eth_validate_addr,
43e4651b 2855 .ndo_do_ioctl = jme_ioctl,
94c5ea02
GFT		 2856 .ndo_start_xmit = jme_start_xmit,
2857 .ndo_set_mac_address = jme_set_macaddr,
2858 .ndo_set_multicast_list = jme_set_multi,
2859 .ndo_change_mtu = jme_change_mtu,
2860 .ndo_tx_timeout = jme_tx_timeout,
2861 .ndo_vlan_rx_register = jme_vlan_rx_register,
aa4d6a67
MM		 2862 .ndo_fix_features = jme_fix_features,
2863 .ndo_set_features = jme_set_features,
94c5ea02
GFT		 2864};
2865
3bf61c55
GFT		 2866static int __devinit
2867jme_init_one(struct pci_dev *pdev,
2868 const struct pci_device_id *ent)
2869{
cdcdc9eb 2870 int rc = 0, using_dac, i;
d7699f87
GFT		 2871 struct net_device *netdev;
2872 struct jme_adapter *jme;
cd0ff491
GFT		 2873 u16 bmcr, bmsr;
2874 u32 apmc;
d7699f87
GFT		 2875
2876 /*
2877 * set up PCI device basics
2878 */
4330c2f2 2879 rc = pci_enable_device(pdev);
cd0ff491 2880 if (rc) {
52a46ba8 2881 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 2882 goto err_out;
2883 }
d7699f87 2884
3bf61c55 2885 using_dac = jme_pci_dma64(pdev);
cd0ff491 2886 if (using_dac < 0) {
52a46ba8 2887 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 2888 rc = -EIO;
2889 goto err_out_disable_pdev;
2890 }
2891
cd0ff491 2892 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
52a46ba8 2893 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 2894 rc = -ENOMEM;
2895 goto err_out_disable_pdev;
2896 }
d7699f87 2897
4330c2f2 2898 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2899 if (rc) {
52a46ba8 2900 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 2901 goto err_out_disable_pdev;
2902 }
d7699f87
GFT		 2903
2904 pci_set_master(pdev);
2905
2906 /*
2907 * alloc and init net device
2908 */
3bf61c55 2909 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2910 if (!netdev) {
52a46ba8 2911 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT		 2912 rc = -ENOMEM;
2913 goto err_out_release_regions;
d7699f87 2914 }
94c5ea02 2915 netdev->netdev_ops = &jme_netdev_ops;
d7699f87 2916 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884 2917 netdev->watchdog_timeo = TX_TIMEOUT;
aa4d6a67
MM		 2918 netdev->hw_features = NETIF_F_IP_CSUM |
2919 NETIF_F_IPV6_CSUM |
2920 NETIF_F_SG |
2921 NETIF_F_TSO |
2922 NETIF_F_TSO6 |
2923 NETIF_F_RXCSUM;
9a08cd10
MM		 2924 netdev->features = NETIF_F_IP_CSUM |
2925 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 2926 NETIF_F_SG |
2927 NETIF_F_TSO |
2928 NETIF_F_TSO6 |
42b1055e
GFT		 2929 NETIF_F_HW_VLAN_TX |
2930 NETIF_F_HW_VLAN_RX;
cd0ff491 2931 if (using_dac)
8c198884 2932 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 2933
2934 SET_NETDEV_DEV(netdev, &pdev->dev);
2935 pci_set_drvdata(pdev, netdev);
2936
2937 /*
2938 * init adapter info
2939 */
2940 jme = netdev_priv(netdev);
2941 jme->pdev = pdev;
2942 jme->dev = netdev;
cdcdc9eb
GFT		 2943 jme->jme_rx = netif_rx;
2944 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2945 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2946 jme->phylink = 0;
b3821cc5
GFT		 2947 jme->tx_ring_size = 1 << 10;
2948 jme->tx_ring_mask = jme->tx_ring_size - 1;
2949 jme->tx_wake_threshold = 1 << 9;
2950 jme->rx_ring_size = 1 << 9;
2951 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2952 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 2953 jme->regs = ioremap(pci_resource_start(pdev, 0),
2954 pci_resource_len(pdev, 0));
4330c2f2 2955 if (!(jme->regs)) {
52a46ba8 2956 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 2957 rc = -ENOMEM;
2958 goto err_out_free_netdev;
2959 }
4330c2f2 2960
cd0ff491
GFT		 2961 if (no_pseudohp) {
2962 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2963 jwrite32(jme, JME_APMC, apmc);
2964 } else if (force_pseudohp) {
2965 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2966 jwrite32(jme, JME_APMC, apmc);
2967 }
2968
cdcdc9eb 2969 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2970
d7699f87 2971 spin_lock_init(&jme->phy_lock);
fcf45b4c 2972 spin_lock_init(&jme->macaddr_lock);
8c198884 2973 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2974
fcf45b4c
GFT		 2975 atomic_set(&jme->link_changing, 1);
2976 atomic_set(&jme->rx_cleaning, 1);
2977 atomic_set(&jme->tx_cleaning, 1);
192570e0 2978 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2979
79ce639c 2980 tasklet_init(&jme->pcc_task,
c97b5740 2981 jme_pcc_tasklet,
79ce639c 2982 (unsigned long) jme);
4330c2f2 2983 tasklet_init(&jme->linkch_task,
c97b5740 2984 jme_link_change_tasklet,
4330c2f2
GFT		 2985 (unsigned long) jme);
2986 tasklet_init(&jme->txclean_task,
c97b5740 2987 jme_tx_clean_tasklet,
4330c2f2
GFT		 2988 (unsigned long) jme);
2989 tasklet_init(&jme->rxclean_task,
c97b5740 2990 jme_rx_clean_tasklet,
4330c2f2 2991 (unsigned long) jme);
fcf45b4c 2992 tasklet_init(&jme->rxempty_task,
c97b5740 2993 jme_rx_empty_tasklet,
fcf45b4c 2994 (unsigned long) jme);
fa97b924 2995 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 2996 tasklet_disable_nosync(&jme->txclean_task);
2997 tasklet_disable_nosync(&jme->rxclean_task);
2998 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 2999 jme->dpi.cur = PCC_P1;
3000
cd0ff491 3001 jme->reg_ghc = 0;
79ce639c 3002 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 3003 jme->reg_rxmcs = RXMCS_DEFAULT;
3004 jme->reg_txpfc = 0;
47220951 3005 jme->reg_pmcs = PMCS_MFEN;
ed830419 3006 jme->reg_gpreg1 = GPREG1_DEFAULT;
aa4d6a67
MM		 3007
3008 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3009 netdev->features |= NETIF_F_RXCSUM;
192570e0 3010
fcf45b4c
GFT		 3011 /*
3012 * Get Max Read Req Size from PCI Config Space
3013 */
cd0ff491
GFT		 3014 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3015 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3016 switch (jme->mrrs) {
3017 case MRRS_128B:
3018 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3019 break;
3020 case MRRS_256B:
3021 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3022 break;
3023 default:
3024 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3025 break;
06527f9b 3026 }
fcf45b4c 3027
d7699f87 3028 /*
cdcdc9eb 3029 * Must check before reset_mac_processor
d7699f87 3030 */
cdcdc9eb
GFT		 3031 jme_check_hw_ver(jme);
3032 jme->mii_if.dev = netdev;
cd0ff491 3033 if (jme->fpgaver) {
cdcdc9eb 3034 jme->mii_if.phy_id = 0;
cd0ff491 3035 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3036 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3037 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3038 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3039 jme->mii_if.phy_id = i;
3040 break;
3041 }
3042 }
3043
cd0ff491 3044 if (!jme->mii_if.phy_id) {
cdcdc9eb 3045 rc = -EIO;
52a46ba8
JP		 3046 pr_err("Can not find phy_id\n");
3047 goto err_out_unmap;
cdcdc9eb
GFT		 3048 }
3049
3050 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3051 } else {
cdcdc9eb
GFT		 3052 jme->mii_if.phy_id = 1;
3053 }
cd0ff491 3054 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3055 jme->mii_if.supports_gmii = true;
3056 else
3057 jme->mii_if.supports_gmii = false;
43e4651b
GFT		 3058 jme->mii_if.phy_id_mask = 0x1F;
3059 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3060 jme->mii_if.mdio_read = jme_mdio_read;
3061 jme->mii_if.mdio_write = jme_mdio_write;
3062
d7699f87 3063 jme_clear_pm(jme);
18783c49
GFT		 3064 pci_set_power_state(jme->pdev, PCI_D0);
3065 device_set_wakeup_enable(&pdev->dev, true);
3066
06168a20 3067 jme_set_phyfifo_5level(jme);
6db67aa5 3068 jme->pcirev = pdev->revision;
cd0ff491 3069 if (!jme->fpgaver)
cdcdc9eb 3070 jme_phy_init(jme);
42b1055e 3071 jme_phy_off(jme);
cdcdc9eb
GFT		 3072
3073 /*
3074 * Reset MAC processor and reload EEPROM for MAC Address
3075 */
d7699f87 3076 jme_reset_mac_processor(jme);
4330c2f2 3077 rc = jme_reload_eeprom(jme);
cd0ff491 3078 if (rc) {
52a46ba8 3079 pr_err("Reload eeprom for reading MAC Address error\n");
fa97b924 3080 goto err_out_unmap;
4330c2f2 3081 }
d7699f87
GFT		 3082 jme_load_macaddr(netdev);
3083
d7699f87
GFT		 3084 /*
3085 * Tell stack that we are not ready to work until open()
3086 */
3087 netif_carrier_off(netdev);
d7699f87 3088
4330c2f2 3089 rc = register_netdev(netdev);
cd0ff491 3090 if (rc) {
52a46ba8 3091 pr_err("Cannot register net device\n");
fa97b924 3092 goto err_out_unmap;
4330c2f2 3093 }
d7699f87 3094
4400ae98 3095 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
c97b5740
GFT		 3096 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3097 "JMC250 Gigabit Ethernet" :
3098 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3099 "JMC260 Fast Ethernet" : "Unknown",
3100 (jme->fpgaver != 0) ? " (FPGA)" : "",
3101 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
4400ae98 3102 jme->pcirev, netdev->dev_addr);
d7699f87
GFT		 3103
3104 return 0;
3105
3106err_out_unmap:
3107 iounmap(jme->regs);
3108err_out_free_netdev:
3109 pci_set_drvdata(pdev, NULL);
3110 free_netdev(netdev);
4330c2f2
GFT		 3111err_out_release_regions:
3112 pci_release_regions(pdev);
d7699f87 3113err_out_disable_pdev:
cd0ff491 3114 pci_disable_device(pdev);
d7699f87 3115err_out:
4330c2f2 3116 return rc;
d7699f87
GFT		 3117}
3118
3bf61c55
GFT		 3119static void __devexit
3120jme_remove_one(struct pci_dev *pdev)
3121{
d7699f87
GFT		 3122 struct net_device *netdev = pci_get_drvdata(pdev);
3123 struct jme_adapter *jme = netdev_priv(netdev);
3124
3125 unregister_netdev(netdev);
3126 iounmap(jme->regs);
3127 pci_set_drvdata(pdev, NULL);
3128 free_netdev(netdev);
3129 pci_release_regions(pdev);
3130 pci_disable_device(pdev);
3131
3132}
3133
fba4bc0c
GFT		 3134static void
3135jme_shutdown(struct pci_dev *pdev)
3136{
3137 struct net_device *netdev = pci_get_drvdata(pdev);
3138 struct jme_adapter *jme = netdev_priv(netdev);
3139
3140 jme_powersave_phy(jme);
3141 pci_pme_active(pdev, true);
3142}
3143
e10cd037 3144#ifdef CONFIG_PM_SLEEP
18783c49
GFT		 3145static int
3146jme_suspend(struct device *dev)
29bdd921 3147{
8ad2ddac 3148 struct pci_dev *pdev = to_pci_dev(dev);
29bdd921
GFT		 3149 struct net_device *netdev = pci_get_drvdata(pdev);
3150 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3151
3152 atomic_dec(&jme->link_changing);
3153
3154 netif_device_detach(netdev);
3155 netif_stop_queue(netdev);
3156 jme_stop_irq(jme);
29bdd921 3157
cd0ff491
GFT		 3158 tasklet_disable(&jme->txclean_task);
3159 tasklet_disable(&jme->rxclean_task);
3160 tasklet_disable(&jme->rxempty_task);
3161
cd0ff491
GFT		 3162 if (netif_carrier_ok(netdev)) {
3163 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3164 jme_polling_mode(jme);
3165
29bdd921 3166 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3167 jme_disable_rx_engine(jme);
3168 jme_disable_tx_engine(jme);
29bdd921
GFT		 3169 jme_reset_mac_processor(jme);
3170 jme_free_rx_resources(jme);
3171 jme_free_tx_resources(jme);
3172 netif_carrier_off(netdev);
3173 jme->phylink = 0;
3174 }
3175
cd0ff491
GFT		 3176 tasklet_enable(&jme->txclean_task);
3177 tasklet_hi_enable(&jme->rxclean_task);
3178 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3179
fba4bc0c 3180 jme_powersave_phy(jme);
29bdd921
GFT		 3181
3182 return 0;
3183}
3184
18783c49
GFT		 3185static int
3186jme_resume(struct device *dev)
29bdd921 3187{
8ad2ddac 3188 struct pci_dev *pdev = to_pci_dev(dev);
29bdd921
GFT		 3189 struct net_device *netdev = pci_get_drvdata(pdev);
3190 struct jme_adapter *jme = netdev_priv(netdev);
3191
18783c49 3192 jme_clear_pm(jme);
e4610a83
GFT		 3193 jme_phy_on(jme);
3194 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3195 jme_set_settings(netdev, &jme->old_ecmd);
e4610a83 3196 else
29bdd921
GFT		 3197 jme_reset_phy_processor(jme);
3198
29bdd921
GFT		 3199 jme_start_irq(jme);
3200 netif_device_attach(netdev);
3201
3202 atomic_inc(&jme->link_changing);
3203
3204 jme_reset_link(jme);
3205
3206 return 0;
3207}
8ad2ddac
RW		 3208
3209static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3210#define JME_PM_OPS (&jme_pm_ops)
3211
3212#else
3213
3214#define JME_PM_OPS NULL
9b9d55de 3215#endif
29bdd921 3216
c97b5740 3217static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
cd0ff491
GFT		 3218 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3219 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3220 { }
3221};
3222
3223static struct pci_driver jme_driver = {
cd0ff491
GFT		 3224 .name = DRV_NAME,
3225 .id_table = jme_pci_tbl,
3226 .probe = jme_init_one,
3227 .remove = __devexit_p(jme_remove_one),
fba4bc0c 3228 .shutdown = jme_shutdown,
8ad2ddac 3229 .driver.pm = JME_PM_OPS,
d7699f87
GFT		 3230};
3231
3bf61c55
GFT		 3232static int __init
3233jme_init_module(void)
d7699f87 3234{
52a46ba8 3235 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3236 return pci_register_driver(&jme_driver);
3237}
3238
3bf61c55
GFT		 3239static void __exit
3240jme_cleanup_module(void)
d7699f87
GFT		 3241{
3242 pci_unregister_driver(&jme_driver);
3243}
3244
3245module_init(jme_init_module);
3246module_exit(jme_cleanup_module);
3247
3bf61c55 3248MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3249MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3250MODULE_LICENSE("GPL");
3251MODULE_VERSION(DRV_VERSION);
3252MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3253
JMicron Ethernet Linux driver