From 63fa71872bdec70f4a82e562fc34f8d87e174774 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 26 Jan 2010 22:18:09 +0100 Subject: [PATCH] ARM: zImage: __armv3_mpu_cache_flush: respect should-be-zero specification MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Probably the register content for cache operations is "don't care" in practice, but as r1 is explicitly zeroed, use that one. Acked-by: Eric Miao Signed-off-by: Uwe Kleine-König --- arch/arm/boot/compressed/head.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 7b7d95c8464..2366613ad50 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -994,7 +994,7 @@ no_cache_id: __armv3_mmu_cache_flush: __armv3_mpu_cache_flush: mov r1, #0 - mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 + mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr /* -- 2.39.3