From 4a8d57a54fb21f32ee17e0a61ca54c7a6f8f83da Mon Sep 17 00:00:00 2001 From: =?utf8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 26 Jan 2010 22:14:23 +0100 Subject: [PATCH] ARM: zImage: some comments for __armv3_mpu_cache_on MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit __armv3_mpu_cache_on seems broken. As there is noone around who knows about these machines just keep the code as is but point out the strange things. Signed-off-by: Uwe Kleine-König --- arch/arm/boot/compressed/head.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 390aa92ef04..7b7d95c8464 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -396,12 +396,18 @@ __armv3_mpu_cache_on: mov r0, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 + /* + * ?? ARMv3 MMU does not allow reading the control register, + * does this really work on ARMv3 MPU? + */ mrc p15, 0, r0, c1, c0, 0 @ read control reg @ .... .... .... WC.M orr r0, r0, #0x000d @ .... .... .... 11.1 + /* ?? this overwrites the value constructed above? */ mov r0, #0 mcr p15, 0, r0, c1, c0, 0 @ write control reg + /* ?? invalidate for the second time? */ mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr -- 2.39.3