Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
/*
* Build the IRQ handler stubs using macros from irq.h.
*/
/*
* Build the IRQ handler stubs using macros from irq.h.
*/
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+BUILD_TIMER_IRQ(0x31, 0)
+#else
BUILD_IRQ(0x32)
BUILD_IRQ(0x33)
BUILD_IRQ(0x34)
BUILD_IRQ(0x32)
BUILD_IRQ(0x33)
BUILD_IRQ(0x34)
BUILD_IRQ(0x48)
BUILD_IRQ(0x49)
BUILD_IRQ(0x4a)
BUILD_IRQ(0x48)
BUILD_IRQ(0x49)
BUILD_IRQ(0x4a)
+#ifdef CONFIG_ETRAXFS
+BUILD_TIMER_IRQ(0x4b, 0)
+#else
BUILD_IRQ(0x4c)
BUILD_IRQ(0x4d)
BUILD_IRQ(0x4e)
BUILD_IRQ(0x4c)
BUILD_IRQ(0x4d)
BUILD_IRQ(0x4e)
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
- if (irq - FIRST_IRQ < 32)
+ /* Remember, 1 let thru, 0 block. */
+ if (irq - FIRST_IRQ < 32) {
intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
rw_mask, 0);
intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
rw_mask, 0);
- else
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 1);
-
- /* Remember; 1 let thru, 0 block. */
- if (irq - FIRST_IRQ < 32)
intr_mask &= ~(1 << (irq - FIRST_IRQ));
intr_mask &= ~(1 << (irq - FIRST_IRQ));
- else
- intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
-
- if (irq - FIRST_IRQ < 32)
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
0, intr_mask);
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
0, intr_mask);
+ } else {
+ intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ rw_mask, 1);
+ intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
1, intr_mask);
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
1, intr_mask);
spin_unlock_irqrestore(&irq_lock, flags);
}
spin_unlock_irqrestore(&irq_lock, flags);
}
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
- if (irq - FIRST_IRQ < 32)
+ /* Remember, 1 let thru, 0 block. */
+ if (irq - FIRST_IRQ < 32) {
intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
rw_mask, 0);
intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
rw_mask, 0);
- else
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 1);
-
- /* Remember; 1 let thru, 0 block. */
- if (irq - FIRST_IRQ < 32)
intr_mask |= (1 << (irq - FIRST_IRQ));
intr_mask |= (1 << (irq - FIRST_IRQ));
- else
- intr_mask |= (1 << (irq - FIRST_IRQ - 32));
-
- if (irq - FIRST_IRQ < 32)
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
0, intr_mask);
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
0, intr_mask);
+ } else {
+ intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ rw_mask, 1);
+ intr_mask |= (1 << (irq - FIRST_IRQ - 32));
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
1, intr_mask);
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
1, intr_mask);
spin_unlock_irqrestore(&irq_lock, flags);
}
spin_unlock_irqrestore(&irq_lock, flags);
}