Its unclear if the PEBS state record will have only a single bit set, in
case it does not and accumulates bits, deal with that by only processing
each event once.
Also, robustify some of the code.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
struct perf_event *event = NULL;
struct perf_raw_record raw;
struct pt_regs regs;
struct perf_event *event = NULL;
struct perf_raw_record raw;
struct pt_regs regs;
int bit, n;
if (!ds || !x86_pmu.pebs)
int bit, n;
if (!ds || !x86_pmu.pebs)
for ( ; at < top; at++) {
for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
for ( ; at < top; at++) {
for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
- if (!cpuc->events[bit]->attr.precise)
+ event = cpuc->events[bit];
+ if (!test_bit(bit, cpuc->active_mask))
- event = cpuc->events[bit];
+ WARN_ON_ONCE(!event);
+
+ if (!event->attr.precise)
+ continue;
+
+ if (__test_and_set_bit(bit, (unsigned long *)&status))
+ continue;
+
+ break;
+ if (!event || bit >= MAX_PEBS_EVENTS)
continue;
if (!intel_pmu_save_and_restart(event))
continue;
if (!intel_pmu_save_and_restart(event))