[MTD] OneNAND: Single bit error detection

[net-next-2.6.git] / include / linux / mtd / onenand_regs.h

diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index 4a2daad7d738ab3769069fd45b858ff19e9d9847..e31c8f5d42712601744823dd22c5f31be157f333 100644 (file)
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -3,7 +3,7 @@
  *
  *  OneNAND Register header file
  *
- *  Copyright (C) 2005 Samsung Electronics
+ *  Copyright (C) 2005-2006 Samsung Electronics
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -72,6 +72,7 @@
 #define ONENAND_DEVICE_VCC_MASK                (0x3)
 
 #define ONENAND_DEVICE_DENSITY_512Mb   (0x002)
+#define ONENAND_DEVICE_DENSITY_1Gb     (0x003)
 
 /*
  * Version ID Register F002h (R)
@@ -110,8 +111,10 @@
 #define ONENAND_CMD_UNLOCK             (0x23)
 #define ONENAND_CMD_LOCK               (0x2A)
 #define ONENAND_CMD_LOCK_TIGHT         (0x2C)
+#define ONENAND_CMD_UNLOCK_ALL         (0x27)
 #define ONENAND_CMD_ERASE              (0x94)
 #define ONENAND_CMD_RESET              (0xF0)
+#define ONENAND_CMD_OTP_ACCESS         (0x65)
 #define ONENAND_CMD_READID             (0x90)
 
 /* NOTE: Those are not *REAL* commands */
@@ -121,8 +124,21 @@
  * System Configuration 1 Register F221h (R, R/W)
  */
 #define ONENAND_SYS_CFG1_SYNC_READ     (1 << 15)
-#define ONENAND_SYS_CFG1_BRL           (1 << 12)
-#define ONENAND_SYS_CFG1_BL            (1 << 9)
+#define ONENAND_SYS_CFG1_BRL_7         (7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6         (6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5         (5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4         (4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3         (3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10                (2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9         (1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8         (0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT     (12)
+#define ONENAND_SYS_CFG1_BL_32         (4 << 9)
+#define ONENAND_SYS_CFG1_BL_16         (3 << 9)
+#define ONENAND_SYS_CFG1_BL_8          (2 << 9)
+#define ONENAND_SYS_CFG1_BL_4          (1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT       (0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT      (9)
 #define ONENAND_SYS_CFG1_NO_ECC                (1 << 8)
 #define ONENAND_SYS_CFG1_RDY           (1 << 7)
 #define ONENAND_SYS_CFG1_INT           (1 << 6)
@@ -139,6 +155,8 @@
 #define ONENAND_CTRL_ERASE             (1 << 11)
 #define ONENAND_CTRL_ERROR             (1 << 10)
 #define ONENAND_CTRL_RSTB              (1 << 7)
+#define ONENAND_CTRL_OTP_L             (1 << 6)
+#define ONENAND_CTRL_OTP_BL            (1 << 5)
 
 /*
  * Interrupt Status Register F241h (R)
@@ -161,7 +179,13 @@
  * ECC Status Reigser FF00h (R)
  */
 #define ONENAND_ECC_1BIT               (1 << 0)
+#define ONENAND_ECC_1BIT_ALL           (0x5555)
 #define ONENAND_ECC_2BIT               (1 << 1)
 #define ONENAND_ECC_2BIT_ALL           (0xAAAA)
 
+/*
+ * One-Time Programmable (OTP)
+ */
+#define ONENAND_OTP_LOCK_OFFSET                (14)
+
 #endif /* __ONENAND_REG_H */