lxfb: rearrange/rename MSR bitfields

[net-next-2.6.git] / drivers / video / geode / lxfb.h

diff --git a/drivers/video/geode/lxfb.h b/drivers/video/geode/lxfb.h
index 0e3cb9191009a3a8ed1583c27f4ba191803fc9aa..b3fbc56ccbd7ae5f81b6e29f04526dba56ef6185 100644 (file)
--- a/drivers/video/geode/lxfb.h
+++ b/drivers/video/geode/lxfb.h
@@ -27,31 +27,6 @@ int lx_blank_display(struct fb_info *, int);
 void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
                        unsigned int, unsigned int);
 
-/* MSRS */
-
-#define GLCP_DOTPLL_RESET    (1 << 0)
-#define GLCP_DOTPLL_BYPASS   (1 << 15)
-#define GLCP_DOTPLL_HALFPIX  (1 << 24)
-#define GLCP_DOTPLL_LOCK     (1 << 25)
-
-#define DF_CONFIG_OUTPUT_MASK       0x38
-#define DF_OUTPUT_PANEL             0x08
-#define DF_OUTPUT_CRT               0x00
-#define DF_SIMULTANEOUS_CRT_AND_FP  (1 << 15)
-
-#define DF_DEFAULT_TFT_PAD_SEL_LOW  0xDFFFFFFF
-#define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F
-
-#define DC_SPARE_DISABLE_CFIFO_HGO         0x00000800
-#define DC_SPARE_VFIFO_ARB_SELECT          0x00000400
-#define DC_SPARE_WM_LPEN_OVRD              0x00000200
-#define DC_SPARE_LOAD_WM_LPEN_MASK         0x00000100
-#define DC_SPARE_DISABLE_INIT_VID_PRI      0x00000080
-#define DC_SPARE_DISABLE_VFIFO_WM          0x00000040
-#define DC_SPARE_DISABLE_CWD_CHECK         0x00000020
-#define DC_SPARE_PIX8_PAN_FIX              0x00000010
-#define DC_SPARE_FIRST_REQ_MASK            0x00000002
-
 
 /* Graphics Processor registers (table 6-29 from the data book) */
 enum gp_registers {
@@ -390,4 +365,31 @@ static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
        writel(val, par->vp_regs + 8*reg + VP_FP_START);
 }
 
+
+/* MSRs are defined in asm/geode.h; their bitfields are here */
+
+#define MSR_GLCP_DOTPLL_LOCK           (1 << 25)       /* r/o */
+#define MSR_GLCP_DOTPLL_HALFPIX                (1 << 24)
+#define MSR_GLCP_DOTPLL_BYPASS         (1 << 15)
+#define MSR_GLCP_DOTPLL_DOTRESET       (1 << 0)
+
+/* note: this is actually the VP's GLD_MSR_CONFIG */
+#define MSR_LX_GLD_MSR_CONFIG_FMT      ((1 << 3) | (1 << 4) | (1 << 5))
+#define MSR_LX_GLD_MSR_CONFIG_FMT_FP   (1 << 3)
+#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT  (0)
+#define MSR_LX_GLD_MSR_CONFIG_FPC      (1 << 15)       /* FP *and* CRT */
+
+#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW  0xDFFFFFFF      /* ??? */
+#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F      /* ??? */
+
+#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11)       /* undocumented */
+#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10)       /* undocumented */
+#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD  (1 << 9)        /* undocumented */
+#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M        (1 << 8)        /* undocumented */
+#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI        (1 << 7)        /* undocumented */
+#define MSR_LX_SPARE_MSR_DIS_VIFO_WM   (1 << 6)
+#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5)        /* undocumented */
+#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX  (1 << 4)        /* undocumented */
+#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK        (1 << 1)        /* undocumented */
+
 #endif