*/
#include <typedefs.h>
+#include <linux/string.h>
+#include <linuxver.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
si_t *sih; /* System interconnect handle */
osl_t *osh; /* OSL handle */
- uint8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */
+ u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */
bool pcie_pr42767;
- uint8 pcie_polarity;
- uint8 pcie_war_aspm_ovr; /* Override ASPM/Clkreq settings */
+ u8 pcie_polarity;
+ u8 pcie_war_aspm_ovr; /* Override ASPM/Clkreq settings */
- uint8 pmecap_offset; /* PM Capability offset in the config space */
+ u8 pmecap_offset; /* PM Capability offset in the config space */
bool pmecap; /* Capable of generating PME */
} pcicore_info_t;
ASSERT(sih->bustype == PCI_BUS);
/* alloc pcicore_info_t */
- if ((pi = MALLOC(osh, sizeof(pcicore_info_t))) == NULL) {
+ pi = MALLOC(osh, sizeof(pcicore_info_t));
+ if (pi == NULL) {
PCI_ERROR(("pci_attach: malloc failed! malloced %d bytes\n",
MALLOCED(osh)));
- return (NULL);
+ return NULL;
}
bzero(pi, sizeof(pcicore_info_t));
pi->osh = osh;
if (sih->buscoretype == PCIE_CORE_ID) {
- uint8 cap_ptr;
+ u8 cap_ptr;
pi->regs.pcieregs = (sbpcieregs_t *) regs;
cap_ptr =
pcicore_find_pci_capability(pi->osh, PCI_CAP_PCIECAP_ID,
/* return cap_offset if requested capability exists in the PCI config space */
/* Note that it's caller's responsibility to make sure it's a pci bus */
-uint8
-pcicore_find_pci_capability(osl_t *osh, uint8 req_cap_id, uchar *buf,
+u8
+pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id, unsigned char *buf,
uint32 *buflen)
{
- uint8 cap_id;
- uint8 cap_ptr = 0;
+ u8 cap_id;
+ u8 cap_ptr = 0;
uint32 bufsize;
- uint8 byte_val;
+ u8 byte_val;
/* check for Header type 0 */
byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
}
/* found the caller requested capability */
if ((buf != NULL) && (buflen != NULL)) {
- uint8 cap_data;
+ u8 cap_data;
bufsize = *buflen;
if (!bufsize)
}
/* ***** Support functions ***** */
-uint8 pcie_clkreq(void *pch, uint32 mask, uint32 val)
+u8 pcie_clkreq(void *pch, uint32 mask, uint32 val)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
uint32 reg_val;
- uint8 offset;
+ u8 offset;
offset = pi->pciecap_lcreg_offset;
if (!offset)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
si_t *sih = pi->sih;
- uint16 val16, *reg16;
+ u16 val16, *reg16;
uint32 w;
if (!PCIE_ASPM(sih))
static void BCMINITFN(pcie_misc_config_fixup) (pcicore_info_t *pi)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- uint16 val16, *reg16;
+ u16 val16, *reg16;
reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
val16 = R_REG(pi->osh, reg16);
static void pcie_war_noplldown(pcicore_info_t *pi)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- uint16 *reg16;
+ u16 *reg16;
ASSERT(pi->sih->buscorerev == 7);
pcie_misc_config_fixup(pi);
}
-void pcie_war_ovr_aspm_update(void *pch, uint8 aspm)
+void pcie_war_ovr_aspm_update(void *pch, u8 aspm)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
/* Just uses PCI config accesses to find out, when needed before sb_attach is done */
bool pcicore_pmecap_fast(osl_t *osh)
{
- uint8 cap_ptr;
+ u8 cap_ptr;
uint32 pmecap;
cap_ptr =
pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(uint32));
- return ((pmecap & PME_CAP_PM_STATES) != 0);
+ return (pmecap & PME_CAP_PM_STATES) != 0;
}
/* return TRUE if PM capability exists in the pci config space
*/
static bool pcicore_pmecap(pcicore_info_t *pi)
{
- uint8 cap_ptr;
+ u8 cap_ptr;
uint32 pmecap;
if (!pi->pmecap_offset) {
pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
}
- return (pi->pmecap);
+ return pi->pmecap;
}
/* Enable PME generation */
uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
- uint8 offset;
+ u8 offset;
offset = pi->pciecap_lcreg_offset;
if (!offset)