wl_intrsrestore(physhim->wl, macintmask);
}
-void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, uint16 v)
+void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, u16 v)
{
wlc_bmac_write_shm(physhim->wlc_hw, offset, v);
}
-uint16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset)
+u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset)
{
return wlc_bmac_read_shm(physhim->wlc_hw, offset);
}
void
-wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, uint8 idx, uint16 mask,
- uint16 val, int bands)
+wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, u16 mask,
+ u16 val, int bands)
{
wlc_bmac_mhf(physhim->wlc_hw, idx, mask, val, bands);
}
wlc_suspend_mac_and_wait(physhim->wlc);
}
-void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, uint8 spurmode)
+void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode)
{
wlc_bmac_switch_macfreq(physhim->wlc_hw, spurmode);
}
wlc_bmac_phy_reset(physhim->wlc_hw);
}
-void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, uint16 bw)
+void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw)
{
wlc_bmac_bw_set(physhim->wlc_hw, bw);
}
-uint16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim)
+u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim)
{
return wlc_bmac_get_txant(physhim->wlc_hw);
}
wlc_bmac_write_template_ram(physhim->wlc_hw, offset, len, buf);
}
-uint16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim, uint8 rate)
+u16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim, u8 rate)
{
return wlc_bmac_rate_shm_offset(physhim->wlc_hw, rate);
}
void
wlapi_bmac_pktengtx(wlc_phy_shim_info_t *physhim, wl_pkteng_t *pkteng,
- uint8 rate, struct ether_addr *sa, uint32 wait_delay)
+ u8 rate, struct ether_addr *sa, uint32 wait_delay)
{
wlc_pktengtx(physhim->wlc, pkteng, rate, sa, wait_delay);
}