[TG3]: Add PHY workaround for 5755M.

[net-next-2.6.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index cf78a7e5997b1734ef6655896817c6d8a7d3cb1a..80f59ac7ec58b3fd8ff7c7783bf2ee5e57da3038 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1658,6 +1658,9 @@
 #define MII_TG3_EPHY_TEST              0x1f /* 5906 PHY register */
 #define MII_TG3_EPHY_SHADOW_EN         0x80
 
+#define MII_TG3_TEST1                  0x1e
+#define MII_TG3_TEST1_TRIM_EN          0x0010
+
 /* There are two ways to manage the TX descriptors on the tigon3.
  * Either the descriptors are in host DMA'able memory, or they
  * exist only in the cards on-chip SRAM.  All 16 send bds are under
@@ -2256,6 +2259,7 @@ struct tg3 {
 #define TG3_FLG2_1SHOT_MSI             0x10000000
 #define TG3_FLG2_PHY_JITTER_BUG                0x20000000
 #define TG3_FLG2_NO_FWARE_REPORTED     0x40000000
+#define TG3_FLG2_PHY_ADJUST_TRIM       0x80000000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3