sdhci: 8-bit data transfer width support

[net-next-2.6.git] / drivers / mmc / host / sdhci.h

diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c8468134adc95db0dbfd5ec901ebf96930c22b84..030de492880eebd58c7cc36ca26507834f4aec59 100644 (file)
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -72,6 +72,7 @@
 #define   SDHCI_CTRL_ADMA1     0x08
 #define   SDHCI_CTRL_ADMA32    0x10
 #define   SDHCI_CTRL_ADMA64    0x18
+#define  SDHCI_CTRL_8BITBUS    0x20
 
 #define SDHCI_POWER_CONTROL    0x29
 #define  SDHCI_POWER_ON                0x01
@@ -240,6 +241,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN              (1<<25)
 /* Controller cannot support End Attribute in NOP ADMA descriptor */
 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC              (1<<26)
+/* Controller is missing device caps. Use caps provided by host */
+#define SDHCI_QUIRK_MISSING_CAPS                       (1<<27)
 
        int                     irq;            /* Device IRQ */
        void __iomem *          ioaddr;         /* Mapped address */
@@ -292,6 +295,8 @@ struct sdhci_host {
 
        struct timer_list       timer;          /* Timer for timeouts */
 
+       unsigned int            caps;           /* Alternative capabilities */
+
        unsigned long           private[0] ____cacheline_aligned;
 };