drm/radeon/kms: avoid corner case issue with unmappable vram V2

[net-next-2.6.git] / drivers / gpu / drm / radeon / rs690.c

diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index f3a8c9344c64b27600bed94bbe9c81a7bfc9f6f7..4dc2a87ea68018f0292cc0724d6ef4868c00e8ac 100644 (file)
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -157,10 +157,11 @@ void rs690_mc_init(struct radeon_device *rdev)
        rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
        rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
        rdev->mc.visible_vram_size = rdev->mc.aper_size;
+       rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
        base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
        base = G_000100_MC_FB_START(base) << 16;
-       rs690_pm_info(rdev);
        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+       rs690_pm_info(rdev);
        radeon_vram_location(rdev, &rdev->mc, base);
        rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
        radeon_gtt_location(rdev, &rdev->mc);
@@ -398,7 +399,9 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
        struct drm_display_mode *mode1 = NULL;
        struct rs690_watermark wm0;
        struct rs690_watermark wm1;
-       u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
+       u32 tmp;
+       u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
+       u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
        fixed20_12 priority_mark02, priority_mark12, fill_rate;
        fixed20_12 a, b;
 
@@ -495,10 +498,6 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                        d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
                        d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
                }
-               WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
-               WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
-               WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
-               WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
        } else if (mode0) {
                if (dfixed_trunc(wm0.dbpp) > 64)
                        a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
@@ -528,13 +527,7 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
                if (rdev->disp_priority == 2)
                        d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
-               WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
-               WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
-               WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
-                       S_006D48_D2MODE_PRIORITY_A_OFF(1));
-               WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
-                       S_006D4C_D2MODE_PRIORITY_B_OFF(1));
-       } else {
+       } else if (mode1) {
                if (dfixed_trunc(wm1.dbpp) > 64)
                        a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
                else
@@ -563,13 +556,12 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
                if (rdev->disp_priority == 2)
                        d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
-               WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
-                       S_006548_D1MODE_PRIORITY_A_OFF(1));
-               WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
-                       S_00654C_D1MODE_PRIORITY_B_OFF(1));
-               WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
-               WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
        }
+
+       WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+       WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
+       WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
+       WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 }
 
 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)