drm/radeon/kms: move a bunch of modesetting debug to correct debug usage.

[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index a68728dbd41dd2db8e4b2d4d66b305f022e54f06..283beedc2cbf4f9e6701686c6b56033e95ff460b 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -42,7 +42,7 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
        struct radeon_device *rdev = dev->dev_private;
        int i;
 
-       DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
+       DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
        WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
 
        WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
@@ -75,7 +75,7 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
        struct radeon_device *rdev = dev->dev_private;
        int i;
 
-       DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
+       DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
        WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 
        WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
@@ -469,7 +469,7 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
        uint32_t post_div;
        u32 pll_out_min, pll_out_max;
 
-       DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
+       DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
        freq = freq * 1000;
 
        if (pll->flags & RADEON_PLL_IS_LCD) {
@@ -805,7 +805,7 @@ done:
        *ref_div_p = ref_div;
        *post_div_p = post_div;
 
-       DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
+       DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
 }
 
 void radeon_compute_pll(struct radeon_pll *pll,