drm/radeon/kms: fix calculation of h/v scaling factors

[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 8154cdf796e4a752a0a33d6983852cabee7acf4a..12a54145b64a75484236825421e1567998b9a8e0 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -42,7 +42,7 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
        struct radeon_device *rdev = dev->dev_private;
        int i;
 
-       DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
+       DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
        WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
 
        WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
@@ -75,7 +75,7 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
        struct radeon_device *rdev = dev->dev_private;
        int i;
 
-       DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
+       DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
        WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 
        WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
@@ -469,7 +469,7 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
        uint32_t post_div;
        u32 pll_out_min, pll_out_max;
 
-       DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
+       DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
        freq = freq * 1000;
 
        if (pll->flags & RADEON_PLL_IS_LCD) {
@@ -558,15 +558,17 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
                                        current_freq = radeon_div(tmp, ref_div * post_div);
 
                                        if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
-                                               error = freq - current_freq;
-                                               error = error < 0 ? 0xffffffff : error;
+                                               if (freq < current_freq)
+                                                       error = 0xffffffff;
+                                               else
+                                                       error = freq - current_freq;
                                        } else
                                                error = abs(current_freq - freq);
                                        vco_diff = abs(vco - best_vco);
 
                                        if ((best_vco == 0 && error < best_error) ||
                                            (best_vco != 0 &&
-                                            (error < best_error - 100 ||
+                                            ((best_error > 100 && error < best_error - 100) ||
                                              (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
                                                best_post_div = post_div;
                                                best_ref_div = ref_div;
@@ -803,7 +805,7 @@ done:
        *ref_div_p = ref_div;
        *post_div_p = post_div;
 
-       DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
+       DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
 }
 
 void radeon_compute_pll(struct radeon_pll *pll,
@@ -1071,11 +1073,13 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct radeon_encoder *radeon_encoder;
        bool first = true;
+       u32 src_v = 1, dst_v = 1;
+       u32 src_h = 1, dst_h = 1;
 
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-               radeon_encoder = to_radeon_encoder(encoder);
                if (encoder->crtc != crtc)
                        continue;
+               radeon_encoder = to_radeon_encoder(encoder);
                if (first) {
                        /* set scaling */
                        if (radeon_encoder->rmx_type == RMX_OFF)
@@ -1085,6 +1089,10 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
                                radeon_crtc->rmx_type = radeon_encoder->rmx_type;
                        else
                                radeon_crtc->rmx_type = RMX_OFF;
+                       src_v = crtc->mode.vdisplay;
+                       dst_v = radeon_crtc->native_mode.vdisplay;
+                       src_h = crtc->mode.hdisplay;
+                       dst_h = radeon_crtc->native_mode.vdisplay;
                        /* copy native mode */
                        memcpy(&radeon_crtc->native_mode,
                               &radeon_encoder->native_mode,
@@ -1094,22 +1102,22 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
                        if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
                                /* WARNING: Right now this can't happen but
                                 * in the future we need to check that scaling
-                                * are consistent accross different encoder
+                                * are consistent across different encoder
                                 * (ie all encoder can work with the same
                                 *  scaling).
                                 */
-                               DRM_ERROR("Scaling not consistent accross encoder.\n");
+                               DRM_ERROR("Scaling not consistent across encoder.\n");
                                return false;
                        }
                }
        }
        if (radeon_crtc->rmx_type != RMX_OFF) {
                fixed20_12 a, b;
-               a.full = dfixed_const(crtc->mode.vdisplay);
-               b.full = dfixed_const(radeon_crtc->native_mode.hdisplay);
+               a.full = dfixed_const(src_v);
+               b.full = dfixed_const(dst_v);
                radeon_crtc->vsc.full = dfixed_div(a, b);
-               a.full = dfixed_const(crtc->mode.hdisplay);
-               b.full = dfixed_const(radeon_crtc->native_mode.vdisplay);
+               a.full = dfixed_const(src_h);
+               b.full = dfixed_const(dst_h);
                radeon_crtc->hsc.full = dfixed_div(a, b);
        } else {
                radeon_crtc->vsc.full = dfixed_const(1);