drm/nouveau: add instmem flush() hook

[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_sgdma.c

diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index 1d6ee8b55154c95aa763ed278c31b14da32fa9a7..1b2ab5a714ceb5e4877e33c4c777a4c161a9c97f 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -97,7 +97,6 @@ nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
 
        NV_DEBUG(dev, "pg=0x%lx\n", mem->mm_node->start);
 
-       dev_priv->engine.instmem.prepare_access(nvbe->dev, true);
        pte = nouveau_sgdma_pte(nvbe->dev, mem->mm_node->start << PAGE_SHIFT);
        nvbe->pte_start = pte;
        for (i = 0; i < nvbe->nr_pages; i++) {
@@ -116,7 +115,7 @@ nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
                        dma_offset += NV_CTXDMA_PAGE_SIZE;
                }
        }
-       dev_priv->engine.instmem.finish_access(nvbe->dev);
+       dev_priv->engine.instmem.flush(nvbe->dev);
 
        if (dev_priv->card_type == NV_50) {
                nv_wr32(dev, 0x100c80, 0x00050001);
@@ -154,7 +153,6 @@ nouveau_sgdma_unbind(struct ttm_backend *be)
        if (!nvbe->bound)
                return 0;
 
-       dev_priv->engine.instmem.prepare_access(nvbe->dev, true);
        pte = nvbe->pte_start;
        for (i = 0; i < nvbe->nr_pages; i++) {
                dma_addr_t dma_offset = dev_priv->gart_info.sg_dummy_bus;
@@ -170,7 +168,7 @@ nouveau_sgdma_unbind(struct ttm_backend *be)
                        dma_offset += NV_CTXDMA_PAGE_SIZE;
                }
        }
-       dev_priv->engine.instmem.finish_access(nvbe->dev);
+       dev_priv->engine.instmem.flush(nvbe->dev);
 
        if (dev_priv->card_type == NV_50) {
                nv_wr32(dev, 0x100c80, 0x00050001);
@@ -272,7 +270,6 @@ nouveau_sgdma_init(struct drm_device *dev)
                pci_map_page(dev->pdev, dev_priv->gart_info.sg_dummy_page, 0,
                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 
-       dev_priv->engine.instmem.prepare_access(dev, true);
        if (dev_priv->card_type < NV_50) {
                /* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and
                 * confirmed to work on c51.  Perhaps means NV_DMA_TARGET_PCIE
@@ -294,7 +291,7 @@ nouveau_sgdma_init(struct drm_device *dev)
                        nv_wo32(dev, gpuobj, (i+4)/4, 0);
                }
        }
-       dev_priv->engine.instmem.finish_access(dev);
+       dev_priv->engine.instmem.flush(dev);
 
        dev_priv->gart_info.type      = NOUVEAU_GART_SGDMA;
        dev_priv->gart_info.aper_base = 0;
@@ -325,14 +322,11 @@ nouveau_sgdma_get_page(struct drm_device *dev, uint32_t offset, uint32_t *page)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
-       struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
        int pte;
 
        pte = (offset >> NV_CTXDMA_PAGE_SHIFT);
        if (dev_priv->card_type < NV_50) {
-               instmem->prepare_access(dev, false);
                *page = nv_ro32(dev, gpuobj, (pte + 2)) & ~NV_CTXDMA_PAGE_MASK;
-               instmem->finish_access(dev);
                return 0;
        }