drm/nouveau: Add some PFB register defines.

[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_calc.c

diff --git a/drivers/gpu/drm/nouveau/nouveau_calc.c b/drivers/gpu/drm/nouveau/nouveau_calc.c
index 88f9bc0941eb293a7cf727f261740900da5e14ba..ca85da78484653180ef6c03b64655df3e8117202 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_calc.c
+++ b/drivers/gpu/drm/nouveau/nouveau_calc.c
@@ -200,7 +200,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
        struct nv_sim_state sim_data;
        int MClk = nouveau_hw_get_clock(dev, MPLL);
        int NVClk = nouveau_hw_get_clock(dev, NVPLL);
-       uint32_t cfg1 = nvReadFB(dev, NV_PFB_CFG1);
+       uint32_t cfg1 = nvReadFB(dev, NV04_PFB_CFG1);
 
        sim_data.pclk_khz = VClk;
        sim_data.mclk_khz = MClk;
@@ -218,7 +218,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
                sim_data.mem_latency = 3;
                sim_data.mem_page_miss = 10;
        } else {
-               sim_data.memory_type = nvReadFB(dev, NV_PFB_CFG0) & 0x1;
+               sim_data.memory_type = nvReadFB(dev, NV04_PFB_CFG0) & 0x1;
                sim_data.memory_width = (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
                sim_data.mem_latency = cfg1 & 0xf;
                sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);