drm/i915: wait for actual vblank, not just 20ms

[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 281db6e5403ad1d9ed024e2924cfbc0344c1951a..67e3ec1a6af9dc482870e842b3739a86581176ae 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -170,6 +170,7 @@
 #define   MI_NO_WRITE_FLUSH    (1 << 2)
 #define   MI_SCENE_COUNT       (1 << 3) /* just increment scene count */
 #define   MI_END_SCENE         (1 << 4) /* flush binner and incr scene count */
+#define   MI_INVALIDATE_ISP    (1 << 5) /* invalidate indirect state pointers */
 #define MI_BATCH_BUFFER_END    MI_INSTR(0x0a, 0)
 #define MI_REPORT_HEAD         MI_INSTR(0x07, 0)
 #define MI_OVERLAY_FLIP                MI_INSTR(0x11,0)
@@ -180,6 +181,12 @@
 #define MI_DISPLAY_FLIP                MI_INSTR(0x14, 2)
 #define MI_DISPLAY_FLIP_I915   MI_INSTR(0x14, 1)
 #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
+#define MI_SET_CONTEXT         MI_INSTR(0x18, 0)
+#define   MI_MM_SPACE_GTT              (1<<8)
+#define   MI_MM_SPACE_PHYSICAL         (0<<8)
+#define   MI_SAVE_EXT_STATE_EN         (1<<3)
+#define   MI_RESTORE_EXT_STATE_EN      (1<<2)
+#define   MI_RESTORE_INHIBIT           (1<<0)
 #define MI_STORE_DWORD_IMM     MI_INSTR(0x20, 1)
 #define   MI_MEM_VIRTUAL       (1 << 22) /* 965+ only */
 #define MI_STORE_DWORD_INDEX   MI_INSTR(0x21, 1)
@@ -1099,6 +1106,11 @@
 #define DDRMPLL1               0X12c20
 #define PEG_BAND_GAP_DATA      0x14d68
 
+/*
+ * Logical Context regs
+ */
+#define CCID                   0x2180
+#define   CCID_EN              (1<<0)
 /*
  * Overlay regs
  */
@@ -2069,6 +2081,7 @@
 #define PIPE_DITHER_TYPE_ST01          (1 << 2)
 /* Pipe A */
 #define PIPEADSL               0x70000
+#define   DSL_LINEMASK         0x00000fff
 #define PIPEACONF              0x70008
 #define   PIPEACONF_ENABLE     (1<<31)
 #define   PIPEACONF_DISABLE    0
@@ -2928,6 +2941,7 @@
 #define  TRANS_DP_VSYNC_ACTIVE_LOW     0
 #define  TRANS_DP_HSYNC_ACTIVE_HIGH    (1<<3)
 #define  TRANS_DP_HSYNC_ACTIVE_LOW     0
+#define  TRANS_DP_SYNC_MASK    (3<<3)
 
 /* SNB eDP training params */
 /* SNB A-stepping */