amd64_edac: wrap-up pci config read error handling

[net-next-2.6.git] / drivers / edac / amd64_edac.h

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index c6f359a85207e24552baac189270cb3702173b51..16f2df449a099e79754dd55b317c17251b3e35ca 100644 (file)
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -147,6 +147,8 @@
 #define MAX_CS_COUNT                   8
 #define DRAM_REG_COUNT                 8
 
+#define ON true
+#define OFF false
 
 /*
  * PCI-defined configuration space registers
@@ -386,10 +388,7 @@ enum {
 #define K8_NBCAP_DUAL_NODE             BIT(1)
 #define K8_NBCAP_DCT_DUAL              BIT(0)
 
-/*
- * MSR Regs
- */
-#define K8_MSR_MCGCTL                  0x017b
+/* MSRs */
 #define K8_MSR_MCGCTL_NBE              BIT(4)
 
 #define K8_MSR_MC4CTL                  0x0410
@@ -487,7 +486,6 @@ struct amd64_pvt {
        /* Save old hw registers' values before we modified them */
        u32 nbctl_mcgctl_saved;         /* When true, following 2 are valid */
        u32 old_nbctl;
-       unsigned long old_mcgctl;       /* per core on this node */
 
        /* MC Type Index value: socket F vs Family 10h */
        u32 mc_type_index;
@@ -495,6 +493,7 @@ struct amd64_pvt {
        /* misc settings */
        struct flags {
                unsigned long cf8_extcfg:1;
+               unsigned long ecc_report:1;
        } flags;
 };
 
@@ -566,6 +565,22 @@ static inline struct low_ops *family_ops(int index)
        return &amd64_family_types[index].ops;
 }
 
+static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
+                                          u32 *val, const char *func)
+{
+       int err = 0;
+
+       err = pci_read_config_dword(pdev, offset, val);
+       if (err)
+               amd64_printk(KERN_WARNING, "%s: error reading F%dx%x.\n",
+                            func, PCI_FUNC(pdev->devfn), offset);
+
+       return err;
+}
+
+#define amd64_read_pci_cfg(pdev, offset, val)  \
+       amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
+
 /*
  * For future CPU versions, verify the following as new 'slow' rates appear and
  * modify the necessary skip values for the supported CPU.