MIPS: Add support for hardware performance events (mipsxx)

[net-next-2.6.git] / arch / mips / kernel / perf_event.c

diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
index 95c833e8dc8165400af0e8f4db76d397e26cbf57..2b7f3f703b83cbeb86f48926517f1e0887f07496 100644 (file)
--- a/arch/mips/kernel/perf_event.c
+++ b/arch/mips/kernel/perf_event.c
@@ -88,6 +88,9 @@ struct mips_perf_event {
 #endif
 };
 
+static struct mips_perf_event raw_event;
+static DEFINE_MUTEX(raw_event_mutex);
+
 #define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
 #define C(x) PERF_COUNT_HW_CACHE_##x
 
@@ -104,6 +107,7 @@ struct mips_pmu {
        void            (*write_counter)(unsigned int idx, u64 val);
        void            (*enable_event)(struct hw_perf_event *evt, int idx);
        void            (*disable_event)(int idx);
+       const struct mips_perf_event *(*map_raw_event)(u64 config);
        const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
        const struct mips_perf_event (*cache_event_map)
                                [PERF_COUNT_HW_CACHE_MAX]
@@ -409,6 +413,7 @@ static int validate_group(struct perf_event *event)
  * mipsxx/rm9000/loongson2 have different performance counters, they have
  * specific low-level init routines.
  */
+static void reset_counters(void *arg);
 static int __hw_perf_event_init(struct perf_event *event);
 
 static void hw_perf_event_destroy(struct perf_event *event)
@@ -488,6 +493,8 @@ handle_associated_event(struct cpu_hw_events *cpuc,
                mipspmu->disable_event(idx);
 }
 
+#include "perf_event_mipsxx.c"
+
 /* Callchain handling code. */
 static inline void
 callchain_store(struct perf_callchain_entry *entry,