2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
27 #define DRV_NAME "jme"
28 #define DRV_VERSION "1.0.6"
29 #define PFX DRV_NAME ": "
31 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35 * Message related definitions
37 #define JME_DEF_MSG_ENABLE \
44 #define jeprintk(pdev, fmt, args...) \
45 printk(KERN_ERR PFX fmt, ## args)
48 #define tx_dbg(priv, fmt, args...) \
49 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
51 #define tx_dbg(priv, fmt, args...) \
54 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
59 * Extra PCI Configuration space interface
61 #define PCI_DCSR_MRRS 0x59
62 #define PCI_DCSR_MRRS_MASK 0x70
64 enum pci_dcsr_mrrs_vals {
86 __u8 wn; /* Number of write actions */
87 __u8 rn; /* Number of read actions */
88 __u8 bitn; /* Number of bits per action */
89 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
90 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
92 /* Internal use only */
96 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
99 enum jme_spi_op_bits {
100 SPI_MODE_CPHA = 0x01,
101 SPI_MODE_CPOL = 0x02,
105 #define HALF_US 500 /* 500 ns */
106 #define JMESPIIOCTL SIOCDEVPRIVATE
109 * Dynamic(adaptive)/Static PCC values
111 enum dynamic_pcc_values {
128 unsigned long last_bytes;
129 unsigned long last_pkts;
130 unsigned long intr_cnt;
132 unsigned char attempt;
135 #define PCC_INTERVAL_US 100000
136 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
137 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
138 #define PCC_P2_THRESHOLD 800
139 #define PCC_INTR_THRESHOLD 800
140 #define PCC_TX_TO 1000
146 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
148 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
149 #define TX_DESC_SIZE 16
151 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
211 enum jme_txdesc_flags_bits {
222 #define TXDESC_MSS_SHIFT 2
223 enum jme_txwbdesc_flags_bits {
226 TXWBFLAG_TMOUT = 0x20,
227 TXWBFLAG_TRYOUT = 0x10,
230 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
235 #define RX_DESC_SIZE 16
237 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
238 #define RX_BUF_DMA_ALIGN 8
239 #define RX_PREPAD_SIZE 10
240 #define ETH_CRC_LEN 2
241 #define RX_VLANHDR_LEN 2
242 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
289 enum jme_rxdesc_flags_bits {
295 enum jme_rxwbdesc_flags_bits {
296 RXWBFLAG_OWN = 0x8000,
297 RXWBFLAG_INT = 0x4000,
298 RXWBFLAG_MF = 0x2000,
299 RXWBFLAG_64BIT = 0x2000,
300 RXWBFLAG_TCPON = 0x1000,
301 RXWBFLAG_UDPON = 0x0800,
302 RXWBFLAG_IPCS = 0x0400,
303 RXWBFLAG_TCPCS = 0x0200,
304 RXWBFLAG_UDPCS = 0x0100,
305 RXWBFLAG_TAGON = 0x0080,
306 RXWBFLAG_IPV4 = 0x0040,
307 RXWBFLAG_IPV6 = 0x0020,
308 RXWBFLAG_PAUSE = 0x0010,
309 RXWBFLAG_MAGIC = 0x0008,
310 RXWBFLAG_WAKEUP = 0x0004,
311 RXWBFLAG_DEST = 0x0003,
312 RXWBFLAG_DEST_UNI = 0x0001,
313 RXWBFLAG_DEST_MUL = 0x0002,
314 RXWBFLAG_DEST_BRO = 0x0003,
317 enum jme_rxwbdesc_desccnt_mask {
318 RXWBDCNT_WBCPL = 0x80,
319 RXWBDCNT_DCNT = 0x7F,
322 enum jme_rxwbdesc_errstat_bits {
323 RXWBERR_LIMIT = 0x80,
324 RXWBERR_MIIER = 0x40,
325 RXWBERR_NIBON = 0x20,
326 RXWBERR_COLON = 0x10,
327 RXWBERR_ABORT = 0x08,
328 RXWBERR_SHORT = 0x04,
329 RXWBERR_OVERUN = 0x02,
330 RXWBERR_CRCERR = 0x01,
331 RXWBERR_ALLERR = 0xFF,
335 * Buffer information corresponding to ring descriptors.
337 struct jme_buffer_info {
342 unsigned long start_xmit;
346 * The structure holding buffer information and ring descriptors all together.
349 void *alloc; /* pointer to allocated memory */
350 void *desc; /* pointer to ring memory */
351 dma_addr_t dmaalloc; /* phys address of ring alloc */
352 dma_addr_t dma; /* phys address for ring dma */
354 /* Buffer information corresponding to each descriptor */
355 struct jme_buffer_info *bufinf;
358 atomic_t next_to_clean;
362 #define NET_STAT(priv) (priv->dev->stats)
363 #define NETDEV_GET_STATS(netdev, fun_ptr)
364 #define DECLARE_NET_DEVICE_STATS
366 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
367 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
368 netif_napi_add(dev, napis, pollfn, q);
369 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
370 #define JME_NAPI_WEIGHT(w) int w
371 #define JME_NAPI_WEIGHT_VAL(w) w
372 #define JME_NAPI_WEIGHT_SET(w, r)
373 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
374 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
375 #define JME_NAPI_DISABLE(priv) \
376 if (!napi_disable_pending(&priv->napi)) \
377 napi_disable(&priv->napi);
378 #define JME_RX_SCHEDULE_PREP(priv) \
379 napi_schedule_prep(&priv->napi)
380 #define JME_RX_SCHEDULE(priv) \
381 __napi_schedule(&priv->napi);
384 * Jmac Adapter Private data
387 struct pci_dev *pdev;
388 struct net_device *dev;
390 struct mii_if_info mii_if;
391 struct jme_ring rxring[RX_RING_NR];
392 struct jme_ring txring[TX_RING_NR];
394 spinlock_t macaddr_lock;
395 spinlock_t rxmcs_lock;
396 spinlock_t vlgrp_lock;
397 struct tasklet_struct rxempty_task;
398 struct tasklet_struct rxclean_task;
399 struct tasklet_struct txclean_task;
400 struct tasklet_struct linkch_task;
401 struct tasklet_struct pcc_task;
412 u32 tx_wake_threshold;
416 unsigned int fpgaver;
417 unsigned int chiprev;
420 struct ethtool_cmd old_ecmd;
421 unsigned int old_mtu;
422 struct vlan_group *vlgrp;
423 struct dynpcc_info dpi;
425 atomic_t link_changing;
426 atomic_t tx_cleaning;
427 atomic_t rx_cleaning;
429 int (*jme_rx)(struct sk_buff *skb);
430 int (*jme_vlan_rx)(struct sk_buff *skb,
431 struct vlan_group *grp,
432 unsigned short vlan_tag);
434 DECLARE_NET_DEVICE_STATS
437 enum jme_flags_bits {
443 JME_FLAG_SHUTDOWN = 6,
446 #define TX_TIMEOUT (5 * HZ)
447 #define JME_REG_LEN 0x500
448 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
450 static inline struct jme_adapter*
451 jme_napi_priv(struct napi_struct *napi)
453 struct jme_adapter *jme;
454 jme = container_of(napi, struct jme_adapter, napi);
461 enum jme_iomap_offsets {
468 enum jme_iomap_lens {
475 enum jme_iomap_regs {
476 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
477 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
478 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
479 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
480 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
481 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
482 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
483 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
485 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
486 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
487 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
488 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
489 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
490 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
491 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
492 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
493 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
494 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
495 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
496 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
498 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
499 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
500 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
503 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
504 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
505 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
506 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
509 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
510 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
511 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
512 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
513 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
514 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
515 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
516 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
517 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
518 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
519 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
520 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
521 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
522 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
523 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
524 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
528 * TX Control/Status Bits
531 TXCS_QUEUE7S = 0x00008000,
532 TXCS_QUEUE6S = 0x00004000,
533 TXCS_QUEUE5S = 0x00002000,
534 TXCS_QUEUE4S = 0x00001000,
535 TXCS_QUEUE3S = 0x00000800,
536 TXCS_QUEUE2S = 0x00000400,
537 TXCS_QUEUE1S = 0x00000200,
538 TXCS_QUEUE0S = 0x00000100,
539 TXCS_FIFOTH = 0x000000C0,
540 TXCS_DMASIZE = 0x00000030,
541 TXCS_BURST = 0x00000004,
542 TXCS_ENABLE = 0x00000001,
545 enum jme_txcs_value {
546 TXCS_FIFOTH_16QW = 0x000000C0,
547 TXCS_FIFOTH_12QW = 0x00000080,
548 TXCS_FIFOTH_8QW = 0x00000040,
549 TXCS_FIFOTH_4QW = 0x00000000,
551 TXCS_DMASIZE_64B = 0x00000000,
552 TXCS_DMASIZE_128B = 0x00000010,
553 TXCS_DMASIZE_256B = 0x00000020,
554 TXCS_DMASIZE_512B = 0x00000030,
556 TXCS_SELECT_QUEUE0 = 0x00000000,
557 TXCS_SELECT_QUEUE1 = 0x00010000,
558 TXCS_SELECT_QUEUE2 = 0x00020000,
559 TXCS_SELECT_QUEUE3 = 0x00030000,
560 TXCS_SELECT_QUEUE4 = 0x00040000,
561 TXCS_SELECT_QUEUE5 = 0x00050000,
562 TXCS_SELECT_QUEUE6 = 0x00060000,
563 TXCS_SELECT_QUEUE7 = 0x00070000,
565 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
569 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
572 * TX MAC Control/Status Bits
574 enum jme_txmcs_bit_masks {
575 TXMCS_IFG2 = 0xC0000000,
576 TXMCS_IFG1 = 0x30000000,
577 TXMCS_TTHOLD = 0x00000300,
578 TXMCS_FBURST = 0x00000080,
579 TXMCS_CARRIEREXT = 0x00000040,
580 TXMCS_DEFER = 0x00000020,
581 TXMCS_BACKOFF = 0x00000010,
582 TXMCS_CARRIERSENSE = 0x00000008,
583 TXMCS_COLLISION = 0x00000004,
584 TXMCS_CRC = 0x00000002,
585 TXMCS_PADDING = 0x00000001,
588 enum jme_txmcs_values {
589 TXMCS_IFG2_6_4 = 0x00000000,
590 TXMCS_IFG2_8_5 = 0x40000000,
591 TXMCS_IFG2_10_6 = 0x80000000,
592 TXMCS_IFG2_12_7 = 0xC0000000,
594 TXMCS_IFG1_8_4 = 0x00000000,
595 TXMCS_IFG1_12_6 = 0x10000000,
596 TXMCS_IFG1_16_8 = 0x20000000,
597 TXMCS_IFG1_20_10 = 0x30000000,
599 TXMCS_TTHOLD_1_8 = 0x00000000,
600 TXMCS_TTHOLD_1_4 = 0x00000100,
601 TXMCS_TTHOLD_1_2 = 0x00000200,
602 TXMCS_TTHOLD_FULL = 0x00000300,
604 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
612 enum jme_txpfc_bits_masks {
613 TXPFC_VLAN_TAG = 0xFFFF0000,
614 TXPFC_VLAN_EN = 0x00008000,
615 TXPFC_PF_EN = 0x00000001,
618 enum jme_txtrhd_bits_masks {
619 TXTRHD_TXPEN = 0x80000000,
620 TXTRHD_TXP = 0x7FFFFF00,
621 TXTRHD_TXREN = 0x00000080,
622 TXTRHD_TXRL = 0x0000007F,
625 enum jme_txtrhd_shifts {
626 TXTRHD_TXP_SHIFT = 8,
627 TXTRHD_TXRL_SHIFT = 0,
631 * RX Control/Status Bits
633 enum jme_rxcs_bit_masks {
634 /* FIFO full threshold for transmitting Tx Pause Packet */
635 RXCS_FIFOTHTP = 0x30000000,
636 /* FIFO threshold for processing next packet */
637 RXCS_FIFOTHNP = 0x0C000000,
638 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
639 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
640 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
641 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
642 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
643 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
644 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
645 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
646 RXCS_QST = 0x00000004, /* Receive queue start */
647 RXCS_SUSPEND = 0x00000002,
648 RXCS_ENABLE = 0x00000001,
651 enum jme_rxcs_values {
652 RXCS_FIFOTHTP_16T = 0x00000000,
653 RXCS_FIFOTHTP_32T = 0x10000000,
654 RXCS_FIFOTHTP_64T = 0x20000000,
655 RXCS_FIFOTHTP_128T = 0x30000000,
657 RXCS_FIFOTHNP_16QW = 0x00000000,
658 RXCS_FIFOTHNP_32QW = 0x04000000,
659 RXCS_FIFOTHNP_64QW = 0x08000000,
660 RXCS_FIFOTHNP_128QW = 0x0C000000,
662 RXCS_DMAREQSZ_16B = 0x00000000,
663 RXCS_DMAREQSZ_32B = 0x01000000,
664 RXCS_DMAREQSZ_64B = 0x02000000,
665 RXCS_DMAREQSZ_128B = 0x03000000,
667 RXCS_QUEUESEL_Q0 = 0x00000000,
668 RXCS_QUEUESEL_Q1 = 0x00010000,
669 RXCS_QUEUESEL_Q2 = 0x00020000,
670 RXCS_QUEUESEL_Q3 = 0x00030000,
672 RXCS_RETRYGAP_256ns = 0x00000000,
673 RXCS_RETRYGAP_512ns = 0x00001000,
674 RXCS_RETRYGAP_1024ns = 0x00002000,
675 RXCS_RETRYGAP_2048ns = 0x00003000,
676 RXCS_RETRYGAP_4096ns = 0x00004000,
677 RXCS_RETRYGAP_8192ns = 0x00005000,
678 RXCS_RETRYGAP_16384ns = 0x00006000,
679 RXCS_RETRYGAP_32768ns = 0x00007000,
681 RXCS_RETRYCNT_0 = 0x00000000,
682 RXCS_RETRYCNT_4 = 0x00000100,
683 RXCS_RETRYCNT_8 = 0x00000200,
684 RXCS_RETRYCNT_12 = 0x00000300,
685 RXCS_RETRYCNT_16 = 0x00000400,
686 RXCS_RETRYCNT_20 = 0x00000500,
687 RXCS_RETRYCNT_24 = 0x00000600,
688 RXCS_RETRYCNT_28 = 0x00000700,
689 RXCS_RETRYCNT_32 = 0x00000800,
690 RXCS_RETRYCNT_36 = 0x00000900,
691 RXCS_RETRYCNT_40 = 0x00000A00,
692 RXCS_RETRYCNT_44 = 0x00000B00,
693 RXCS_RETRYCNT_48 = 0x00000C00,
694 RXCS_RETRYCNT_52 = 0x00000D00,
695 RXCS_RETRYCNT_56 = 0x00000E00,
696 RXCS_RETRYCNT_60 = 0x00000F00,
698 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
699 RXCS_FIFOTHNP_128QW |
701 RXCS_RETRYGAP_256ns |
705 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
708 * RX MAC Control/Status Bits
710 enum jme_rxmcs_bits {
711 RXMCS_ALLFRAME = 0x00000800,
712 RXMCS_BRDFRAME = 0x00000400,
713 RXMCS_MULFRAME = 0x00000200,
714 RXMCS_UNIFRAME = 0x00000100,
715 RXMCS_ALLMULFRAME = 0x00000080,
716 RXMCS_MULFILTERED = 0x00000040,
717 RXMCS_RXCOLLDEC = 0x00000020,
718 RXMCS_FLOWCTRL = 0x00000008,
719 RXMCS_VTAGRM = 0x00000004,
720 RXMCS_PREPAD = 0x00000002,
721 RXMCS_CHECKSUM = 0x00000001,
723 RXMCS_DEFAULT = RXMCS_VTAGRM |
730 * Wakeup Frame setup interface registers
732 #define WAKEUP_FRAME_NR 8
733 #define WAKEUP_FRAME_MASK_DWNR 4
735 enum jme_wfoi_bit_masks {
736 WFOI_MASK_SEL = 0x00000070,
737 WFOI_CRC_SEL = 0x00000008,
738 WFOI_FRAME_SEL = 0x00000007,
741 enum jme_wfoi_shifts {
746 * SMI Related definitions
748 enum jme_smi_bit_mask {
749 SMI_DATA_MASK = 0xFFFF0000,
750 SMI_REG_ADDR_MASK = 0x0000F800,
751 SMI_PHY_ADDR_MASK = 0x000007C0,
752 SMI_OP_WRITE = 0x00000020,
753 /* Set to 1, after req done it'll be cleared to 0 */
754 SMI_OP_REQ = 0x00000010,
755 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
756 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
757 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
758 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
761 enum jme_smi_bit_shift {
763 SMI_REG_ADDR_SHIFT = 11,
764 SMI_PHY_ADDR_SHIFT = 6,
767 static inline u32 smi_reg_addr(int x)
769 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
772 static inline u32 smi_phy_addr(int x)
774 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
777 #define JME_PHY_TIMEOUT 100 /* 100 msec */
778 #define JME_PHY_REG_NR 32
781 * Global Host Control
783 enum jme_ghc_bit_mask {
784 GHC_SWRST = 0x40000000,
785 GHC_DPX = 0x00000040,
786 GHC_SPEED = 0x00000030,
787 GHC_LINK_POLL = 0x00000001,
790 enum jme_ghc_speed_val {
791 GHC_SPEED_10M = 0x00000010,
792 GHC_SPEED_100M = 0x00000020,
793 GHC_SPEED_1000M = 0x00000030,
796 enum jme_ghc_to_clk {
797 GHC_TO_CLK_OFF = 0x00000000,
798 GHC_TO_CLK_GPHY = 0x00400000,
799 GHC_TO_CLK_PCIE = 0x00800000,
800 GHC_TO_CLK_INVALID = 0x00C00000,
803 enum jme_ghc_txmac_clk {
804 GHC_TXMAC_CLK_OFF = 0x00000000,
805 GHC_TXMAC_CLK_GPHY = 0x00100000,
806 GHC_TXMAC_CLK_PCIE = 0x00200000,
807 GHC_TXMAC_CLK_INVALID = 0x00300000,
811 * Power management control and status register
813 enum jme_pmcs_bit_masks {
814 PMCS_WF7DET = 0x80000000,
815 PMCS_WF6DET = 0x40000000,
816 PMCS_WF5DET = 0x20000000,
817 PMCS_WF4DET = 0x10000000,
818 PMCS_WF3DET = 0x08000000,
819 PMCS_WF2DET = 0x04000000,
820 PMCS_WF1DET = 0x02000000,
821 PMCS_WF0DET = 0x01000000,
822 PMCS_LFDET = 0x00040000,
823 PMCS_LRDET = 0x00020000,
824 PMCS_MFDET = 0x00010000,
825 PMCS_WF7EN = 0x00008000,
826 PMCS_WF6EN = 0x00004000,
827 PMCS_WF5EN = 0x00002000,
828 PMCS_WF4EN = 0x00001000,
829 PMCS_WF3EN = 0x00000800,
830 PMCS_WF2EN = 0x00000400,
831 PMCS_WF1EN = 0x00000200,
832 PMCS_WF0EN = 0x00000100,
833 PMCS_LFEN = 0x00000004,
834 PMCS_LREN = 0x00000002,
835 PMCS_MFEN = 0x00000001,
839 * Giga PHY Status Registers
841 enum jme_phy_link_bit_mask {
842 PHY_LINK_SPEED_MASK = 0x0000C000,
843 PHY_LINK_DUPLEX = 0x00002000,
844 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
845 PHY_LINK_UP = 0x00000400,
846 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
847 PHY_LINK_MDI_STAT = 0x00000040,
850 enum jme_phy_link_speed_val {
851 PHY_LINK_SPEED_10M = 0x00000000,
852 PHY_LINK_SPEED_100M = 0x00004000,
853 PHY_LINK_SPEED_1000M = 0x00008000,
856 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
859 * SMB Control and Status
861 enum jme_smbcsr_bit_mask {
862 SMBCSR_CNACK = 0x00020000,
863 SMBCSR_RELOAD = 0x00010000,
864 SMBCSR_EEPROMD = 0x00000020,
865 SMBCSR_INITDONE = 0x00000010,
866 SMBCSR_BUSY = 0x0000000F,
869 enum jme_smbintf_bit_mask {
870 SMBINTF_HWDATR = 0xFF000000,
871 SMBINTF_HWDATW = 0x00FF0000,
872 SMBINTF_HWADDR = 0x0000FF00,
873 SMBINTF_HWRWN = 0x00000020,
874 SMBINTF_HWCMD = 0x00000010,
875 SMBINTF_FASTM = 0x00000008,
876 SMBINTF_GPIOSCL = 0x00000004,
877 SMBINTF_GPIOSDA = 0x00000002,
878 SMBINTF_GPIOEN = 0x00000001,
881 enum jme_smbintf_vals {
882 SMBINTF_HWRWN_READ = 0x00000020,
883 SMBINTF_HWRWN_WRITE = 0x00000000,
886 enum jme_smbintf_shifts {
887 SMBINTF_HWDATR_SHIFT = 24,
888 SMBINTF_HWDATW_SHIFT = 16,
889 SMBINTF_HWADDR_SHIFT = 8,
892 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
893 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
894 #define JME_SMB_LEN 256
895 #define JME_EEPROM_MAGIC 0x250
898 * Timer Control/Status Register
900 enum jme_tmcsr_bit_masks {
901 TMCSR_SWIT = 0x80000000,
902 TMCSR_EN = 0x01000000,
903 TMCSR_CNT = 0x00FFFFFF,
907 * General Purpose REG-0
909 enum jme_gpreg0_masks {
910 GPREG0_DISSH = 0xFF000000,
911 GPREG0_PCIRLMT = 0x00300000,
912 GPREG0_PCCNOMUTCLR = 0x00040000,
913 GPREG0_LNKINTPOLL = 0x00001000,
914 GPREG0_PCCTMR = 0x00000300,
915 GPREG0_PHYADDR = 0x0000001F,
918 enum jme_gpreg0_vals {
919 GPREG0_DISSH_DW7 = 0x80000000,
920 GPREG0_DISSH_DW6 = 0x40000000,
921 GPREG0_DISSH_DW5 = 0x20000000,
922 GPREG0_DISSH_DW4 = 0x10000000,
923 GPREG0_DISSH_DW3 = 0x08000000,
924 GPREG0_DISSH_DW2 = 0x04000000,
925 GPREG0_DISSH_DW1 = 0x02000000,
926 GPREG0_DISSH_DW0 = 0x01000000,
927 GPREG0_DISSH_ALL = 0xFF000000,
929 GPREG0_PCIRLMT_8 = 0x00000000,
930 GPREG0_PCIRLMT_6 = 0x00100000,
931 GPREG0_PCIRLMT_5 = 0x00200000,
932 GPREG0_PCIRLMT_4 = 0x00300000,
934 GPREG0_PCCTMR_16ns = 0x00000000,
935 GPREG0_PCCTMR_256ns = 0x00000100,
936 GPREG0_PCCTMR_1us = 0x00000200,
937 GPREG0_PCCTMR_1ms = 0x00000300,
939 GPREG0_PHYADDR_1 = 0x00000001,
941 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
947 * General Purpose REG-1
948 * Note: All theses bits defined here are for
949 * Chip mode revision 0x11 only
951 enum jme_gpreg1_masks {
952 GPREG1_INTRDELAYUNIT = 0x00000018,
953 GPREG1_INTRDELAYENABLE = 0x00000007,
956 enum jme_gpreg1_vals {
957 GPREG1_RSSPATCH = 0x00000040,
958 GPREG1_HALFMODEPATCH = 0x00000020,
960 GPREG1_INTDLYUNIT_16NS = 0x00000000,
961 GPREG1_INTDLYUNIT_256NS = 0x00000008,
962 GPREG1_INTDLYUNIT_1US = 0x00000010,
963 GPREG1_INTDLYUNIT_16US = 0x00000018,
965 GPREG1_INTDLYEN_1U = 0x00000001,
966 GPREG1_INTDLYEN_2U = 0x00000002,
967 GPREG1_INTDLYEN_3U = 0x00000003,
968 GPREG1_INTDLYEN_4U = 0x00000004,
969 GPREG1_INTDLYEN_5U = 0x00000005,
970 GPREG1_INTDLYEN_6U = 0x00000006,
971 GPREG1_INTDLYEN_7U = 0x00000007,
973 GPREG1_DEFAULT = 0x00000000,
977 * Interrupt Status Bits
979 enum jme_interrupt_bits {
980 INTR_SWINTR = 0x80000000,
981 INTR_TMINTR = 0x40000000,
982 INTR_LINKCH = 0x20000000,
983 INTR_PAUSERCV = 0x10000000,
984 INTR_MAGICRCV = 0x08000000,
985 INTR_WAKERCV = 0x04000000,
986 INTR_PCCRX0TO = 0x02000000,
987 INTR_PCCRX1TO = 0x01000000,
988 INTR_PCCRX2TO = 0x00800000,
989 INTR_PCCRX3TO = 0x00400000,
990 INTR_PCCTXTO = 0x00200000,
991 INTR_PCCRX0 = 0x00100000,
992 INTR_PCCRX1 = 0x00080000,
993 INTR_PCCRX2 = 0x00040000,
994 INTR_PCCRX3 = 0x00020000,
995 INTR_PCCTX = 0x00010000,
996 INTR_RX3EMP = 0x00008000,
997 INTR_RX2EMP = 0x00004000,
998 INTR_RX1EMP = 0x00002000,
999 INTR_RX0EMP = 0x00001000,
1000 INTR_RX3 = 0x00000800,
1001 INTR_RX2 = 0x00000400,
1002 INTR_RX1 = 0x00000200,
1003 INTR_RX0 = 0x00000100,
1004 INTR_TX7 = 0x00000080,
1005 INTR_TX6 = 0x00000040,
1006 INTR_TX5 = 0x00000020,
1007 INTR_TX4 = 0x00000010,
1008 INTR_TX3 = 0x00000008,
1009 INTR_TX2 = 0x00000004,
1010 INTR_TX1 = 0x00000002,
1011 INTR_TX0 = 0x00000001,
1014 static const u32 INTR_ENABLE = INTR_SWINTR |
1024 * PCC Control Registers
1026 enum jme_pccrx_masks {
1027 PCCRXTO_MASK = 0xFFFF0000,
1028 PCCRX_MASK = 0x0000FF00,
1031 enum jme_pcctx_masks {
1032 PCCTXTO_MASK = 0xFFFF0000,
1033 PCCTX_MASK = 0x0000FF00,
1034 PCCTX_QS_MASK = 0x000000FF,
1037 enum jme_pccrx_shifts {
1042 enum jme_pcctx_shifts {
1047 enum jme_pcctx_bits {
1048 PCCTXQ0_EN = 0x00000001,
1049 PCCTXQ1_EN = 0x00000002,
1050 PCCTXQ2_EN = 0x00000004,
1051 PCCTXQ3_EN = 0x00000008,
1052 PCCTXQ4_EN = 0x00000010,
1053 PCCTXQ5_EN = 0x00000020,
1054 PCCTXQ6_EN = 0x00000040,
1055 PCCTXQ7_EN = 0x00000080,
1059 * Chip Mode Register
1061 enum jme_chipmode_bit_masks {
1062 CM_FPGAVER_MASK = 0xFFFF0000,
1063 CM_CHIPREV_MASK = 0x0000FF00,
1064 CM_CHIPMODE_MASK = 0x0000000F,
1067 enum jme_chipmode_shifts {
1068 CM_FPGAVER_SHIFT = 16,
1069 CM_CHIPREV_SHIFT = 8,
1073 * Aggressive Power Mode Control
1075 enum jme_apmc_bits {
1076 JME_APMC_PCIE_SD_EN = 0x40000000,
1077 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1078 JME_APMC_EPIEN = 0x04000000,
1079 JME_APMC_EPIEN_CTRL = 0x03000000,
1082 enum jme_apmc_values {
1083 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1084 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1087 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1090 static char *MAC_REG_NAME[] = {
1091 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1092 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1093 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1094 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1095 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1096 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1099 static char *PE_REG_NAME[] = {
1100 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1101 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1102 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1103 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1104 "JME_SMBCSR", "JME_SMBINTF"};
1106 static char *MISC_REG_NAME[] = {
1107 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1108 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1109 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1110 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1111 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1112 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1113 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1114 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1117 static inline void reg_dbg(const struct jme_adapter *jme,
1118 const char *msg, u32 val, u32 reg)
1120 const char *regname;
1121 switch (reg & 0xF00) {
1123 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1126 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1129 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1132 regname = PE_REG_NAME[0];
1134 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1138 static inline void reg_dbg(const struct jme_adapter *jme,
1139 const char *msg, u32 val, u32 reg) {}
1143 * Read/Write MMaped I/O Registers
1145 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1147 return readl(jme->regs + reg);
1150 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1152 reg_dbg(jme, "REG WRITE", val, reg);
1153 writel(val, jme->regs + reg);
1154 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1157 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1160 * Read after write should cause flush
1162 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1163 writel(val, jme->regs + reg);
1164 readl(jme->regs + reg);
1165 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1171 enum jme_phy_reg17_bit_masks {
1172 PREG17_SPEED = 0xC000,
1173 PREG17_DUPLEX = 0x2000,
1174 PREG17_SPDRSV = 0x0800,
1175 PREG17_LNKUP = 0x0400,
1176 PREG17_MDI = 0x0040,
1179 enum jme_phy_reg17_vals {
1180 PREG17_SPEED_10M = 0x0000,
1181 PREG17_SPEED_100M = 0x4000,
1182 PREG17_SPEED_1000M = 0x8000,
1185 #define BMSR_ANCOMP 0x0020
1190 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1192 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1196 * Function prototypes
1198 static int jme_set_settings(struct net_device *netdev,
1199 struct ethtool_cmd *ecmd);
1200 static void jme_set_multi(struct net_device *netdev);