2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/version.h>
26 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
46 #include <linux/slab.h>
47 #include <net/ip6_checksum.h>
50 static int force_pseudohp = -1;
51 static int no_pseudohp = -1;
52 static int no_extplug = -1;
53 module_param(force_pseudohp, int, 0);
54 MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56 module_param(no_pseudohp, int, 0);
57 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58 module_param(no_extplug, int, 0);
59 MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
63 jme_mdio_read(struct net_device *netdev, int phy, int reg)
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
93 jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
96 struct jme_adapter *jme = netdev_priv(netdev);
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
115 jme_reset_phy_processor(struct jme_adapter *jme)
119 jme_mdio_write(jme->dev,
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
125 jme_mdio_write(jme->dev,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
130 val = jme_mdio_read(jme->dev,
134 jme_mdio_write(jme->dev,
136 MII_BMCR, val | BMCR_RESET);
140 jme_setup_wakeup_frame(struct jme_adapter *jme,
141 const u32 *mask, u32 crc, int fnr)
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
150 jwrite32(jme, JME_WFODP, crc);
156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
161 jwrite32(jme, JME_WFODP, mask[i]);
167 jme_mac_rxclk_off(struct jme_adapter *jme)
169 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
170 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
174 jme_mac_rxclk_on(struct jme_adapter *jme)
176 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
177 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
181 jme_mac_txclk_off(struct jme_adapter *jme)
183 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
184 jwrite32f(jme, JME_GHC, jme->reg_ghc);
188 jme_mac_txclk_on(struct jme_adapter *jme)
190 u32 speed = jme->reg_ghc & GHC_SPEED;
191 if (speed == GHC_SPEED_1000M)
192 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
194 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
195 jwrite32f(jme, JME_GHC, jme->reg_ghc);
199 jme_reset_ghc_speed(struct jme_adapter *jme)
201 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
202 jwrite32f(jme, JME_GHC, jme->reg_ghc);
206 jme_reset_250A2_workaround(struct jme_adapter *jme)
208 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
210 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
214 jme_assert_ghc_reset(struct jme_adapter *jme)
216 jme->reg_ghc |= GHC_SWRST;
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
221 jme_clear_ghc_reset(struct jme_adapter *jme)
223 jme->reg_ghc &= ~GHC_SWRST;
224 jwrite32f(jme, JME_GHC, jme->reg_ghc);
228 jme_reset_mac_processor(struct jme_adapter *jme)
230 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
231 u32 crc = 0xCDCDCDCD;
235 jme_reset_ghc_speed(jme);
236 jme_reset_250A2_workaround(jme);
238 jme_mac_rxclk_on(jme);
239 jme_mac_txclk_on(jme);
241 jme_assert_ghc_reset(jme);
243 jme_mac_rxclk_off(jme);
244 jme_mac_txclk_off(jme);
246 jme_clear_ghc_reset(jme);
248 jme_mac_rxclk_on(jme);
249 jme_mac_txclk_on(jme);
251 jme_mac_rxclk_off(jme);
252 jme_mac_txclk_off(jme);
254 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
255 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
256 jwrite32(jme, JME_RXQDC, 0x00000000);
257 jwrite32(jme, JME_RXNDA, 0x00000000);
258 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
259 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
260 jwrite32(jme, JME_TXQDC, 0x00000000);
261 jwrite32(jme, JME_TXNDA, 0x00000000);
263 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
264 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
265 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
266 jme_setup_wakeup_frame(jme, mask, crc, i);
268 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
270 gpreg0 = GPREG0_DEFAULT;
271 jwrite32(jme, JME_GPREG0, gpreg0);
275 jme_clear_pm(struct jme_adapter *jme)
277 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
278 pci_set_power_state(jme->pdev, PCI_D0);
279 pci_enable_wake(jme->pdev, PCI_D0, false);
283 jme_reload_eeprom(struct jme_adapter *jme)
288 val = jread32(jme, JME_SMBCSR);
290 if (val & SMBCSR_EEPROMD) {
292 jwrite32(jme, JME_SMBCSR, val);
293 val |= SMBCSR_RELOAD;
294 jwrite32(jme, JME_SMBCSR, val);
297 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
299 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
304 pr_err("eeprom reload timeout\n");
313 jme_load_macaddr(struct net_device *netdev)
315 struct jme_adapter *jme = netdev_priv(netdev);
316 unsigned char macaddr[6];
319 spin_lock_bh(&jme->macaddr_lock);
320 val = jread32(jme, JME_RXUMA_LO);
321 macaddr[0] = (val >> 0) & 0xFF;
322 macaddr[1] = (val >> 8) & 0xFF;
323 macaddr[2] = (val >> 16) & 0xFF;
324 macaddr[3] = (val >> 24) & 0xFF;
325 val = jread32(jme, JME_RXUMA_HI);
326 macaddr[4] = (val >> 0) & 0xFF;
327 macaddr[5] = (val >> 8) & 0xFF;
328 memcpy(netdev->dev_addr, macaddr, 6);
329 spin_unlock_bh(&jme->macaddr_lock);
333 jme_set_rx_pcc(struct jme_adapter *jme, int p)
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
352 jwrite32(jme, JME_PCCRX0,
353 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
354 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
361 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
362 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
366 jme_start_irq(struct jme_adapter *jme)
368 register struct dynpcc_info *dpi = &(jme->dpi);
370 jme_set_rx_pcc(jme, PCC_P1);
372 dpi->attempt = PCC_P1;
375 jwrite32(jme, JME_PCCTX,
376 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
377 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
384 jwrite32(jme, JME_IENS, INTR_ENABLE);
388 jme_stop_irq(struct jme_adapter *jme)
393 jwrite32f(jme, JME_IENC, INTR_ENABLE);
397 jme_linkstat_from_phy(struct jme_adapter *jme)
401 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
402 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
403 if (bmsr & BMSR_ANCOMP)
404 phylink |= PHY_LINK_AUTONEG_COMPLETE;
410 jme_set_phyfifo_5level(struct jme_adapter *jme)
412 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
416 jme_set_phyfifo_8level(struct jme_adapter *jme)
418 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
422 jme_check_link(struct net_device *netdev, int testonly)
424 struct jme_adapter *jme = netdev_priv(netdev);
425 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
432 phylink = jme_linkstat_from_phy(jme);
434 phylink = jread32(jme, JME_PHY_LINK);
436 if (phylink & PHY_LINK_UP) {
437 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
439 * If we did not enable AN
440 * Speed/Duplex Info should be obtained from SMI
442 phylink = PHY_LINK_UP;
444 bmcr = jme_mdio_read(jme->dev,
448 phylink |= ((bmcr & BMCR_SPEED1000) &&
449 (bmcr & BMCR_SPEED100) == 0) ?
450 PHY_LINK_SPEED_1000M :
451 (bmcr & BMCR_SPEED100) ?
452 PHY_LINK_SPEED_100M :
455 phylink |= (bmcr & BMCR_FULLDPLX) ?
458 strcat(linkmsg, "Forced: ");
461 * Keep polling for speed/duplex resolve complete
463 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
469 phylink = jme_linkstat_from_phy(jme);
471 phylink = jread32(jme, JME_PHY_LINK);
474 pr_err("Waiting speed resolve timeout\n");
476 strcat(linkmsg, "ANed: ");
479 if (jme->phylink == phylink) {
486 jme->phylink = phylink;
489 * The speed/duplex setting of jme->reg_ghc already cleared
490 * by jme_reset_mac_processor()
492 switch (phylink & PHY_LINK_SPEED_MASK) {
493 case PHY_LINK_SPEED_10M:
494 jme->reg_ghc |= GHC_SPEED_10M;
495 strcat(linkmsg, "10 Mbps, ");
497 case PHY_LINK_SPEED_100M:
498 jme->reg_ghc |= GHC_SPEED_100M;
499 strcat(linkmsg, "100 Mbps, ");
501 case PHY_LINK_SPEED_1000M:
502 jme->reg_ghc |= GHC_SPEED_1000M;
503 strcat(linkmsg, "1000 Mbps, ");
509 if (phylink & PHY_LINK_DUPLEX) {
510 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
511 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
512 jme->reg_ghc |= GHC_DPX;
514 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
518 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
521 jwrite32(jme, JME_GHC, jme->reg_ghc);
523 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
524 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
526 if (!(phylink & PHY_LINK_DUPLEX))
527 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
528 switch (phylink & PHY_LINK_SPEED_MASK) {
529 case PHY_LINK_SPEED_10M:
530 jme_set_phyfifo_8level(jme);
531 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
533 case PHY_LINK_SPEED_100M:
534 jme_set_phyfifo_5level(jme);
535 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
537 case PHY_LINK_SPEED_1000M:
538 jme_set_phyfifo_8level(jme);
544 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
546 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
549 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
552 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
553 netif_carrier_on(netdev);
558 netif_info(jme, link, jme->dev, "Link is down\n");
560 netif_carrier_off(netdev);
568 jme_setup_tx_resources(struct jme_adapter *jme)
570 struct jme_ring *txring = &(jme->txring[0]);
572 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
583 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
585 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
586 txring->next_to_use = 0;
587 atomic_set(&txring->next_to_clean, 0);
588 atomic_set(&txring->nr_free, jme->tx_ring_size);
590 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
591 jme->tx_ring_size, GFP_ATOMIC);
592 if (unlikely(!(txring->bufinf)))
593 goto err_free_txring;
596 * Initialize Transmit Descriptors
598 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
599 memset(txring->bufinf, 0,
600 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
605 dma_free_coherent(&(jme->pdev->dev),
606 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
612 txring->dmaalloc = 0;
614 txring->bufinf = NULL;
620 jme_free_tx_resources(struct jme_adapter *jme)
623 struct jme_ring *txring = &(jme->txring[0]);
624 struct jme_buffer_info *txbi;
627 if (txring->bufinf) {
628 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
629 txbi = txring->bufinf + i;
631 dev_kfree_skb(txbi->skb);
637 txbi->start_xmit = 0;
639 kfree(txring->bufinf);
642 dma_free_coherent(&(jme->pdev->dev),
643 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
647 txring->alloc = NULL;
649 txring->dmaalloc = 0;
651 txring->bufinf = NULL;
653 txring->next_to_use = 0;
654 atomic_set(&txring->next_to_clean, 0);
655 atomic_set(&txring->nr_free, 0);
659 jme_enable_tx_engine(struct jme_adapter *jme)
664 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
668 * Setup TX Queue 0 DMA Bass Address
670 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
671 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
672 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
675 * Setup TX Descptor Count
677 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
683 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
688 * Start clock for TX MAC Processor
690 jme_mac_txclk_on(jme);
694 jme_restart_tx_engine(struct jme_adapter *jme)
699 jwrite32(jme, JME_TXCS, jme->reg_txcs |
705 jme_disable_tx_engine(struct jme_adapter *jme)
713 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
716 val = jread32(jme, JME_TXCS);
717 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
719 val = jread32(jme, JME_TXCS);
724 pr_err("Disable TX engine timeout\n");
727 * Stop clock for TX MAC Processor
729 jme_mac_txclk_off(jme);
733 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
735 struct jme_ring *rxring = &(jme->rxring[0]);
736 register struct rxdesc *rxdesc = rxring->desc;
737 struct jme_buffer_info *rxbi = rxring->bufinf;
743 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
744 rxdesc->desc1.bufaddrl = cpu_to_le32(
745 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
746 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
747 if (jme->dev->features & NETIF_F_HIGHDMA)
748 rxdesc->desc1.flags = RXFLAG_64BIT;
750 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
754 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
756 struct jme_ring *rxring = &(jme->rxring[0]);
757 struct jme_buffer_info *rxbi = rxring->bufinf + i;
760 skb = netdev_alloc_skb(jme->dev,
761 jme->dev->mtu + RX_EXTRA_LEN);
764 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
769 rxbi->len = skb_tailroom(skb);
770 rxbi->mapping = pci_map_page(jme->pdev,
771 virt_to_page(skb->data),
772 offset_in_page(skb->data),
780 jme_free_rx_buf(struct jme_adapter *jme, int i)
782 struct jme_ring *rxring = &(jme->rxring[0]);
783 struct jme_buffer_info *rxbi = rxring->bufinf;
787 pci_unmap_page(jme->pdev,
791 dev_kfree_skb(rxbi->skb);
799 jme_free_rx_resources(struct jme_adapter *jme)
802 struct jme_ring *rxring = &(jme->rxring[0]);
805 if (rxring->bufinf) {
806 for (i = 0 ; i < jme->rx_ring_size ; ++i)
807 jme_free_rx_buf(jme, i);
808 kfree(rxring->bufinf);
811 dma_free_coherent(&(jme->pdev->dev),
812 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
815 rxring->alloc = NULL;
817 rxring->dmaalloc = 0;
819 rxring->bufinf = NULL;
821 rxring->next_to_use = 0;
822 atomic_set(&rxring->next_to_clean, 0);
826 jme_setup_rx_resources(struct jme_adapter *jme)
829 struct jme_ring *rxring = &(jme->rxring[0]);
831 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
832 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
841 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
843 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
844 rxring->next_to_use = 0;
845 atomic_set(&rxring->next_to_clean, 0);
847 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
848 jme->rx_ring_size, GFP_ATOMIC);
849 if (unlikely(!(rxring->bufinf)))
850 goto err_free_rxring;
853 * Initiallize Receive Descriptors
855 memset(rxring->bufinf, 0,
856 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
857 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
858 if (unlikely(jme_make_new_rx_buf(jme, i))) {
859 jme_free_rx_resources(jme);
863 jme_set_clean_rxdesc(jme, i);
869 dma_free_coherent(&(jme->pdev->dev),
870 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
875 rxring->dmaalloc = 0;
877 rxring->bufinf = NULL;
883 jme_enable_rx_engine(struct jme_adapter *jme)
888 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
893 * Setup RX DMA Bass Address
895 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
896 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
897 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
900 * Setup RX Descriptor Count
902 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
905 * Setup Unicast Filter
907 jme_set_unicastaddr(jme->dev);
908 jme_set_multi(jme->dev);
914 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
920 * Start clock for RX MAC Processor
922 jme_mac_rxclk_on(jme);
926 jme_restart_rx_engine(struct jme_adapter *jme)
931 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
938 jme_disable_rx_engine(struct jme_adapter *jme)
946 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
949 val = jread32(jme, JME_RXCS);
950 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
952 val = jread32(jme, JME_RXCS);
957 pr_err("Disable RX engine timeout\n");
960 * Stop clock for RX MAC Processor
962 jme_mac_rxclk_off(jme);
966 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
968 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
971 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
972 == RXWBFLAG_TCPON)) {
973 if (flags & RXWBFLAG_IPV4)
974 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
978 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
979 == RXWBFLAG_UDPON)) {
980 if (flags & RXWBFLAG_IPV4)
981 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
985 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
987 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
995 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
997 struct jme_ring *rxring = &(jme->rxring[0]);
998 struct rxdesc *rxdesc = rxring->desc;
999 struct jme_buffer_info *rxbi = rxring->bufinf;
1000 struct sk_buff *skb;
1007 pci_dma_sync_single_for_cpu(jme->pdev,
1010 PCI_DMA_FROMDEVICE);
1012 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1013 pci_dma_sync_single_for_device(jme->pdev,
1016 PCI_DMA_FROMDEVICE);
1018 ++(NET_STAT(jme).rx_dropped);
1020 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1023 skb_reserve(skb, RX_PREPAD_SIZE);
1024 skb_put(skb, framesize);
1025 skb->protocol = eth_type_trans(skb, jme->dev);
1027 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
1028 skb->ip_summed = CHECKSUM_UNNECESSARY;
1030 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
1031 skb->ip_summed = CHECKSUM_NONE;
1033 skb_checksum_none_assert(skb);
1036 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1038 jme->jme_vlan_rx(skb, jme->vlgrp,
1039 le16_to_cpu(rxdesc->descwb.vlan));
1040 NET_STAT(jme).rx_bytes += 4;
1048 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1049 cpu_to_le16(RXWBFLAG_DEST_MUL))
1050 ++(NET_STAT(jme).multicast);
1052 NET_STAT(jme).rx_bytes += framesize;
1053 ++(NET_STAT(jme).rx_packets);
1056 jme_set_clean_rxdesc(jme, idx);
1061 jme_process_receive(struct jme_adapter *jme, int limit)
1063 struct jme_ring *rxring = &(jme->rxring[0]);
1064 struct rxdesc *rxdesc = rxring->desc;
1065 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1067 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1070 if (unlikely(atomic_read(&jme->link_changing) != 1))
1073 if (unlikely(!netif_carrier_ok(jme->dev)))
1076 i = atomic_read(&rxring->next_to_clean);
1078 rxdesc = rxring->desc;
1081 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1082 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1087 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1089 if (unlikely(desccnt > 1 ||
1090 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1092 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1093 ++(NET_STAT(jme).rx_crc_errors);
1094 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1095 ++(NET_STAT(jme).rx_fifo_errors);
1097 ++(NET_STAT(jme).rx_errors);
1100 limit -= desccnt - 1;
1102 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1103 jme_set_clean_rxdesc(jme, j);
1104 j = (j + 1) & (mask);
1108 jme_alloc_and_feed_skb(jme, i);
1111 i = (i + desccnt) & (mask);
1115 atomic_set(&rxring->next_to_clean, i);
1118 atomic_inc(&jme->rx_cleaning);
1120 return limit > 0 ? limit : 0;
1125 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1127 if (likely(atmp == dpi->cur)) {
1132 if (dpi->attempt == atmp) {
1135 dpi->attempt = atmp;
1142 jme_dynamic_pcc(struct jme_adapter *jme)
1144 register struct dynpcc_info *dpi = &(jme->dpi);
1146 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1147 jme_attempt_pcc(dpi, PCC_P3);
1148 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1149 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1150 jme_attempt_pcc(dpi, PCC_P2);
1152 jme_attempt_pcc(dpi, PCC_P1);
1154 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1155 if (dpi->attempt < dpi->cur)
1156 tasklet_schedule(&jme->rxclean_task);
1157 jme_set_rx_pcc(jme, dpi->attempt);
1158 dpi->cur = dpi->attempt;
1164 jme_start_pcc_timer(struct jme_adapter *jme)
1166 struct dynpcc_info *dpi = &(jme->dpi);
1167 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1168 dpi->last_pkts = NET_STAT(jme).rx_packets;
1170 jwrite32(jme, JME_TMCSR,
1171 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1175 jme_stop_pcc_timer(struct jme_adapter *jme)
1177 jwrite32(jme, JME_TMCSR, 0);
1181 jme_shutdown_nic(struct jme_adapter *jme)
1185 phylink = jme_linkstat_from_phy(jme);
1187 if (!(phylink & PHY_LINK_UP)) {
1189 * Disable all interrupt before issue timer
1192 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1197 jme_pcc_tasklet(unsigned long arg)
1199 struct jme_adapter *jme = (struct jme_adapter *)arg;
1200 struct net_device *netdev = jme->dev;
1202 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1203 jme_shutdown_nic(jme);
1207 if (unlikely(!netif_carrier_ok(netdev) ||
1208 (atomic_read(&jme->link_changing) != 1)
1210 jme_stop_pcc_timer(jme);
1214 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1215 jme_dynamic_pcc(jme);
1217 jme_start_pcc_timer(jme);
1221 jme_polling_mode(struct jme_adapter *jme)
1223 jme_set_rx_pcc(jme, PCC_OFF);
1227 jme_interrupt_mode(struct jme_adapter *jme)
1229 jme_set_rx_pcc(jme, PCC_P1);
1233 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1236 apmc = jread32(jme, JME_APMC);
1237 return apmc & JME_APMC_PSEUDO_HP_EN;
1241 jme_start_shutdown_timer(struct jme_adapter *jme)
1245 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1246 apmc &= ~JME_APMC_EPIEN_CTRL;
1248 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1251 jwrite32f(jme, JME_APMC, apmc);
1253 jwrite32f(jme, JME_TIMER2, 0);
1254 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1255 jwrite32(jme, JME_TMCSR,
1256 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1260 jme_stop_shutdown_timer(struct jme_adapter *jme)
1264 jwrite32f(jme, JME_TMCSR, 0);
1265 jwrite32f(jme, JME_TIMER2, 0);
1266 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1268 apmc = jread32(jme, JME_APMC);
1269 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1270 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1272 jwrite32f(jme, JME_APMC, apmc);
1276 jme_link_change_tasklet(unsigned long arg)
1278 struct jme_adapter *jme = (struct jme_adapter *)arg;
1279 struct net_device *netdev = jme->dev;
1282 while (!atomic_dec_and_test(&jme->link_changing)) {
1283 atomic_inc(&jme->link_changing);
1284 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1285 while (atomic_read(&jme->link_changing) != 1)
1286 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1289 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1292 jme->old_mtu = netdev->mtu;
1293 netif_stop_queue(netdev);
1294 if (jme_pseudo_hotplug_enabled(jme))
1295 jme_stop_shutdown_timer(jme);
1297 jme_stop_pcc_timer(jme);
1298 tasklet_disable(&jme->txclean_task);
1299 tasklet_disable(&jme->rxclean_task);
1300 tasklet_disable(&jme->rxempty_task);
1302 if (netif_carrier_ok(netdev)) {
1303 jme_disable_rx_engine(jme);
1304 jme_disable_tx_engine(jme);
1305 jme_reset_mac_processor(jme);
1306 jme_free_rx_resources(jme);
1307 jme_free_tx_resources(jme);
1309 if (test_bit(JME_FLAG_POLL, &jme->flags))
1310 jme_polling_mode(jme);
1312 netif_carrier_off(netdev);
1315 jme_check_link(netdev, 0);
1316 if (netif_carrier_ok(netdev)) {
1317 rc = jme_setup_rx_resources(jme);
1319 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1320 goto out_enable_tasklet;
1323 rc = jme_setup_tx_resources(jme);
1325 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1326 goto err_out_free_rx_resources;
1329 jme_enable_rx_engine(jme);
1330 jme_enable_tx_engine(jme);
1332 netif_start_queue(netdev);
1334 if (test_bit(JME_FLAG_POLL, &jme->flags))
1335 jme_interrupt_mode(jme);
1337 jme_start_pcc_timer(jme);
1338 } else if (jme_pseudo_hotplug_enabled(jme)) {
1339 jme_start_shutdown_timer(jme);
1342 goto out_enable_tasklet;
1344 err_out_free_rx_resources:
1345 jme_free_rx_resources(jme);
1347 tasklet_enable(&jme->txclean_task);
1348 tasklet_hi_enable(&jme->rxclean_task);
1349 tasklet_hi_enable(&jme->rxempty_task);
1351 atomic_inc(&jme->link_changing);
1355 jme_rx_clean_tasklet(unsigned long arg)
1357 struct jme_adapter *jme = (struct jme_adapter *)arg;
1358 struct dynpcc_info *dpi = &(jme->dpi);
1360 jme_process_receive(jme, jme->rx_ring_size);
1366 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1368 struct jme_adapter *jme = jme_napi_priv(holder);
1372 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1374 while (atomic_read(&jme->rx_empty) > 0) {
1375 atomic_dec(&jme->rx_empty);
1376 ++(NET_STAT(jme).rx_dropped);
1377 jme_restart_rx_engine(jme);
1379 atomic_inc(&jme->rx_empty);
1382 JME_RX_COMPLETE(netdev, holder);
1383 jme_interrupt_mode(jme);
1386 JME_NAPI_WEIGHT_SET(budget, rest);
1387 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1391 jme_rx_empty_tasklet(unsigned long arg)
1393 struct jme_adapter *jme = (struct jme_adapter *)arg;
1395 if (unlikely(atomic_read(&jme->link_changing) != 1))
1398 if (unlikely(!netif_carrier_ok(jme->dev)))
1401 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1403 jme_rx_clean_tasklet(arg);
1405 while (atomic_read(&jme->rx_empty) > 0) {
1406 atomic_dec(&jme->rx_empty);
1407 ++(NET_STAT(jme).rx_dropped);
1408 jme_restart_rx_engine(jme);
1410 atomic_inc(&jme->rx_empty);
1414 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1416 struct jme_ring *txring = &(jme->txring[0]);
1419 if (unlikely(netif_queue_stopped(jme->dev) &&
1420 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1421 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1422 netif_wake_queue(jme->dev);
1428 jme_tx_clean_tasklet(unsigned long arg)
1430 struct jme_adapter *jme = (struct jme_adapter *)arg;
1431 struct jme_ring *txring = &(jme->txring[0]);
1432 struct txdesc *txdesc = txring->desc;
1433 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1434 int i, j, cnt = 0, max, err, mask;
1436 tx_dbg(jme, "Into txclean\n");
1438 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1441 if (unlikely(atomic_read(&jme->link_changing) != 1))
1444 if (unlikely(!netif_carrier_ok(jme->dev)))
1447 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1448 mask = jme->tx_ring_mask;
1450 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1454 if (likely(ctxbi->skb &&
1455 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1457 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1458 i, ctxbi->nr_desc, jiffies);
1460 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1462 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1463 ttxbi = txbi + ((i + j) & (mask));
1464 txdesc[(i + j) & (mask)].dw[0] = 0;
1466 pci_unmap_page(jme->pdev,
1475 dev_kfree_skb(ctxbi->skb);
1477 cnt += ctxbi->nr_desc;
1479 if (unlikely(err)) {
1480 ++(NET_STAT(jme).tx_carrier_errors);
1482 ++(NET_STAT(jme).tx_packets);
1483 NET_STAT(jme).tx_bytes += ctxbi->len;
1488 ctxbi->start_xmit = 0;
1494 i = (i + ctxbi->nr_desc) & mask;
1499 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1500 atomic_set(&txring->next_to_clean, i);
1501 atomic_add(cnt, &txring->nr_free);
1503 jme_wake_queue_if_stopped(jme);
1506 atomic_inc(&jme->tx_cleaning);
1510 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1515 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1517 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1519 * Link change event is critical
1520 * all other events are ignored
1522 jwrite32(jme, JME_IEVE, intrstat);
1523 tasklet_schedule(&jme->linkch_task);
1527 if (intrstat & INTR_TMINTR) {
1528 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1529 tasklet_schedule(&jme->pcc_task);
1532 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1533 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1534 tasklet_schedule(&jme->txclean_task);
1537 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1538 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1544 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1545 if (intrstat & INTR_RX0EMP)
1546 atomic_inc(&jme->rx_empty);
1548 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1549 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1550 jme_polling_mode(jme);
1551 JME_RX_SCHEDULE(jme);
1555 if (intrstat & INTR_RX0EMP) {
1556 atomic_inc(&jme->rx_empty);
1557 tasklet_hi_schedule(&jme->rxempty_task);
1558 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1559 tasklet_hi_schedule(&jme->rxclean_task);
1565 * Re-enable interrupt
1567 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1570 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1572 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1575 jme_intr(int irq, void *dev_id)
1578 struct net_device *netdev = dev_id;
1579 struct jme_adapter *jme = netdev_priv(netdev);
1582 intrstat = jread32(jme, JME_IEVE);
1585 * Check if it's really an interrupt for us
1587 if (unlikely((intrstat & INTR_ENABLE) == 0))
1591 * Check if the device still exist
1593 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1596 jme_intr_msi(jme, intrstat);
1601 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1603 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1606 jme_msi(int irq, void *dev_id)
1609 struct net_device *netdev = dev_id;
1610 struct jme_adapter *jme = netdev_priv(netdev);
1613 intrstat = jread32(jme, JME_IEVE);
1615 jme_intr_msi(jme, intrstat);
1621 jme_reset_link(struct jme_adapter *jme)
1623 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1627 jme_restart_an(struct jme_adapter *jme)
1631 spin_lock_bh(&jme->phy_lock);
1632 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1633 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1634 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1635 spin_unlock_bh(&jme->phy_lock);
1639 jme_request_irq(struct jme_adapter *jme)
1642 struct net_device *netdev = jme->dev;
1643 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1644 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1645 int irq_flags = SA_SHIRQ;
1647 irq_handler_t handler = jme_intr;
1648 int irq_flags = IRQF_SHARED;
1651 if (!pci_enable_msi(jme->pdev)) {
1652 set_bit(JME_FLAG_MSI, &jme->flags);
1657 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1661 "Unable to request %s interrupt (return: %d)\n",
1662 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1665 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1666 pci_disable_msi(jme->pdev);
1667 clear_bit(JME_FLAG_MSI, &jme->flags);
1670 netdev->irq = jme->pdev->irq;
1677 jme_free_irq(struct jme_adapter *jme)
1679 free_irq(jme->pdev->irq, jme->dev);
1680 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1681 pci_disable_msi(jme->pdev);
1682 clear_bit(JME_FLAG_MSI, &jme->flags);
1683 jme->dev->irq = jme->pdev->irq;
1688 jme_new_phy_on(struct jme_adapter *jme)
1692 reg = jread32(jme, JME_PHY_PWR);
1693 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1694 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1695 jwrite32(jme, JME_PHY_PWR, reg);
1697 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1698 reg &= ~PE1_GPREG0_PBG;
1699 reg |= PE1_GPREG0_ENBG;
1700 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1704 jme_new_phy_off(struct jme_adapter *jme)
1708 reg = jread32(jme, JME_PHY_PWR);
1709 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1710 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1711 jwrite32(jme, JME_PHY_PWR, reg);
1713 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1714 reg &= ~PE1_GPREG0_PBG;
1715 reg |= PE1_GPREG0_PDD3COLD;
1716 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1720 jme_phy_on(struct jme_adapter *jme)
1724 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1725 bmcr &= ~BMCR_PDOWN;
1726 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1728 if (new_phy_power_ctrl(jme->chip_main_rev))
1729 jme_new_phy_on(jme);
1733 jme_phy_off(struct jme_adapter *jme)
1737 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1739 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1741 if (new_phy_power_ctrl(jme->chip_main_rev))
1742 jme_new_phy_off(jme);
1746 jme_open(struct net_device *netdev)
1748 struct jme_adapter *jme = netdev_priv(netdev);
1752 JME_NAPI_ENABLE(jme);
1754 tasklet_enable(&jme->linkch_task);
1755 tasklet_enable(&jme->txclean_task);
1756 tasklet_hi_enable(&jme->rxclean_task);
1757 tasklet_hi_enable(&jme->rxempty_task);
1759 rc = jme_request_irq(jme);
1766 if (test_bit(JME_FLAG_SSET, &jme->flags))
1767 jme_set_settings(netdev, &jme->old_ecmd);
1769 jme_reset_phy_processor(jme);
1771 jme_reset_link(jme);
1776 netif_stop_queue(netdev);
1777 netif_carrier_off(netdev);
1782 jme_set_100m_half(struct jme_adapter *jme)
1787 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1788 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1789 BMCR_SPEED1000 | BMCR_FULLDPLX);
1790 tmp |= BMCR_SPEED100;
1793 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1796 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1798 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1801 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1803 jme_wait_link(struct jme_adapter *jme)
1805 u32 phylink, to = JME_WAIT_LINK_TIME;
1808 phylink = jme_linkstat_from_phy(jme);
1809 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1811 phylink = jme_linkstat_from_phy(jme);
1816 jme_powersave_phy(struct jme_adapter *jme)
1818 if (jme->reg_pmcs) {
1819 jme_set_100m_half(jme);
1821 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1824 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1831 jme_close(struct net_device *netdev)
1833 struct jme_adapter *jme = netdev_priv(netdev);
1835 netif_stop_queue(netdev);
1836 netif_carrier_off(netdev);
1841 JME_NAPI_DISABLE(jme);
1843 tasklet_disable(&jme->linkch_task);
1844 tasklet_disable(&jme->txclean_task);
1845 tasklet_disable(&jme->rxclean_task);
1846 tasklet_disable(&jme->rxempty_task);
1848 jme_disable_rx_engine(jme);
1849 jme_disable_tx_engine(jme);
1850 jme_reset_mac_processor(jme);
1851 jme_free_rx_resources(jme);
1852 jme_free_tx_resources(jme);
1860 jme_alloc_txdesc(struct jme_adapter *jme,
1861 struct sk_buff *skb)
1863 struct jme_ring *txring = &(jme->txring[0]);
1864 int idx, nr_alloc, mask = jme->tx_ring_mask;
1866 idx = txring->next_to_use;
1867 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1869 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1872 atomic_sub(nr_alloc, &txring->nr_free);
1874 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1880 jme_fill_tx_map(struct pci_dev *pdev,
1881 struct txdesc *txdesc,
1882 struct jme_buffer_info *txbi,
1890 dmaaddr = pci_map_page(pdev,
1896 pci_dma_sync_single_for_device(pdev,
1903 txdesc->desc2.flags = TXFLAG_OWN;
1904 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1905 txdesc->desc2.datalen = cpu_to_le16(len);
1906 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1907 txdesc->desc2.bufaddrl = cpu_to_le32(
1908 (__u64)dmaaddr & 0xFFFFFFFFUL);
1910 txbi->mapping = dmaaddr;
1915 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1917 struct jme_ring *txring = &(jme->txring[0]);
1918 struct txdesc *txdesc = txring->desc, *ctxdesc;
1919 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1920 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1921 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1922 int mask = jme->tx_ring_mask;
1923 struct skb_frag_struct *frag;
1926 for (i = 0 ; i < nr_frags ; ++i) {
1927 frag = &skb_shinfo(skb)->frags[i];
1928 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1929 ctxbi = txbi + ((idx + i + 2) & (mask));
1931 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1932 frag->page_offset, frag->size, hidma);
1935 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1936 ctxdesc = txdesc + ((idx + 1) & (mask));
1937 ctxbi = txbi + ((idx + 1) & (mask));
1938 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1939 offset_in_page(skb->data), len, hidma);
1944 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1947 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1948 skb_shinfo(skb)->tso_size
1950 skb_shinfo(skb)->gso_size
1952 && skb_header_cloned(skb) &&
1953 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1962 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1964 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1965 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1967 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1970 *flags |= TXFLAG_LSEN;
1972 if (skb->protocol == htons(ETH_P_IP)) {
1973 struct iphdr *iph = ip_hdr(skb);
1976 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1981 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1983 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1996 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1998 #ifdef CHECKSUM_PARTIAL
1999 if (skb->ip_summed == CHECKSUM_PARTIAL)
2001 if (skb->ip_summed == CHECKSUM_HW)
2006 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2007 if (skb->protocol == htons(ETH_P_IP))
2008 ip_proto = ip_hdr(skb)->protocol;
2009 else if (skb->protocol == htons(ETH_P_IPV6))
2010 ip_proto = ipv6_hdr(skb)->nexthdr;
2014 switch (skb->protocol) {
2015 case htons(ETH_P_IP):
2016 ip_proto = ip_hdr(skb)->protocol;
2018 case htons(ETH_P_IPV6):
2019 ip_proto = ipv6_hdr(skb)->nexthdr;
2029 *flags |= TXFLAG_TCPCS;
2032 *flags |= TXFLAG_UDPCS;
2035 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2042 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2044 if (vlan_tx_tag_present(skb)) {
2045 *flags |= TXFLAG_TAGON;
2046 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2051 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2053 struct jme_ring *txring = &(jme->txring[0]);
2054 struct txdesc *txdesc;
2055 struct jme_buffer_info *txbi;
2058 txdesc = (struct txdesc *)txring->desc + idx;
2059 txbi = txring->bufinf + idx;
2065 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2067 * Set OWN bit at final.
2068 * When kernel transmit faster than NIC.
2069 * And NIC trying to send this descriptor before we tell
2070 * it to start sending this TX queue.
2071 * Other fields are already filled correctly.
2074 flags = TXFLAG_OWN | TXFLAG_INT;
2076 * Set checksum flags while not tso
2078 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2079 jme_tx_csum(jme, skb, &flags);
2080 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2081 jme_map_tx_skb(jme, skb, idx);
2082 txdesc->desc1.flags = flags;
2084 * Set tx buffer info after telling NIC to send
2085 * For better tx_clean timing
2088 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2090 txbi->len = skb->len;
2091 txbi->start_xmit = jiffies;
2092 if (!txbi->start_xmit)
2093 txbi->start_xmit = (0UL-1);
2099 jme_stop_queue_if_full(struct jme_adapter *jme)
2101 struct jme_ring *txring = &(jme->txring[0]);
2102 struct jme_buffer_info *txbi = txring->bufinf;
2103 int idx = atomic_read(&txring->next_to_clean);
2108 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2109 netif_stop_queue(jme->dev);
2110 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2112 if (atomic_read(&txring->nr_free)
2113 >= (jme->tx_wake_threshold)) {
2114 netif_wake_queue(jme->dev);
2115 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2119 if (unlikely(txbi->start_xmit &&
2120 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2122 netif_stop_queue(jme->dev);
2123 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2128 * This function is already protected by netif_tx_lock()
2131 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2136 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2138 struct jme_adapter *jme = netdev_priv(netdev);
2141 if (unlikely(jme_expand_header(jme, skb))) {
2142 ++(NET_STAT(jme).tx_dropped);
2143 return NETDEV_TX_OK;
2146 idx = jme_alloc_txdesc(jme, skb);
2148 if (unlikely(idx < 0)) {
2149 netif_stop_queue(netdev);
2150 netif_err(jme, tx_err, jme->dev,
2151 "BUG! Tx ring full when queue awake!\n");
2153 return NETDEV_TX_BUSY;
2156 jme_fill_tx_desc(jme, skb, idx);
2158 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2159 TXCS_SELECT_QUEUE0 |
2162 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2163 netdev->trans_start = jiffies;
2166 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2167 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2168 jme_stop_queue_if_full(jme);
2170 return NETDEV_TX_OK;
2174 jme_set_unicastaddr(struct net_device *netdev)
2176 struct jme_adapter *jme = netdev_priv(netdev);
2179 val = (netdev->dev_addr[3] & 0xff) << 24 |
2180 (netdev->dev_addr[2] & 0xff) << 16 |
2181 (netdev->dev_addr[1] & 0xff) << 8 |
2182 (netdev->dev_addr[0] & 0xff);
2183 jwrite32(jme, JME_RXUMA_LO, val);
2184 val = (netdev->dev_addr[5] & 0xff) << 8 |
2185 (netdev->dev_addr[4] & 0xff);
2186 jwrite32(jme, JME_RXUMA_HI, val);
2190 jme_set_macaddr(struct net_device *netdev, void *p)
2192 struct jme_adapter *jme = netdev_priv(netdev);
2193 struct sockaddr *addr = p;
2195 if (netif_running(netdev))
2198 spin_lock_bh(&jme->macaddr_lock);
2199 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2200 jme_set_unicastaddr(netdev);
2201 spin_unlock_bh(&jme->macaddr_lock);
2207 jme_set_multi(struct net_device *netdev)
2209 struct jme_adapter *jme = netdev_priv(netdev);
2210 u32 mc_hash[2] = {};
2211 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2215 spin_lock_bh(&jme->rxmcs_lock);
2217 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2219 if (netdev->flags & IFF_PROMISC) {
2220 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2221 } else if (netdev->flags & IFF_ALLMULTI) {
2222 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2223 } else if (netdev->flags & IFF_MULTICAST) {
2224 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2225 struct dev_mc_list *mclist;
2227 struct netdev_hw_addr *ha;
2231 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2232 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2233 for (i = 0, mclist = netdev->mc_list;
2234 mclist && i < netdev->mc_count;
2235 ++i, mclist = mclist->next) {
2236 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2237 netdev_for_each_mc_addr(mclist, netdev) {
2239 netdev_for_each_mc_addr(ha, netdev) {
2241 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2242 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2244 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2246 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2249 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2250 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2254 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2256 spin_unlock_bh(&jme->rxmcs_lock);
2260 jme_change_mtu(struct net_device *netdev, int new_mtu)
2262 struct jme_adapter *jme = netdev_priv(netdev);
2264 if (new_mtu == jme->old_mtu)
2267 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2268 ((new_mtu) < IPV6_MIN_MTU))
2271 if (new_mtu > 4000) {
2272 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2273 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2274 jme_restart_rx_engine(jme);
2276 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2277 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2278 jme_restart_rx_engine(jme);
2281 if (new_mtu > 1900) {
2282 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2283 NETIF_F_TSO | NETIF_F_TSO6);
2285 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2286 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2287 if (test_bit(JME_FLAG_TSO, &jme->flags))
2288 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2291 netdev->mtu = new_mtu;
2292 jme_reset_link(jme);
2298 jme_tx_timeout(struct net_device *netdev)
2300 struct jme_adapter *jme = netdev_priv(netdev);
2303 jme_reset_phy_processor(jme);
2304 if (test_bit(JME_FLAG_SSET, &jme->flags))
2305 jme_set_settings(netdev, &jme->old_ecmd);
2308 * Force to Reset the link again
2310 jme_reset_link(jme);
2313 static inline void jme_pause_rx(struct jme_adapter *jme)
2315 atomic_dec(&jme->link_changing);
2317 jme_set_rx_pcc(jme, PCC_OFF);
2318 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2319 JME_NAPI_DISABLE(jme);
2321 tasklet_disable(&jme->rxclean_task);
2322 tasklet_disable(&jme->rxempty_task);
2326 static inline void jme_resume_rx(struct jme_adapter *jme)
2328 struct dynpcc_info *dpi = &(jme->dpi);
2330 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2331 JME_NAPI_ENABLE(jme);
2333 tasklet_hi_enable(&jme->rxclean_task);
2334 tasklet_hi_enable(&jme->rxempty_task);
2337 dpi->attempt = PCC_P1;
2339 jme_set_rx_pcc(jme, PCC_P1);
2341 atomic_inc(&jme->link_changing);
2345 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2347 struct jme_adapter *jme = netdev_priv(netdev);
2354 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2356 jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2358 struct jme_adapter *jme = netdev_priv(netdev);
2362 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2363 jme->vlgrp->vlan_devices[vid] = NULL;
2365 vlan_group_set_device(jme->vlgrp, vid, NULL);
2373 jme_get_drvinfo(struct net_device *netdev,
2374 struct ethtool_drvinfo *info)
2376 struct jme_adapter *jme = netdev_priv(netdev);
2378 strcpy(info->driver, DRV_NAME);
2379 strcpy(info->version, DRV_VERSION);
2380 strcpy(info->bus_info, pci_name(jme->pdev));
2384 jme_get_regs_len(struct net_device *netdev)
2390 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2394 for (i = 0 ; i < len ; i += 4)
2395 p[i >> 2] = jread32(jme, reg + i);
2399 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2402 u16 *p16 = (u16 *)p;
2404 for (i = 0 ; i < reg_nr ; ++i)
2405 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2409 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2411 struct jme_adapter *jme = netdev_priv(netdev);
2412 u32 *p32 = (u32 *)p;
2414 memset(p, 0xFF, JME_REG_LEN);
2417 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2420 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2423 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2426 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2429 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2433 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2435 struct jme_adapter *jme = netdev_priv(netdev);
2437 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2438 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2440 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2441 ecmd->use_adaptive_rx_coalesce = false;
2442 ecmd->rx_coalesce_usecs = 0;
2443 ecmd->rx_max_coalesced_frames = 0;
2447 ecmd->use_adaptive_rx_coalesce = true;
2449 switch (jme->dpi.cur) {
2451 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2452 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2455 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2456 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2459 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2460 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2470 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2472 struct jme_adapter *jme = netdev_priv(netdev);
2473 struct dynpcc_info *dpi = &(jme->dpi);
2475 if (netif_running(netdev))
2478 if (ecmd->use_adaptive_rx_coalesce &&
2479 test_bit(JME_FLAG_POLL, &jme->flags)) {
2480 clear_bit(JME_FLAG_POLL, &jme->flags);
2481 jme->jme_rx = netif_rx;
2482 jme->jme_vlan_rx = vlan_hwaccel_rx;
2484 dpi->attempt = PCC_P1;
2486 jme_set_rx_pcc(jme, PCC_P1);
2487 jme_interrupt_mode(jme);
2488 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2489 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2490 set_bit(JME_FLAG_POLL, &jme->flags);
2491 jme->jme_rx = netif_receive_skb;
2492 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2493 jme_interrupt_mode(jme);
2500 jme_get_pauseparam(struct net_device *netdev,
2501 struct ethtool_pauseparam *ecmd)
2503 struct jme_adapter *jme = netdev_priv(netdev);
2506 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2507 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2509 spin_lock_bh(&jme->phy_lock);
2510 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2511 spin_unlock_bh(&jme->phy_lock);
2514 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2518 jme_set_pauseparam(struct net_device *netdev,
2519 struct ethtool_pauseparam *ecmd)
2521 struct jme_adapter *jme = netdev_priv(netdev);
2524 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2525 (ecmd->tx_pause != 0)) {
2528 jme->reg_txpfc |= TXPFC_PF_EN;
2530 jme->reg_txpfc &= ~TXPFC_PF_EN;
2532 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2535 spin_lock_bh(&jme->rxmcs_lock);
2536 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2537 (ecmd->rx_pause != 0)) {
2540 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2542 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2544 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2546 spin_unlock_bh(&jme->rxmcs_lock);
2548 spin_lock_bh(&jme->phy_lock);
2549 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2550 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2551 (ecmd->autoneg != 0)) {
2554 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2556 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2558 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2559 MII_ADVERTISE, val);
2561 spin_unlock_bh(&jme->phy_lock);
2567 jme_get_wol(struct net_device *netdev,
2568 struct ethtool_wolinfo *wol)
2570 struct jme_adapter *jme = netdev_priv(netdev);
2572 wol->supported = WAKE_MAGIC | WAKE_PHY;
2576 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2577 wol->wolopts |= WAKE_PHY;
2579 if (jme->reg_pmcs & PMCS_MFEN)
2580 wol->wolopts |= WAKE_MAGIC;
2585 jme_set_wol(struct net_device *netdev,
2586 struct ethtool_wolinfo *wol)
2588 struct jme_adapter *jme = netdev_priv(netdev);
2590 if (wol->wolopts & (WAKE_MAGICSECURE |
2599 if (wol->wolopts & WAKE_PHY)
2600 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2602 if (wol->wolopts & WAKE_MAGIC)
2603 jme->reg_pmcs |= PMCS_MFEN;
2605 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2611 jme_get_settings(struct net_device *netdev,
2612 struct ethtool_cmd *ecmd)
2614 struct jme_adapter *jme = netdev_priv(netdev);
2617 spin_lock_bh(&jme->phy_lock);
2618 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2619 spin_unlock_bh(&jme->phy_lock);
2624 jme_set_settings(struct net_device *netdev,
2625 struct ethtool_cmd *ecmd)
2627 struct jme_adapter *jme = netdev_priv(netdev);
2630 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2634 * Check If user changed duplex only while force_media.
2635 * Hardware would not generate link change interrupt.
2637 if (jme->mii_if.force_media &&
2638 ecmd->autoneg != AUTONEG_ENABLE &&
2639 (jme->mii_if.full_duplex != ecmd->duplex))
2642 spin_lock_bh(&jme->phy_lock);
2643 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2644 spin_unlock_bh(&jme->phy_lock);
2648 jme_reset_link(jme);
2649 jme->old_ecmd = *ecmd;
2650 set_bit(JME_FLAG_SSET, &jme->flags);
2657 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2660 struct jme_adapter *jme = netdev_priv(netdev);
2661 struct mii_ioctl_data *mii_data = if_mii(rq);
2662 unsigned int duplex_chg;
2664 if (cmd == SIOCSMIIREG) {
2665 u16 val = mii_data->val_in;
2666 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2667 (val & BMCR_SPEED1000))
2671 spin_lock_bh(&jme->phy_lock);
2672 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2673 spin_unlock_bh(&jme->phy_lock);
2675 if (!rc && (cmd == SIOCSMIIREG)) {
2677 jme_reset_link(jme);
2678 jme_get_settings(netdev, &jme->old_ecmd);
2679 set_bit(JME_FLAG_SSET, &jme->flags);
2686 jme_get_link(struct net_device *netdev)
2688 struct jme_adapter *jme = netdev_priv(netdev);
2689 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2693 jme_get_msglevel(struct net_device *netdev)
2695 struct jme_adapter *jme = netdev_priv(netdev);
2696 return jme->msg_enable;
2700 jme_set_msglevel(struct net_device *netdev, u32 value)
2702 struct jme_adapter *jme = netdev_priv(netdev);
2703 jme->msg_enable = value;
2707 jme_get_rx_csum(struct net_device *netdev)
2709 struct jme_adapter *jme = netdev_priv(netdev);
2710 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2714 jme_set_rx_csum(struct net_device *netdev, u32 on)
2716 struct jme_adapter *jme = netdev_priv(netdev);
2718 spin_lock_bh(&jme->rxmcs_lock);
2720 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2722 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2723 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2724 spin_unlock_bh(&jme->rxmcs_lock);
2730 jme_set_tx_csum(struct net_device *netdev, u32 on)
2732 struct jme_adapter *jme = netdev_priv(netdev);
2735 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2736 if (netdev->mtu <= 1900)
2738 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2740 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2742 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2749 jme_set_tso(struct net_device *netdev, u32 on)
2751 struct jme_adapter *jme = netdev_priv(netdev);
2754 set_bit(JME_FLAG_TSO, &jme->flags);
2755 if (netdev->mtu <= 1900)
2756 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2758 clear_bit(JME_FLAG_TSO, &jme->flags);
2759 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2766 jme_nway_reset(struct net_device *netdev)
2768 struct jme_adapter *jme = netdev_priv(netdev);
2769 jme_restart_an(jme);
2774 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2779 val = jread32(jme, JME_SMBCSR);
2780 to = JME_SMB_BUSY_TIMEOUT;
2781 while ((val & SMBCSR_BUSY) && --to) {
2783 val = jread32(jme, JME_SMBCSR);
2786 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2790 jwrite32(jme, JME_SMBINTF,
2791 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2792 SMBINTF_HWRWN_READ |
2795 val = jread32(jme, JME_SMBINTF);
2796 to = JME_SMB_BUSY_TIMEOUT;
2797 while ((val & SMBINTF_HWCMD) && --to) {
2799 val = jread32(jme, JME_SMBINTF);
2802 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2806 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2810 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2815 val = jread32(jme, JME_SMBCSR);
2816 to = JME_SMB_BUSY_TIMEOUT;
2817 while ((val & SMBCSR_BUSY) && --to) {
2819 val = jread32(jme, JME_SMBCSR);
2822 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2826 jwrite32(jme, JME_SMBINTF,
2827 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2828 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2829 SMBINTF_HWRWN_WRITE |
2832 val = jread32(jme, JME_SMBINTF);
2833 to = JME_SMB_BUSY_TIMEOUT;
2834 while ((val & SMBINTF_HWCMD) && --to) {
2836 val = jread32(jme, JME_SMBINTF);
2839 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2847 jme_get_eeprom_len(struct net_device *netdev)
2849 struct jme_adapter *jme = netdev_priv(netdev);
2851 val = jread32(jme, JME_SMBCSR);
2852 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2856 jme_get_eeprom(struct net_device *netdev,
2857 struct ethtool_eeprom *eeprom, u8 *data)
2859 struct jme_adapter *jme = netdev_priv(netdev);
2860 int i, offset = eeprom->offset, len = eeprom->len;
2863 * ethtool will check the boundary for us
2865 eeprom->magic = JME_EEPROM_MAGIC;
2866 for (i = 0 ; i < len ; ++i)
2867 data[i] = jme_smb_read(jme, i + offset);
2873 jme_set_eeprom(struct net_device *netdev,
2874 struct ethtool_eeprom *eeprom, u8 *data)
2876 struct jme_adapter *jme = netdev_priv(netdev);
2877 int i, offset = eeprom->offset, len = eeprom->len;
2879 if (eeprom->magic != JME_EEPROM_MAGIC)
2883 * ethtool will check the boundary for us
2885 for (i = 0 ; i < len ; ++i)
2886 jme_smb_write(jme, i + offset, data[i]);
2891 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2892 static struct ethtool_ops jme_ethtool_ops = {
2894 static const struct ethtool_ops jme_ethtool_ops = {
2896 .get_drvinfo = jme_get_drvinfo,
2897 .get_regs_len = jme_get_regs_len,
2898 .get_regs = jme_get_regs,
2899 .get_coalesce = jme_get_coalesce,
2900 .set_coalesce = jme_set_coalesce,
2901 .get_pauseparam = jme_get_pauseparam,
2902 .set_pauseparam = jme_set_pauseparam,
2903 .get_wol = jme_get_wol,
2904 .set_wol = jme_set_wol,
2905 .get_settings = jme_get_settings,
2906 .set_settings = jme_set_settings,
2907 .get_link = jme_get_link,
2908 .get_msglevel = jme_get_msglevel,
2909 .set_msglevel = jme_set_msglevel,
2910 .get_rx_csum = jme_get_rx_csum,
2911 .set_rx_csum = jme_set_rx_csum,
2912 .set_tx_csum = jme_set_tx_csum,
2913 .set_tso = jme_set_tso,
2914 .set_sg = ethtool_op_set_sg,
2915 .nway_reset = jme_nway_reset,
2916 .get_eeprom_len = jme_get_eeprom_len,
2917 .get_eeprom = jme_get_eeprom,
2918 .set_eeprom = jme_set_eeprom,
2922 jme_pci_dma64(struct pci_dev *pdev)
2924 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2925 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2926 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2928 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2931 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2932 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2934 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2938 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2939 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2940 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2942 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2945 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2946 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2948 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2952 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2953 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2954 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2956 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2957 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2965 jme_phy_init(struct jme_adapter *jme)
2969 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2970 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2974 jme_check_hw_ver(struct jme_adapter *jme)
2978 chipmode = jread32(jme, JME_CHIPMODE);
2980 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2981 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2982 jme->chip_main_rev = jme->chiprev & 0xF;
2983 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2986 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2987 static const struct net_device_ops jme_netdev_ops = {
2988 .ndo_open = jme_open,
2989 .ndo_stop = jme_close,
2990 .ndo_validate_addr = eth_validate_addr,
2991 .ndo_do_ioctl = jme_ioctl,
2992 .ndo_start_xmit = jme_start_xmit,
2993 .ndo_set_mac_address = jme_set_macaddr,
2994 .ndo_set_multicast_list = jme_set_multi,
2995 .ndo_change_mtu = jme_change_mtu,
2996 .ndo_tx_timeout = jme_tx_timeout,
2997 .ndo_vlan_rx_register = jme_vlan_rx_register,
3001 static int __devinit
3002 jme_init_one(struct pci_dev *pdev,
3003 const struct pci_device_id *ent)
3005 int rc = 0, using_dac, i;
3006 struct net_device *netdev;
3007 struct jme_adapter *jme;
3012 * set up PCI device basics
3014 rc = pci_enable_device(pdev);
3016 pr_err("Cannot enable PCI device\n");
3020 using_dac = jme_pci_dma64(pdev);
3021 if (using_dac < 0) {
3022 pr_err("Cannot set PCI DMA Mask\n");
3024 goto err_out_disable_pdev;
3027 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3028 pr_err("No PCI resource region found\n");
3030 goto err_out_disable_pdev;
3033 rc = pci_request_regions(pdev, DRV_NAME);
3035 pr_err("Cannot obtain PCI resource region\n");
3036 goto err_out_disable_pdev;
3039 pci_set_master(pdev);
3042 * alloc and init net device
3044 netdev = alloc_etherdev(sizeof(*jme));
3046 pr_err("Cannot allocate netdev structure\n");
3048 goto err_out_release_regions;
3050 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3051 netdev->netdev_ops = &jme_netdev_ops;
3053 netdev->open = jme_open;
3054 netdev->stop = jme_close;
3055 netdev->do_ioctl = jme_ioctl;
3056 netdev->hard_start_xmit = jme_start_xmit;
3057 netdev->set_mac_address = jme_set_macaddr;
3058 netdev->set_multicast_list = jme_set_multi;
3059 netdev->change_mtu = jme_change_mtu;
3060 netdev->tx_timeout = jme_tx_timeout;
3061 netdev->vlan_rx_register = jme_vlan_rx_register;
3062 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3063 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3065 NETDEV_GET_STATS(netdev, &jme_get_stats);
3067 netdev->ethtool_ops = &jme_ethtool_ops;
3068 netdev->watchdog_timeo = TX_TIMEOUT;
3069 netdev->features = NETIF_F_IP_CSUM |
3074 NETIF_F_HW_VLAN_TX |
3077 netdev->features |= NETIF_F_HIGHDMA;
3079 SET_NETDEV_DEV(netdev, &pdev->dev);
3080 pci_set_drvdata(pdev, netdev);
3085 jme = netdev_priv(netdev);
3088 jme->jme_rx = netif_rx;
3089 jme->jme_vlan_rx = vlan_hwaccel_rx;
3090 jme->old_mtu = netdev->mtu = 1500;
3092 jme->tx_ring_size = 1 << 10;
3093 jme->tx_ring_mask = jme->tx_ring_size - 1;
3094 jme->tx_wake_threshold = 1 << 9;
3095 jme->rx_ring_size = 1 << 9;
3096 jme->rx_ring_mask = jme->rx_ring_size - 1;
3097 jme->msg_enable = JME_DEF_MSG_ENABLE;
3098 jme->regs = ioremap(pci_resource_start(pdev, 0),
3099 pci_resource_len(pdev, 0));
3101 pr_err("Mapping PCI resource region error\n");
3103 goto err_out_free_netdev;
3107 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3108 jwrite32(jme, JME_APMC, apmc);
3109 } else if (force_pseudohp) {
3110 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3111 jwrite32(jme, JME_APMC, apmc);
3114 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3116 spin_lock_init(&jme->phy_lock);
3117 spin_lock_init(&jme->macaddr_lock);
3118 spin_lock_init(&jme->rxmcs_lock);
3120 atomic_set(&jme->link_changing, 1);
3121 atomic_set(&jme->rx_cleaning, 1);
3122 atomic_set(&jme->tx_cleaning, 1);
3123 atomic_set(&jme->rx_empty, 1);
3125 tasklet_init(&jme->pcc_task,
3127 (unsigned long) jme);
3128 tasklet_init(&jme->linkch_task,
3129 jme_link_change_tasklet,
3130 (unsigned long) jme);
3131 tasklet_init(&jme->txclean_task,
3132 jme_tx_clean_tasklet,
3133 (unsigned long) jme);
3134 tasklet_init(&jme->rxclean_task,
3135 jme_rx_clean_tasklet,
3136 (unsigned long) jme);
3137 tasklet_init(&jme->rxempty_task,
3138 jme_rx_empty_tasklet,
3139 (unsigned long) jme);
3140 tasklet_disable_nosync(&jme->linkch_task);
3141 tasklet_disable_nosync(&jme->txclean_task);
3142 tasklet_disable_nosync(&jme->rxclean_task);
3143 tasklet_disable_nosync(&jme->rxempty_task);
3144 jme->dpi.cur = PCC_P1;
3147 jme->reg_rxcs = RXCS_DEFAULT;
3148 jme->reg_rxmcs = RXMCS_DEFAULT;
3150 jme->reg_pmcs = PMCS_MFEN;
3151 jme->reg_gpreg1 = GPREG1_DEFAULT;
3152 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3153 set_bit(JME_FLAG_TSO, &jme->flags);
3156 * Get Max Read Req Size from PCI Config Space
3158 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3159 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3160 switch (jme->mrrs) {
3162 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3165 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3168 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3173 * Must check before reset_mac_processor
3175 jme_check_hw_ver(jme);
3176 jme->mii_if.dev = netdev;
3178 jme->mii_if.phy_id = 0;
3179 for (i = 1 ; i < 32 ; ++i) {
3180 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3181 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3182 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3183 jme->mii_if.phy_id = i;
3188 if (!jme->mii_if.phy_id) {
3190 pr_err("Can not find phy_id\n");
3194 jme->reg_ghc |= GHC_LINK_POLL;
3196 jme->mii_if.phy_id = 1;
3198 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3199 jme->mii_if.supports_gmii = true;
3201 jme->mii_if.supports_gmii = false;
3202 jme->mii_if.phy_id_mask = 0x1F;
3203 jme->mii_if.reg_num_mask = 0x1F;
3204 jme->mii_if.mdio_read = jme_mdio_read;
3205 jme->mii_if.mdio_write = jme_mdio_write;
3208 jme_set_phyfifo_5level(jme);
3209 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3215 * Reset MAC processor and reload EEPROM for MAC Address
3217 jme_reset_mac_processor(jme);
3218 rc = jme_reload_eeprom(jme);
3220 pr_err("Reload eeprom for reading MAC Address error\n");
3223 jme_load_macaddr(netdev);
3226 * Tell stack that we are not ready to work until open()
3228 netif_carrier_off(netdev);
3230 rc = register_netdev(netdev);
3232 pr_err("Cannot register net device\n");
3236 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3237 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3238 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3239 "JMC250 Gigabit Ethernet" :
3240 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3241 "JMC260 Fast Ethernet" : "Unknown",
3242 (jme->fpgaver != 0) ? " (FPGA)" : "",
3243 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3245 netdev->dev_addr[0],
3246 netdev->dev_addr[1],
3247 netdev->dev_addr[2],
3248 netdev->dev_addr[3],
3249 netdev->dev_addr[4],
3250 netdev->dev_addr[5]);
3256 err_out_free_netdev:
3257 pci_set_drvdata(pdev, NULL);
3258 free_netdev(netdev);
3259 err_out_release_regions:
3260 pci_release_regions(pdev);
3261 err_out_disable_pdev:
3262 pci_disable_device(pdev);
3267 static void __devexit
3268 jme_remove_one(struct pci_dev *pdev)
3270 struct net_device *netdev = pci_get_drvdata(pdev);
3271 struct jme_adapter *jme = netdev_priv(netdev);
3273 unregister_netdev(netdev);
3275 pci_set_drvdata(pdev, NULL);
3276 free_netdev(netdev);
3277 pci_release_regions(pdev);
3278 pci_disable_device(pdev);
3283 jme_shutdown(struct pci_dev *pdev)
3285 struct net_device *netdev = pci_get_drvdata(pdev);
3286 struct jme_adapter *jme = netdev_priv(netdev);
3288 jme_powersave_phy(jme);
3289 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3290 pci_enable_wake(pdev, PCI_D3hot, true);
3292 pci_pme_active(pdev, true);
3298 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3300 struct net_device *netdev = pci_get_drvdata(pdev);
3301 struct jme_adapter *jme = netdev_priv(netdev);
3303 atomic_dec(&jme->link_changing);
3305 netif_device_detach(netdev);
3306 netif_stop_queue(netdev);
3309 tasklet_disable(&jme->txclean_task);
3310 tasklet_disable(&jme->rxclean_task);
3311 tasklet_disable(&jme->rxempty_task);
3313 if (netif_carrier_ok(netdev)) {
3314 if (test_bit(JME_FLAG_POLL, &jme->flags))
3315 jme_polling_mode(jme);
3317 jme_stop_pcc_timer(jme);
3318 jme_disable_rx_engine(jme);
3319 jme_disable_tx_engine(jme);
3320 jme_reset_mac_processor(jme);
3321 jme_free_rx_resources(jme);
3322 jme_free_tx_resources(jme);
3323 netif_carrier_off(netdev);
3327 tasklet_enable(&jme->txclean_task);
3328 tasklet_hi_enable(&jme->rxclean_task);
3329 tasklet_hi_enable(&jme->rxempty_task);
3331 pci_save_state(pdev);
3332 jme_powersave_phy(jme);
3333 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3334 pci_enable_wake(pdev, PCI_D3hot, true);
3336 pci_pme_active(pdev, true);
3338 pci_set_power_state(pdev, PCI_D3hot);
3344 jme_resume(struct pci_dev *pdev)
3346 struct net_device *netdev = pci_get_drvdata(pdev);
3347 struct jme_adapter *jme = netdev_priv(netdev);
3350 pci_restore_state(pdev);
3353 if (test_bit(JME_FLAG_SSET, &jme->flags))
3354 jme_set_settings(netdev, &jme->old_ecmd);
3356 jme_reset_phy_processor(jme);
3359 netif_device_attach(netdev);
3361 atomic_inc(&jme->link_changing);
3363 jme_reset_link(jme);
3369 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3370 static struct pci_device_id jme_pci_tbl[] = {
3372 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3374 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3375 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3379 static struct pci_driver jme_driver = {
3381 .id_table = jme_pci_tbl,
3382 .probe = jme_init_one,
3383 .remove = __devexit_p(jme_remove_one),
3385 .suspend = jme_suspend,
3386 .resume = jme_resume,
3387 #endif /* CONFIG_PM */
3388 .shutdown = jme_shutdown,
3392 jme_init_module(void)
3394 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3395 return pci_register_driver(&jme_driver);
3399 jme_cleanup_module(void)
3401 pci_unregister_driver(&jme_driver);
3404 module_init(jme_init_module);
3405 module_exit(jme_cleanup_module);
3407 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3408 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3409 MODULE_LICENSE("GPL");
3410 MODULE_VERSION(DRV_VERSION);
3411 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);