2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/pci.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/mii.h>
33 #include <linux/crc32.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
38 #include <linux/ipv6.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/if_vlan.h>
42 #include <linux/slab.h>
43 #include <net/ip6_checksum.h>
46 static int force_pseudohp = -1;
47 static int no_pseudohp = -1;
48 static int no_extplug = -1;
49 module_param(force_pseudohp, int, 0);
50 MODULE_PARM_DESC(force_pseudohp,
51 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
52 module_param(no_pseudohp, int, 0);
53 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
54 module_param(no_extplug, int, 0);
55 MODULE_PARM_DESC(no_extplug,
56 "Do not use external plug signal for pseudo hot-plug.");
59 jme_mdio_read(struct net_device *netdev, int phy, int reg)
61 struct jme_adapter *jme = netdev_priv(netdev);
62 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
65 jwrite32(jme, JME_SMI, SMI_OP_REQ |
70 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72 val = jread32(jme, JME_SMI);
73 if ((val & SMI_OP_REQ) == 0)
78 pr_err("phy(%d) read timeout : %d\n", phy, reg);
85 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
89 jme_mdio_write(struct net_device *netdev,
90 int phy, int reg, int val)
92 struct jme_adapter *jme = netdev_priv(netdev);
95 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
96 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
97 smi_phy_addr(phy) | smi_reg_addr(reg));
100 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
107 pr_err("phy(%d) write timeout : %d\n", phy, reg);
111 jme_reset_phy_processor(struct jme_adapter *jme)
115 jme_mdio_write(jme->dev,
117 MII_ADVERTISE, ADVERTISE_ALL |
118 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
121 jme_mdio_write(jme->dev,
124 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126 val = jme_mdio_read(jme->dev,
130 jme_mdio_write(jme->dev,
132 MII_BMCR, val | BMCR_RESET);
136 jme_setup_wakeup_frame(struct jme_adapter *jme,
137 u32 *mask, u32 crc, int fnr)
144 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 jwrite32(jme, JME_WFODP, crc);
152 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
153 jwrite32(jme, JME_WFOI,
154 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
155 (fnr & WFOI_FRAME_SEL));
157 jwrite32(jme, JME_WFODP, mask[i]);
163 jme_reset_mac_processor(struct jme_adapter *jme)
165 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
166 u32 crc = 0xCDCDCDCD;
170 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 jwrite32(jme, JME_GHC, jme->reg_ghc);
174 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
175 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
176 jwrite32(jme, JME_RXQDC, 0x00000000);
177 jwrite32(jme, JME_RXNDA, 0x00000000);
178 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_TXQDC, 0x00000000);
181 jwrite32(jme, JME_TXNDA, 0x00000000);
183 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
185 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
186 jme_setup_wakeup_frame(jme, mask, crc, i);
188 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 gpreg0 = GPREG0_DEFAULT;
191 jwrite32(jme, JME_GPREG0, gpreg0);
192 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
196 jme_reset_ghc_speed(struct jme_adapter *jme)
198 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
199 jwrite32(jme, JME_GHC, jme->reg_ghc);
203 jme_clear_pm(struct jme_adapter *jme)
205 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
206 pci_set_power_state(jme->pdev, PCI_D0);
207 pci_enable_wake(jme->pdev, PCI_D0, false);
211 jme_reload_eeprom(struct jme_adapter *jme)
216 val = jread32(jme, JME_SMBCSR);
218 if (val & SMBCSR_EEPROMD) {
220 jwrite32(jme, JME_SMBCSR, val);
221 val |= SMBCSR_RELOAD;
222 jwrite32(jme, JME_SMBCSR, val);
225 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
232 pr_err("eeprom reload timeout\n");
241 jme_load_macaddr(struct net_device *netdev)
243 struct jme_adapter *jme = netdev_priv(netdev);
244 unsigned char macaddr[6];
247 spin_lock_bh(&jme->macaddr_lock);
248 val = jread32(jme, JME_RXUMA_LO);
249 macaddr[0] = (val >> 0) & 0xFF;
250 macaddr[1] = (val >> 8) & 0xFF;
251 macaddr[2] = (val >> 16) & 0xFF;
252 macaddr[3] = (val >> 24) & 0xFF;
253 val = jread32(jme, JME_RXUMA_HI);
254 macaddr[4] = (val >> 0) & 0xFF;
255 macaddr[5] = (val >> 8) & 0xFF;
256 memcpy(netdev->dev_addr, macaddr, 6);
257 spin_unlock_bh(&jme->macaddr_lock);
261 jme_set_rx_pcc(struct jme_adapter *jme, int p)
265 jwrite32(jme, JME_PCCRX0,
266 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
267 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
270 jwrite32(jme, JME_PCCRX0,
271 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
272 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
275 jwrite32(jme, JME_PCCRX0,
276 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
277 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
280 jwrite32(jme, JME_PCCRX0,
281 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
282 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
289 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
290 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
294 jme_start_irq(struct jme_adapter *jme)
296 register struct dynpcc_info *dpi = &(jme->dpi);
298 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->attempt = PCC_P1;
303 jwrite32(jme, JME_PCCTX,
304 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
305 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
312 jwrite32(jme, JME_IENS, INTR_ENABLE);
316 jme_stop_irq(struct jme_adapter *jme)
321 jwrite32f(jme, JME_IENC, INTR_ENABLE);
325 jme_linkstat_from_phy(struct jme_adapter *jme)
329 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
330 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
331 if (bmsr & BMSR_ANCOMP)
332 phylink |= PHY_LINK_AUTONEG_COMPLETE;
338 jme_set_phyfifoa(struct jme_adapter *jme)
340 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
344 jme_set_phyfifob(struct jme_adapter *jme)
346 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
350 jme_check_link(struct net_device *netdev, int testonly)
352 struct jme_adapter *jme = netdev_priv(netdev);
353 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
360 phylink = jme_linkstat_from_phy(jme);
362 phylink = jread32(jme, JME_PHY_LINK);
364 if (phylink & PHY_LINK_UP) {
365 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
367 * If we did not enable AN
368 * Speed/Duplex Info should be obtained from SMI
370 phylink = PHY_LINK_UP;
372 bmcr = jme_mdio_read(jme->dev,
376 phylink |= ((bmcr & BMCR_SPEED1000) &&
377 (bmcr & BMCR_SPEED100) == 0) ?
378 PHY_LINK_SPEED_1000M :
379 (bmcr & BMCR_SPEED100) ?
380 PHY_LINK_SPEED_100M :
383 phylink |= (bmcr & BMCR_FULLDPLX) ?
386 strcat(linkmsg, "Forced: ");
389 * Keep polling for speed/duplex resolve complete
391 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
397 phylink = jme_linkstat_from_phy(jme);
399 phylink = jread32(jme, JME_PHY_LINK);
402 pr_err("Waiting speed resolve timeout\n");
404 strcat(linkmsg, "ANed: ");
407 if (jme->phylink == phylink) {
414 jme->phylink = phylink;
416 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
417 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
418 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
419 switch (phylink & PHY_LINK_SPEED_MASK) {
420 case PHY_LINK_SPEED_10M:
421 ghc |= GHC_SPEED_10M |
422 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
423 strcat(linkmsg, "10 Mbps, ");
425 case PHY_LINK_SPEED_100M:
426 ghc |= GHC_SPEED_100M |
427 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
428 strcat(linkmsg, "100 Mbps, ");
430 case PHY_LINK_SPEED_1000M:
431 ghc |= GHC_SPEED_1000M |
432 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
433 strcat(linkmsg, "1000 Mbps, ");
439 if (phylink & PHY_LINK_DUPLEX) {
440 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
447 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
448 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
450 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
453 gpreg1 = GPREG1_DEFAULT;
454 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
455 if (!(phylink & PHY_LINK_DUPLEX))
456 gpreg1 |= GPREG1_HALFMODEPATCH;
457 switch (phylink & PHY_LINK_SPEED_MASK) {
458 case PHY_LINK_SPEED_10M:
459 jme_set_phyfifoa(jme);
460 gpreg1 |= GPREG1_RSSPATCH;
462 case PHY_LINK_SPEED_100M:
463 jme_set_phyfifob(jme);
464 gpreg1 |= GPREG1_RSSPATCH;
466 case PHY_LINK_SPEED_1000M:
467 jme_set_phyfifoa(jme);
474 jwrite32(jme, JME_GPREG1, gpreg1);
475 jwrite32(jme, JME_GHC, ghc);
478 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
481 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
484 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
485 netif_carrier_on(netdev);
490 netif_info(jme, link, jme->dev, "Link is down\n");
492 netif_carrier_off(netdev);
500 jme_setup_tx_resources(struct jme_adapter *jme)
502 struct jme_ring *txring = &(jme->txring[0]);
504 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
505 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
515 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
517 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
518 txring->next_to_use = 0;
519 atomic_set(&txring->next_to_clean, 0);
520 atomic_set(&txring->nr_free, jme->tx_ring_size);
522 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
523 jme->tx_ring_size, GFP_ATOMIC);
524 if (unlikely(!(txring->bufinf)))
525 goto err_free_txring;
528 * Initialize Transmit Descriptors
530 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
531 memset(txring->bufinf, 0,
532 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
537 dma_free_coherent(&(jme->pdev->dev),
538 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
544 txring->dmaalloc = 0;
546 txring->bufinf = NULL;
552 jme_free_tx_resources(struct jme_adapter *jme)
555 struct jme_ring *txring = &(jme->txring[0]);
556 struct jme_buffer_info *txbi;
559 if (txring->bufinf) {
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
563 dev_kfree_skb(txbi->skb);
569 txbi->start_xmit = 0;
571 kfree(txring->bufinf);
574 dma_free_coherent(&(jme->pdev->dev),
575 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
579 txring->alloc = NULL;
581 txring->dmaalloc = 0;
583 txring->bufinf = NULL;
585 txring->next_to_use = 0;
586 atomic_set(&txring->next_to_clean, 0);
587 atomic_set(&txring->nr_free, 0);
591 jme_enable_tx_engine(struct jme_adapter *jme)
596 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
600 * Setup TX Queue 0 DMA Bass Address
602 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
603 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
604 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
607 * Setup TX Descptor Count
609 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
615 jwrite32(jme, JME_TXCS, jme->reg_txcs |
622 jme_restart_tx_engine(struct jme_adapter *jme)
627 jwrite32(jme, JME_TXCS, jme->reg_txcs |
633 jme_disable_tx_engine(struct jme_adapter *jme)
641 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
644 val = jread32(jme, JME_TXCS);
645 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
647 val = jread32(jme, JME_TXCS);
652 pr_err("Disable TX engine timeout\n");
656 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
658 struct jme_ring *rxring = &(jme->rxring[0]);
659 register struct rxdesc *rxdesc = rxring->desc;
660 struct jme_buffer_info *rxbi = rxring->bufinf;
666 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
667 rxdesc->desc1.bufaddrl = cpu_to_le32(
668 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
669 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
670 if (jme->dev->features & NETIF_F_HIGHDMA)
671 rxdesc->desc1.flags = RXFLAG_64BIT;
673 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
677 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
679 struct jme_ring *rxring = &(jme->rxring[0]);
680 struct jme_buffer_info *rxbi = rxring->bufinf + i;
683 skb = netdev_alloc_skb(jme->dev,
684 jme->dev->mtu + RX_EXTRA_LEN);
689 rxbi->len = skb_tailroom(skb);
690 rxbi->mapping = pci_map_page(jme->pdev,
691 virt_to_page(skb->data),
692 offset_in_page(skb->data),
700 jme_free_rx_buf(struct jme_adapter *jme, int i)
702 struct jme_ring *rxring = &(jme->rxring[0]);
703 struct jme_buffer_info *rxbi = rxring->bufinf;
707 pci_unmap_page(jme->pdev,
711 dev_kfree_skb(rxbi->skb);
719 jme_free_rx_resources(struct jme_adapter *jme)
722 struct jme_ring *rxring = &(jme->rxring[0]);
725 if (rxring->bufinf) {
726 for (i = 0 ; i < jme->rx_ring_size ; ++i)
727 jme_free_rx_buf(jme, i);
728 kfree(rxring->bufinf);
731 dma_free_coherent(&(jme->pdev->dev),
732 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
735 rxring->alloc = NULL;
737 rxring->dmaalloc = 0;
739 rxring->bufinf = NULL;
741 rxring->next_to_use = 0;
742 atomic_set(&rxring->next_to_clean, 0);
746 jme_setup_rx_resources(struct jme_adapter *jme)
749 struct jme_ring *rxring = &(jme->rxring[0]);
751 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
752 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
761 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
763 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
764 rxring->next_to_use = 0;
765 atomic_set(&rxring->next_to_clean, 0);
767 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
768 jme->rx_ring_size, GFP_ATOMIC);
769 if (unlikely(!(rxring->bufinf)))
770 goto err_free_rxring;
773 * Initiallize Receive Descriptors
775 memset(rxring->bufinf, 0,
776 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
777 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
778 if (unlikely(jme_make_new_rx_buf(jme, i))) {
779 jme_free_rx_resources(jme);
783 jme_set_clean_rxdesc(jme, i);
789 dma_free_coherent(&(jme->pdev->dev),
790 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
795 rxring->dmaalloc = 0;
797 rxring->bufinf = NULL;
803 jme_enable_rx_engine(struct jme_adapter *jme)
808 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
813 * Setup RX DMA Bass Address
815 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
816 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
817 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
820 * Setup RX Descriptor Count
822 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
825 * Setup Unicast Filter
827 jme_set_multi(jme->dev);
833 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
840 jme_restart_rx_engine(struct jme_adapter *jme)
845 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
852 jme_disable_rx_engine(struct jme_adapter *jme)
860 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
863 val = jread32(jme, JME_RXCS);
864 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
866 val = jread32(jme, JME_RXCS);
871 pr_err("Disable RX engine timeout\n");
876 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
878 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
881 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
882 == RXWBFLAG_TCPON)) {
883 if (flags & RXWBFLAG_IPV4)
884 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
889 == RXWBFLAG_UDPON)) {
890 if (flags & RXWBFLAG_IPV4)
891 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
895 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
897 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
905 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
907 struct jme_ring *rxring = &(jme->rxring[0]);
908 struct rxdesc *rxdesc = rxring->desc;
909 struct jme_buffer_info *rxbi = rxring->bufinf;
917 pci_dma_sync_single_for_cpu(jme->pdev,
922 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
923 pci_dma_sync_single_for_device(jme->pdev,
928 ++(NET_STAT(jme).rx_dropped);
930 framesize = le16_to_cpu(rxdesc->descwb.framesize)
933 skb_reserve(skb, RX_PREPAD_SIZE);
934 skb_put(skb, framesize);
935 skb->protocol = eth_type_trans(skb, jme->dev);
937 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
938 skb->ip_summed = CHECKSUM_UNNECESSARY;
940 skb_checksum_none_assert(skb);
942 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
944 jme->jme_vlan_rx(skb, jme->vlgrp,
945 le16_to_cpu(rxdesc->descwb.vlan));
946 NET_STAT(jme).rx_bytes += 4;
954 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
955 cpu_to_le16(RXWBFLAG_DEST_MUL))
956 ++(NET_STAT(jme).multicast);
958 NET_STAT(jme).rx_bytes += framesize;
959 ++(NET_STAT(jme).rx_packets);
962 jme_set_clean_rxdesc(jme, idx);
967 jme_process_receive(struct jme_adapter *jme, int limit)
969 struct jme_ring *rxring = &(jme->rxring[0]);
970 struct rxdesc *rxdesc = rxring->desc;
971 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
973 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
976 if (unlikely(atomic_read(&jme->link_changing) != 1))
979 if (unlikely(!netif_carrier_ok(jme->dev)))
982 i = atomic_read(&rxring->next_to_clean);
984 rxdesc = rxring->desc;
987 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
988 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
993 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
995 if (unlikely(desccnt > 1 ||
996 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
998 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
999 ++(NET_STAT(jme).rx_crc_errors);
1000 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1001 ++(NET_STAT(jme).rx_fifo_errors);
1003 ++(NET_STAT(jme).rx_errors);
1006 limit -= desccnt - 1;
1008 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1009 jme_set_clean_rxdesc(jme, j);
1010 j = (j + 1) & (mask);
1014 jme_alloc_and_feed_skb(jme, i);
1017 i = (i + desccnt) & (mask);
1021 atomic_set(&rxring->next_to_clean, i);
1024 atomic_inc(&jme->rx_cleaning);
1026 return limit > 0 ? limit : 0;
1031 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1033 if (likely(atmp == dpi->cur)) {
1038 if (dpi->attempt == atmp) {
1041 dpi->attempt = atmp;
1048 jme_dynamic_pcc(struct jme_adapter *jme)
1050 register struct dynpcc_info *dpi = &(jme->dpi);
1052 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1053 jme_attempt_pcc(dpi, PCC_P3);
1054 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1055 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1056 jme_attempt_pcc(dpi, PCC_P2);
1058 jme_attempt_pcc(dpi, PCC_P1);
1060 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1061 if (dpi->attempt < dpi->cur)
1062 tasklet_schedule(&jme->rxclean_task);
1063 jme_set_rx_pcc(jme, dpi->attempt);
1064 dpi->cur = dpi->attempt;
1070 jme_start_pcc_timer(struct jme_adapter *jme)
1072 struct dynpcc_info *dpi = &(jme->dpi);
1073 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1074 dpi->last_pkts = NET_STAT(jme).rx_packets;
1076 jwrite32(jme, JME_TMCSR,
1077 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1081 jme_stop_pcc_timer(struct jme_adapter *jme)
1083 jwrite32(jme, JME_TMCSR, 0);
1087 jme_shutdown_nic(struct jme_adapter *jme)
1091 phylink = jme_linkstat_from_phy(jme);
1093 if (!(phylink & PHY_LINK_UP)) {
1095 * Disable all interrupt before issue timer
1098 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1103 jme_pcc_tasklet(unsigned long arg)
1105 struct jme_adapter *jme = (struct jme_adapter *)arg;
1106 struct net_device *netdev = jme->dev;
1108 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1109 jme_shutdown_nic(jme);
1113 if (unlikely(!netif_carrier_ok(netdev) ||
1114 (atomic_read(&jme->link_changing) != 1)
1116 jme_stop_pcc_timer(jme);
1120 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1121 jme_dynamic_pcc(jme);
1123 jme_start_pcc_timer(jme);
1127 jme_polling_mode(struct jme_adapter *jme)
1129 jme_set_rx_pcc(jme, PCC_OFF);
1133 jme_interrupt_mode(struct jme_adapter *jme)
1135 jme_set_rx_pcc(jme, PCC_P1);
1139 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1142 apmc = jread32(jme, JME_APMC);
1143 return apmc & JME_APMC_PSEUDO_HP_EN;
1147 jme_start_shutdown_timer(struct jme_adapter *jme)
1151 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1152 apmc &= ~JME_APMC_EPIEN_CTRL;
1154 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1157 jwrite32f(jme, JME_APMC, apmc);
1159 jwrite32f(jme, JME_TIMER2, 0);
1160 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1161 jwrite32(jme, JME_TMCSR,
1162 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1166 jme_stop_shutdown_timer(struct jme_adapter *jme)
1170 jwrite32f(jme, JME_TMCSR, 0);
1171 jwrite32f(jme, JME_TIMER2, 0);
1172 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1174 apmc = jread32(jme, JME_APMC);
1175 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1176 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1178 jwrite32f(jme, JME_APMC, apmc);
1182 jme_link_change_tasklet(unsigned long arg)
1184 struct jme_adapter *jme = (struct jme_adapter *)arg;
1185 struct net_device *netdev = jme->dev;
1188 while (!atomic_dec_and_test(&jme->link_changing)) {
1189 atomic_inc(&jme->link_changing);
1190 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1191 while (atomic_read(&jme->link_changing) != 1)
1192 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1195 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1198 jme->old_mtu = netdev->mtu;
1199 netif_stop_queue(netdev);
1200 if (jme_pseudo_hotplug_enabled(jme))
1201 jme_stop_shutdown_timer(jme);
1203 jme_stop_pcc_timer(jme);
1204 tasklet_disable(&jme->txclean_task);
1205 tasklet_disable(&jme->rxclean_task);
1206 tasklet_disable(&jme->rxempty_task);
1208 if (netif_carrier_ok(netdev)) {
1209 jme_reset_ghc_speed(jme);
1210 jme_disable_rx_engine(jme);
1211 jme_disable_tx_engine(jme);
1212 jme_reset_mac_processor(jme);
1213 jme_free_rx_resources(jme);
1214 jme_free_tx_resources(jme);
1216 if (test_bit(JME_FLAG_POLL, &jme->flags))
1217 jme_polling_mode(jme);
1219 netif_carrier_off(netdev);
1222 jme_check_link(netdev, 0);
1223 if (netif_carrier_ok(netdev)) {
1224 rc = jme_setup_rx_resources(jme);
1226 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1227 goto out_enable_tasklet;
1230 rc = jme_setup_tx_resources(jme);
1232 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1233 goto err_out_free_rx_resources;
1236 jme_enable_rx_engine(jme);
1237 jme_enable_tx_engine(jme);
1239 netif_start_queue(netdev);
1241 if (test_bit(JME_FLAG_POLL, &jme->flags))
1242 jme_interrupt_mode(jme);
1244 jme_start_pcc_timer(jme);
1245 } else if (jme_pseudo_hotplug_enabled(jme)) {
1246 jme_start_shutdown_timer(jme);
1249 goto out_enable_tasklet;
1251 err_out_free_rx_resources:
1252 jme_free_rx_resources(jme);
1254 tasklet_enable(&jme->txclean_task);
1255 tasklet_hi_enable(&jme->rxclean_task);
1256 tasklet_hi_enable(&jme->rxempty_task);
1258 atomic_inc(&jme->link_changing);
1262 jme_rx_clean_tasklet(unsigned long arg)
1264 struct jme_adapter *jme = (struct jme_adapter *)arg;
1265 struct dynpcc_info *dpi = &(jme->dpi);
1267 jme_process_receive(jme, jme->rx_ring_size);
1273 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1275 struct jme_adapter *jme = jme_napi_priv(holder);
1278 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1280 while (atomic_read(&jme->rx_empty) > 0) {
1281 atomic_dec(&jme->rx_empty);
1282 ++(NET_STAT(jme).rx_dropped);
1283 jme_restart_rx_engine(jme);
1285 atomic_inc(&jme->rx_empty);
1288 JME_RX_COMPLETE(netdev, holder);
1289 jme_interrupt_mode(jme);
1292 JME_NAPI_WEIGHT_SET(budget, rest);
1293 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1297 jme_rx_empty_tasklet(unsigned long arg)
1299 struct jme_adapter *jme = (struct jme_adapter *)arg;
1301 if (unlikely(atomic_read(&jme->link_changing) != 1))
1304 if (unlikely(!netif_carrier_ok(jme->dev)))
1307 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1309 jme_rx_clean_tasklet(arg);
1311 while (atomic_read(&jme->rx_empty) > 0) {
1312 atomic_dec(&jme->rx_empty);
1313 ++(NET_STAT(jme).rx_dropped);
1314 jme_restart_rx_engine(jme);
1316 atomic_inc(&jme->rx_empty);
1320 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1322 struct jme_ring *txring = &(jme->txring[0]);
1325 if (unlikely(netif_queue_stopped(jme->dev) &&
1326 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1327 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1328 netif_wake_queue(jme->dev);
1334 jme_tx_clean_tasklet(unsigned long arg)
1336 struct jme_adapter *jme = (struct jme_adapter *)arg;
1337 struct jme_ring *txring = &(jme->txring[0]);
1338 struct txdesc *txdesc = txring->desc;
1339 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1340 int i, j, cnt = 0, max, err, mask;
1342 tx_dbg(jme, "Into txclean\n");
1344 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1347 if (unlikely(atomic_read(&jme->link_changing) != 1))
1350 if (unlikely(!netif_carrier_ok(jme->dev)))
1353 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1354 mask = jme->tx_ring_mask;
1356 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1360 if (likely(ctxbi->skb &&
1361 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1363 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1364 i, ctxbi->nr_desc, jiffies);
1366 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1368 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1369 ttxbi = txbi + ((i + j) & (mask));
1370 txdesc[(i + j) & (mask)].dw[0] = 0;
1372 pci_unmap_page(jme->pdev,
1381 dev_kfree_skb(ctxbi->skb);
1383 cnt += ctxbi->nr_desc;
1385 if (unlikely(err)) {
1386 ++(NET_STAT(jme).tx_carrier_errors);
1388 ++(NET_STAT(jme).tx_packets);
1389 NET_STAT(jme).tx_bytes += ctxbi->len;
1394 ctxbi->start_xmit = 0;
1400 i = (i + ctxbi->nr_desc) & mask;
1405 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1406 atomic_set(&txring->next_to_clean, i);
1407 atomic_add(cnt, &txring->nr_free);
1409 jme_wake_queue_if_stopped(jme);
1412 atomic_inc(&jme->tx_cleaning);
1416 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1421 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1423 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1425 * Link change event is critical
1426 * all other events are ignored
1428 jwrite32(jme, JME_IEVE, intrstat);
1429 tasklet_schedule(&jme->linkch_task);
1433 if (intrstat & INTR_TMINTR) {
1434 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1435 tasklet_schedule(&jme->pcc_task);
1438 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1439 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1440 tasklet_schedule(&jme->txclean_task);
1443 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1444 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1450 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1451 if (intrstat & INTR_RX0EMP)
1452 atomic_inc(&jme->rx_empty);
1454 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1455 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1456 jme_polling_mode(jme);
1457 JME_RX_SCHEDULE(jme);
1461 if (intrstat & INTR_RX0EMP) {
1462 atomic_inc(&jme->rx_empty);
1463 tasklet_hi_schedule(&jme->rxempty_task);
1464 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1465 tasklet_hi_schedule(&jme->rxclean_task);
1471 * Re-enable interrupt
1473 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1477 jme_intr(int irq, void *dev_id)
1479 struct net_device *netdev = dev_id;
1480 struct jme_adapter *jme = netdev_priv(netdev);
1483 intrstat = jread32(jme, JME_IEVE);
1486 * Check if it's really an interrupt for us
1488 if (unlikely((intrstat & INTR_ENABLE) == 0))
1492 * Check if the device still exist
1494 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1497 jme_intr_msi(jme, intrstat);
1503 jme_msi(int irq, void *dev_id)
1505 struct net_device *netdev = dev_id;
1506 struct jme_adapter *jme = netdev_priv(netdev);
1509 intrstat = jread32(jme, JME_IEVE);
1511 jme_intr_msi(jme, intrstat);
1517 jme_reset_link(struct jme_adapter *jme)
1519 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1523 jme_restart_an(struct jme_adapter *jme)
1527 spin_lock_bh(&jme->phy_lock);
1528 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1529 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1530 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1531 spin_unlock_bh(&jme->phy_lock);
1535 jme_request_irq(struct jme_adapter *jme)
1538 struct net_device *netdev = jme->dev;
1539 irq_handler_t handler = jme_intr;
1540 int irq_flags = IRQF_SHARED;
1542 if (!pci_enable_msi(jme->pdev)) {
1543 set_bit(JME_FLAG_MSI, &jme->flags);
1548 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1552 "Unable to request %s interrupt (return: %d)\n",
1553 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1556 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1557 pci_disable_msi(jme->pdev);
1558 clear_bit(JME_FLAG_MSI, &jme->flags);
1561 netdev->irq = jme->pdev->irq;
1568 jme_free_irq(struct jme_adapter *jme)
1570 free_irq(jme->pdev->irq, jme->dev);
1571 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1572 pci_disable_msi(jme->pdev);
1573 clear_bit(JME_FLAG_MSI, &jme->flags);
1574 jme->dev->irq = jme->pdev->irq;
1579 jme_phy_on(struct jme_adapter *jme)
1583 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1584 bmcr &= ~BMCR_PDOWN;
1585 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1589 jme_open(struct net_device *netdev)
1591 struct jme_adapter *jme = netdev_priv(netdev);
1595 JME_NAPI_ENABLE(jme);
1597 tasklet_enable(&jme->linkch_task);
1598 tasklet_enable(&jme->txclean_task);
1599 tasklet_hi_enable(&jme->rxclean_task);
1600 tasklet_hi_enable(&jme->rxempty_task);
1602 rc = jme_request_irq(jme);
1608 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1610 jme_set_settings(netdev, &jme->old_ecmd);
1612 jme_reset_phy_processor(jme);
1615 jme_reset_link(jme);
1620 netif_stop_queue(netdev);
1621 netif_carrier_off(netdev);
1627 jme_set_100m_half(struct jme_adapter *jme)
1631 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1632 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1633 BMCR_SPEED1000 | BMCR_FULLDPLX);
1634 tmp |= BMCR_SPEED100;
1637 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1640 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1642 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1645 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1647 jme_wait_link(struct jme_adapter *jme)
1649 u32 phylink, to = JME_WAIT_LINK_TIME;
1652 phylink = jme_linkstat_from_phy(jme);
1653 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1655 phylink = jme_linkstat_from_phy(jme);
1661 jme_phy_off(struct jme_adapter *jme)
1663 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1667 jme_close(struct net_device *netdev)
1669 struct jme_adapter *jme = netdev_priv(netdev);
1671 netif_stop_queue(netdev);
1672 netif_carrier_off(netdev);
1677 JME_NAPI_DISABLE(jme);
1679 tasklet_disable(&jme->linkch_task);
1680 tasklet_disable(&jme->txclean_task);
1681 tasklet_disable(&jme->rxclean_task);
1682 tasklet_disable(&jme->rxempty_task);
1684 jme_reset_ghc_speed(jme);
1685 jme_disable_rx_engine(jme);
1686 jme_disable_tx_engine(jme);
1687 jme_reset_mac_processor(jme);
1688 jme_free_rx_resources(jme);
1689 jme_free_tx_resources(jme);
1697 jme_alloc_txdesc(struct jme_adapter *jme,
1698 struct sk_buff *skb)
1700 struct jme_ring *txring = &(jme->txring[0]);
1701 int idx, nr_alloc, mask = jme->tx_ring_mask;
1703 idx = txring->next_to_use;
1704 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1706 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1709 atomic_sub(nr_alloc, &txring->nr_free);
1711 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1717 jme_fill_tx_map(struct pci_dev *pdev,
1718 struct txdesc *txdesc,
1719 struct jme_buffer_info *txbi,
1727 dmaaddr = pci_map_page(pdev,
1733 pci_dma_sync_single_for_device(pdev,
1740 txdesc->desc2.flags = TXFLAG_OWN;
1741 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1742 txdesc->desc2.datalen = cpu_to_le16(len);
1743 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1744 txdesc->desc2.bufaddrl = cpu_to_le32(
1745 (__u64)dmaaddr & 0xFFFFFFFFUL);
1747 txbi->mapping = dmaaddr;
1752 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1754 struct jme_ring *txring = &(jme->txring[0]);
1755 struct txdesc *txdesc = txring->desc, *ctxdesc;
1756 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1757 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1758 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1759 int mask = jme->tx_ring_mask;
1760 struct skb_frag_struct *frag;
1763 for (i = 0 ; i < nr_frags ; ++i) {
1764 frag = &skb_shinfo(skb)->frags[i];
1765 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1766 ctxbi = txbi + ((idx + i + 2) & (mask));
1768 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1769 frag->page_offset, frag->size, hidma);
1772 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1773 ctxdesc = txdesc + ((idx + 1) & (mask));
1774 ctxbi = txbi + ((idx + 1) & (mask));
1775 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1776 offset_in_page(skb->data), len, hidma);
1781 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1783 if (unlikely(skb_shinfo(skb)->gso_size &&
1784 skb_header_cloned(skb) &&
1785 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1794 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1796 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1798 *flags |= TXFLAG_LSEN;
1800 if (skb->protocol == htons(ETH_P_IP)) {
1801 struct iphdr *iph = ip_hdr(skb);
1804 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1809 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1811 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1824 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1826 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1829 switch (skb->protocol) {
1830 case htons(ETH_P_IP):
1831 ip_proto = ip_hdr(skb)->protocol;
1833 case htons(ETH_P_IPV6):
1834 ip_proto = ipv6_hdr(skb)->nexthdr;
1843 *flags |= TXFLAG_TCPCS;
1846 *flags |= TXFLAG_UDPCS;
1849 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1856 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1858 if (vlan_tx_tag_present(skb)) {
1859 *flags |= TXFLAG_TAGON;
1860 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1865 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1867 struct jme_ring *txring = &(jme->txring[0]);
1868 struct txdesc *txdesc;
1869 struct jme_buffer_info *txbi;
1872 txdesc = (struct txdesc *)txring->desc + idx;
1873 txbi = txring->bufinf + idx;
1879 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1881 * Set OWN bit at final.
1882 * When kernel transmit faster than NIC.
1883 * And NIC trying to send this descriptor before we tell
1884 * it to start sending this TX queue.
1885 * Other fields are already filled correctly.
1888 flags = TXFLAG_OWN | TXFLAG_INT;
1890 * Set checksum flags while not tso
1892 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1893 jme_tx_csum(jme, skb, &flags);
1894 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1895 jme_map_tx_skb(jme, skb, idx);
1896 txdesc->desc1.flags = flags;
1898 * Set tx buffer info after telling NIC to send
1899 * For better tx_clean timing
1902 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1904 txbi->len = skb->len;
1905 txbi->start_xmit = jiffies;
1906 if (!txbi->start_xmit)
1907 txbi->start_xmit = (0UL-1);
1913 jme_stop_queue_if_full(struct jme_adapter *jme)
1915 struct jme_ring *txring = &(jme->txring[0]);
1916 struct jme_buffer_info *txbi = txring->bufinf;
1917 int idx = atomic_read(&txring->next_to_clean);
1922 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1923 netif_stop_queue(jme->dev);
1924 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1926 if (atomic_read(&txring->nr_free)
1927 >= (jme->tx_wake_threshold)) {
1928 netif_wake_queue(jme->dev);
1929 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1933 if (unlikely(txbi->start_xmit &&
1934 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1936 netif_stop_queue(jme->dev);
1937 netif_info(jme, tx_queued, jme->dev,
1938 "TX Queue Stopped %d@%lu\n", idx, jiffies);
1943 * This function is already protected by netif_tx_lock()
1947 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1949 struct jme_adapter *jme = netdev_priv(netdev);
1952 if (unlikely(jme_expand_header(jme, skb))) {
1953 ++(NET_STAT(jme).tx_dropped);
1954 return NETDEV_TX_OK;
1957 idx = jme_alloc_txdesc(jme, skb);
1959 if (unlikely(idx < 0)) {
1960 netif_stop_queue(netdev);
1961 netif_err(jme, tx_err, jme->dev,
1962 "BUG! Tx ring full when queue awake!\n");
1964 return NETDEV_TX_BUSY;
1967 jme_fill_tx_desc(jme, skb, idx);
1969 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1970 TXCS_SELECT_QUEUE0 |
1974 tx_dbg(jme, "xmit: %d+%d@%lu\n",
1975 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
1976 jme_stop_queue_if_full(jme);
1978 return NETDEV_TX_OK;
1982 jme_set_macaddr(struct net_device *netdev, void *p)
1984 struct jme_adapter *jme = netdev_priv(netdev);
1985 struct sockaddr *addr = p;
1988 if (netif_running(netdev))
1991 spin_lock_bh(&jme->macaddr_lock);
1992 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1994 val = (addr->sa_data[3] & 0xff) << 24 |
1995 (addr->sa_data[2] & 0xff) << 16 |
1996 (addr->sa_data[1] & 0xff) << 8 |
1997 (addr->sa_data[0] & 0xff);
1998 jwrite32(jme, JME_RXUMA_LO, val);
1999 val = (addr->sa_data[5] & 0xff) << 8 |
2000 (addr->sa_data[4] & 0xff);
2001 jwrite32(jme, JME_RXUMA_HI, val);
2002 spin_unlock_bh(&jme->macaddr_lock);
2008 jme_set_multi(struct net_device *netdev)
2010 struct jme_adapter *jme = netdev_priv(netdev);
2011 u32 mc_hash[2] = {};
2013 spin_lock_bh(&jme->rxmcs_lock);
2015 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2017 if (netdev->flags & IFF_PROMISC) {
2018 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2019 } else if (netdev->flags & IFF_ALLMULTI) {
2020 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2021 } else if (netdev->flags & IFF_MULTICAST) {
2022 struct netdev_hw_addr *ha;
2025 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2026 netdev_for_each_mc_addr(ha, netdev) {
2027 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2028 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2031 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2032 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2036 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2038 spin_unlock_bh(&jme->rxmcs_lock);
2042 jme_change_mtu(struct net_device *netdev, int new_mtu)
2044 struct jme_adapter *jme = netdev_priv(netdev);
2046 if (new_mtu == jme->old_mtu)
2049 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2050 ((new_mtu) < IPV6_MIN_MTU))
2053 if (new_mtu > 4000) {
2054 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2055 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2056 jme_restart_rx_engine(jme);
2058 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2059 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2060 jme_restart_rx_engine(jme);
2063 if (new_mtu > 1900) {
2064 netdev->features &= ~(NETIF_F_HW_CSUM |
2068 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2069 netdev->features |= NETIF_F_HW_CSUM;
2070 if (test_bit(JME_FLAG_TSO, &jme->flags))
2071 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2074 netdev->mtu = new_mtu;
2075 jme_reset_link(jme);
2081 jme_tx_timeout(struct net_device *netdev)
2083 struct jme_adapter *jme = netdev_priv(netdev);
2086 jme_reset_phy_processor(jme);
2087 if (test_bit(JME_FLAG_SSET, &jme->flags))
2088 jme_set_settings(netdev, &jme->old_ecmd);
2091 * Force to Reset the link again
2093 jme_reset_link(jme);
2096 static inline void jme_pause_rx(struct jme_adapter *jme)
2098 atomic_dec(&jme->link_changing);
2100 jme_set_rx_pcc(jme, PCC_OFF);
2101 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2102 JME_NAPI_DISABLE(jme);
2104 tasklet_disable(&jme->rxclean_task);
2105 tasklet_disable(&jme->rxempty_task);
2109 static inline void jme_resume_rx(struct jme_adapter *jme)
2111 struct dynpcc_info *dpi = &(jme->dpi);
2113 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2114 JME_NAPI_ENABLE(jme);
2116 tasklet_hi_enable(&jme->rxclean_task);
2117 tasklet_hi_enable(&jme->rxempty_task);
2120 dpi->attempt = PCC_P1;
2122 jme_set_rx_pcc(jme, PCC_P1);
2124 atomic_inc(&jme->link_changing);
2128 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2130 struct jme_adapter *jme = netdev_priv(netdev);
2138 jme_get_drvinfo(struct net_device *netdev,
2139 struct ethtool_drvinfo *info)
2141 struct jme_adapter *jme = netdev_priv(netdev);
2143 strcpy(info->driver, DRV_NAME);
2144 strcpy(info->version, DRV_VERSION);
2145 strcpy(info->bus_info, pci_name(jme->pdev));
2149 jme_get_regs_len(struct net_device *netdev)
2155 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2159 for (i = 0 ; i < len ; i += 4)
2160 p[i >> 2] = jread32(jme, reg + i);
2164 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2167 u16 *p16 = (u16 *)p;
2169 for (i = 0 ; i < reg_nr ; ++i)
2170 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2174 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2176 struct jme_adapter *jme = netdev_priv(netdev);
2177 u32 *p32 = (u32 *)p;
2179 memset(p, 0xFF, JME_REG_LEN);
2182 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2185 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2188 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2191 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2194 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2198 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2200 struct jme_adapter *jme = netdev_priv(netdev);
2202 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2203 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2205 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2206 ecmd->use_adaptive_rx_coalesce = false;
2207 ecmd->rx_coalesce_usecs = 0;
2208 ecmd->rx_max_coalesced_frames = 0;
2212 ecmd->use_adaptive_rx_coalesce = true;
2214 switch (jme->dpi.cur) {
2216 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2217 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2220 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2221 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2224 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2225 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2235 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2237 struct jme_adapter *jme = netdev_priv(netdev);
2238 struct dynpcc_info *dpi = &(jme->dpi);
2240 if (netif_running(netdev))
2243 if (ecmd->use_adaptive_rx_coalesce &&
2244 test_bit(JME_FLAG_POLL, &jme->flags)) {
2245 clear_bit(JME_FLAG_POLL, &jme->flags);
2246 jme->jme_rx = netif_rx;
2247 jme->jme_vlan_rx = vlan_hwaccel_rx;
2249 dpi->attempt = PCC_P1;
2251 jme_set_rx_pcc(jme, PCC_P1);
2252 jme_interrupt_mode(jme);
2253 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2254 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2255 set_bit(JME_FLAG_POLL, &jme->flags);
2256 jme->jme_rx = netif_receive_skb;
2257 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2258 jme_interrupt_mode(jme);
2265 jme_get_pauseparam(struct net_device *netdev,
2266 struct ethtool_pauseparam *ecmd)
2268 struct jme_adapter *jme = netdev_priv(netdev);
2271 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2272 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2274 spin_lock_bh(&jme->phy_lock);
2275 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2276 spin_unlock_bh(&jme->phy_lock);
2279 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2283 jme_set_pauseparam(struct net_device *netdev,
2284 struct ethtool_pauseparam *ecmd)
2286 struct jme_adapter *jme = netdev_priv(netdev);
2289 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2290 (ecmd->tx_pause != 0)) {
2293 jme->reg_txpfc |= TXPFC_PF_EN;
2295 jme->reg_txpfc &= ~TXPFC_PF_EN;
2297 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2300 spin_lock_bh(&jme->rxmcs_lock);
2301 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2302 (ecmd->rx_pause != 0)) {
2305 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2307 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2309 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2311 spin_unlock_bh(&jme->rxmcs_lock);
2313 spin_lock_bh(&jme->phy_lock);
2314 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2315 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2316 (ecmd->autoneg != 0)) {
2319 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2321 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2323 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2324 MII_ADVERTISE, val);
2326 spin_unlock_bh(&jme->phy_lock);
2332 jme_get_wol(struct net_device *netdev,
2333 struct ethtool_wolinfo *wol)
2335 struct jme_adapter *jme = netdev_priv(netdev);
2337 wol->supported = WAKE_MAGIC | WAKE_PHY;
2341 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2342 wol->wolopts |= WAKE_PHY;
2344 if (jme->reg_pmcs & PMCS_MFEN)
2345 wol->wolopts |= WAKE_MAGIC;
2350 jme_set_wol(struct net_device *netdev,
2351 struct ethtool_wolinfo *wol)
2353 struct jme_adapter *jme = netdev_priv(netdev);
2355 if (wol->wolopts & (WAKE_MAGICSECURE |
2364 if (wol->wolopts & WAKE_PHY)
2365 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2367 if (wol->wolopts & WAKE_MAGIC)
2368 jme->reg_pmcs |= PMCS_MFEN;
2370 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2376 jme_get_settings(struct net_device *netdev,
2377 struct ethtool_cmd *ecmd)
2379 struct jme_adapter *jme = netdev_priv(netdev);
2382 spin_lock_bh(&jme->phy_lock);
2383 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2384 spin_unlock_bh(&jme->phy_lock);
2389 jme_set_settings(struct net_device *netdev,
2390 struct ethtool_cmd *ecmd)
2392 struct jme_adapter *jme = netdev_priv(netdev);
2395 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2399 * Check If user changed duplex only while force_media.
2400 * Hardware would not generate link change interrupt.
2402 if (jme->mii_if.force_media &&
2403 ecmd->autoneg != AUTONEG_ENABLE &&
2404 (jme->mii_if.full_duplex != ecmd->duplex))
2407 spin_lock_bh(&jme->phy_lock);
2408 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2409 spin_unlock_bh(&jme->phy_lock);
2413 jme_reset_link(jme);
2414 set_bit(JME_FLAG_SSET, &jme->flags);
2415 jme->old_ecmd = *ecmd;
2422 jme_get_link(struct net_device *netdev)
2424 struct jme_adapter *jme = netdev_priv(netdev);
2425 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2429 jme_get_msglevel(struct net_device *netdev)
2431 struct jme_adapter *jme = netdev_priv(netdev);
2432 return jme->msg_enable;
2436 jme_set_msglevel(struct net_device *netdev, u32 value)
2438 struct jme_adapter *jme = netdev_priv(netdev);
2439 jme->msg_enable = value;
2443 jme_get_rx_csum(struct net_device *netdev)
2445 struct jme_adapter *jme = netdev_priv(netdev);
2446 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2450 jme_set_rx_csum(struct net_device *netdev, u32 on)
2452 struct jme_adapter *jme = netdev_priv(netdev);
2454 spin_lock_bh(&jme->rxmcs_lock);
2456 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2458 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2459 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2460 spin_unlock_bh(&jme->rxmcs_lock);
2466 jme_set_tx_csum(struct net_device *netdev, u32 on)
2468 struct jme_adapter *jme = netdev_priv(netdev);
2471 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2472 if (netdev->mtu <= 1900)
2473 netdev->features |= NETIF_F_HW_CSUM;
2475 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2476 netdev->features &= ~NETIF_F_HW_CSUM;
2483 jme_set_tso(struct net_device *netdev, u32 on)
2485 struct jme_adapter *jme = netdev_priv(netdev);
2488 set_bit(JME_FLAG_TSO, &jme->flags);
2489 if (netdev->mtu <= 1900)
2490 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2492 clear_bit(JME_FLAG_TSO, &jme->flags);
2493 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2500 jme_nway_reset(struct net_device *netdev)
2502 struct jme_adapter *jme = netdev_priv(netdev);
2503 jme_restart_an(jme);
2508 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2513 val = jread32(jme, JME_SMBCSR);
2514 to = JME_SMB_BUSY_TIMEOUT;
2515 while ((val & SMBCSR_BUSY) && --to) {
2517 val = jread32(jme, JME_SMBCSR);
2520 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2524 jwrite32(jme, JME_SMBINTF,
2525 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2526 SMBINTF_HWRWN_READ |
2529 val = jread32(jme, JME_SMBINTF);
2530 to = JME_SMB_BUSY_TIMEOUT;
2531 while ((val & SMBINTF_HWCMD) && --to) {
2533 val = jread32(jme, JME_SMBINTF);
2536 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2540 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2544 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2549 val = jread32(jme, JME_SMBCSR);
2550 to = JME_SMB_BUSY_TIMEOUT;
2551 while ((val & SMBCSR_BUSY) && --to) {
2553 val = jread32(jme, JME_SMBCSR);
2556 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2560 jwrite32(jme, JME_SMBINTF,
2561 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2562 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2563 SMBINTF_HWRWN_WRITE |
2566 val = jread32(jme, JME_SMBINTF);
2567 to = JME_SMB_BUSY_TIMEOUT;
2568 while ((val & SMBINTF_HWCMD) && --to) {
2570 val = jread32(jme, JME_SMBINTF);
2573 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2581 jme_get_eeprom_len(struct net_device *netdev)
2583 struct jme_adapter *jme = netdev_priv(netdev);
2585 val = jread32(jme, JME_SMBCSR);
2586 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2590 jme_get_eeprom(struct net_device *netdev,
2591 struct ethtool_eeprom *eeprom, u8 *data)
2593 struct jme_adapter *jme = netdev_priv(netdev);
2594 int i, offset = eeprom->offset, len = eeprom->len;
2597 * ethtool will check the boundary for us
2599 eeprom->magic = JME_EEPROM_MAGIC;
2600 for (i = 0 ; i < len ; ++i)
2601 data[i] = jme_smb_read(jme, i + offset);
2607 jme_set_eeprom(struct net_device *netdev,
2608 struct ethtool_eeprom *eeprom, u8 *data)
2610 struct jme_adapter *jme = netdev_priv(netdev);
2611 int i, offset = eeprom->offset, len = eeprom->len;
2613 if (eeprom->magic != JME_EEPROM_MAGIC)
2617 * ethtool will check the boundary for us
2619 for (i = 0 ; i < len ; ++i)
2620 jme_smb_write(jme, i + offset, data[i]);
2625 static const struct ethtool_ops jme_ethtool_ops = {
2626 .get_drvinfo = jme_get_drvinfo,
2627 .get_regs_len = jme_get_regs_len,
2628 .get_regs = jme_get_regs,
2629 .get_coalesce = jme_get_coalesce,
2630 .set_coalesce = jme_set_coalesce,
2631 .get_pauseparam = jme_get_pauseparam,
2632 .set_pauseparam = jme_set_pauseparam,
2633 .get_wol = jme_get_wol,
2634 .set_wol = jme_set_wol,
2635 .get_settings = jme_get_settings,
2636 .set_settings = jme_set_settings,
2637 .get_link = jme_get_link,
2638 .get_msglevel = jme_get_msglevel,
2639 .set_msglevel = jme_set_msglevel,
2640 .get_rx_csum = jme_get_rx_csum,
2641 .set_rx_csum = jme_set_rx_csum,
2642 .set_tx_csum = jme_set_tx_csum,
2643 .set_tso = jme_set_tso,
2644 .set_sg = ethtool_op_set_sg,
2645 .nway_reset = jme_nway_reset,
2646 .get_eeprom_len = jme_get_eeprom_len,
2647 .get_eeprom = jme_get_eeprom,
2648 .set_eeprom = jme_set_eeprom,
2652 jme_pci_dma64(struct pci_dev *pdev)
2654 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2655 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2656 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2659 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2660 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2661 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2664 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2665 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2672 jme_phy_init(struct jme_adapter *jme)
2676 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2677 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2681 jme_check_hw_ver(struct jme_adapter *jme)
2685 chipmode = jread32(jme, JME_CHIPMODE);
2687 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2688 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2691 static const struct net_device_ops jme_netdev_ops = {
2692 .ndo_open = jme_open,
2693 .ndo_stop = jme_close,
2694 .ndo_validate_addr = eth_validate_addr,
2695 .ndo_start_xmit = jme_start_xmit,
2696 .ndo_set_mac_address = jme_set_macaddr,
2697 .ndo_set_multicast_list = jme_set_multi,
2698 .ndo_change_mtu = jme_change_mtu,
2699 .ndo_tx_timeout = jme_tx_timeout,
2700 .ndo_vlan_rx_register = jme_vlan_rx_register,
2703 static int __devinit
2704 jme_init_one(struct pci_dev *pdev,
2705 const struct pci_device_id *ent)
2707 int rc = 0, using_dac, i;
2708 struct net_device *netdev;
2709 struct jme_adapter *jme;
2714 * set up PCI device basics
2716 rc = pci_enable_device(pdev);
2718 pr_err("Cannot enable PCI device\n");
2722 using_dac = jme_pci_dma64(pdev);
2723 if (using_dac < 0) {
2724 pr_err("Cannot set PCI DMA Mask\n");
2726 goto err_out_disable_pdev;
2729 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2730 pr_err("No PCI resource region found\n");
2732 goto err_out_disable_pdev;
2735 rc = pci_request_regions(pdev, DRV_NAME);
2737 pr_err("Cannot obtain PCI resource region\n");
2738 goto err_out_disable_pdev;
2741 pci_set_master(pdev);
2744 * alloc and init net device
2746 netdev = alloc_etherdev(sizeof(*jme));
2748 pr_err("Cannot allocate netdev structure\n");
2750 goto err_out_release_regions;
2752 netdev->netdev_ops = &jme_netdev_ops;
2753 netdev->ethtool_ops = &jme_ethtool_ops;
2754 netdev->watchdog_timeo = TX_TIMEOUT;
2755 netdev->features = NETIF_F_HW_CSUM |
2759 NETIF_F_HW_VLAN_TX |
2762 netdev->features |= NETIF_F_HIGHDMA;
2764 SET_NETDEV_DEV(netdev, &pdev->dev);
2765 pci_set_drvdata(pdev, netdev);
2770 jme = netdev_priv(netdev);
2773 jme->jme_rx = netif_rx;
2774 jme->jme_vlan_rx = vlan_hwaccel_rx;
2775 jme->old_mtu = netdev->mtu = 1500;
2777 jme->tx_ring_size = 1 << 10;
2778 jme->tx_ring_mask = jme->tx_ring_size - 1;
2779 jme->tx_wake_threshold = 1 << 9;
2780 jme->rx_ring_size = 1 << 9;
2781 jme->rx_ring_mask = jme->rx_ring_size - 1;
2782 jme->msg_enable = JME_DEF_MSG_ENABLE;
2783 jme->regs = ioremap(pci_resource_start(pdev, 0),
2784 pci_resource_len(pdev, 0));
2786 pr_err("Mapping PCI resource region error\n");
2788 goto err_out_free_netdev;
2792 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2793 jwrite32(jme, JME_APMC, apmc);
2794 } else if (force_pseudohp) {
2795 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2796 jwrite32(jme, JME_APMC, apmc);
2799 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2801 spin_lock_init(&jme->phy_lock);
2802 spin_lock_init(&jme->macaddr_lock);
2803 spin_lock_init(&jme->rxmcs_lock);
2805 atomic_set(&jme->link_changing, 1);
2806 atomic_set(&jme->rx_cleaning, 1);
2807 atomic_set(&jme->tx_cleaning, 1);
2808 atomic_set(&jme->rx_empty, 1);
2810 tasklet_init(&jme->pcc_task,
2812 (unsigned long) jme);
2813 tasklet_init(&jme->linkch_task,
2814 jme_link_change_tasklet,
2815 (unsigned long) jme);
2816 tasklet_init(&jme->txclean_task,
2817 jme_tx_clean_tasklet,
2818 (unsigned long) jme);
2819 tasklet_init(&jme->rxclean_task,
2820 jme_rx_clean_tasklet,
2821 (unsigned long) jme);
2822 tasklet_init(&jme->rxempty_task,
2823 jme_rx_empty_tasklet,
2824 (unsigned long) jme);
2825 tasklet_disable_nosync(&jme->linkch_task);
2826 tasklet_disable_nosync(&jme->txclean_task);
2827 tasklet_disable_nosync(&jme->rxclean_task);
2828 tasklet_disable_nosync(&jme->rxempty_task);
2829 jme->dpi.cur = PCC_P1;
2832 jme->reg_rxcs = RXCS_DEFAULT;
2833 jme->reg_rxmcs = RXMCS_DEFAULT;
2835 jme->reg_pmcs = PMCS_MFEN;
2836 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2837 set_bit(JME_FLAG_TSO, &jme->flags);
2840 * Get Max Read Req Size from PCI Config Space
2842 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2843 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2844 switch (jme->mrrs) {
2846 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2849 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2852 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2857 * Must check before reset_mac_processor
2859 jme_check_hw_ver(jme);
2860 jme->mii_if.dev = netdev;
2862 jme->mii_if.phy_id = 0;
2863 for (i = 1 ; i < 32 ; ++i) {
2864 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2865 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2866 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2867 jme->mii_if.phy_id = i;
2872 if (!jme->mii_if.phy_id) {
2874 pr_err("Can not find phy_id\n");
2878 jme->reg_ghc |= GHC_LINK_POLL;
2880 jme->mii_if.phy_id = 1;
2882 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2883 jme->mii_if.supports_gmii = true;
2885 jme->mii_if.supports_gmii = false;
2886 jme->mii_if.mdio_read = jme_mdio_read;
2887 jme->mii_if.mdio_write = jme_mdio_write;
2890 jme_set_phyfifoa(jme);
2891 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2897 * Reset MAC processor and reload EEPROM for MAC Address
2899 jme_reset_mac_processor(jme);
2900 rc = jme_reload_eeprom(jme);
2902 pr_err("Reload eeprom for reading MAC Address error\n");
2905 jme_load_macaddr(netdev);
2908 * Tell stack that we are not ready to work until open()
2910 netif_carrier_off(netdev);
2911 netif_stop_queue(netdev);
2916 rc = register_netdev(netdev);
2918 pr_err("Cannot register net device\n");
2922 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2923 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2924 "JMC250 Gigabit Ethernet" :
2925 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2926 "JMC260 Fast Ethernet" : "Unknown",
2927 (jme->fpgaver != 0) ? " (FPGA)" : "",
2928 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2929 jme->rev, netdev->dev_addr);
2935 err_out_free_netdev:
2936 pci_set_drvdata(pdev, NULL);
2937 free_netdev(netdev);
2938 err_out_release_regions:
2939 pci_release_regions(pdev);
2940 err_out_disable_pdev:
2941 pci_disable_device(pdev);
2946 static void __devexit
2947 jme_remove_one(struct pci_dev *pdev)
2949 struct net_device *netdev = pci_get_drvdata(pdev);
2950 struct jme_adapter *jme = netdev_priv(netdev);
2952 unregister_netdev(netdev);
2954 pci_set_drvdata(pdev, NULL);
2955 free_netdev(netdev);
2956 pci_release_regions(pdev);
2957 pci_disable_device(pdev);
2963 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2965 struct net_device *netdev = pci_get_drvdata(pdev);
2966 struct jme_adapter *jme = netdev_priv(netdev);
2968 atomic_dec(&jme->link_changing);
2970 netif_device_detach(netdev);
2971 netif_stop_queue(netdev);
2974 tasklet_disable(&jme->txclean_task);
2975 tasklet_disable(&jme->rxclean_task);
2976 tasklet_disable(&jme->rxempty_task);
2978 if (netif_carrier_ok(netdev)) {
2979 if (test_bit(JME_FLAG_POLL, &jme->flags))
2980 jme_polling_mode(jme);
2982 jme_stop_pcc_timer(jme);
2983 jme_reset_ghc_speed(jme);
2984 jme_disable_rx_engine(jme);
2985 jme_disable_tx_engine(jme);
2986 jme_reset_mac_processor(jme);
2987 jme_free_rx_resources(jme);
2988 jme_free_tx_resources(jme);
2989 netif_carrier_off(netdev);
2993 tasklet_enable(&jme->txclean_task);
2994 tasklet_hi_enable(&jme->rxclean_task);
2995 tasklet_hi_enable(&jme->rxempty_task);
2997 pci_save_state(pdev);
2998 if (jme->reg_pmcs) {
2999 jme_set_100m_half(jme);
3001 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3004 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3006 pci_enable_wake(pdev, PCI_D3cold, true);
3010 pci_set_power_state(pdev, PCI_D3cold);
3016 jme_resume(struct pci_dev *pdev)
3018 struct net_device *netdev = pci_get_drvdata(pdev);
3019 struct jme_adapter *jme = netdev_priv(netdev);
3022 pci_restore_state(pdev);
3024 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3026 jme_set_settings(netdev, &jme->old_ecmd);
3028 jme_reset_phy_processor(jme);
3032 netif_device_attach(netdev);
3034 atomic_inc(&jme->link_changing);
3036 jme_reset_link(jme);
3042 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3043 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3044 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3048 static struct pci_driver jme_driver = {
3050 .id_table = jme_pci_tbl,
3051 .probe = jme_init_one,
3052 .remove = __devexit_p(jme_remove_one),
3054 .suspend = jme_suspend,
3055 .resume = jme_resume,
3056 #endif /* CONFIG_PM */
3060 jme_init_module(void)
3062 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3063 return pci_register_driver(&jme_driver);
3067 jme_cleanup_module(void)
3069 pci_unregister_driver(&jme_driver);
3072 module_init(jme_init_module);
3073 module_exit(jme_cleanup_module);
3075 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3076 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3077 MODULE_LICENSE("GPL");
3078 MODULE_VERSION(DRV_VERSION);
3079 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);