include/asm-ia64/processor.h

   1 #ifndef _ASM_IA64_PROCESSOR_H
   2 #define _ASM_IA64_PROCESSOR_H
   3
   4 /*
   5  * Copyright (C) 1998-2004 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *      Stephane Eranian <eranian@hpl.hp.com>
   8  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   9  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  10  *
  11  * 11/24/98     S.Eranian       added ia64_set_iva()
  12  * 12/03/99     D. Mosberger    implement thread_saved_pc() via kernel unwind API
  13  * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 support
  14  */
  15
  16 #include <linux/config.h>
  17
  18 #include <asm/intrinsics.h>
  19 #include <asm/kregs.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/ustack.h>
  22
  23 /* Our arch specific arch_init_sched_domain is in arch/ia64/kernel/domain.c */
  24 #define ARCH_HAS_SCHED_DOMAIN
  25
  26 #define IA64_NUM_DBG_REGS       8
  27 /*
  28  * Limits for PMC and PMD are set to less than maximum architected values
  29  * but should be sufficient for a while
  30  */
  31 #define IA64_NUM_PMC_REGS       32
  32 #define IA64_NUM_PMD_REGS       32
  33
  34 #define DEFAULT_MAP_BASE        __IA64_UL_CONST(0x2000000000000000)
  35 #define DEFAULT_TASK_SIZE       __IA64_UL_CONST(0xa000000000000000)
  36
  37 /*
  38  * TASK_SIZE really is a mis-named.  It really is the maximum user
  39  * space address (plus one).  On IA-64, there are five regions of 2TB
  40  * each (assuming 8KB page size), for a total of 8TB of user virtual
  41  * address space.
  42  */
  43 #define TASK_SIZE               (current->thread.task_size)
  44
  45 /*
  46  * This decides where the kernel will search for a free chunk of vm
  47  * space during mmap's.
  48  */
  49 #define TASK_UNMAPPED_BASE      (current->thread.map_base)
  50
  51 #define IA64_THREAD_FPH_VALID   (__IA64_UL(1) << 0)     /* floating-point high state valid? */
  52 #define IA64_THREAD_DBG_VALID   (__IA64_UL(1) << 1)     /* debug registers valid? */
  53 #define IA64_THREAD_PM_VALID    (__IA64_UL(1) << 2)     /* performance registers valid? */
  54 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3)     /* don't log unaligned accesses */
  55 #define IA64_THREAD_UAC_SIGBUS  (__IA64_UL(1) << 4)     /* generate SIGBUS on unaligned acc. */
  56                                                         /* bit 5 is currently unused */
  57 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)   /* don't log any fpswa faults */
  58 #define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)   /* send a SIGFPE for fpswa faults */
  59
  60 #define IA64_THREAD_UAC_SHIFT   3
  61 #define IA64_THREAD_UAC_MASK    (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
  62 #define IA64_THREAD_FPEMU_SHIFT 6
  63 #define IA64_THREAD_FPEMU_MASK  (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
  64
  65
  66 /*
  67  * This shift should be large enough to be able to represent 1000000000/itc_freq with good
  68  * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
  69  * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
  70  */
  71 #define IA64_NSEC_PER_CYC_SHIFT 30
  72
  73 #ifndef __ASSEMBLY__
  74
  75 #include <linux/cache.h>
  76 #include <linux/compiler.h>
  77 #include <linux/threads.h>
  78 #include <linux/types.h>
  79
  80 #include <asm/fpu.h>
  81 #include <asm/page.h>
  82 #include <asm/percpu.h>
  83 #include <asm/rse.h>
  84 #include <asm/unwind.h>
  85 #include <asm/atomic.h>
  86 #ifdef CONFIG_NUMA
  87 #include <asm/nodedata.h>
  88 #endif
  89
  90 /* like above but expressed as bitfields for more efficient access: */
  91 struct ia64_psr {
  92         __u64 reserved0 : 1;
  93         __u64 be : 1;
  94         __u64 up : 1;
  95         __u64 ac : 1;
  96         __u64 mfl : 1;
  97         __u64 mfh : 1;
  98         __u64 reserved1 : 7;
  99         __u64 ic : 1;
 100         __u64 i : 1;
 101         __u64 pk : 1;
 102         __u64 reserved2 : 1;
 103         __u64 dt : 1;
 104         __u64 dfl : 1;
 105         __u64 dfh : 1;
 106         __u64 sp : 1;
 107         __u64 pp : 1;
 108         __u64 di : 1;
 109         __u64 si : 1;
 110         __u64 db : 1;
 111         __u64 lp : 1;
 112         __u64 tb : 1;
 113         __u64 rt : 1;
 114         __u64 reserved3 : 4;
 115         __u64 cpl : 2;
 116         __u64 is : 1;
 117         __u64 mc : 1;
 118         __u64 it : 1;
 119         __u64 id : 1;
 120         __u64 da : 1;
 121         __u64 dd : 1;
 122         __u64 ss : 1;
 123         __u64 ri : 2;
 124         __u64 ed : 1;
 125         __u64 bn : 1;
 126         __u64 reserved4 : 19;
 127 };
 128
 129 /*
 130  * CPU type, hardware bug flags, and per-CPU state.  Frequently used
 131  * state comes earlier:
 132  */
 133 struct cpuinfo_ia64 {
 134         __u32 softirq_pending;
 135         __u64 itm_delta;        /* # of clock cycles between clock ticks */
 136         __u64 itm_next;         /* interval timer mask value to use for next clock tick */
 137         __u64 nsec_per_cyc;     /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
 138         __u64 unimpl_va_mask;   /* mask of unimplemented virtual address bits (from PAL) */
 139         __u64 unimpl_pa_mask;   /* mask of unimplemented physical address bits (from PAL) */
 140         __u64 itc_freq;         /* frequency of ITC counter */
 141         __u64 proc_freq;        /* frequency of processor */
 142         __u64 cyc_per_usec;     /* itc_freq/1000000 */
 143         __u64 ptce_base;
 144         __u32 ptce_count[2];
 145         __u32 ptce_stride[2];
 146         struct task_struct *ksoftirqd;  /* kernel softirq daemon for this CPU */
 147
 148 #ifdef CONFIG_SMP
 149         __u64 loops_per_jiffy;
 150         int cpu;
 151 #endif
 152
 153         /* CPUID-derived information: */
 154         __u64 ppn;
 155         __u64 features;
 156         __u8 number;
 157         __u8 revision;
 158         __u8 model;
 159         __u8 family;
 160         __u8 archrev;
 161         char vendor[16];
 162
 163 #ifdef CONFIG_NUMA
 164         struct ia64_node_data *node_data;
 165 #endif
 166 };
 167
 168 DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
 169
 170 /*
 171  * The "local" data variable.  It refers to the per-CPU data of the currently executing
 172  * CPU, much like "current" points to the per-task data of the currently executing task.
 173  * Do not use the address of local_cpu_data, since it will be different from
 174  * cpu_data(smp_processor_id())!
 175  */
 176 #define local_cpu_data          (&__ia64_per_cpu_var(cpu_info))
 177 #define cpu_data(cpu)           (&per_cpu(cpu_info, cpu))
 178
 179 extern void identify_cpu (struct cpuinfo_ia64 *);
 180 extern void print_cpu_info (struct cpuinfo_ia64 *);
 181
 182 typedef struct {
 183         unsigned long seg;
 184 } mm_segment_t;
 185
 186 #define SET_UNALIGN_CTL(task,value)                                                             \
 187 ({                                                                                              \
 188         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)                  \
 189                                 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
 190         0;                                                                                      \
 191 })
 192 #define GET_UNALIGN_CTL(task,addr)                                                              \
 193 ({                                                                                              \
 194         put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,        \
 195                  (int __user *) (addr));                                                        \
 196 })
 197
 198 #define SET_FPEMU_CTL(task,value)                                                               \
 199 ({                                                                                              \
 200         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)                \
 201                           | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));   \
 202         0;                                                                                      \
 203 })
 204 #define GET_FPEMU_CTL(task,addr)                                                                \
 205 ({                                                                                              \
 206         put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,    \
 207                  (int __user *) (addr));                                                        \
 208 })
 209
 210 #ifdef CONFIG_IA32_SUPPORT
 211 struct desc_struct {
 212         unsigned int a, b;
 213 };
 214
 215 #define desc_empty(desc)                (!((desc)->a + (desc)->b))
 216 #define desc_equal(desc1, desc2)        (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
 217
 218 #define GDT_ENTRY_TLS_ENTRIES   3
 219 #define GDT_ENTRY_TLS_MIN       6
 220 #define GDT_ENTRY_TLS_MAX       (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
 221
 222 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
 223
 224 struct partial_page_list;
 225 #endif
 226
 227 struct thread_struct {
 228         __u32 flags;                    /* various thread flags (see IA64_THREAD_*) */
 229         /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
 230         __u8 on_ustack;                 /* executing on user-stacks? */
 231         __u8 pad[3];
 232         __u64 ksp;                      /* kernel stack pointer */
 233         __u64 map_base;                 /* base address for get_unmapped_area() */
 234         __u64 task_size;                /* limit for task size */
 235         __u64 rbs_bot;                  /* the base address for the RBS */
 236         int last_fph_cpu;               /* CPU that may hold the contents of f32-f127 */
 237
 238 #ifdef CONFIG_IA32_SUPPORT
 239         __u64 eflag;                    /* IA32 EFLAGS reg */
 240         __u64 fsr;                      /* IA32 floating pt status reg */
 241         __u64 fcr;                      /* IA32 floating pt control reg */
 242         __u64 fir;                      /* IA32 fp except. instr. reg */
 243         __u64 fdr;                      /* IA32 fp except. data reg */
 244         __u64 old_k1;                   /* old value of ar.k1 */
 245         __u64 old_iob;                  /* old IOBase value */
 246         struct partial_page_list *ppl;  /* partial page list for 4K page size issue */
 247         /* cached TLS descriptors. */
 248         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 249
 250 # define INIT_THREAD_IA32       .eflag =        0,                      \
 251                                 .fsr =          0,                      \
 252                                 .fcr =          0x17800000037fULL,      \
 253                                 .fir =          0,                      \
 254                                 .fdr =          0,                      \
 255                                 .old_k1 =       0,                      \
 256                                 .old_iob =      0,                      \
 257                                 .ppl =          NULL,
 258 #else
 259 # define INIT_THREAD_IA32
 260 #endif /* CONFIG_IA32_SUPPORT */
 261 #ifdef CONFIG_PERFMON
 262         __u64 pmcs[IA64_NUM_PMC_REGS];
 263         __u64 pmds[IA64_NUM_PMD_REGS];
 264         void *pfm_context;                   /* pointer to detailed PMU context */
 265         unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
 266 # define INIT_THREAD_PM         .pmcs =                 {0UL, },  \
 267                                 .pmds =                 {0UL, },  \
 268                                 .pfm_context =          NULL,     \
 269                                 .pfm_needs_checking =   0UL,
 270 #else
 271 # define INIT_THREAD_PM
 272 #endif
 273         __u64 dbr[IA64_NUM_DBG_REGS];
 274         __u64 ibr[IA64_NUM_DBG_REGS];
 275         struct ia64_fpreg fph[96];      /* saved/loaded on demand */
 276 };
 277
 278 #define INIT_THREAD {                                           \
 279         .flags =        0,                                      \
 280         .on_ustack =    0,                                      \
 281         .ksp =          0,                                      \
 282         .map_base =     DEFAULT_MAP_BASE,                       \
 283         .rbs_bot =      STACK_TOP - DEFAULT_USER_STACK_SIZE,    \
 284         .task_size =    DEFAULT_TASK_SIZE,                      \
 285         .last_fph_cpu =  -1,                                    \
 286         INIT_THREAD_IA32                                        \
 287         INIT_THREAD_PM                                          \
 288         .dbr =          {0, },                                  \
 289         .ibr =          {0, },                                  \
 290         .fph =          {{{{0}}}, }                             \
 291 }
 292
 293 #define start_thread(regs,new_ip,new_sp) do {                                                   \
 294         set_fs(USER_DS);                                                                        \
 295         regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))                \
 296                          & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));              \
 297         regs->cr_iip = new_ip;                                                                  \
 298         regs->ar_rsc = 0xf;             /* eager mode, privilege level 3 */                     \
 299         regs->ar_rnat = 0;                                                                      \
 300         regs->ar_bspstore = current->thread.rbs_bot;                                            \
 301         regs->ar_fpsr = FPSR_DEFAULT;                                                           \
 302         regs->loadrs = 0;                                                                       \
 303         regs->r8 = current->mm->dumpable;       /* set "don't zap registers" flag */            \
 304         regs->r12 = new_sp - 16;        /* allocate 16 byte scratch area */                     \
 305         if (unlikely(!current->mm->dumpable)) {                                                 \
 306                 /*                                                                              \
 307                  * Zap scratch regs to avoid leaking bits between processes with different      \
 308                  * uid/privileges.                                                              \
 309                  */                                                                             \
 310                 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;                                   \
 311                 regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;       \
 312         }                                                                                       \
 313 } while (0)
 314
 315 /* Forward declarations, a strange C thing... */
 316 struct mm_struct;
 317 struct task_struct;
 318
 319 /*
 320  * Free all resources held by a thread. This is called after the
 321  * parent of DEAD_TASK has collected the exit status of the task via
 322  * wait().
 323  */
 324 #define release_thread(dead_task)
 325
 326 /* Prepare to copy thread state - unlazy all lazy status */
 327 #define prepare_to_copy(tsk)    do { } while (0)
 328
 329 /*
 330  * This is the mechanism for creating a new kernel thread.
 331  *
 332  * NOTE 1: Only a kernel-only process (ie the swapper or direct
 333  * descendants who haven't done an "execve()") should use this: it
 334  * will work within a system call from a "real" process, but the
 335  * process memory space will not be free'd until both the parent and
 336  * the child have exited.
 337  *
 338  * NOTE 2: This MUST NOT be an inlined function.  Otherwise, we get
 339  * into trouble in init/main.c when the child thread returns to
 340  * do_basic_setup() and the timing is such that free_initmem() has
 341  * been called already.
 342  */
 343 extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
 344
 345 /* Get wait channel for task P.  */
 346 extern unsigned long get_wchan (struct task_struct *p);
 347
 348 /* Return instruction pointer of blocked task TSK.  */
 349 #define KSTK_EIP(tsk)                                   \
 350   ({                                                    \
 351         struct pt_regs *_regs = ia64_task_regs(tsk);    \
 352         _regs->cr_iip + ia64_psr(_regs)->ri;            \
 353   })
 354
 355 /* Return stack pointer of blocked task TSK.  */
 356 #define KSTK_ESP(tsk)  ((tsk)->thread.ksp)
 357
 358 extern void ia64_getreg_unknown_kr (void);
 359 extern void ia64_setreg_unknown_kr (void);
 360
 361 #define ia64_get_kr(regnum)                                     \
 362 ({                                                              \
 363         unsigned long r = 0;                                    \
 364                                                                 \
 365         switch (regnum) {                                       \
 366             case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;   \
 367             case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;   \
 368             case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;   \
 369             case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;   \
 370             case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;   \
 371             case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;   \
 372             case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;   \
 373             case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;   \
 374             default: ia64_getreg_unknown_kr(); break;           \
 375         }                                                       \
 376         r;                                                      \
 377 })
 378
 379 #define ia64_set_kr(regnum, r)                                  \
 380 ({                                                              \
 381         switch (regnum) {                                       \
 382             case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;    \
 383             case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;    \
 384             case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;    \
 385             case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;    \
 386             case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;    \
 387             case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;    \
 388             case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;    \
 389             case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;    \
 390             default: ia64_setreg_unknown_kr(); break;           \
 391         }                                                       \
 392 })
 393
 394 /*
 395  * The following three macros can't be inline functions because we don't have struct
 396  * task_struct at this point.
 397  */
 398
 399 /* Return TRUE if task T owns the fph partition of the CPU we're running on. */
 400 #define ia64_is_local_fpu_owner(t)                                                              \
 401 ({                                                                                              \
 402         struct task_struct *__ia64_islfo_task = (t);                                            \
 403         (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()                           \
 404          && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));        \
 405 })
 406
 407 /* Mark task T as owning the fph partition of the CPU we're running on. */
 408 #define ia64_set_local_fpu_owner(t) do {                                                \
 409         struct task_struct *__ia64_slfo_task = (t);                                     \
 410         __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();                     \
 411         ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);               \
 412 } while (0)
 413
 414 /* Mark the fph partition of task T as being invalid on all CPUs.  */
 415 #define ia64_drop_fpu(t)        ((t)->thread.last_fph_cpu = -1)
 416
 417 extern void __ia64_init_fpu (void);
 418 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
 419 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
 420 extern void ia64_save_debug_regs (unsigned long *save_area);
 421 extern void ia64_load_debug_regs (unsigned long *save_area);
 422
 423 #ifdef CONFIG_IA32_SUPPORT
 424 extern void ia32_save_state (struct task_struct *task);
 425 extern void ia32_load_state (struct task_struct *task);
 426 #endif
 427
 428 #define ia64_fph_enable()       do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 429 #define ia64_fph_disable()      do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 430
 431 /* load fp 0.0 into fph */
 432 static inline void
 433 ia64_init_fpu (void) {
 434         ia64_fph_enable();
 435         __ia64_init_fpu();
 436         ia64_fph_disable();
 437 }
 438
 439 /* save f32-f127 at FPH */
 440 static inline void
 441 ia64_save_fpu (struct ia64_fpreg *fph) {
 442         ia64_fph_enable();
 443         __ia64_save_fpu(fph);
 444         ia64_fph_disable();
 445 }
 446
 447 /* load f32-f127 from FPH */
 448 static inline void
 449 ia64_load_fpu (struct ia64_fpreg *fph) {
 450         ia64_fph_enable();
 451         __ia64_load_fpu(fph);
 452         ia64_fph_disable();
 453 }
 454
 455 static inline __u64
 456 ia64_clear_ic (void)
 457 {
 458         __u64 psr;
 459         psr = ia64_getreg(_IA64_REG_PSR);
 460         ia64_stop();
 461         ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
 462         ia64_srlz_i();
 463         return psr;
 464 }
 465
 466 /*
 467  * Restore the psr.
 468  */
 469 static inline void
 470 ia64_set_psr (__u64 psr)
 471 {
 472         ia64_stop();
 473         ia64_setreg(_IA64_REG_PSR_L, psr);
 474         ia64_srlz_d();
 475 }
 476
 477 /*
 478  * Insert a translation into an instruction and/or data translation
 479  * register.
 480  */
 481 static inline void
 482 ia64_itr (__u64 target_mask, __u64 tr_num,
 483           __u64 vmaddr, __u64 pte,
 484           __u64 log_page_size)
 485 {
 486         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 487         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 488         ia64_stop();
 489         if (target_mask & 0x1)
 490                 ia64_itri(tr_num, pte);
 491         if (target_mask & 0x2)
 492                 ia64_itrd(tr_num, pte);
 493 }
 494
 495 /*
 496  * Insert a translation into the instruction and/or data translation
 497  * cache.
 498  */
 499 static inline void
 500 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
 501           __u64 log_page_size)
 502 {
 503         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 504         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 505         ia64_stop();
 506         /* as per EAS2.6, itc must be the last instruction in an instruction group */
 507         if (target_mask & 0x1)
 508                 ia64_itci(pte);
 509         if (target_mask & 0x2)
 510                 ia64_itcd(pte);
 511 }
 512
 513 /*
 514  * Purge a range of addresses from instruction and/or data translation
 515  * register(s).
 516  */
 517 static inline void
 518 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
 519 {
 520         if (target_mask & 0x1)
 521                 ia64_ptri(vmaddr, (log_size << 2));
 522         if (target_mask & 0x2)
 523                 ia64_ptrd(vmaddr, (log_size << 2));
 524 }
 525
 526 /* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
 527 static inline void
 528 ia64_set_iva (void *ivt_addr)
 529 {
 530         ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
 531         ia64_srlz_i();
 532 }
 533
 534 /* Set the page table address and control bits.  */
 535 static inline void
 536 ia64_set_pta (__u64 pta)
 537 {
 538         /* Note: srlz.i implies srlz.d */
 539         ia64_setreg(_IA64_REG_CR_PTA, pta);
 540         ia64_srlz_i();
 541 }
 542
 543 static inline void
 544 ia64_eoi (void)
 545 {
 546         ia64_setreg(_IA64_REG_CR_EOI, 0);
 547         ia64_srlz_d();
 548 }
 549
 550 #define cpu_relax()     ia64_hint(ia64_hint_pause)
 551
 552 static inline void
 553 ia64_set_lrr0 (unsigned long val)
 554 {
 555         ia64_setreg(_IA64_REG_CR_LRR0, val);
 556         ia64_srlz_d();
 557 }
 558
 559 static inline void
 560 ia64_set_lrr1 (unsigned long val)
 561 {
 562         ia64_setreg(_IA64_REG_CR_LRR1, val);
 563         ia64_srlz_d();
 564 }
 565
 566
 567 /*
 568  * Given the address to which a spill occurred, return the unat bit
 569  * number that corresponds to this address.
 570  */
 571 static inline __u64
 572 ia64_unat_pos (void *spill_addr)
 573 {
 574         return ((__u64) spill_addr >> 3) & 0x3f;
 575 }
 576
 577 /*
 578  * Set the NaT bit of an integer register which was spilled at address
 579  * SPILL_ADDR.  UNAT is the mask to be updated.
 580  */
 581 static inline void
 582 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
 583 {
 584         __u64 bit = ia64_unat_pos(spill_addr);
 585         __u64 mask = 1UL << bit;
 586
 587         *unat = (*unat & ~mask) | (nat << bit);
 588 }
 589
 590 /*
 591  * Return saved PC of a blocked thread.
 592  * Note that the only way T can block is through a call to schedule() -> switch_to().
 593  */
 594 static inline unsigned long
 595 thread_saved_pc (struct task_struct *t)
 596 {
 597         struct unw_frame_info info;
 598         unsigned long ip;
 599
 600         unw_init_from_blocked_task(&info, t);
 601         if (unw_unwind(&info) < 0)
 602                 return 0;
 603         unw_get_ip(&info, &ip);
 604         return ip;
 605 }
 606
 607 /*
 608  * Get the current instruction/program counter value.
 609  */
 610 #define current_text_addr() \
 611         ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
 612
 613 static inline __u64
 614 ia64_get_ivr (void)
 615 {
 616         __u64 r;
 617         ia64_srlz_d();
 618         r = ia64_getreg(_IA64_REG_CR_IVR);
 619         ia64_srlz_d();
 620         return r;
 621 }
 622
 623 static inline void
 624 ia64_set_dbr (__u64 regnum, __u64 value)
 625 {
 626         __ia64_set_dbr(regnum, value);
 627 #ifdef CONFIG_ITANIUM
 628         ia64_srlz_d();
 629 #endif
 630 }
 631
 632 static inline __u64
 633 ia64_get_dbr (__u64 regnum)
 634 {
 635         __u64 retval;
 636
 637         retval = __ia64_get_dbr(regnum);
 638 #ifdef CONFIG_ITANIUM
 639         ia64_srlz_d();
 640 #endif
 641         return retval;
 642 }
 643
 644 static inline __u64
 645 ia64_rotr (__u64 w, __u64 n)
 646 {
 647         return (w >> n) | (w << (64 - n));
 648 }
 649
 650 #define ia64_rotl(w,n)  ia64_rotr((w), (64) - (n))
 651
 652 /*
 653  * Take a mapped kernel address and return the equivalent address
 654  * in the region 7 identity mapped virtual area.
 655  */
 656 static inline void *
 657 ia64_imva (void *addr)
 658 {
 659         void *result;
 660         result = (void *) ia64_tpa(addr);
 661         return __va(result);
 662 }
 663
 664 #define ARCH_HAS_PREFETCH
 665 #define ARCH_HAS_PREFETCHW
 666 #define ARCH_HAS_SPINLOCK_PREFETCH
 667 #define PREFETCH_STRIDE                 L1_CACHE_BYTES
 668
 669 static inline void
 670 prefetch (const void *x)
 671 {
 672          ia64_lfetch(ia64_lfhint_none, x);
 673 }
 674
 675 static inline void
 676 prefetchw (const void *x)
 677 {
 678         ia64_lfetch_excl(ia64_lfhint_none, x);
 679 }
 680
 681 #define spin_lock_prefetch(x)   prefetchw(x)
 682
 683 extern unsigned long boot_option_idle_override;
 684
 685 #endif /* !__ASSEMBLY__ */
 686
 687 #endif /* _ASM_IA64_PROCESSOR_H */