include/asm-i386/system.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/config.h>
   5 #include <linux/kernel.h>
   6 #include <asm/segment.h>
   7 #include <asm/cpufeature.h>
   8 #include <linux/bitops.h> /* for LOCK_PREFIX */
   9
  10 #ifdef __KERNEL__
  11
  12 struct task_struct;     /* one of the stranger aspects of C forward declarations.. */
  13 extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
  14
  15 #define switch_to(prev,next,last) do {                                  \
  16         unsigned long esi,edi;                                          \
  17         asm volatile("pushl %%ebp\n\t"                                  \
  18                      "movl %%esp,%0\n\t"        /* save ESP */          \
  19                      "movl %5,%%esp\n\t"        /* restore ESP */       \
  20                      "movl $1f,%1\n\t"          /* save EIP */          \
  21                      "pushl %6\n\t"             /* restore EIP */       \
  22                      "jmp __switch_to\n"                                \
  23                      "1:\t"                                             \
  24                      "popl %%ebp\n\t"                                   \
  25                      :"=m" (prev->thread.esp),"=m" (prev->thread.eip),  \
  26                       "=a" (last),"=S" (esi),"=D" (edi)                 \
  27                      :"m" (next->thread.esp),"m" (next->thread.eip),    \
  28                       "2" (prev), "d" (next));                          \
  29 } while (0)
  30
  31 #define _set_base(addr,base) do { unsigned long __pr; \
  32 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  33         "rorl $16,%%edx\n\t" \
  34         "movb %%dl,%2\n\t" \
  35         "movb %%dh,%3" \
  36         :"=&d" (__pr) \
  37         :"m" (*((addr)+2)), \
  38          "m" (*((addr)+4)), \
  39          "m" (*((addr)+7)), \
  40          "0" (base) \
  41         ); } while(0)
  42
  43 #define _set_limit(addr,limit) do { unsigned long __lr; \
  44 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  45         "rorl $16,%%edx\n\t" \
  46         "movb %2,%%dh\n\t" \
  47         "andb $0xf0,%%dh\n\t" \
  48         "orb %%dh,%%dl\n\t" \
  49         "movb %%dl,%2" \
  50         :"=&d" (__lr) \
  51         :"m" (*(addr)), \
  52          "m" (*((addr)+6)), \
  53          "0" (limit) \
  54         ); } while(0)
  55
  56 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
  57 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1)>>12 )
  58
  59 static inline unsigned long _get_base(char * addr)
  60 {
  61         unsigned long __base;
  62         __asm__("movb %3,%%dh\n\t"
  63                 "movb %2,%%dl\n\t"
  64                 "shll $16,%%edx\n\t"
  65                 "movw %1,%%dx"
  66                 :"=&d" (__base)
  67                 :"m" (*((addr)+2)),
  68                  "m" (*((addr)+4)),
  69                  "m" (*((addr)+7)));
  70         return __base;
  71 }
  72
  73 #define get_base(ldt) _get_base( ((char *)&(ldt)) )
  74
  75 /*
  76  * Load a segment. Fall back on loading the zero
  77  * segment if something goes wrong..
  78  */
  79 #define loadsegment(seg,value)                  \
  80         asm volatile("\n"                       \
  81                 "1:\t"                          \
  82                 "mov %0,%%" #seg "\n"           \
  83                 "2:\n"                          \
  84                 ".section .fixup,\"ax\"\n"      \
  85                 "3:\t"                          \
  86                 "pushl $0\n\t"                  \
  87                 "popl %%" #seg "\n\t"           \
  88                 "jmp 2b\n"                      \
  89                 ".previous\n"                   \
  90                 ".section __ex_table,\"a\"\n\t" \
  91                 ".align 4\n\t"                  \
  92                 ".long 1b,3b\n"                 \
  93                 ".previous"                     \
  94                 : :"rm" (value))
  95
  96 /*
  97  * Save a segment register away
  98  */
  99 #define savesegment(seg, value) \
 100         asm volatile("mov %%" #seg ",%0":"=rm" (value))
 101
 102 /*
 103  * Clear and set 'TS' bit respectively
 104  */
 105 #define clts() __asm__ __volatile__ ("clts")
 106 #define read_cr0() ({ \
 107         unsigned int __dummy; \
 108         __asm__ __volatile__( \
 109                 "movl %%cr0,%0\n\t" \
 110                 :"=r" (__dummy)); \
 111         __dummy; \
 112 })
 113 #define write_cr0(x) \
 114         __asm__ __volatile__("movl %0,%%cr0": :"r" (x));
 115
 116 #define read_cr2() ({ \
 117         unsigned int __dummy; \
 118         __asm__ __volatile__( \
 119                 "movl %%cr2,%0\n\t" \
 120                 :"=r" (__dummy)); \
 121         __dummy; \
 122 })
 123 #define write_cr2(x) \
 124         __asm__ __volatile__("movl %0,%%cr2": :"r" (x));
 125
 126 #define read_cr3() ({ \
 127         unsigned int __dummy; \
 128         __asm__ ( \
 129                 "movl %%cr3,%0\n\t" \
 130                 :"=r" (__dummy)); \
 131         __dummy; \
 132 })
 133 #define write_cr3(x) \
 134         __asm__ __volatile__("movl %0,%%cr3": :"r" (x));
 135
 136 #define read_cr4() ({ \
 137         unsigned int __dummy; \
 138         __asm__( \
 139                 "movl %%cr4,%0\n\t" \
 140                 :"=r" (__dummy)); \
 141         __dummy; \
 142 })
 143
 144 #define read_cr4_safe() ({                            \
 145         unsigned int __dummy;                         \
 146         /* This could fault if %cr4 does not exist */ \
 147         __asm__("1: movl %%cr4, %0              \n"   \
 148                 "2:                             \n"   \
 149                 ".section __ex_table,\"a\"      \n"   \
 150                 ".long 1b,2b                    \n"   \
 151                 ".previous                      \n"   \
 152                 : "=r" (__dummy): "0" (0));           \
 153         __dummy;                                      \
 154 })
 155
 156 #define write_cr4(x) \
 157         __asm__ __volatile__("movl %0,%%cr4": :"r" (x));
 158 #define stts() write_cr0(8 | read_cr0())
 159
 160 #endif  /* __KERNEL__ */
 161
 162 #define wbinvd() \
 163         __asm__ __volatile__ ("wbinvd": : :"memory");
 164
 165 static inline unsigned long get_limit(unsigned long segment)
 166 {
 167         unsigned long __limit;
 168         __asm__("lsll %1,%0"
 169                 :"=r" (__limit):"r" (segment));
 170         return __limit+1;
 171 }
 172
 173 #define nop() __asm__ __volatile__ ("nop")
 174
 175 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 176
 177 #define tas(ptr) (xchg((ptr),1))
 178
 179 struct __xchg_dummy { unsigned long a[100]; };
 180 #define __xg(x) ((struct __xchg_dummy *)(x))
 181
 182
 183 #ifdef CONFIG_X86_CMPXCHG64
 184
 185 /*
 186  * The semantics of XCHGCMP8B are a bit strange, this is why
 187  * there is a loop and the loading of %%eax and %%edx has to
 188  * be inside. This inlines well in most cases, the cached
 189  * cost is around ~38 cycles. (in the future we might want
 190  * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
 191  * might have an implicit FPU-save as a cost, so it's not
 192  * clear which path to go.)
 193  *
 194  * cmpxchg8b must be used with the lock prefix here to allow
 195  * the instruction to be executed atomically, see page 3-102
 196  * of the instruction set reference 24319102.pdf. We need
 197  * the reader side to see the coherent 64bit value.
 198  */
 199 static inline void __set_64bit (unsigned long long * ptr,
 200                 unsigned int low, unsigned int high)
 201 {
 202         __asm__ __volatile__ (
 203                 "\n1:\t"
 204                 "movl (%0), %%eax\n\t"
 205                 "movl 4(%0), %%edx\n\t"
 206                 "lock cmpxchg8b (%0)\n\t"
 207                 "jnz 1b"
 208                 : /* no outputs */
 209                 :       "D"(ptr),
 210                         "b"(low),
 211                         "c"(high)
 212                 :       "ax","dx","memory");
 213 }
 214
 215 static inline void __set_64bit_constant (unsigned long long *ptr,
 216                                                  unsigned long long value)
 217 {
 218         __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
 219 }
 220 #define ll_low(x)       *(((unsigned int*)&(x))+0)
 221 #define ll_high(x)      *(((unsigned int*)&(x))+1)
 222
 223 static inline void __set_64bit_var (unsigned long long *ptr,
 224                          unsigned long long value)
 225 {
 226         __set_64bit(ptr,ll_low(value), ll_high(value));
 227 }
 228
 229 #define set_64bit(ptr,value) \
 230 (__builtin_constant_p(value) ? \
 231  __set_64bit_constant(ptr, value) : \
 232  __set_64bit_var(ptr, value) )
 233
 234 #define _set_64bit(ptr,value) \
 235 (__builtin_constant_p(value) ? \
 236  __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
 237  __set_64bit(ptr, ll_low(value), ll_high(value)) )
 238
 239 #endif
 240
 241 /*
 242  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 243  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 244  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 245  */
 246 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 247 {
 248         switch (size) {
 249                 case 1:
 250                         __asm__ __volatile__("xchgb %b0,%1"
 251                                 :"=q" (x)
 252                                 :"m" (*__xg(ptr)), "0" (x)
 253                                 :"memory");
 254                         break;
 255                 case 2:
 256                         __asm__ __volatile__("xchgw %w0,%1"
 257                                 :"=r" (x)
 258                                 :"m" (*__xg(ptr)), "0" (x)
 259                                 :"memory");
 260                         break;
 261                 case 4:
 262                         __asm__ __volatile__("xchgl %0,%1"
 263                                 :"=r" (x)
 264                                 :"m" (*__xg(ptr)), "0" (x)
 265                                 :"memory");
 266                         break;
 267         }
 268         return x;
 269 }
 270
 271 /*
 272  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 273  * store NEW in MEM.  Return the initial value in MEM.  Success is
 274  * indicated by comparing RETURN with OLD.
 275  */
 276
 277 #ifdef CONFIG_X86_CMPXCHG
 278 #define __HAVE_ARCH_CMPXCHG 1
 279 #define cmpxchg(ptr,o,n)\
 280         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 281                                         (unsigned long)(n),sizeof(*(ptr))))
 282 #endif
 283
 284 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 285                                       unsigned long new, int size)
 286 {
 287         unsigned long prev;
 288         switch (size) {
 289         case 1:
 290                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
 291                                      : "=a"(prev)
 292                                      : "q"(new), "m"(*__xg(ptr)), "0"(old)
 293                                      : "memory");
 294                 return prev;
 295         case 2:
 296                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
 297                                      : "=a"(prev)
 298                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 299                                      : "memory");
 300                 return prev;
 301         case 4:
 302                 __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
 303                                      : "=a"(prev)
 304                                      : "r"(new), "m"(*__xg(ptr)), "0"(old)
 305                                      : "memory");
 306                 return prev;
 307         }
 308         return old;
 309 }
 310
 311 #ifndef CONFIG_X86_CMPXCHG
 312 /*
 313  * Building a kernel capable running on 80386. It may be necessary to
 314  * simulate the cmpxchg on the 80386 CPU. For that purpose we define
 315  * a function for each of the sizes we support.
 316  */
 317
 318 extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
 319 extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
 320 extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
 321
 322 static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
 323                                       unsigned long new, int size)
 324 {
 325         switch (size) {
 326         case 1:
 327                 return cmpxchg_386_u8(ptr, old, new);
 328         case 2:
 329                 return cmpxchg_386_u16(ptr, old, new);
 330         case 4:
 331                 return cmpxchg_386_u32(ptr, old, new);
 332         }
 333         return old;
 334 }
 335
 336 #define cmpxchg(ptr,o,n)                                                \
 337 ({                                                                      \
 338         __typeof__(*(ptr)) __ret;                                       \
 339         if (likely(boot_cpu_data.x86 > 3))                              \
 340                 __ret = __cmpxchg((ptr), (unsigned long)(o),            \
 341                                         (unsigned long)(n), sizeof(*(ptr))); \
 342         else                                                            \
 343                 __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
 344                                         (unsigned long)(n), sizeof(*(ptr))); \
 345         __ret;                                                          \
 346 })
 347 #endif
 348
 349 #ifdef CONFIG_X86_CMPXCHG64
 350
 351 static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
 352                                       unsigned long long new)
 353 {
 354         unsigned long long prev;
 355         __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
 356                              : "=A"(prev)
 357                              : "b"((unsigned long)new),
 358                                "c"((unsigned long)(new >> 32)),
 359                                "m"(*__xg(ptr)),
 360                                "0"(old)
 361                              : "memory");
 362         return prev;
 363 }
 364
 365 #define cmpxchg64(ptr,o,n)\
 366         ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
 367                                         (unsigned long long)(n)))
 368
 369 #endif
 370
 371 #ifdef __KERNEL__
 372 struct alt_instr {
 373         __u8 *instr;            /* original instruction */
 374         __u8 *replacement;
 375         __u8  cpuid;            /* cpuid bit set for replacement */
 376         __u8  instrlen;         /* length of original instruction */
 377         __u8  replacementlen;   /* length of new instruction, <= instrlen */
 378         __u8  pad;
 379 };
 380 #endif
 381
 382 /*
 383  * Alternative instructions for different CPU types or capabilities.
 384  *
 385  * This allows to use optimized instructions even on generic binary
 386  * kernels.
 387  *
 388  * length of oldinstr must be longer or equal the length of newinstr
 389  * It can be padded with nops as needed.
 390  *
 391  * For non barrier like inlines please define new variants
 392  * without volatile and memory clobber.
 393  */
 394 #define alternative(oldinstr, newinstr, feature)        \
 395         asm volatile ("661:\n\t" oldinstr "\n662:\n"                 \
 396                       ".section .altinstructions,\"a\"\n"            \
 397                       "  .align 4\n"                                   \
 398                       "  .long 661b\n"            /* label */          \
 399                       "  .long 663f\n"            /* new instruction */         \
 400                       "  .byte %c0\n"             /* feature bit */    \
 401                       "  .byte 662b-661b\n"       /* sourcelen */      \
 402                       "  .byte 664f-663f\n"       /* replacementlen */ \
 403                       ".previous\n"                                             \
 404                       ".section .altinstr_replacement,\"ax\"\n"                 \
 405                       "663:\n\t" newinstr "\n664:\n"   /* replacement */    \
 406                       ".previous" :: "i" (feature) : "memory")
 407
 408 /*
 409  * Alternative inline assembly with input.
 410  *
 411  * Pecularities:
 412  * No memory clobber here.
 413  * Argument numbers start with 1.
 414  * Best is to use constraints that are fixed size (like (%1) ... "r")
 415  * If you use variable sized constraints like "m" or "g" in the
 416  * replacement maake sure to pad to the worst case length.
 417  */
 418 #define alternative_input(oldinstr, newinstr, feature, input...)                \
 419         asm volatile ("661:\n\t" oldinstr "\n662:\n"                            \
 420                       ".section .altinstructions,\"a\"\n"                       \
 421                       "  .align 4\n"                                            \
 422                       "  .long 661b\n"            /* label */                   \
 423                       "  .long 663f\n"            /* new instruction */         \
 424                       "  .byte %c0\n"             /* feature bit */             \
 425                       "  .byte 662b-661b\n"       /* sourcelen */               \
 426                       "  .byte 664f-663f\n"       /* replacementlen */          \
 427                       ".previous\n"                                             \
 428                       ".section .altinstr_replacement,\"ax\"\n"                 \
 429                       "663:\n\t" newinstr "\n664:\n"   /* replacement */        \
 430                       ".previous" :: "i" (feature), ##input)
 431
 432 /*
 433  * Force strict CPU ordering.
 434  * And yes, this is required on UP too when we're talking
 435  * to devices.
 436  *
 437  * For now, "wmb()" doesn't actually do anything, as all
 438  * Intel CPU's follow what Intel calls a *Processor Order*,
 439  * in which all writes are seen in the program order even
 440  * outside the CPU.
 441  *
 442  * I expect future Intel CPU's to have a weaker ordering,
 443  * but I'd also expect them to finally get their act together
 444  * and add some real memory barriers if so.
 445  *
 446  * Some non intel clones support out of order store. wmb() ceases to be a
 447  * nop for these.
 448  */
 449
 450
 451 /*
 452  * Actually only lfence would be needed for mb() because all stores done
 453  * by the kernel should be already ordered. But keep a full barrier for now.
 454  */
 455
 456 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 457 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 458
 459 /**
 460  * read_barrier_depends - Flush all pending reads that subsequents reads
 461  * depend on.
 462  *
 463  * No data-dependent reads from memory-like regions are ever reordered
 464  * over this barrier.  All reads preceding this primitive are guaranteed
 465  * to access memory (but not necessarily other CPUs' caches) before any
 466  * reads following this primitive that depend on the data return by
 467  * any of the preceding reads.  This primitive is much lighter weight than
 468  * rmb() on most CPUs, and is never heavier weight than is
 469  * rmb().
 470  *
 471  * These ordering constraints are respected by both the local CPU
 472  * and the compiler.
 473  *
 474  * Ordering is not guaranteed by anything other than these primitives,
 475  * not even by data dependencies.  See the documentation for
 476  * memory_barrier() for examples and URLs to more information.
 477  *
 478  * For example, the following code would force ordering (the initial
 479  * value of "a" is zero, "b" is one, and "p" is "&a"):
 480  *
 481  * <programlisting>
 482  *      CPU 0                           CPU 1
 483  *
 484  *      b = 2;
 485  *      memory_barrier();
 486  *      p = &b;                         q = p;
 487  *                                      read_barrier_depends();
 488  *                                      d = *q;
 489  * </programlisting>
 490  *
 491  * because the read of "*q" depends on the read of "p" and these
 492  * two reads are separated by a read_barrier_depends().  However,
 493  * the following code, with the same initial values for "a" and "b":
 494  *
 495  * <programlisting>
 496  *      CPU 0                           CPU 1
 497  *
 498  *      a = 2;
 499  *      memory_barrier();
 500  *      b = 3;                          y = b;
 501  *                                      read_barrier_depends();
 502  *                                      x = a;
 503  * </programlisting>
 504  *
 505  * does not enforce ordering, since there is no data dependency between
 506  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 507  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 508  * in cases like thiswhere there are no data dependencies.
 509  **/
 510
 511 #define read_barrier_depends()  do { } while(0)
 512
 513 #ifdef CONFIG_X86_OOSTORE
 514 /* Actually there are no OOO store capable CPUs for now that do SSE,
 515    but make it already an possibility. */
 516 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 517 #else
 518 #define wmb()   __asm__ __volatile__ ("": : :"memory")
 519 #endif
 520
 521 #ifdef CONFIG_SMP
 522 #define smp_mb()        mb()
 523 #define smp_rmb()       rmb()
 524 #define smp_wmb()       wmb()
 525 #define smp_read_barrier_depends()      read_barrier_depends()
 526 #define set_mb(var, value) do { xchg(&var, value); } while (0)
 527 #else
 528 #define smp_mb()        barrier()
 529 #define smp_rmb()       barrier()
 530 #define smp_wmb()       barrier()
 531 #define smp_read_barrier_depends()      do { } while(0)
 532 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 533 #endif
 534
 535 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 536
 537 /* interrupt control.. */
 538 #define local_save_flags(x)     do { typecheck(unsigned long,x); __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */); } while (0)
 539 #define local_irq_restore(x)    do { typecheck(unsigned long,x); __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc"); } while (0)
 540 #define local_irq_disable()     __asm__ __volatile__("cli": : :"memory")
 541 #define local_irq_enable()      __asm__ __volatile__("sti": : :"memory")
 542 /* used in the idle loop; sti takes one instruction cycle to complete */
 543 #define safe_halt()             __asm__ __volatile__("sti; hlt": : :"memory")
 544 /* used when interrupts are already enabled or to shutdown the processor */
 545 #define halt()                  __asm__ __volatile__("hlt": : :"memory")
 546
 547 #define irqs_disabled()                 \
 548 ({                                      \
 549         unsigned long flags;            \
 550         local_save_flags(flags);        \
 551         !(flags & (1<<9));              \
 552 })
 553
 554 /* For spinlocks etc */
 555 #define local_irq_save(x)       __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (x): /* no input */ :"memory")
 556
 557 /*
 558  * disable hlt during certain critical i/o operations
 559  */
 560 #define HAVE_DISABLE_HLT
 561 void disable_hlt(void);
 562 void enable_hlt(void);
 563
 564 extern int es7000_plat;
 565 void cpu_idle_wait(void);
 566
 567 extern unsigned long arch_align_stack(unsigned long sp);
 568
 569 #endif