drivers/staging/dream/smd/smd_private.h

   1 /* arch/arm/mach-msm/smd_private.h
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  * Copyright (c) 2007 QUALCOMM Incorporated
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16 #ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
  17 #define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
  18
  19 struct smem_heap_info {
  20         unsigned initialized;
  21         unsigned free_offset;
  22         unsigned heap_remaining;
  23         unsigned reserved;
  24 };
  25
  26 struct smem_heap_entry {
  27         unsigned allocated;
  28         unsigned offset;
  29         unsigned size;
  30         unsigned reserved;
  31 };
  32
  33 struct smem_proc_comm {
  34         unsigned command;
  35         unsigned status;
  36         unsigned data1;
  37         unsigned data2;
  38 };
  39
  40 #define PC_APPS  0
  41 #define PC_MODEM 1
  42
  43 #define VERSION_QDSP6     4
  44 #define VERSION_APPS_SBL  6
  45 #define VERSION_MODEM_SBL 7
  46 #define VERSION_APPS      8
  47 #define VERSION_MODEM     9
  48
  49 struct smem_shared {
  50         struct smem_proc_comm proc_comm[4];
  51         unsigned version[32];
  52         struct smem_heap_info heap_info;
  53         struct smem_heap_entry heap_toc[128];
  54 };
  55
  56 struct smsm_shared {
  57         unsigned host;
  58         unsigned state;
  59 };
  60
  61 struct smsm_interrupt_info {
  62         uint32_t aArm_en_mask;
  63         uint32_t aArm_interrupts_pending;
  64         uint32_t aArm_wakeup_reason;
  65 };
  66
  67 #define SZ_DIAG_ERR_MSG 0xC8
  68 #define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
  69 #define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
  70 #define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
  71 #define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
  72
  73 #define SMSM_INIT          0x000001
  74 #define SMSM_SMDINIT       0x000008
  75 #define SMSM_RPCINIT       0x000020
  76 #define SMSM_RESET         0x000040
  77 #define SMSM_RSA               0x0080
  78 #define SMSM_RUN           0x000100
  79 #define SMSM_PWRC              0x0200
  80 #define SMSM_TIMEWAIT          0x0400
  81 #define SMSM_TIMEINIT          0x0800
  82 #define SMSM_PWRC_EARLY_EXIT   0x1000
  83 #define SMSM_WFPI              0x2000
  84 #define SMSM_SLEEP             0x4000
  85 #define SMSM_SLEEPEXIT         0x8000
  86 #define SMSM_OEMSBL_RELEASE    0x10000
  87 #define SMSM_PWRC_SUSPEND      0x200000
  88
  89 #define SMSM_WKUP_REASON_RPC    0x00000001
  90 #define SMSM_WKUP_REASON_INT    0x00000002
  91 #define SMSM_WKUP_REASON_GPIO   0x00000004
  92 #define SMSM_WKUP_REASON_TIMER  0x00000008
  93 #define SMSM_WKUP_REASON_ALARM  0x00000010
  94 #define SMSM_WKUP_REASON_RESET  0x00000020
  95
  96 void *smem_alloc(unsigned id, unsigned size);
  97 int smsm_change_state(uint32_t clear_mask, uint32_t set_mask);
  98 uint32_t smsm_get_state(void);
  99 int smsm_set_sleep_duration(uint32_t delay);
 100 int smsm_set_interrupt_info(struct smsm_interrupt_info *info);
 101 void smsm_print_sleep_info(void);
 102
 103 #define SMEM_NUM_SMD_CHANNELS        64
 104
 105 typedef enum {
 106         /* fixed items */
 107         SMEM_PROC_COMM = 0,
 108         SMEM_HEAP_INFO,
 109         SMEM_ALLOCATION_TABLE,
 110         SMEM_VERSION_INFO,
 111         SMEM_HW_RESET_DETECT,
 112         SMEM_AARM_WARM_BOOT,
 113         SMEM_DIAG_ERR_MESSAGE,
 114         SMEM_SPINLOCK_ARRAY,
 115         SMEM_MEMORY_BARRIER_LOCATION,
 116
 117         /* dynamic items */
 118         SMEM_AARM_PARTITION_TABLE,
 119         SMEM_AARM_BAD_BLOCK_TABLE,
 120         SMEM_RESERVE_BAD_BLOCKS,
 121         SMEM_WM_UUID,
 122         SMEM_CHANNEL_ALLOC_TBL,
 123         SMEM_SMD_BASE_ID,
 124         SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
 125         SMEM_SMEM_LOG_EVENTS,
 126         SMEM_SMEM_STATIC_LOG_IDX,
 127         SMEM_SMEM_STATIC_LOG_EVENTS,
 128         SMEM_SMEM_SLOW_CLOCK_SYNC,
 129         SMEM_SMEM_SLOW_CLOCK_VALUE,
 130         SMEM_BIO_LED_BUF,
 131         SMEM_SMSM_SHARED_STATE,
 132         SMEM_SMSM_INT_INFO,
 133         SMEM_SMSM_SLEEP_DELAY,
 134         SMEM_SMSM_LIMIT_SLEEP,
 135         SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
 136         SMEM_KEYPAD_KEYS_PRESSED,
 137         SMEM_KEYPAD_STATE_UPDATED,
 138         SMEM_KEYPAD_STATE_IDX,
 139         SMEM_GPIO_INT,
 140         SMEM_MDDI_LCD_IDX,
 141         SMEM_MDDI_HOST_DRIVER_STATE,
 142         SMEM_MDDI_LCD_DISP_STATE,
 143         SMEM_LCD_CUR_PANEL,
 144         SMEM_MARM_BOOT_SEGMENT_INFO,
 145         SMEM_AARM_BOOT_SEGMENT_INFO,
 146         SMEM_SLEEP_STATIC,
 147         SMEM_SCORPION_FREQUENCY,
 148         SMEM_SMD_PROFILES,
 149         SMEM_TSSC_BUSY,
 150         SMEM_HS_SUSPEND_FILTER_INFO,
 151         SMEM_BATT_INFO,
 152         SMEM_APPS_BOOT_MODE,
 153         SMEM_VERSION_FIRST,
 154         SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
 155         SMEM_OSS_RRCASN1_BUF1,
 156         SMEM_OSS_RRCASN1_BUF2,
 157         SMEM_ID_VENDOR0,
 158         SMEM_ID_VENDOR1,
 159         SMEM_ID_VENDOR2,
 160         SMEM_HW_SW_BUILD_ID,
 161         SMEM_NUM_ITEMS,
 162 } smem_mem_type;
 163
 164 #endif